arch/x86/kernel/cpu/mcheck/p6.c

   1 /*
   2  * P6 specific Machine Check Exception Reporting
   3  * (C) Copyright 2002 Alan Cox <alan@redhat.com>
   4  */
   5
   6 #include <linux/init.h>
   7 #include <linux/types.h>
   8 #include <linux/kernel.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/smp.h>
  11
  12 #include <asm/processor.h>
  13 #include <asm/system.h>
  14 #include <asm/msr.h>
  15
  16 #include "mce.h"
  17
  18 /* Machine Check Handler For PII/PIII */
  19 static void intel_machine_check(struct pt_regs *regs, long error_code)
  20 {
  21         int recover = 1;
  22         u32 alow, ahigh, high, low;
  23         u32 mcgstl, mcgsth;
  24         int i;
  25
  26         rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
  27         if (mcgstl & (1<<0))    /* Recoverable ? */
  28                 recover = 0;
  29
  30         printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
  31                 smp_processor_id(), mcgsth, mcgstl);
  32
  33         for (i = 0; i < nr_mce_banks; i++) {
  34                 rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
  35                 if (high & (1<<31)) {
  36                         char misc[20];
  37                         char addr[24];
  38                         misc[0] = addr[0] = '\0';
  39                         if (high & (1<<29))
  40                                 recover |= 1;
  41                         if (high & (1<<25))
  42                                 recover |= 2;
  43                         high &= ~(1<<31);
  44                         if (high & (1<<27)) {
  45                                 rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
  46                                 snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
  47                         }
  48                         if (high & (1<<26)) {
  49                                 rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
  50                                 snprintf(addr, 24, " at %08x%08x", ahigh, alow);
  51                         }
  52                         printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
  53                                 smp_processor_id(), i, high, low, misc, addr);
  54                 }
  55         }
  56
  57         if (recover & 2)
  58                 panic("CPU context corrupt");
  59         if (recover & 1)
  60                 panic("Unable to continue");
  61
  62         printk(KERN_EMERG "Attempting to continue.\n");
  63         /*
  64          * Do not clear the MSR_IA32_MCi_STATUS if the error is not
  65          * recoverable/continuable.This will allow BIOS to look at the MSRs
  66          * for errors if the OS could not log the error.
  67          */
  68         for (i = 0; i < nr_mce_banks; i++) {
  69                 unsigned int msr;
  70                 msr = MSR_IA32_MC0_STATUS+i*4;
  71                 rdmsr(msr, low, high);
  72                 if (high & (1<<31)) {
  73                         /* Clear it */
  74                         wrmsr(msr, 0UL, 0UL);
  75                         /* Serialize */
  76                         wmb();
  77                         add_taint(TAINT_MACHINE_CHECK);
  78                 }
  79         }
  80         mcgstl &= ~(1<<2);
  81         wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
  82 }
  83
  84 /* Set up machine check reporting for processors with Intel style MCE */
  85 void intel_p6_mcheck_init(struct cpuinfo_x86 *c)
  86 {
  87         u32 l, h;
  88         int i;
  89
  90         /* Check for MCE support */
  91         if (!cpu_has(c, X86_FEATURE_MCE))
  92                 return;
  93
  94         /* Check for PPro style MCA */
  95         if (!cpu_has(c, X86_FEATURE_MCA))
  96                 return;
  97
  98         /* Ok machine check is available */
  99         machine_check_vector = intel_machine_check;
 100         wmb();
 101
 102         printk(KERN_INFO "Intel machine check architecture supported.\n");
 103         rdmsr(MSR_IA32_MCG_CAP, l, h);
 104         if (l & (1<<8)) /* Control register present ? */
 105                 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
 106         nr_mce_banks = l & 0xff;
 107
 108         /*
 109          * Following the example in IA-32 SDM Vol 3:
 110          * - MC0_CTL should not be written
 111          * - Status registers on all banks should be cleared on reset
 112          */
 113         for (i = 1; i < nr_mce_banks; i++)
 114                 wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
 115
 116         for (i = 0; i < nr_mce_banks; i++)
 117                 wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
 118
 119         set_in_cr4(X86_CR4_MCE);
 120         printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
 121                 smp_processor_id());
 122 }