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KVM: MMU: Map device MMIO as UC in EPT
[linux-2.6/mini2440.git] / arch / x86 / kvm / vmx.c
blob07491c9c6ed03c1306b4bf5f7dfe04db9e830441
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
29 #include "x86.h"
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33 #include <asm/vmx.h>
34 #include <asm/virtext.h>
35
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
37
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
40
41 static int bypass_guest_pf = 1;
42 module_param(bypass_guest_pf, bool, 0);
43
44 static int enable_vpid = 1;
45 module_param(enable_vpid, bool, 0);
46
47 static int flexpriority_enabled = 1;
48 module_param(flexpriority_enabled, bool, 0);
49
50 static int enable_ept = 1;
51 module_param(enable_ept, bool, 0);
52
53 static int emulate_invalid_guest_state = 0;
54 module_param(emulate_invalid_guest_state, bool, 0);
55
56 struct vmcs {
57 u32 revision_id;
58 u32 abort;
59 char data[0];
60 };
61
62 struct vcpu_vmx {
63 struct kvm_vcpu vcpu;
64 struct list_head local_vcpus_link;
65 unsigned long host_rsp;
66 int launched;
67 u8 fail;
68 u32 idt_vectoring_info;
69 struct kvm_msr_entry *guest_msrs;
70 struct kvm_msr_entry *host_msrs;
71 int nmsrs;
72 int save_nmsrs;
73 int msr_offset_efer;
74 #ifdef CONFIG_X86_64
75 int msr_offset_kernel_gs_base;
76 #endif
77 struct vmcs *vmcs;
78 struct {
79 int loaded;
80 u16 fs_sel, gs_sel, ldt_sel;
81 int gs_ldt_reload_needed;
82 int fs_reload_needed;
83 int guest_efer_loaded;
84 } host_state;
85 struct {
86 struct {
87 bool pending;
88 u8 vector;
89 unsigned rip;
90 } irq;
91 } rmode;
92 int vpid;
93 bool emulation_required;
94
95 /* Support for vnmi-less CPUs */
96 int soft_vnmi_blocked;
97 ktime_t entry_time;
98 s64 vnmi_blocked_time;
99 };
100
101 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
102 {
103 return container_of(vcpu, struct vcpu_vmx, vcpu);
104 }
105
106 static int init_rmode(struct kvm *kvm);
107 static u64 construct_eptp(unsigned long root_hpa);
108
109 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
110 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
111 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
112
113 static struct page *vmx_io_bitmap_a;
114 static struct page *vmx_io_bitmap_b;
115 static struct page *vmx_msr_bitmap;
116
117 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
118 static DEFINE_SPINLOCK(vmx_vpid_lock);
119
120 static struct vmcs_config {
121 int size;
122 int order;
123 u32 revision_id;
124 u32 pin_based_exec_ctrl;
125 u32 cpu_based_exec_ctrl;
126 u32 cpu_based_2nd_exec_ctrl;
127 u32 vmexit_ctrl;
128 u32 vmentry_ctrl;
129 } vmcs_config;
130
131 static struct vmx_capability {
132 u32 ept;
133 u32 vpid;
134 } vmx_capability;
135
136 #define VMX_SEGMENT_FIELD(seg) \
137 [VCPU_SREG_##seg] = { \
138 .selector = GUEST_##seg##_SELECTOR, \
139 .base = GUEST_##seg##_BASE, \
140 .limit = GUEST_##seg##_LIMIT, \
141 .ar_bytes = GUEST_##seg##_AR_BYTES, \
142 }
143
144 static struct kvm_vmx_segment_field {
145 unsigned selector;
146 unsigned base;
147 unsigned limit;
148 unsigned ar_bytes;
149 } kvm_vmx_segment_fields[] = {
150 VMX_SEGMENT_FIELD(CS),
151 VMX_SEGMENT_FIELD(DS),
152 VMX_SEGMENT_FIELD(ES),
153 VMX_SEGMENT_FIELD(FS),
154 VMX_SEGMENT_FIELD(GS),
155 VMX_SEGMENT_FIELD(SS),
156 VMX_SEGMENT_FIELD(TR),
157 VMX_SEGMENT_FIELD(LDTR),
158 };
159
160 /*
161 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
162 * away by decrementing the array size.
163 */
164 static const u32 vmx_msr_index[] = {
165 #ifdef CONFIG_X86_64
166 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
167 #endif
168 MSR_EFER, MSR_K6_STAR,
169 };
170 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
171
172 static void load_msrs(struct kvm_msr_entry *e, int n)
173 {
174 int i;
175
176 for (i = 0; i < n; ++i)
177 wrmsrl(e[i].index, e[i].data);
178 }
179
180 static void save_msrs(struct kvm_msr_entry *e, int n)
181 {
182 int i;
183
184 for (i = 0; i < n; ++i)
185 rdmsrl(e[i].index, e[i].data);
186 }
187
188 static inline int is_page_fault(u32 intr_info)
189 {
190 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
191 INTR_INFO_VALID_MASK)) ==
192 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
193 }
194
195 static inline int is_no_device(u32 intr_info)
196 {
197 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
198 INTR_INFO_VALID_MASK)) ==
199 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
200 }
201
202 static inline int is_invalid_opcode(u32 intr_info)
203 {
204 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
205 INTR_INFO_VALID_MASK)) ==
206 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
207 }
208
209 static inline int is_external_interrupt(u32 intr_info)
210 {
211 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
212 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
213 }
214
215 static inline int cpu_has_vmx_msr_bitmap(void)
216 {
217 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
218 }
219
220 static inline int cpu_has_vmx_tpr_shadow(void)
221 {
222 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
223 }
224
225 static inline int vm_need_tpr_shadow(struct kvm *kvm)
226 {
227 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
228 }
229
230 static inline int cpu_has_secondary_exec_ctrls(void)
231 {
232 return (vmcs_config.cpu_based_exec_ctrl &
233 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
234 }
235
236 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
237 {
238 return flexpriority_enabled
239 && (vmcs_config.cpu_based_2nd_exec_ctrl &
240 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
241 }
242
243 static inline int cpu_has_vmx_invept_individual_addr(void)
244 {
245 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
246 }
247
248 static inline int cpu_has_vmx_invept_context(void)
249 {
250 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
251 }
252
253 static inline int cpu_has_vmx_invept_global(void)
254 {
255 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
256 }
257
258 static inline int cpu_has_vmx_ept(void)
259 {
260 return (vmcs_config.cpu_based_2nd_exec_ctrl &
261 SECONDARY_EXEC_ENABLE_EPT);
262 }
263
264 static inline int vm_need_ept(void)
265 {
266 return (cpu_has_vmx_ept() && enable_ept);
267 }
268
269 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
270 {
271 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
272 (irqchip_in_kernel(kvm)));
273 }
274
275 static inline int cpu_has_vmx_vpid(void)
276 {
277 return (vmcs_config.cpu_based_2nd_exec_ctrl &
278 SECONDARY_EXEC_ENABLE_VPID);
279 }
280
281 static inline int cpu_has_virtual_nmis(void)
282 {
283 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
284 }
285
286 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
287 {
288 int i;
289
290 for (i = 0; i < vmx->nmsrs; ++i)
291 if (vmx->guest_msrs[i].index == msr)
292 return i;
293 return -1;
294 }
295
296 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
297 {
298 struct {
299 u64 vpid : 16;
300 u64 rsvd : 48;
301 u64 gva;
302 } operand = { vpid, 0, gva };
303
304 asm volatile (__ex(ASM_VMX_INVVPID)
305 /* CF==1 or ZF==1 --> rc = -1 */
306 "; ja 1f ; ud2 ; 1:"
307 : : "a"(&operand), "c"(ext) : "cc", "memory");
308 }
309
310 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
311 {
312 struct {
313 u64 eptp, gpa;
314 } operand = {eptp, gpa};
315
316 asm volatile (__ex(ASM_VMX_INVEPT)
317 /* CF==1 or ZF==1 --> rc = -1 */
318 "; ja 1f ; ud2 ; 1:\n"
319 : : "a" (&operand), "c" (ext) : "cc", "memory");
320 }
321
322 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
323 {
324 int i;
325
326 i = __find_msr_index(vmx, msr);
327 if (i >= 0)
328 return &vmx->guest_msrs[i];
329 return NULL;
330 }
331
332 static void vmcs_clear(struct vmcs *vmcs)
333 {
334 u64 phys_addr = __pa(vmcs);
335 u8 error;
336
337 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
338 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
339 : "cc", "memory");
340 if (error)
341 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
342 vmcs, phys_addr);
343 }
344
345 static void __vcpu_clear(void *arg)
346 {
347 struct vcpu_vmx *vmx = arg;
348 int cpu = raw_smp_processor_id();
349
350 if (vmx->vcpu.cpu == cpu)
351 vmcs_clear(vmx->vmcs);
352 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
353 per_cpu(current_vmcs, cpu) = NULL;
354 rdtscll(vmx->vcpu.arch.host_tsc);
355 list_del(&vmx->local_vcpus_link);
356 vmx->vcpu.cpu = -1;
357 vmx->launched = 0;
358 }
359
360 static void vcpu_clear(struct vcpu_vmx *vmx)
361 {
362 if (vmx->vcpu.cpu == -1)
363 return;
364 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
365 }
366
367 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
368 {
369 if (vmx->vpid == 0)
370 return;
371
372 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
373 }
374
375 static inline void ept_sync_global(void)
376 {
377 if (cpu_has_vmx_invept_global())
378 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
379 }
380
381 static inline void ept_sync_context(u64 eptp)
382 {
383 if (vm_need_ept()) {
384 if (cpu_has_vmx_invept_context())
385 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
386 else
387 ept_sync_global();
388 }
389 }
390
391 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
392 {
393 if (vm_need_ept()) {
394 if (cpu_has_vmx_invept_individual_addr())
395 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
396 eptp, gpa);
397 else
398 ept_sync_context(eptp);
399 }
400 }
401
402 static unsigned long vmcs_readl(unsigned long field)
403 {
404 unsigned long value;
405
406 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
407 : "=a"(value) : "d"(field) : "cc");
408 return value;
409 }
410
411 static u16 vmcs_read16(unsigned long field)
412 {
413 return vmcs_readl(field);
414 }
415
416 static u32 vmcs_read32(unsigned long field)
417 {
418 return vmcs_readl(field);
419 }
420
421 static u64 vmcs_read64(unsigned long field)
422 {
423 #ifdef CONFIG_X86_64
424 return vmcs_readl(field);
425 #else
426 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
427 #endif
428 }
429
430 static noinline void vmwrite_error(unsigned long field, unsigned long value)
431 {
432 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
433 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
434 dump_stack();
435 }
436
437 static void vmcs_writel(unsigned long field, unsigned long value)
438 {
439 u8 error;
440
441 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
442 : "=q"(error) : "a"(value), "d"(field) : "cc");
443 if (unlikely(error))
444 vmwrite_error(field, value);
445 }
446
447 static void vmcs_write16(unsigned long field, u16 value)
448 {
449 vmcs_writel(field, value);
450 }
451
452 static void vmcs_write32(unsigned long field, u32 value)
453 {
454 vmcs_writel(field, value);
455 }
456
457 static void vmcs_write64(unsigned long field, u64 value)
458 {
459 vmcs_writel(field, value);
460 #ifndef CONFIG_X86_64
461 asm volatile ("");
462 vmcs_writel(field+1, value >> 32);
463 #endif
464 }
465
466 static void vmcs_clear_bits(unsigned long field, u32 mask)
467 {
468 vmcs_writel(field, vmcs_readl(field) & ~mask);
469 }
470
471 static void vmcs_set_bits(unsigned long field, u32 mask)
472 {
473 vmcs_writel(field, vmcs_readl(field) | mask);
474 }
475
476 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
477 {
478 u32 eb;
479
480 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
481 if (!vcpu->fpu_active)
482 eb |= 1u << NM_VECTOR;
483 if (vcpu->guest_debug.enabled)
484 eb |= 1u << DB_VECTOR;
485 if (vcpu->arch.rmode.active)
486 eb = ~0;
487 if (vm_need_ept())
488 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
489 vmcs_write32(EXCEPTION_BITMAP, eb);
490 }
491
492 static void reload_tss(void)
493 {
494 /*
495 * VT restores TR but not its size. Useless.
496 */
497 struct descriptor_table gdt;
498 struct desc_struct *descs;
499
500 kvm_get_gdt(&gdt);
501 descs = (void *)gdt.base;
502 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
503 load_TR_desc();
504 }
505
506 static void load_transition_efer(struct vcpu_vmx *vmx)
507 {
508 int efer_offset = vmx->msr_offset_efer;
509 u64 host_efer = vmx->host_msrs[efer_offset].data;
510 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
511 u64 ignore_bits;
512
513 if (efer_offset < 0)
514 return;
515 /*
516 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
517 * outside long mode
518 */
519 ignore_bits = EFER_NX | EFER_SCE;
520 #ifdef CONFIG_X86_64
521 ignore_bits |= EFER_LMA | EFER_LME;
522 /* SCE is meaningful only in long mode on Intel */
523 if (guest_efer & EFER_LMA)
524 ignore_bits &= ~(u64)EFER_SCE;
525 #endif
526 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
527 return;
528
529 vmx->host_state.guest_efer_loaded = 1;
530 guest_efer &= ~ignore_bits;
531 guest_efer |= host_efer & ignore_bits;
532 wrmsrl(MSR_EFER, guest_efer);
533 vmx->vcpu.stat.efer_reload++;
534 }
535
536 static void reload_host_efer(struct vcpu_vmx *vmx)
537 {
538 if (vmx->host_state.guest_efer_loaded) {
539 vmx->host_state.guest_efer_loaded = 0;
540 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
541 }
542 }
543
544 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
545 {
546 struct vcpu_vmx *vmx = to_vmx(vcpu);
547
548 if (vmx->host_state.loaded)
549 return;
550
551 vmx->host_state.loaded = 1;
552 /*
553 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
554 * allow segment selectors with cpl > 0 or ti == 1.
555 */
556 vmx->host_state.ldt_sel = kvm_read_ldt();
557 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
558 vmx->host_state.fs_sel = kvm_read_fs();
559 if (!(vmx->host_state.fs_sel & 7)) {
560 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
561 vmx->host_state.fs_reload_needed = 0;
562 } else {
563 vmcs_write16(HOST_FS_SELECTOR, 0);
564 vmx->host_state.fs_reload_needed = 1;
565 }
566 vmx->host_state.gs_sel = kvm_read_gs();
567 if (!(vmx->host_state.gs_sel & 7))
568 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
569 else {
570 vmcs_write16(HOST_GS_SELECTOR, 0);
571 vmx->host_state.gs_ldt_reload_needed = 1;
572 }
573
574 #ifdef CONFIG_X86_64
575 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
576 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
577 #else
578 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
579 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
580 #endif
581
582 #ifdef CONFIG_X86_64
583 if (is_long_mode(&vmx->vcpu))
584 save_msrs(vmx->host_msrs +
585 vmx->msr_offset_kernel_gs_base, 1);
586
587 #endif
588 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
589 load_transition_efer(vmx);
590 }
591
592 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
593 {
594 unsigned long flags;
595
596 if (!vmx->host_state.loaded)
597 return;
598
599 ++vmx->vcpu.stat.host_state_reload;
600 vmx->host_state.loaded = 0;
601 if (vmx->host_state.fs_reload_needed)
602 kvm_load_fs(vmx->host_state.fs_sel);
603 if (vmx->host_state.gs_ldt_reload_needed) {
604 kvm_load_ldt(vmx->host_state.ldt_sel);
605 /*
606 * If we have to reload gs, we must take care to
607 * preserve our gs base.
608 */
609 local_irq_save(flags);
610 kvm_load_gs(vmx->host_state.gs_sel);
611 #ifdef CONFIG_X86_64
612 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
613 #endif
614 local_irq_restore(flags);
615 }
616 reload_tss();
617 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
618 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
619 reload_host_efer(vmx);
620 }
621
622 static void vmx_load_host_state(struct vcpu_vmx *vmx)
623 {
624 preempt_disable();
625 __vmx_load_host_state(vmx);
626 preempt_enable();
627 }
628
629 /*
630 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
631 * vcpu mutex is already taken.
632 */
633 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
634 {
635 struct vcpu_vmx *vmx = to_vmx(vcpu);
636 u64 phys_addr = __pa(vmx->vmcs);
637 u64 tsc_this, delta, new_offset;
638
639 if (vcpu->cpu != cpu) {
640 vcpu_clear(vmx);
641 kvm_migrate_timers(vcpu);
642 vpid_sync_vcpu_all(vmx);
643 local_irq_disable();
644 list_add(&vmx->local_vcpus_link,
645 &per_cpu(vcpus_on_cpu, cpu));
646 local_irq_enable();
647 }
648
649 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
650 u8 error;
651
652 per_cpu(current_vmcs, cpu) = vmx->vmcs;
653 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
654 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
655 : "cc");
656 if (error)
657 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
658 vmx->vmcs, phys_addr);
659 }
660
661 if (vcpu->cpu != cpu) {
662 struct descriptor_table dt;
663 unsigned long sysenter_esp;
664
665 vcpu->cpu = cpu;
666 /*
667 * Linux uses per-cpu TSS and GDT, so set these when switching
668 * processors.
669 */
670 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
671 kvm_get_gdt(&dt);
672 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
673
674 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
675 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
676
677 /*
678 * Make sure the time stamp counter is monotonous.
679 */
680 rdtscll(tsc_this);
681 if (tsc_this < vcpu->arch.host_tsc) {
682 delta = vcpu->arch.host_tsc - tsc_this;
683 new_offset = vmcs_read64(TSC_OFFSET) + delta;
684 vmcs_write64(TSC_OFFSET, new_offset);
685 }
686 }
687 }
688
689 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
690 {
691 __vmx_load_host_state(to_vmx(vcpu));
692 }
693
694 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
695 {
696 if (vcpu->fpu_active)
697 return;
698 vcpu->fpu_active = 1;
699 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
700 if (vcpu->arch.cr0 & X86_CR0_TS)
701 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
702 update_exception_bitmap(vcpu);
703 }
704
705 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
706 {
707 if (!vcpu->fpu_active)
708 return;
709 vcpu->fpu_active = 0;
710 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
711 update_exception_bitmap(vcpu);
712 }
713
714 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
715 {
716 return vmcs_readl(GUEST_RFLAGS);
717 }
718
719 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
720 {
721 if (vcpu->arch.rmode.active)
722 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
723 vmcs_writel(GUEST_RFLAGS, rflags);
724 }
725
726 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
727 {
728 unsigned long rip;
729 u32 interruptibility;
730
731 rip = kvm_rip_read(vcpu);
732 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
733 kvm_rip_write(vcpu, rip);
734
735 /*
736 * We emulated an instruction, so temporary interrupt blocking
737 * should be removed, if set.
738 */
739 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
740 if (interruptibility & 3)
741 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
742 interruptibility & ~3);
743 vcpu->arch.interrupt_window_open = 1;
744 }
745
746 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
747 bool has_error_code, u32 error_code)
748 {
749 struct vcpu_vmx *vmx = to_vmx(vcpu);
750
751 if (has_error_code)
752 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
753
754 if (vcpu->arch.rmode.active) {
755 vmx->rmode.irq.pending = true;
756 vmx->rmode.irq.vector = nr;
757 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
758 if (nr == BP_VECTOR)
759 vmx->rmode.irq.rip++;
760 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
761 nr | INTR_TYPE_SOFT_INTR
762 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
763 | INTR_INFO_VALID_MASK);
764 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
765 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
766 return;
767 }
768
769 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
770 nr | INTR_TYPE_EXCEPTION
771 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
772 | INTR_INFO_VALID_MASK);
773 }
774
775 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
776 {
777 return false;
778 }
779
780 /*
781 * Swap MSR entry in host/guest MSR entry array.
782 */
783 #ifdef CONFIG_X86_64
784 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
785 {
786 struct kvm_msr_entry tmp;
787
788 tmp = vmx->guest_msrs[to];
789 vmx->guest_msrs[to] = vmx->guest_msrs[from];
790 vmx->guest_msrs[from] = tmp;
791 tmp = vmx->host_msrs[to];
792 vmx->host_msrs[to] = vmx->host_msrs[from];
793 vmx->host_msrs[from] = tmp;
794 }
795 #endif
796
797 /*
798 * Set up the vmcs to automatically save and restore system
799 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
800 * mode, as fiddling with msrs is very expensive.
801 */
802 static void setup_msrs(struct vcpu_vmx *vmx)
803 {
804 int save_nmsrs;
805
806 vmx_load_host_state(vmx);
807 save_nmsrs = 0;
808 #ifdef CONFIG_X86_64
809 if (is_long_mode(&vmx->vcpu)) {
810 int index;
811
812 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
813 if (index >= 0)
814 move_msr_up(vmx, index, save_nmsrs++);
815 index = __find_msr_index(vmx, MSR_LSTAR);
816 if (index >= 0)
817 move_msr_up(vmx, index, save_nmsrs++);
818 index = __find_msr_index(vmx, MSR_CSTAR);
819 if (index >= 0)
820 move_msr_up(vmx, index, save_nmsrs++);
821 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
822 if (index >= 0)
823 move_msr_up(vmx, index, save_nmsrs++);
824 /*
825 * MSR_K6_STAR is only needed on long mode guests, and only
826 * if efer.sce is enabled.
827 */
828 index = __find_msr_index(vmx, MSR_K6_STAR);
829 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
830 move_msr_up(vmx, index, save_nmsrs++);
831 }
832 #endif
833 vmx->save_nmsrs = save_nmsrs;
834
835 #ifdef CONFIG_X86_64
836 vmx->msr_offset_kernel_gs_base =
837 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
838 #endif
839 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
840 }
841
842 /*
843 * reads and returns guest's timestamp counter "register"
844 * guest_tsc = host_tsc + tsc_offset -- 21.3
845 */
846 static u64 guest_read_tsc(void)
847 {
848 u64 host_tsc, tsc_offset;
849
850 rdtscll(host_tsc);
851 tsc_offset = vmcs_read64(TSC_OFFSET);
852 return host_tsc + tsc_offset;
853 }
854
855 /*
856 * writes 'guest_tsc' into guest's timestamp counter "register"
857 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
858 */
859 static void guest_write_tsc(u64 guest_tsc)
860 {
861 u64 host_tsc;
862
863 rdtscll(host_tsc);
864 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
865 }
866
867 /*
868 * Reads an msr value (of 'msr_index') into 'pdata'.
869 * Returns 0 on success, non-0 otherwise.
870 * Assumes vcpu_load() was already called.
871 */
872 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
873 {
874 u64 data;
875 struct kvm_msr_entry *msr;
876
877 if (!pdata) {
878 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
879 return -EINVAL;
880 }
881
882 switch (msr_index) {
883 #ifdef CONFIG_X86_64
884 case MSR_FS_BASE:
885 data = vmcs_readl(GUEST_FS_BASE);
886 break;
887 case MSR_GS_BASE:
888 data = vmcs_readl(GUEST_GS_BASE);
889 break;
890 case MSR_EFER:
891 return kvm_get_msr_common(vcpu, msr_index, pdata);
892 #endif
893 case MSR_IA32_TIME_STAMP_COUNTER:
894 data = guest_read_tsc();
895 break;
896 case MSR_IA32_SYSENTER_CS:
897 data = vmcs_read32(GUEST_SYSENTER_CS);
898 break;
899 case MSR_IA32_SYSENTER_EIP:
900 data = vmcs_readl(GUEST_SYSENTER_EIP);
901 break;
902 case MSR_IA32_SYSENTER_ESP:
903 data = vmcs_readl(GUEST_SYSENTER_ESP);
904 break;
905 default:
906 msr = find_msr_entry(to_vmx(vcpu), msr_index);
907 if (msr) {
908 data = msr->data;
909 break;
910 }
911 return kvm_get_msr_common(vcpu, msr_index, pdata);
912 }
913
914 *pdata = data;
915 return 0;
916 }
917
918 /*
919 * Writes msr value into into the appropriate "register".
920 * Returns 0 on success, non-0 otherwise.
921 * Assumes vcpu_load() was already called.
922 */
923 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
924 {
925 struct vcpu_vmx *vmx = to_vmx(vcpu);
926 struct kvm_msr_entry *msr;
927 int ret = 0;
928
929 switch (msr_index) {
930 #ifdef CONFIG_X86_64
931 case MSR_EFER:
932 vmx_load_host_state(vmx);
933 ret = kvm_set_msr_common(vcpu, msr_index, data);
934 break;
935 case MSR_FS_BASE:
936 vmcs_writel(GUEST_FS_BASE, data);
937 break;
938 case MSR_GS_BASE:
939 vmcs_writel(GUEST_GS_BASE, data);
940 break;
941 #endif
942 case MSR_IA32_SYSENTER_CS:
943 vmcs_write32(GUEST_SYSENTER_CS, data);
944 break;
945 case MSR_IA32_SYSENTER_EIP:
946 vmcs_writel(GUEST_SYSENTER_EIP, data);
947 break;
948 case MSR_IA32_SYSENTER_ESP:
949 vmcs_writel(GUEST_SYSENTER_ESP, data);
950 break;
951 case MSR_IA32_TIME_STAMP_COUNTER:
952 guest_write_tsc(data);
953 break;
954 case MSR_P6_PERFCTR0:
955 case MSR_P6_PERFCTR1:
956 case MSR_P6_EVNTSEL0:
957 case MSR_P6_EVNTSEL1:
958 /*
959 * Just discard all writes to the performance counters; this
960 * should keep both older linux and windows 64-bit guests
961 * happy
962 */
963 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
964
965 break;
966 case MSR_IA32_CR_PAT:
967 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
968 vmcs_write64(GUEST_IA32_PAT, data);
969 vcpu->arch.pat = data;
970 break;
971 }
972 /* Otherwise falls through to kvm_set_msr_common */
973 default:
974 vmx_load_host_state(vmx);
975 msr = find_msr_entry(vmx, msr_index);
976 if (msr) {
977 msr->data = data;
978 break;
979 }
980 ret = kvm_set_msr_common(vcpu, msr_index, data);
981 }
982
983 return ret;
984 }
985
986 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
987 {
988 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
989 switch (reg) {
990 case VCPU_REGS_RSP:
991 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
992 break;
993 case VCPU_REGS_RIP:
994 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
995 break;
996 default:
997 break;
998 }
999 }
1000
1001 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
1002 {
1003 unsigned long dr7 = 0x400;
1004 int old_singlestep;
1005
1006 old_singlestep = vcpu->guest_debug.singlestep;
1007
1008 vcpu->guest_debug.enabled = dbg->enabled;
1009 if (vcpu->guest_debug.enabled) {
1010 int i;
1011
1012 dr7 |= 0x200; /* exact */
1013 for (i = 0; i < 4; ++i) {
1014 if (!dbg->breakpoints[i].enabled)
1015 continue;
1016 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
1017 dr7 |= 2 << (i*2); /* global enable */
1018 dr7 |= 0 << (i*4+16); /* execution breakpoint */
1019 }
1020
1021 vcpu->guest_debug.singlestep = dbg->singlestep;
1022 } else
1023 vcpu->guest_debug.singlestep = 0;
1024
1025 if (old_singlestep && !vcpu->guest_debug.singlestep) {
1026 unsigned long flags;
1027
1028 flags = vmcs_readl(GUEST_RFLAGS);
1029 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1030 vmcs_writel(GUEST_RFLAGS, flags);
1031 }
1032
1033 update_exception_bitmap(vcpu);
1034 vmcs_writel(GUEST_DR7, dr7);
1035
1036 return 0;
1037 }
1038
1039 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1040 {
1041 if (!vcpu->arch.interrupt.pending)
1042 return -1;
1043 return vcpu->arch.interrupt.nr;
1044 }
1045
1046 static __init int cpu_has_kvm_support(void)
1047 {
1048 return cpu_has_vmx();
1049 }
1050
1051 static __init int vmx_disabled_by_bios(void)
1052 {
1053 u64 msr;
1054
1055 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1056 return (msr & (FEATURE_CONTROL_LOCKED |
1057 FEATURE_CONTROL_VMXON_ENABLED))
1058 == FEATURE_CONTROL_LOCKED;
1059 /* locked but not enabled */
1060 }
1061
1062 static void hardware_enable(void *garbage)
1063 {
1064 int cpu = raw_smp_processor_id();
1065 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1066 u64 old;
1067
1068 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1069 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1070 if ((old & (FEATURE_CONTROL_LOCKED |
1071 FEATURE_CONTROL_VMXON_ENABLED))
1072 != (FEATURE_CONTROL_LOCKED |
1073 FEATURE_CONTROL_VMXON_ENABLED))
1074 /* enable and lock */
1075 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1076 FEATURE_CONTROL_LOCKED |
1077 FEATURE_CONTROL_VMXON_ENABLED);
1078 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1079 asm volatile (ASM_VMX_VMXON_RAX
1080 : : "a"(&phys_addr), "m"(phys_addr)
1081 : "memory", "cc");
1082 }
1083
1084 static void vmclear_local_vcpus(void)
1085 {
1086 int cpu = raw_smp_processor_id();
1087 struct vcpu_vmx *vmx, *n;
1088
1089 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1090 local_vcpus_link)
1091 __vcpu_clear(vmx);
1092 }
1093
1094
1095 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1096 * tricks.
1097 */
1098 static void kvm_cpu_vmxoff(void)
1099 {
1100 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1101 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1102 }
1103
1104 static void hardware_disable(void *garbage)
1105 {
1106 vmclear_local_vcpus();
1107 kvm_cpu_vmxoff();
1108 }
1109
1110 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1111 u32 msr, u32 *result)
1112 {
1113 u32 vmx_msr_low, vmx_msr_high;
1114 u32 ctl = ctl_min | ctl_opt;
1115
1116 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1117
1118 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1119 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1120
1121 /* Ensure minimum (required) set of control bits are supported. */
1122 if (ctl_min & ~ctl)
1123 return -EIO;
1124
1125 *result = ctl;
1126 return 0;
1127 }
1128
1129 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1130 {
1131 u32 vmx_msr_low, vmx_msr_high;
1132 u32 min, opt, min2, opt2;
1133 u32 _pin_based_exec_control = 0;
1134 u32 _cpu_based_exec_control = 0;
1135 u32 _cpu_based_2nd_exec_control = 0;
1136 u32 _vmexit_control = 0;
1137 u32 _vmentry_control = 0;
1138
1139 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1140 opt = PIN_BASED_VIRTUAL_NMIS;
1141 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1142 &_pin_based_exec_control) < 0)
1143 return -EIO;
1144
1145 min = CPU_BASED_HLT_EXITING |
1146 #ifdef CONFIG_X86_64
1147 CPU_BASED_CR8_LOAD_EXITING |
1148 CPU_BASED_CR8_STORE_EXITING |
1149 #endif
1150 CPU_BASED_CR3_LOAD_EXITING |
1151 CPU_BASED_CR3_STORE_EXITING |
1152 CPU_BASED_USE_IO_BITMAPS |
1153 CPU_BASED_MOV_DR_EXITING |
1154 CPU_BASED_USE_TSC_OFFSETING |
1155 CPU_BASED_INVLPG_EXITING;
1156 opt = CPU_BASED_TPR_SHADOW |
1157 CPU_BASED_USE_MSR_BITMAPS |
1158 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1159 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1160 &_cpu_based_exec_control) < 0)
1161 return -EIO;
1162 #ifdef CONFIG_X86_64
1163 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1164 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1165 ~CPU_BASED_CR8_STORE_EXITING;
1166 #endif
1167 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1168 min2 = 0;
1169 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1170 SECONDARY_EXEC_WBINVD_EXITING |
1171 SECONDARY_EXEC_ENABLE_VPID |
1172 SECONDARY_EXEC_ENABLE_EPT;
1173 if (adjust_vmx_controls(min2, opt2,
1174 MSR_IA32_VMX_PROCBASED_CTLS2,
1175 &_cpu_based_2nd_exec_control) < 0)
1176 return -EIO;
1177 }
1178 #ifndef CONFIG_X86_64
1179 if (!(_cpu_based_2nd_exec_control &
1180 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1181 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1182 #endif
1183 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1184 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1185 enabled */
1186 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1187 CPU_BASED_CR3_STORE_EXITING |
1188 CPU_BASED_INVLPG_EXITING);
1189 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1190 &_cpu_based_exec_control) < 0)
1191 return -EIO;
1192 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1193 vmx_capability.ept, vmx_capability.vpid);
1194 }
1195
1196 min = 0;
1197 #ifdef CONFIG_X86_64
1198 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1199 #endif
1200 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1201 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1202 &_vmexit_control) < 0)
1203 return -EIO;
1204
1205 min = 0;
1206 opt = VM_ENTRY_LOAD_IA32_PAT;
1207 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1208 &_vmentry_control) < 0)
1209 return -EIO;
1210
1211 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1212
1213 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1214 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1215 return -EIO;
1216
1217 #ifdef CONFIG_X86_64
1218 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1219 if (vmx_msr_high & (1u<<16))
1220 return -EIO;
1221 #endif
1222
1223 /* Require Write-Back (WB) memory type for VMCS accesses. */
1224 if (((vmx_msr_high >> 18) & 15) != 6)
1225 return -EIO;
1226
1227 vmcs_conf->size = vmx_msr_high & 0x1fff;
1228 vmcs_conf->order = get_order(vmcs_config.size);
1229 vmcs_conf->revision_id = vmx_msr_low;
1230
1231 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1232 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1233 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1234 vmcs_conf->vmexit_ctrl = _vmexit_control;
1235 vmcs_conf->vmentry_ctrl = _vmentry_control;
1236
1237 return 0;
1238 }
1239
1240 static struct vmcs *alloc_vmcs_cpu(int cpu)
1241 {
1242 int node = cpu_to_node(cpu);
1243 struct page *pages;
1244 struct vmcs *vmcs;
1245
1246 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1247 if (!pages)
1248 return NULL;
1249 vmcs = page_address(pages);
1250 memset(vmcs, 0, vmcs_config.size);
1251 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1252 return vmcs;
1253 }
1254
1255 static struct vmcs *alloc_vmcs(void)
1256 {
1257 return alloc_vmcs_cpu(raw_smp_processor_id());
1258 }
1259
1260 static void free_vmcs(struct vmcs *vmcs)
1261 {
1262 free_pages((unsigned long)vmcs, vmcs_config.order);
1263 }
1264
1265 static void free_kvm_area(void)
1266 {
1267 int cpu;
1268
1269 for_each_online_cpu(cpu)
1270 free_vmcs(per_cpu(vmxarea, cpu));
1271 }
1272
1273 static __init int alloc_kvm_area(void)
1274 {
1275 int cpu;
1276
1277 for_each_online_cpu(cpu) {
1278 struct vmcs *vmcs;
1279
1280 vmcs = alloc_vmcs_cpu(cpu);
1281 if (!vmcs) {
1282 free_kvm_area();
1283 return -ENOMEM;
1284 }
1285
1286 per_cpu(vmxarea, cpu) = vmcs;
1287 }
1288 return 0;
1289 }
1290
1291 static __init int hardware_setup(void)
1292 {
1293 if (setup_vmcs_config(&vmcs_config) < 0)
1294 return -EIO;
1295
1296 if (boot_cpu_has(X86_FEATURE_NX))
1297 kvm_enable_efer_bits(EFER_NX);
1298
1299 return alloc_kvm_area();
1300 }
1301
1302 static __exit void hardware_unsetup(void)
1303 {
1304 free_kvm_area();
1305 }
1306
1307 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1308 {
1309 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1310
1311 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1312 vmcs_write16(sf->selector, save->selector);
1313 vmcs_writel(sf->base, save->base);
1314 vmcs_write32(sf->limit, save->limit);
1315 vmcs_write32(sf->ar_bytes, save->ar);
1316 } else {
1317 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1318 << AR_DPL_SHIFT;
1319 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1320 }
1321 }
1322
1323 static void enter_pmode(struct kvm_vcpu *vcpu)
1324 {
1325 unsigned long flags;
1326 struct vcpu_vmx *vmx = to_vmx(vcpu);
1327
1328 vmx->emulation_required = 1;
1329 vcpu->arch.rmode.active = 0;
1330
1331 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1332 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1333 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1334
1335 flags = vmcs_readl(GUEST_RFLAGS);
1336 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1337 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1338 vmcs_writel(GUEST_RFLAGS, flags);
1339
1340 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1341 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1342
1343 update_exception_bitmap(vcpu);
1344
1345 if (emulate_invalid_guest_state)
1346 return;
1347
1348 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1349 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1350 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1351 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1352
1353 vmcs_write16(GUEST_SS_SELECTOR, 0);
1354 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1355
1356 vmcs_write16(GUEST_CS_SELECTOR,
1357 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1358 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1359 }
1360
1361 static gva_t rmode_tss_base(struct kvm *kvm)
1362 {
1363 if (!kvm->arch.tss_addr) {
1364 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1365 kvm->memslots[0].npages - 3;
1366 return base_gfn << PAGE_SHIFT;
1367 }
1368 return kvm->arch.tss_addr;
1369 }
1370
1371 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1372 {
1373 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1374
1375 save->selector = vmcs_read16(sf->selector);
1376 save->base = vmcs_readl(sf->base);
1377 save->limit = vmcs_read32(sf->limit);
1378 save->ar = vmcs_read32(sf->ar_bytes);
1379 vmcs_write16(sf->selector, save->base >> 4);
1380 vmcs_write32(sf->base, save->base & 0xfffff);
1381 vmcs_write32(sf->limit, 0xffff);
1382 vmcs_write32(sf->ar_bytes, 0xf3);
1383 }
1384
1385 static void enter_rmode(struct kvm_vcpu *vcpu)
1386 {
1387 unsigned long flags;
1388 struct vcpu_vmx *vmx = to_vmx(vcpu);
1389
1390 vmx->emulation_required = 1;
1391 vcpu->arch.rmode.active = 1;
1392
1393 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1394 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1395
1396 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1397 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1398
1399 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1400 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1401
1402 flags = vmcs_readl(GUEST_RFLAGS);
1403 vcpu->arch.rmode.save_iopl
1404 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1405
1406 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1407
1408 vmcs_writel(GUEST_RFLAGS, flags);
1409 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1410 update_exception_bitmap(vcpu);
1411
1412 if (emulate_invalid_guest_state)
1413 goto continue_rmode;
1414
1415 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1416 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1417 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1418
1419 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1420 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1421 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1422 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1423 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1424
1425 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1426 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1427 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1428 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1429
1430 continue_rmode:
1431 kvm_mmu_reset_context(vcpu);
1432 init_rmode(vcpu->kvm);
1433 }
1434
1435 #ifdef CONFIG_X86_64
1436
1437 static void enter_lmode(struct kvm_vcpu *vcpu)
1438 {
1439 u32 guest_tr_ar;
1440
1441 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1442 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1443 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1444 __func__);
1445 vmcs_write32(GUEST_TR_AR_BYTES,
1446 (guest_tr_ar & ~AR_TYPE_MASK)
1447 | AR_TYPE_BUSY_64_TSS);
1448 }
1449
1450 vcpu->arch.shadow_efer |= EFER_LMA;
1451
1452 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1453 vmcs_write32(VM_ENTRY_CONTROLS,
1454 vmcs_read32(VM_ENTRY_CONTROLS)
1455 | VM_ENTRY_IA32E_MODE);
1456 }
1457
1458 static void exit_lmode(struct kvm_vcpu *vcpu)
1459 {
1460 vcpu->arch.shadow_efer &= ~EFER_LMA;
1461
1462 vmcs_write32(VM_ENTRY_CONTROLS,
1463 vmcs_read32(VM_ENTRY_CONTROLS)
1464 & ~VM_ENTRY_IA32E_MODE);
1465 }
1466
1467 #endif
1468
1469 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1470 {
1471 vpid_sync_vcpu_all(to_vmx(vcpu));
1472 if (vm_need_ept())
1473 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1474 }
1475
1476 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1477 {
1478 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1479 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1480 }
1481
1482 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1483 {
1484 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1485 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1486 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1487 return;
1488 }
1489 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1490 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1491 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1492 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1493 }
1494 }
1495
1496 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1497
1498 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1499 unsigned long cr0,
1500 struct kvm_vcpu *vcpu)
1501 {
1502 if (!(cr0 & X86_CR0_PG)) {
1503 /* From paging/starting to nonpaging */
1504 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1505 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1506 (CPU_BASED_CR3_LOAD_EXITING |
1507 CPU_BASED_CR3_STORE_EXITING));
1508 vcpu->arch.cr0 = cr0;
1509 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1510 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1511 *hw_cr0 &= ~X86_CR0_WP;
1512 } else if (!is_paging(vcpu)) {
1513 /* From nonpaging to paging */
1514 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1515 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1516 ~(CPU_BASED_CR3_LOAD_EXITING |
1517 CPU_BASED_CR3_STORE_EXITING));
1518 vcpu->arch.cr0 = cr0;
1519 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1520 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1521 *hw_cr0 &= ~X86_CR0_WP;
1522 }
1523 }
1524
1525 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1526 struct kvm_vcpu *vcpu)
1527 {
1528 if (!is_paging(vcpu)) {
1529 *hw_cr4 &= ~X86_CR4_PAE;
1530 *hw_cr4 |= X86_CR4_PSE;
1531 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1532 *hw_cr4 &= ~X86_CR4_PAE;
1533 }
1534
1535 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1536 {
1537 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1538 KVM_VM_CR0_ALWAYS_ON;
1539
1540 vmx_fpu_deactivate(vcpu);
1541
1542 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1543 enter_pmode(vcpu);
1544
1545 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1546 enter_rmode(vcpu);
1547
1548 #ifdef CONFIG_X86_64
1549 if (vcpu->arch.shadow_efer & EFER_LME) {
1550 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1551 enter_lmode(vcpu);
1552 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1553 exit_lmode(vcpu);
1554 }
1555 #endif
1556
1557 if (vm_need_ept())
1558 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1559
1560 vmcs_writel(CR0_READ_SHADOW, cr0);
1561 vmcs_writel(GUEST_CR0, hw_cr0);
1562 vcpu->arch.cr0 = cr0;
1563
1564 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1565 vmx_fpu_activate(vcpu);
1566 }
1567
1568 static u64 construct_eptp(unsigned long root_hpa)
1569 {
1570 u64 eptp;
1571
1572 /* TODO write the value reading from MSR */
1573 eptp = VMX_EPT_DEFAULT_MT |
1574 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1575 eptp |= (root_hpa & PAGE_MASK);
1576
1577 return eptp;
1578 }
1579
1580 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1581 {
1582 unsigned long guest_cr3;
1583 u64 eptp;
1584
1585 guest_cr3 = cr3;
1586 if (vm_need_ept()) {
1587 eptp = construct_eptp(cr3);
1588 vmcs_write64(EPT_POINTER, eptp);
1589 ept_sync_context(eptp);
1590 ept_load_pdptrs(vcpu);
1591 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1592 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1593 }
1594
1595 vmx_flush_tlb(vcpu);
1596 vmcs_writel(GUEST_CR3, guest_cr3);
1597 if (vcpu->arch.cr0 & X86_CR0_PE)
1598 vmx_fpu_deactivate(vcpu);
1599 }
1600
1601 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1602 {
1603 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1604 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1605
1606 vcpu->arch.cr4 = cr4;
1607 if (vm_need_ept())
1608 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1609
1610 vmcs_writel(CR4_READ_SHADOW, cr4);
1611 vmcs_writel(GUEST_CR4, hw_cr4);
1612 }
1613
1614 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1615 {
1616 struct vcpu_vmx *vmx = to_vmx(vcpu);
1617 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1618
1619 vcpu->arch.shadow_efer = efer;
1620 if (!msr)
1621 return;
1622 if (efer & EFER_LMA) {
1623 vmcs_write32(VM_ENTRY_CONTROLS,
1624 vmcs_read32(VM_ENTRY_CONTROLS) |
1625 VM_ENTRY_IA32E_MODE);
1626 msr->data = efer;
1627
1628 } else {
1629 vmcs_write32(VM_ENTRY_CONTROLS,
1630 vmcs_read32(VM_ENTRY_CONTROLS) &
1631 ~VM_ENTRY_IA32E_MODE);
1632
1633 msr->data = efer & ~EFER_LME;
1634 }
1635 setup_msrs(vmx);
1636 }
1637
1638 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1639 {
1640 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1641
1642 return vmcs_readl(sf->base);
1643 }
1644
1645 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1646 struct kvm_segment *var, int seg)
1647 {
1648 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1649 u32 ar;
1650
1651 var->base = vmcs_readl(sf->base);
1652 var->limit = vmcs_read32(sf->limit);
1653 var->selector = vmcs_read16(sf->selector);
1654 ar = vmcs_read32(sf->ar_bytes);
1655 if (ar & AR_UNUSABLE_MASK)
1656 ar = 0;
1657 var->type = ar & 15;
1658 var->s = (ar >> 4) & 1;
1659 var->dpl = (ar >> 5) & 3;
1660 var->present = (ar >> 7) & 1;
1661 var->avl = (ar >> 12) & 1;
1662 var->l = (ar >> 13) & 1;
1663 var->db = (ar >> 14) & 1;
1664 var->g = (ar >> 15) & 1;
1665 var->unusable = (ar >> 16) & 1;
1666 }
1667
1668 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1669 {
1670 struct kvm_segment kvm_seg;
1671
1672 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1673 return 0;
1674
1675 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1676 return 3;
1677
1678 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1679 return kvm_seg.selector & 3;
1680 }
1681
1682 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1683 {
1684 u32 ar;
1685
1686 if (var->unusable)
1687 ar = 1 << 16;
1688 else {
1689 ar = var->type & 15;
1690 ar |= (var->s & 1) << 4;
1691 ar |= (var->dpl & 3) << 5;
1692 ar |= (var->present & 1) << 7;
1693 ar |= (var->avl & 1) << 12;
1694 ar |= (var->l & 1) << 13;
1695 ar |= (var->db & 1) << 14;
1696 ar |= (var->g & 1) << 15;
1697 }
1698 if (ar == 0) /* a 0 value means unusable */
1699 ar = AR_UNUSABLE_MASK;
1700
1701 return ar;
1702 }
1703
1704 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1705 struct kvm_segment *var, int seg)
1706 {
1707 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1708 u32 ar;
1709
1710 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1711 vcpu->arch.rmode.tr.selector = var->selector;
1712 vcpu->arch.rmode.tr.base = var->base;
1713 vcpu->arch.rmode.tr.limit = var->limit;
1714 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1715 return;
1716 }
1717 vmcs_writel(sf->base, var->base);
1718 vmcs_write32(sf->limit, var->limit);
1719 vmcs_write16(sf->selector, var->selector);
1720 if (vcpu->arch.rmode.active && var->s) {
1721 /*
1722 * Hack real-mode segments into vm86 compatibility.
1723 */
1724 if (var->base == 0xffff0000 && var->selector == 0xf000)
1725 vmcs_writel(sf->base, 0xf0000);
1726 ar = 0xf3;
1727 } else
1728 ar = vmx_segment_access_rights(var);
1729 vmcs_write32(sf->ar_bytes, ar);
1730 }
1731
1732 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1733 {
1734 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1735
1736 *db = (ar >> 14) & 1;
1737 *l = (ar >> 13) & 1;
1738 }
1739
1740 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1741 {
1742 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1743 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1744 }
1745
1746 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1747 {
1748 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1749 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1750 }
1751
1752 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1753 {
1754 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1755 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1756 }
1757
1758 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1759 {
1760 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1761 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1762 }
1763
1764 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1765 {
1766 struct kvm_segment var;
1767 u32 ar;
1768
1769 vmx_get_segment(vcpu, &var, seg);
1770 ar = vmx_segment_access_rights(&var);
1771
1772 if (var.base != (var.selector << 4))
1773 return false;
1774 if (var.limit != 0xffff)
1775 return false;
1776 if (ar != 0xf3)
1777 return false;
1778
1779 return true;
1780 }
1781
1782 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1783 {
1784 struct kvm_segment cs;
1785 unsigned int cs_rpl;
1786
1787 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1788 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1789
1790 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1791 return false;
1792 if (!cs.s)
1793 return false;
1794 if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1795 if (cs.dpl > cs_rpl)
1796 return false;
1797 } else if (cs.type & AR_TYPE_CODE_MASK) {
1798 if (cs.dpl != cs_rpl)
1799 return false;
1800 }
1801 if (!cs.present)
1802 return false;
1803
1804 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1805 return true;
1806 }
1807
1808 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1809 {
1810 struct kvm_segment ss;
1811 unsigned int ss_rpl;
1812
1813 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1814 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1815
1816 if ((ss.type != 3) || (ss.type != 7))
1817 return false;
1818 if (!ss.s)
1819 return false;
1820 if (ss.dpl != ss_rpl) /* DPL != RPL */
1821 return false;
1822 if (!ss.present)
1823 return false;
1824
1825 return true;
1826 }
1827
1828 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1829 {
1830 struct kvm_segment var;
1831 unsigned int rpl;
1832
1833 vmx_get_segment(vcpu, &var, seg);
1834 rpl = var.selector & SELECTOR_RPL_MASK;
1835
1836 if (!var.s)
1837 return false;
1838 if (!var.present)
1839 return false;
1840 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1841 if (var.dpl < rpl) /* DPL < RPL */
1842 return false;
1843 }
1844
1845 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1846 * rights flags
1847 */
1848 return true;
1849 }
1850
1851 static bool tr_valid(struct kvm_vcpu *vcpu)
1852 {
1853 struct kvm_segment tr;
1854
1855 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1856
1857 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1858 return false;
1859 if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1860 return false;
1861 if (!tr.present)
1862 return false;
1863
1864 return true;
1865 }
1866
1867 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1868 {
1869 struct kvm_segment ldtr;
1870
1871 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1872
1873 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1874 return false;
1875 if (ldtr.type != 2)
1876 return false;
1877 if (!ldtr.present)
1878 return false;
1879
1880 return true;
1881 }
1882
1883 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1884 {
1885 struct kvm_segment cs, ss;
1886
1887 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1888 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1889
1890 return ((cs.selector & SELECTOR_RPL_MASK) ==
1891 (ss.selector & SELECTOR_RPL_MASK));
1892 }
1893
1894 /*
1895 * Check if guest state is valid. Returns true if valid, false if
1896 * not.
1897 * We assume that registers are always usable
1898 */
1899 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1900 {
1901 /* real mode guest state checks */
1902 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1903 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1904 return false;
1905 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1906 return false;
1907 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1908 return false;
1909 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1910 return false;
1911 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1912 return false;
1913 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1914 return false;
1915 } else {
1916 /* protected mode guest state checks */
1917 if (!cs_ss_rpl_check(vcpu))
1918 return false;
1919 if (!code_segment_valid(vcpu))
1920 return false;
1921 if (!stack_segment_valid(vcpu))
1922 return false;
1923 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1924 return false;
1925 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1926 return false;
1927 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1928 return false;
1929 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1930 return false;
1931 if (!tr_valid(vcpu))
1932 return false;
1933 if (!ldtr_valid(vcpu))
1934 return false;
1935 }
1936 /* TODO:
1937 * - Add checks on RIP
1938 * - Add checks on RFLAGS
1939 */
1940
1941 return true;
1942 }
1943
1944 static int init_rmode_tss(struct kvm *kvm)
1945 {
1946 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1947 u16 data = 0;
1948 int ret = 0;
1949 int r;
1950
1951 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1952 if (r < 0)
1953 goto out;
1954 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1955 r = kvm_write_guest_page(kvm, fn++, &data,
1956 TSS_IOPB_BASE_OFFSET, sizeof(u16));
1957 if (r < 0)
1958 goto out;
1959 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1960 if (r < 0)
1961 goto out;
1962 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1963 if (r < 0)
1964 goto out;
1965 data = ~0;
1966 r = kvm_write_guest_page(kvm, fn, &data,
1967 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1968 sizeof(u8));
1969 if (r < 0)
1970 goto out;
1971
1972 ret = 1;
1973 out:
1974 return ret;
1975 }
1976
1977 static int init_rmode_identity_map(struct kvm *kvm)
1978 {
1979 int i, r, ret;
1980 pfn_t identity_map_pfn;
1981 u32 tmp;
1982
1983 if (!vm_need_ept())
1984 return 1;
1985 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1986 printk(KERN_ERR "EPT: identity-mapping pagetable "
1987 "haven't been allocated!\n");
1988 return 0;
1989 }
1990 if (likely(kvm->arch.ept_identity_pagetable_done))
1991 return 1;
1992 ret = 0;
1993 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1994 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1995 if (r < 0)
1996 goto out;
1997 /* Set up identity-mapping pagetable for EPT in real mode */
1998 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1999 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2000 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2001 r = kvm_write_guest_page(kvm, identity_map_pfn,
2002 &tmp, i * sizeof(tmp), sizeof(tmp));
2003 if (r < 0)
2004 goto out;
2005 }
2006 kvm->arch.ept_identity_pagetable_done = true;
2007 ret = 1;
2008 out:
2009 return ret;
2010 }
2011
2012 static void seg_setup(int seg)
2013 {
2014 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2015
2016 vmcs_write16(sf->selector, 0);
2017 vmcs_writel(sf->base, 0);
2018 vmcs_write32(sf->limit, 0xffff);
2019 vmcs_write32(sf->ar_bytes, 0xf3);
2020 }
2021
2022 static int alloc_apic_access_page(struct kvm *kvm)
2023 {
2024 struct kvm_userspace_memory_region kvm_userspace_mem;
2025 int r = 0;
2026
2027 down_write(&kvm->slots_lock);
2028 if (kvm->arch.apic_access_page)
2029 goto out;
2030 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2031 kvm_userspace_mem.flags = 0;
2032 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2033 kvm_userspace_mem.memory_size = PAGE_SIZE;
2034 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2035 if (r)
2036 goto out;
2037
2038 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2039 out:
2040 up_write(&kvm->slots_lock);
2041 return r;
2042 }
2043
2044 static int alloc_identity_pagetable(struct kvm *kvm)
2045 {
2046 struct kvm_userspace_memory_region kvm_userspace_mem;
2047 int r = 0;
2048
2049 down_write(&kvm->slots_lock);
2050 if (kvm->arch.ept_identity_pagetable)
2051 goto out;
2052 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2053 kvm_userspace_mem.flags = 0;
2054 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2055 kvm_userspace_mem.memory_size = PAGE_SIZE;
2056 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2057 if (r)
2058 goto out;
2059
2060 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2061 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2062 out:
2063 up_write(&kvm->slots_lock);
2064 return r;
2065 }
2066
2067 static void allocate_vpid(struct vcpu_vmx *vmx)
2068 {
2069 int vpid;
2070
2071 vmx->vpid = 0;
2072 if (!enable_vpid || !cpu_has_vmx_vpid())
2073 return;
2074 spin_lock(&vmx_vpid_lock);
2075 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2076 if (vpid < VMX_NR_VPIDS) {
2077 vmx->vpid = vpid;
2078 __set_bit(vpid, vmx_vpid_bitmap);
2079 }
2080 spin_unlock(&vmx_vpid_lock);
2081 }
2082
2083 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2084 {
2085 void *va;
2086
2087 if (!cpu_has_vmx_msr_bitmap())
2088 return;
2089
2090 /*
2091 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2092 * have the write-low and read-high bitmap offsets the wrong way round.
2093 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2094 */
2095 va = kmap(msr_bitmap);
2096 if (msr <= 0x1fff) {
2097 __clear_bit(msr, va + 0x000); /* read-low */
2098 __clear_bit(msr, va + 0x800); /* write-low */
2099 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2100 msr &= 0x1fff;
2101 __clear_bit(msr, va + 0x400); /* read-high */
2102 __clear_bit(msr, va + 0xc00); /* write-high */
2103 }
2104 kunmap(msr_bitmap);
2105 }
2106
2107 /*
2108 * Sets up the vmcs for emulated real mode.
2109 */
2110 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2111 {
2112 u32 host_sysenter_cs, msr_low, msr_high;
2113 u32 junk;
2114 u64 host_pat;
2115 unsigned long a;
2116 struct descriptor_table dt;
2117 int i;
2118 unsigned long kvm_vmx_return;
2119 u32 exec_control;
2120
2121 /* I/O */
2122 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2123 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2124
2125 if (cpu_has_vmx_msr_bitmap())
2126 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2127
2128 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2129
2130 /* Control */
2131 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2132 vmcs_config.pin_based_exec_ctrl);
2133
2134 exec_control = vmcs_config.cpu_based_exec_ctrl;
2135 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2136 exec_control &= ~CPU_BASED_TPR_SHADOW;
2137 #ifdef CONFIG_X86_64
2138 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2139 CPU_BASED_CR8_LOAD_EXITING;
2140 #endif
2141 }
2142 if (!vm_need_ept())
2143 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2144 CPU_BASED_CR3_LOAD_EXITING |
2145 CPU_BASED_INVLPG_EXITING;
2146 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2147
2148 if (cpu_has_secondary_exec_ctrls()) {
2149 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2150 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2151 exec_control &=
2152 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2153 if (vmx->vpid == 0)
2154 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2155 if (!vm_need_ept())
2156 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2157 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2158 }
2159
2160 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2161 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2162 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2163
2164 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2165 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2166 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2167
2168 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2169 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2170 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2171 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2172 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2173 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2174 #ifdef CONFIG_X86_64
2175 rdmsrl(MSR_FS_BASE, a);
2176 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2177 rdmsrl(MSR_GS_BASE, a);
2178 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2179 #else
2180 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2181 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2182 #endif
2183
2184 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2185
2186 kvm_get_idt(&dt);
2187 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2188
2189 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2190 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2191 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2192 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2193 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2194
2195 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2196 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2197 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2198 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2199 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2200 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2201
2202 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2203 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2204 host_pat = msr_low | ((u64) msr_high << 32);
2205 vmcs_write64(HOST_IA32_PAT, host_pat);
2206 }
2207 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2208 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2209 host_pat = msr_low | ((u64) msr_high << 32);
2210 /* Write the default value follow host pat */
2211 vmcs_write64(GUEST_IA32_PAT, host_pat);
2212 /* Keep arch.pat sync with GUEST_IA32_PAT */
2213 vmx->vcpu.arch.pat = host_pat;
2214 }
2215
2216 for (i = 0; i < NR_VMX_MSR; ++i) {
2217 u32 index = vmx_msr_index[i];
2218 u32 data_low, data_high;
2219 u64 data;
2220 int j = vmx->nmsrs;
2221
2222 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2223 continue;
2224 if (wrmsr_safe(index, data_low, data_high) < 0)
2225 continue;
2226 data = data_low | ((u64)data_high << 32);
2227 vmx->host_msrs[j].index = index;
2228 vmx->host_msrs[j].reserved = 0;
2229 vmx->host_msrs[j].data = data;
2230 vmx->guest_msrs[j] = vmx->host_msrs[j];
2231 ++vmx->nmsrs;
2232 }
2233
2234 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2235
2236 /* 22.2.1, 20.8.1 */
2237 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2238
2239 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2240 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2241
2242
2243 return 0;
2244 }
2245
2246 static int init_rmode(struct kvm *kvm)
2247 {
2248 if (!init_rmode_tss(kvm))
2249 return 0;
2250 if (!init_rmode_identity_map(kvm))
2251 return 0;
2252 return 1;
2253 }
2254
2255 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2256 {
2257 struct vcpu_vmx *vmx = to_vmx(vcpu);
2258 u64 msr;
2259 int ret;
2260
2261 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2262 down_read(&vcpu->kvm->slots_lock);
2263 if (!init_rmode(vmx->vcpu.kvm)) {
2264 ret = -ENOMEM;
2265 goto out;
2266 }
2267
2268 vmx->vcpu.arch.rmode.active = 0;
2269
2270 vmx->soft_vnmi_blocked = 0;
2271
2272 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2273 kvm_set_cr8(&vmx->vcpu, 0);
2274 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2275 if (vmx->vcpu.vcpu_id == 0)
2276 msr |= MSR_IA32_APICBASE_BSP;
2277 kvm_set_apic_base(&vmx->vcpu, msr);
2278
2279 fx_init(&vmx->vcpu);
2280
2281 seg_setup(VCPU_SREG_CS);
2282 /*
2283 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2284 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2285 */
2286 if (vmx->vcpu.vcpu_id == 0) {
2287 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2288 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2289 } else {
2290 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2291 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2292 }
2293
2294 seg_setup(VCPU_SREG_DS);
2295 seg_setup(VCPU_SREG_ES);
2296 seg_setup(VCPU_SREG_FS);
2297 seg_setup(VCPU_SREG_GS);
2298 seg_setup(VCPU_SREG_SS);
2299
2300 vmcs_write16(GUEST_TR_SELECTOR, 0);
2301 vmcs_writel(GUEST_TR_BASE, 0);
2302 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2303 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2304
2305 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2306 vmcs_writel(GUEST_LDTR_BASE, 0);
2307 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2308 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2309
2310 vmcs_write32(GUEST_SYSENTER_CS, 0);
2311 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2312 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2313
2314 vmcs_writel(GUEST_RFLAGS, 0x02);
2315 if (vmx->vcpu.vcpu_id == 0)
2316 kvm_rip_write(vcpu, 0xfff0);
2317 else
2318 kvm_rip_write(vcpu, 0);
2319 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2320
2321 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2322 vmcs_writel(GUEST_DR7, 0x400);
2323
2324 vmcs_writel(GUEST_GDTR_BASE, 0);
2325 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2326
2327 vmcs_writel(GUEST_IDTR_BASE, 0);
2328 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2329
2330 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2331 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2332 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2333
2334 guest_write_tsc(0);
2335
2336 /* Special registers */
2337 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2338
2339 setup_msrs(vmx);
2340
2341 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2342
2343 if (cpu_has_vmx_tpr_shadow()) {
2344 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2345 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2346 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2347 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2348 vmcs_write32(TPR_THRESHOLD, 0);
2349 }
2350
2351 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2352 vmcs_write64(APIC_ACCESS_ADDR,
2353 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2354
2355 if (vmx->vpid != 0)
2356 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2357
2358 vmx->vcpu.arch.cr0 = 0x60000010;
2359 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2360 vmx_set_cr4(&vmx->vcpu, 0);
2361 vmx_set_efer(&vmx->vcpu, 0);
2362 vmx_fpu_activate(&vmx->vcpu);
2363 update_exception_bitmap(&vmx->vcpu);
2364
2365 vpid_sync_vcpu_all(vmx);
2366
2367 ret = 0;
2368
2369 /* HACK: Don't enable emulation on guest boot/reset */
2370 vmx->emulation_required = 0;
2371
2372 out:
2373 up_read(&vcpu->kvm->slots_lock);
2374 return ret;
2375 }
2376
2377 static void enable_irq_window(struct kvm_vcpu *vcpu)
2378 {
2379 u32 cpu_based_vm_exec_control;
2380
2381 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2382 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2383 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2384 }
2385
2386 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2387 {
2388 u32 cpu_based_vm_exec_control;
2389
2390 if (!cpu_has_virtual_nmis()) {
2391 enable_irq_window(vcpu);
2392 return;
2393 }
2394
2395 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2396 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2397 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2398 }
2399
2400 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2401 {
2402 struct vcpu_vmx *vmx = to_vmx(vcpu);
2403
2404 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2405
2406 ++vcpu->stat.irq_injections;
2407 if (vcpu->arch.rmode.active) {
2408 vmx->rmode.irq.pending = true;
2409 vmx->rmode.irq.vector = irq;
2410 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2411 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2412 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2413 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2414 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2415 return;
2416 }
2417 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2418 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2419 }
2420
2421 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2422 {
2423 struct vcpu_vmx *vmx = to_vmx(vcpu);
2424
2425 if (!cpu_has_virtual_nmis()) {
2426 /*
2427 * Tracking the NMI-blocked state in software is built upon
2428 * finding the next open IRQ window. This, in turn, depends on
2429 * well-behaving guests: They have to keep IRQs disabled at
2430 * least as long as the NMI handler runs. Otherwise we may
2431 * cause NMI nesting, maybe breaking the guest. But as this is
2432 * highly unlikely, we can live with the residual risk.
2433 */
2434 vmx->soft_vnmi_blocked = 1;
2435 vmx->vnmi_blocked_time = 0;
2436 }
2437
2438 ++vcpu->stat.nmi_injections;
2439 if (vcpu->arch.rmode.active) {
2440 vmx->rmode.irq.pending = true;
2441 vmx->rmode.irq.vector = NMI_VECTOR;
2442 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2443 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2444 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2445 INTR_INFO_VALID_MASK);
2446 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2447 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2448 return;
2449 }
2450 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2451 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2452 }
2453
2454 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2455 {
2456 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2457
2458 vcpu->arch.nmi_window_open =
2459 !(guest_intr & (GUEST_INTR_STATE_STI |
2460 GUEST_INTR_STATE_MOV_SS |
2461 GUEST_INTR_STATE_NMI));
2462 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2463 vcpu->arch.nmi_window_open = 0;
2464
2465 vcpu->arch.interrupt_window_open =
2466 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2467 !(guest_intr & (GUEST_INTR_STATE_STI |
2468 GUEST_INTR_STATE_MOV_SS)));
2469 }
2470
2471 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2472 {
2473 int word_index = __ffs(vcpu->arch.irq_summary);
2474 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2475 int irq = word_index * BITS_PER_LONG + bit_index;
2476
2477 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2478 if (!vcpu->arch.irq_pending[word_index])
2479 clear_bit(word_index, &vcpu->arch.irq_summary);
2480 kvm_queue_interrupt(vcpu, irq);
2481 }
2482
2483 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2484 struct kvm_run *kvm_run)
2485 {
2486 vmx_update_window_states(vcpu);
2487
2488 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2489 if (vcpu->arch.interrupt.pending) {
2490 enable_nmi_window(vcpu);
2491 } else if (vcpu->arch.nmi_window_open) {
2492 vcpu->arch.nmi_pending = false;
2493 vcpu->arch.nmi_injected = true;
2494 } else {
2495 enable_nmi_window(vcpu);
2496 return;
2497 }
2498 }
2499 if (vcpu->arch.nmi_injected) {
2500 vmx_inject_nmi(vcpu);
2501 if (vcpu->arch.nmi_pending)
2502 enable_nmi_window(vcpu);
2503 else if (vcpu->arch.irq_summary
2504 || kvm_run->request_interrupt_window)
2505 enable_irq_window(vcpu);
2506 return;
2507 }
2508
2509 if (vcpu->arch.interrupt_window_open) {
2510 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2511 kvm_do_inject_irq(vcpu);
2512
2513 if (vcpu->arch.interrupt.pending)
2514 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2515 }
2516 if (!vcpu->arch.interrupt_window_open &&
2517 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2518 enable_irq_window(vcpu);
2519 }
2520
2521 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2522 {
2523 int ret;
2524 struct kvm_userspace_memory_region tss_mem = {
2525 .slot = TSS_PRIVATE_MEMSLOT,
2526 .guest_phys_addr = addr,
2527 .memory_size = PAGE_SIZE * 3,
2528 .flags = 0,
2529 };
2530
2531 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2532 if (ret)
2533 return ret;
2534 kvm->arch.tss_addr = addr;
2535 return 0;
2536 }
2537
2538 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2539 {
2540 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2541
2542 set_debugreg(dbg->bp[0], 0);
2543 set_debugreg(dbg->bp[1], 1);
2544 set_debugreg(dbg->bp[2], 2);
2545 set_debugreg(dbg->bp[3], 3);
2546
2547 if (dbg->singlestep) {
2548 unsigned long flags;
2549
2550 flags = vmcs_readl(GUEST_RFLAGS);
2551 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2552 vmcs_writel(GUEST_RFLAGS, flags);
2553 }
2554 }
2555
2556 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2557 int vec, u32 err_code)
2558 {
2559 /*
2560 * Instruction with address size override prefix opcode 0x67
2561 * Cause the #SS fault with 0 error code in VM86 mode.
2562 */
2563 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2564 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2565 return 1;
2566 /*
2567 * Forward all other exceptions that are valid in real mode.
2568 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2569 * the required debugging infrastructure rework.
2570 */
2571 switch (vec) {
2572 case DE_VECTOR:
2573 case DB_VECTOR:
2574 case BP_VECTOR:
2575 case OF_VECTOR:
2576 case BR_VECTOR:
2577 case UD_VECTOR:
2578 case DF_VECTOR:
2579 case SS_VECTOR:
2580 case GP_VECTOR:
2581 case MF_VECTOR:
2582 kvm_queue_exception(vcpu, vec);
2583 return 1;
2584 }
2585 return 0;
2586 }
2587
2588 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2589 {
2590 struct vcpu_vmx *vmx = to_vmx(vcpu);
2591 u32 intr_info, error_code;
2592 unsigned long cr2, rip;
2593 u32 vect_info;
2594 enum emulation_result er;
2595
2596 vect_info = vmx->idt_vectoring_info;
2597 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2598
2599 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2600 !is_page_fault(intr_info))
2601 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2602 "intr info 0x%x\n", __func__, vect_info, intr_info);
2603
2604 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2605 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2606 set_bit(irq, vcpu->arch.irq_pending);
2607 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2608 }
2609
2610 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2611 return 1; /* already handled by vmx_vcpu_run() */
2612
2613 if (is_no_device(intr_info)) {
2614 vmx_fpu_activate(vcpu);
2615 return 1;
2616 }
2617
2618 if (is_invalid_opcode(intr_info)) {
2619 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2620 if (er != EMULATE_DONE)
2621 kvm_queue_exception(vcpu, UD_VECTOR);
2622 return 1;
2623 }
2624
2625 error_code = 0;
2626 rip = kvm_rip_read(vcpu);
2627 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2628 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2629 if (is_page_fault(intr_info)) {
2630 /* EPT won't cause page fault directly */
2631 if (vm_need_ept())
2632 BUG();
2633 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2634 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2635 (u32)((u64)cr2 >> 32), handler);
2636 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2637 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2638 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2639 }
2640
2641 if (vcpu->arch.rmode.active &&
2642 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2643 error_code)) {
2644 if (vcpu->arch.halt_request) {
2645 vcpu->arch.halt_request = 0;
2646 return kvm_emulate_halt(vcpu);
2647 }
2648 return 1;
2649 }
2650
2651 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2652 (INTR_TYPE_EXCEPTION | 1)) {
2653 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2654 return 0;
2655 }
2656 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2657 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2658 kvm_run->ex.error_code = error_code;
2659 return 0;
2660 }
2661
2662 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2663 struct kvm_run *kvm_run)
2664 {
2665 ++vcpu->stat.irq_exits;
2666 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2667 return 1;
2668 }
2669
2670 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2671 {
2672 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2673 return 0;
2674 }
2675
2676 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2677 {
2678 unsigned long exit_qualification;
2679 int size, down, in, string, rep;
2680 unsigned port;
2681
2682 ++vcpu->stat.io_exits;
2683 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2684 string = (exit_qualification & 16) != 0;
2685
2686 if (string) {
2687 if (emulate_instruction(vcpu,
2688 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2689 return 0;
2690 return 1;
2691 }
2692
2693 size = (exit_qualification & 7) + 1;
2694 in = (exit_qualification & 8) != 0;
2695 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2696 rep = (exit_qualification & 32) != 0;
2697 port = exit_qualification >> 16;
2698
2699 skip_emulated_instruction(vcpu);
2700 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2701 }
2702
2703 static void
2704 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2705 {
2706 /*
2707 * Patch in the VMCALL instruction:
2708 */
2709 hypercall[0] = 0x0f;
2710 hypercall[1] = 0x01;
2711 hypercall[2] = 0xc1;
2712 }
2713
2714 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2715 {
2716 unsigned long exit_qualification;
2717 int cr;
2718 int reg;
2719
2720 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2721 cr = exit_qualification & 15;
2722 reg = (exit_qualification >> 8) & 15;
2723 switch ((exit_qualification >> 4) & 3) {
2724 case 0: /* mov to cr */
2725 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2726 (u32)kvm_register_read(vcpu, reg),
2727 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2728 handler);
2729 switch (cr) {
2730 case 0:
2731 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2732 skip_emulated_instruction(vcpu);
2733 return 1;
2734 case 3:
2735 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2736 skip_emulated_instruction(vcpu);
2737 return 1;
2738 case 4:
2739 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2740 skip_emulated_instruction(vcpu);
2741 return 1;
2742 case 8:
2743 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2744 skip_emulated_instruction(vcpu);
2745 if (irqchip_in_kernel(vcpu->kvm))
2746 return 1;
2747 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2748 return 0;
2749 };
2750 break;
2751 case 2: /* clts */
2752 vmx_fpu_deactivate(vcpu);
2753 vcpu->arch.cr0 &= ~X86_CR0_TS;
2754 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2755 vmx_fpu_activate(vcpu);
2756 KVMTRACE_0D(CLTS, vcpu, handler);
2757 skip_emulated_instruction(vcpu);
2758 return 1;
2759 case 1: /*mov from cr*/
2760 switch (cr) {
2761 case 3:
2762 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2763 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2764 (u32)kvm_register_read(vcpu, reg),
2765 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2766 handler);
2767 skip_emulated_instruction(vcpu);
2768 return 1;
2769 case 8:
2770 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2771 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2772 (u32)kvm_register_read(vcpu, reg), handler);
2773 skip_emulated_instruction(vcpu);
2774 return 1;
2775 }
2776 break;
2777 case 3: /* lmsw */
2778 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2779
2780 skip_emulated_instruction(vcpu);
2781 return 1;
2782 default:
2783 break;
2784 }
2785 kvm_run->exit_reason = 0;
2786 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2787 (int)(exit_qualification >> 4) & 3, cr);
2788 return 0;
2789 }
2790
2791 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2792 {
2793 unsigned long exit_qualification;
2794 unsigned long val;
2795 int dr, reg;
2796
2797 /*
2798 * FIXME: this code assumes the host is debugging the guest.
2799 * need to deal with guest debugging itself too.
2800 */
2801 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2802 dr = exit_qualification & 7;
2803 reg = (exit_qualification >> 8) & 15;
2804 if (exit_qualification & 16) {
2805 /* mov from dr */
2806 switch (dr) {
2807 case 6:
2808 val = 0xffff0ff0;
2809 break;
2810 case 7:
2811 val = 0x400;
2812 break;
2813 default:
2814 val = 0;
2815 }
2816 kvm_register_write(vcpu, reg, val);
2817 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2818 } else {
2819 /* mov to dr */
2820 }
2821 skip_emulated_instruction(vcpu);
2822 return 1;
2823 }
2824
2825 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2826 {
2827 kvm_emulate_cpuid(vcpu);
2828 return 1;
2829 }
2830
2831 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2832 {
2833 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2834 u64 data;
2835
2836 if (vmx_get_msr(vcpu, ecx, &data)) {
2837 kvm_inject_gp(vcpu, 0);
2838 return 1;
2839 }
2840
2841 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2842 handler);
2843
2844 /* FIXME: handling of bits 32:63 of rax, rdx */
2845 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2846 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2847 skip_emulated_instruction(vcpu);
2848 return 1;
2849 }
2850
2851 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2852 {
2853 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2854 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2855 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2856
2857 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2858 handler);
2859
2860 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2861 kvm_inject_gp(vcpu, 0);
2862 return 1;
2863 }
2864
2865 skip_emulated_instruction(vcpu);
2866 return 1;
2867 }
2868
2869 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2870 struct kvm_run *kvm_run)
2871 {
2872 return 1;
2873 }
2874
2875 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2876 struct kvm_run *kvm_run)
2877 {
2878 u32 cpu_based_vm_exec_control;
2879
2880 /* clear pending irq */
2881 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2882 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2883 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2884
2885 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2886 ++vcpu->stat.irq_window_exits;
2887
2888 /*
2889 * If the user space waits to inject interrupts, exit as soon as
2890 * possible
2891 */
2892 if (kvm_run->request_interrupt_window &&
2893 !vcpu->arch.irq_summary) {
2894 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2895 return 0;
2896 }
2897 return 1;
2898 }
2899
2900 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2901 {
2902 skip_emulated_instruction(vcpu);
2903 return kvm_emulate_halt(vcpu);
2904 }
2905
2906 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2907 {
2908 skip_emulated_instruction(vcpu);
2909 kvm_emulate_hypercall(vcpu);
2910 return 1;
2911 }
2912
2913 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2914 {
2915 u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2916
2917 kvm_mmu_invlpg(vcpu, exit_qualification);
2918 skip_emulated_instruction(vcpu);
2919 return 1;
2920 }
2921
2922 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2923 {
2924 skip_emulated_instruction(vcpu);
2925 /* TODO: Add support for VT-d/pass-through device */
2926 return 1;
2927 }
2928
2929 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2930 {
2931 u64 exit_qualification;
2932 enum emulation_result er;
2933 unsigned long offset;
2934
2935 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2936 offset = exit_qualification & 0xffful;
2937
2938 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2939
2940 if (er != EMULATE_DONE) {
2941 printk(KERN_ERR
2942 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2943 offset);
2944 return -ENOTSUPP;
2945 }
2946 return 1;
2947 }
2948
2949 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2950 {
2951 struct vcpu_vmx *vmx = to_vmx(vcpu);
2952 unsigned long exit_qualification;
2953 u16 tss_selector;
2954 int reason;
2955
2956 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2957
2958 reason = (u32)exit_qualification >> 30;
2959 if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
2960 (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
2961 (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
2962 == INTR_TYPE_NMI_INTR) {
2963 vcpu->arch.nmi_injected = false;
2964 if (cpu_has_virtual_nmis())
2965 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2966 GUEST_INTR_STATE_NMI);
2967 }
2968 tss_selector = exit_qualification;
2969
2970 return kvm_task_switch(vcpu, tss_selector, reason);
2971 }
2972
2973 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2974 {
2975 u64 exit_qualification;
2976 enum emulation_result er;
2977 gpa_t gpa;
2978 unsigned long hva;
2979 int gla_validity;
2980 int r;
2981
2982 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2983
2984 if (exit_qualification & (1 << 6)) {
2985 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2986 return -ENOTSUPP;
2987 }
2988
2989 gla_validity = (exit_qualification >> 7) & 0x3;
2990 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2991 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2992 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2993 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2994 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2995 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2996 (long unsigned int)exit_qualification);
2997 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2998 kvm_run->hw.hardware_exit_reason = 0;
2999 return -ENOTSUPP;
3000 }
3001
3002 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3003 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
3004 if (!kvm_is_error_hva(hva)) {
3005 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3006 if (r < 0) {
3007 printk(KERN_ERR "EPT: Not enough memory!\n");
3008 return -ENOMEM;
3009 }
3010 return 1;
3011 } else {
3012 /* must be MMIO */
3013 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3014
3015 if (er == EMULATE_FAIL) {
3016 printk(KERN_ERR
3017 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
3018 er);
3019 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3020 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3021 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3022 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3023 (long unsigned int)exit_qualification);
3024 return -ENOTSUPP;
3025 } else if (er == EMULATE_DO_MMIO)
3026 return 0;
3027 }
3028 return 1;
3029 }
3030
3031 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3032 {
3033 u32 cpu_based_vm_exec_control;
3034
3035 /* clear pending NMI */
3036 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3037 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3038 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3039 ++vcpu->stat.nmi_window_exits;
3040
3041 return 1;
3042 }
3043
3044 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3045 struct kvm_run *kvm_run)
3046 {
3047 struct vcpu_vmx *vmx = to_vmx(vcpu);
3048 int err;
3049
3050 preempt_enable();
3051 local_irq_enable();
3052
3053 while (!guest_state_valid(vcpu)) {
3054 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3055
3056 if (err == EMULATE_DO_MMIO)
3057 break;
3058
3059 if (err != EMULATE_DONE) {
3060 kvm_report_emulation_failure(vcpu, "emulation failure");
3061 return;
3062 }
3063
3064 if (signal_pending(current))
3065 break;
3066 if (need_resched())
3067 schedule();
3068 }
3069
3070 local_irq_disable();
3071 preempt_disable();
3072
3073 /* Guest state should be valid now except if we need to
3074 * emulate an MMIO */
3075 if (guest_state_valid(vcpu))
3076 vmx->emulation_required = 0;
3077 }
3078
3079 /*
3080 * The exit handlers return 1 if the exit was handled fully and guest execution
3081 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3082 * to be done to userspace and return 0.
3083 */
3084 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3085 struct kvm_run *kvm_run) = {
3086 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3087 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3088 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3089 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3090 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3091 [EXIT_REASON_CR_ACCESS] = handle_cr,
3092 [EXIT_REASON_DR_ACCESS] = handle_dr,
3093 [EXIT_REASON_CPUID] = handle_cpuid,
3094 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3095 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3096 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3097 [EXIT_REASON_HLT] = handle_halt,
3098 [EXIT_REASON_INVLPG] = handle_invlpg,
3099 [EXIT_REASON_VMCALL] = handle_vmcall,
3100 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3101 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3102 [EXIT_REASON_WBINVD] = handle_wbinvd,
3103 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3104 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3105 };
3106
3107 static const int kvm_vmx_max_exit_handlers =
3108 ARRAY_SIZE(kvm_vmx_exit_handlers);
3109
3110 /*
3111 * The guest has exited. See if we can fix it or if we need userspace
3112 * assistance.
3113 */
3114 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3115 {
3116 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
3117 struct vcpu_vmx *vmx = to_vmx(vcpu);
3118 u32 vectoring_info = vmx->idt_vectoring_info;
3119
3120 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3121 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3122
3123 /* If we need to emulate an MMIO from handle_invalid_guest_state
3124 * we just return 0 */
3125 if (vmx->emulation_required && emulate_invalid_guest_state)
3126 return 0;
3127
3128 /* Access CR3 don't cause VMExit in paging mode, so we need
3129 * to sync with guest real CR3. */
3130 if (vm_need_ept() && is_paging(vcpu)) {
3131 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3132 ept_load_pdptrs(vcpu);
3133 }
3134
3135 if (unlikely(vmx->fail)) {
3136 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3137 kvm_run->fail_entry.hardware_entry_failure_reason
3138 = vmcs_read32(VM_INSTRUCTION_ERROR);
3139 return 0;
3140 }
3141
3142 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3143 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3144 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3145 exit_reason != EXIT_REASON_TASK_SWITCH))
3146 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3147 "(0x%x) and exit reason is 0x%x\n",
3148 __func__, vectoring_info, exit_reason);
3149
3150 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3151 if (vcpu->arch.interrupt_window_open) {
3152 vmx->soft_vnmi_blocked = 0;
3153 vcpu->arch.nmi_window_open = 1;
3154 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3155 vcpu->arch.nmi_pending) {
3156 /*
3157 * This CPU don't support us in finding the end of an
3158 * NMI-blocked window if the guest runs with IRQs
3159 * disabled. So we pull the trigger after 1 s of
3160 * futile waiting, but inform the user about this.
3161 */
3162 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3163 "state on VCPU %d after 1 s timeout\n",
3164 __func__, vcpu->vcpu_id);
3165 vmx->soft_vnmi_blocked = 0;
3166 vmx->vcpu.arch.nmi_window_open = 1;
3167 }
3168 }
3169
3170 if (exit_reason < kvm_vmx_max_exit_handlers
3171 && kvm_vmx_exit_handlers[exit_reason])
3172 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3173 else {
3174 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3175 kvm_run->hw.hardware_exit_reason = exit_reason;
3176 }
3177 return 0;
3178 }
3179
3180 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3181 {
3182 int max_irr, tpr;
3183
3184 if (!vm_need_tpr_shadow(vcpu->kvm))
3185 return;
3186
3187 if (!kvm_lapic_enabled(vcpu) ||
3188 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3189 vmcs_write32(TPR_THRESHOLD, 0);
3190 return;
3191 }
3192
3193 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3194 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3195 }
3196
3197 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3198 {
3199 u32 exit_intr_info;
3200 u32 idt_vectoring_info;
3201 bool unblock_nmi;
3202 u8 vector;
3203 int type;
3204 bool idtv_info_valid;
3205 u32 error;
3206
3207 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3208 if (cpu_has_virtual_nmis()) {
3209 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3210 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3211 /*
3212 * SDM 3: 25.7.1.2
3213 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3214 * a guest IRET fault.
3215 */
3216 if (unblock_nmi && vector != DF_VECTOR)
3217 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3218 GUEST_INTR_STATE_NMI);
3219 } else if (unlikely(vmx->soft_vnmi_blocked))
3220 vmx->vnmi_blocked_time +=
3221 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3222
3223 idt_vectoring_info = vmx->idt_vectoring_info;
3224 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3225 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3226 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3227 if (vmx->vcpu.arch.nmi_injected) {
3228 /*
3229 * SDM 3: 25.7.1.2
3230 * Clear bit "block by NMI" before VM entry if a NMI delivery
3231 * faulted.
3232 */
3233 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3234 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3235 GUEST_INTR_STATE_NMI);
3236 else
3237 vmx->vcpu.arch.nmi_injected = false;
3238 }
3239 kvm_clear_exception_queue(&vmx->vcpu);
3240 if (idtv_info_valid && type == INTR_TYPE_EXCEPTION) {
3241 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3242 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3243 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3244 } else
3245 kvm_queue_exception(&vmx->vcpu, vector);
3246 vmx->idt_vectoring_info = 0;
3247 }
3248 kvm_clear_interrupt_queue(&vmx->vcpu);
3249 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3250 kvm_queue_interrupt(&vmx->vcpu, vector);
3251 vmx->idt_vectoring_info = 0;
3252 }
3253 }
3254
3255 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3256 {
3257 update_tpr_threshold(vcpu);
3258
3259 vmx_update_window_states(vcpu);
3260
3261 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3262 if (vcpu->arch.interrupt.pending) {
3263 enable_nmi_window(vcpu);
3264 } else if (vcpu->arch.nmi_window_open) {
3265 vcpu->arch.nmi_pending = false;
3266 vcpu->arch.nmi_injected = true;
3267 } else {
3268 enable_nmi_window(vcpu);
3269 return;
3270 }
3271 }
3272 if (vcpu->arch.nmi_injected) {
3273 vmx_inject_nmi(vcpu);
3274 if (vcpu->arch.nmi_pending)
3275 enable_nmi_window(vcpu);
3276 else if (kvm_cpu_has_interrupt(vcpu))
3277 enable_irq_window(vcpu);
3278 return;
3279 }
3280 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3281 if (vcpu->arch.interrupt_window_open)
3282 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3283 else
3284 enable_irq_window(vcpu);
3285 }
3286 if (vcpu->arch.interrupt.pending) {
3287 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3288 kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr);
3289 if (kvm_cpu_has_interrupt(vcpu))
3290 enable_irq_window(vcpu);
3291 }
3292 }
3293
3294 /*
3295 * Failure to inject an interrupt should give us the information
3296 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3297 * when fetching the interrupt redirection bitmap in the real-mode
3298 * tss, this doesn't happen. So we do it ourselves.
3299 */
3300 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3301 {
3302 vmx->rmode.irq.pending = 0;
3303 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3304 return;
3305 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3306 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3307 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3308 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3309 return;
3310 }
3311 vmx->idt_vectoring_info =
3312 VECTORING_INFO_VALID_MASK
3313 | INTR_TYPE_EXT_INTR
3314 | vmx->rmode.irq.vector;
3315 }
3316
3317 #ifdef CONFIG_X86_64
3318 #define R "r"
3319 #define Q "q"
3320 #else
3321 #define R "e"
3322 #define Q "l"
3323 #endif
3324
3325 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3326 {
3327 struct vcpu_vmx *vmx = to_vmx(vcpu);
3328 u32 intr_info;
3329
3330 /* Record the guest's net vcpu time for enforced NMI injections. */
3331 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3332 vmx->entry_time = ktime_get();
3333
3334 /* Handle invalid guest state instead of entering VMX */
3335 if (vmx->emulation_required && emulate_invalid_guest_state) {
3336 handle_invalid_guest_state(vcpu, kvm_run);
3337 return;
3338 }
3339
3340 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3341 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3342 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3343 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3344
3345 /*
3346 * Loading guest fpu may have cleared host cr0.ts
3347 */
3348 vmcs_writel(HOST_CR0, read_cr0());
3349
3350 asm(
3351 /* Store host registers */
3352 "push %%"R"dx; push %%"R"bp;"
3353 "push %%"R"cx \n\t"
3354 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3355 "je 1f \n\t"
3356 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3357 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3358 "1: \n\t"
3359 /* Check if vmlaunch of vmresume is needed */
3360 "cmpl $0, %c[launched](%0) \n\t"
3361 /* Load guest registers. Don't clobber flags. */
3362 "mov %c[cr2](%0), %%"R"ax \n\t"
3363 "mov %%"R"ax, %%cr2 \n\t"
3364 "mov %c[rax](%0), %%"R"ax \n\t"
3365 "mov %c[rbx](%0), %%"R"bx \n\t"
3366 "mov %c[rdx](%0), %%"R"dx \n\t"
3367 "mov %c[rsi](%0), %%"R"si \n\t"
3368 "mov %c[rdi](%0), %%"R"di \n\t"
3369 "mov %c[rbp](%0), %%"R"bp \n\t"
3370 #ifdef CONFIG_X86_64
3371 "mov %c[r8](%0), %%r8 \n\t"
3372 "mov %c[r9](%0), %%r9 \n\t"
3373 "mov %c[r10](%0), %%r10 \n\t"
3374 "mov %c[r11](%0), %%r11 \n\t"
3375 "mov %c[r12](%0), %%r12 \n\t"
3376 "mov %c[r13](%0), %%r13 \n\t"
3377 "mov %c[r14](%0), %%r14 \n\t"
3378 "mov %c[r15](%0), %%r15 \n\t"
3379 #endif
3380 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3381
3382 /* Enter guest mode */
3383 "jne .Llaunched \n\t"
3384 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3385 "jmp .Lkvm_vmx_return \n\t"
3386 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3387 ".Lkvm_vmx_return: "
3388 /* Save guest registers, load host registers, keep flags */
3389 "xchg %0, (%%"R"sp) \n\t"
3390 "mov %%"R"ax, %c[rax](%0) \n\t"
3391 "mov %%"R"bx, %c[rbx](%0) \n\t"
3392 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3393 "mov %%"R"dx, %c[rdx](%0) \n\t"
3394 "mov %%"R"si, %c[rsi](%0) \n\t"
3395 "mov %%"R"di, %c[rdi](%0) \n\t"
3396 "mov %%"R"bp, %c[rbp](%0) \n\t"
3397 #ifdef CONFIG_X86_64
3398 "mov %%r8, %c[r8](%0) \n\t"
3399 "mov %%r9, %c[r9](%0) \n\t"
3400 "mov %%r10, %c[r10](%0) \n\t"
3401 "mov %%r11, %c[r11](%0) \n\t"
3402 "mov %%r12, %c[r12](%0) \n\t"
3403 "mov %%r13, %c[r13](%0) \n\t"
3404 "mov %%r14, %c[r14](%0) \n\t"
3405 "mov %%r15, %c[r15](%0) \n\t"
3406 #endif
3407 "mov %%cr2, %%"R"ax \n\t"
3408 "mov %%"R"ax, %c[cr2](%0) \n\t"
3409
3410 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3411 "setbe %c[fail](%0) \n\t"
3412 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3413 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3414 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3415 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3416 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3417 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3418 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3419 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3420 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3421 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3422 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3423 #ifdef CONFIG_X86_64
3424 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3425 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3426 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3427 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3428 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3429 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3430 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3431 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3432 #endif
3433 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3434 : "cc", "memory"
3435 , R"bx", R"di", R"si"
3436 #ifdef CONFIG_X86_64
3437 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3438 #endif
3439 );
3440
3441 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3442 vcpu->arch.regs_dirty = 0;
3443
3444 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3445 if (vmx->rmode.irq.pending)
3446 fixup_rmode_irq(vmx);
3447
3448 vmx_update_window_states(vcpu);
3449
3450 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3451 vmx->launched = 1;
3452
3453 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3454
3455 /* We need to handle NMIs before interrupts are enabled */
3456 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3457 (intr_info & INTR_INFO_VALID_MASK)) {
3458 KVMTRACE_0D(NMI, vcpu, handler);
3459 asm("int $2");
3460 }
3461
3462 vmx_complete_interrupts(vmx);
3463 }
3464
3465 #undef R
3466 #undef Q
3467
3468 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3469 {
3470 struct vcpu_vmx *vmx = to_vmx(vcpu);
3471
3472 if (vmx->vmcs) {
3473 vcpu_clear(vmx);
3474 free_vmcs(vmx->vmcs);
3475 vmx->vmcs = NULL;
3476 }
3477 }
3478
3479 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3480 {
3481 struct vcpu_vmx *vmx = to_vmx(vcpu);
3482
3483 spin_lock(&vmx_vpid_lock);
3484 if (vmx->vpid != 0)
3485 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3486 spin_unlock(&vmx_vpid_lock);
3487 vmx_free_vmcs(vcpu);
3488 kfree(vmx->host_msrs);
3489 kfree(vmx->guest_msrs);
3490 kvm_vcpu_uninit(vcpu);
3491 kmem_cache_free(kvm_vcpu_cache, vmx);
3492 }
3493
3494 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3495 {
3496 int err;
3497 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3498 int cpu;
3499
3500 if (!vmx)
3501 return ERR_PTR(-ENOMEM);
3502
3503 allocate_vpid(vmx);
3504
3505 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3506 if (err)
3507 goto free_vcpu;
3508
3509 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3510 if (!vmx->guest_msrs) {
3511 err = -ENOMEM;
3512 goto uninit_vcpu;
3513 }
3514
3515 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3516 if (!vmx->host_msrs)
3517 goto free_guest_msrs;
3518
3519 vmx->vmcs = alloc_vmcs();
3520 if (!vmx->vmcs)
3521 goto free_msrs;
3522
3523 vmcs_clear(vmx->vmcs);
3524
3525 cpu = get_cpu();
3526 vmx_vcpu_load(&vmx->vcpu, cpu);
3527 err = vmx_vcpu_setup(vmx);
3528 vmx_vcpu_put(&vmx->vcpu);
3529 put_cpu();
3530 if (err)
3531 goto free_vmcs;
3532 if (vm_need_virtualize_apic_accesses(kvm))
3533 if (alloc_apic_access_page(kvm) != 0)
3534 goto free_vmcs;
3535
3536 if (vm_need_ept())
3537 if (alloc_identity_pagetable(kvm) != 0)
3538 goto free_vmcs;
3539
3540 return &vmx->vcpu;
3541
3542 free_vmcs:
3543 free_vmcs(vmx->vmcs);
3544 free_msrs:
3545 kfree(vmx->host_msrs);
3546 free_guest_msrs:
3547 kfree(vmx->guest_msrs);
3548 uninit_vcpu:
3549 kvm_vcpu_uninit(&vmx->vcpu);
3550 free_vcpu:
3551 kmem_cache_free(kvm_vcpu_cache, vmx);
3552 return ERR_PTR(err);
3553 }
3554
3555 static void __init vmx_check_processor_compat(void *rtn)
3556 {
3557 struct vmcs_config vmcs_conf;
3558
3559 *(int *)rtn = 0;
3560 if (setup_vmcs_config(&vmcs_conf) < 0)
3561 *(int *)rtn = -EIO;
3562 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3563 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3564 smp_processor_id());
3565 *(int *)rtn = -EIO;
3566 }
3567 }
3568
3569 static int get_ept_level(void)
3570 {
3571 return VMX_EPT_DEFAULT_GAW + 1;
3572 }
3573
3574 static int vmx_get_mt_mask_shift(void)
3575 {
3576 return VMX_EPT_MT_EPTE_SHIFT;
3577 }
3578
3579 static struct kvm_x86_ops vmx_x86_ops = {
3580 .cpu_has_kvm_support = cpu_has_kvm_support,
3581 .disabled_by_bios = vmx_disabled_by_bios,
3582 .hardware_setup = hardware_setup,
3583 .hardware_unsetup = hardware_unsetup,
3584 .check_processor_compatibility = vmx_check_processor_compat,
3585 .hardware_enable = hardware_enable,
3586 .hardware_disable = hardware_disable,
3587 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3588
3589 .vcpu_create = vmx_create_vcpu,
3590 .vcpu_free = vmx_free_vcpu,
3591 .vcpu_reset = vmx_vcpu_reset,
3592
3593 .prepare_guest_switch = vmx_save_host_state,
3594 .vcpu_load = vmx_vcpu_load,
3595 .vcpu_put = vmx_vcpu_put,
3596
3597 .set_guest_debug = set_guest_debug,
3598 .guest_debug_pre = kvm_guest_debug_pre,
3599 .get_msr = vmx_get_msr,
3600 .set_msr = vmx_set_msr,
3601 .get_segment_base = vmx_get_segment_base,
3602 .get_segment = vmx_get_segment,
3603 .set_segment = vmx_set_segment,
3604 .get_cpl = vmx_get_cpl,
3605 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3606 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3607 .set_cr0 = vmx_set_cr0,
3608 .set_cr3 = vmx_set_cr3,
3609 .set_cr4 = vmx_set_cr4,
3610 .set_efer = vmx_set_efer,
3611 .get_idt = vmx_get_idt,
3612 .set_idt = vmx_set_idt,
3613 .get_gdt = vmx_get_gdt,
3614 .set_gdt = vmx_set_gdt,
3615 .cache_reg = vmx_cache_reg,
3616 .get_rflags = vmx_get_rflags,
3617 .set_rflags = vmx_set_rflags,
3618
3619 .tlb_flush = vmx_flush_tlb,
3620
3621 .run = vmx_vcpu_run,
3622 .handle_exit = kvm_handle_exit,
3623 .skip_emulated_instruction = skip_emulated_instruction,
3624 .patch_hypercall = vmx_patch_hypercall,
3625 .get_irq = vmx_get_irq,
3626 .set_irq = vmx_inject_irq,
3627 .queue_exception = vmx_queue_exception,
3628 .exception_injected = vmx_exception_injected,
3629 .inject_pending_irq = vmx_intr_assist,
3630 .inject_pending_vectors = do_interrupt_requests,
3631
3632 .set_tss_addr = vmx_set_tss_addr,
3633 .get_tdp_level = get_ept_level,
3634 .get_mt_mask_shift = vmx_get_mt_mask_shift,
3635 };
3636
3637 static int __init vmx_init(void)
3638 {
3639 void *va;
3640 int r;
3641
3642 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3643 if (!vmx_io_bitmap_a)
3644 return -ENOMEM;
3645
3646 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3647 if (!vmx_io_bitmap_b) {
3648 r = -ENOMEM;
3649 goto out;
3650 }
3651
3652 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3653 if (!vmx_msr_bitmap) {
3654 r = -ENOMEM;
3655 goto out1;
3656 }
3657
3658 /*
3659 * Allow direct access to the PC debug port (it is often used for I/O
3660 * delays, but the vmexits simply slow things down).
3661 */
3662 va = kmap(vmx_io_bitmap_a);
3663 memset(va, 0xff, PAGE_SIZE);
3664 clear_bit(0x80, va);
3665 kunmap(vmx_io_bitmap_a);
3666
3667 va = kmap(vmx_io_bitmap_b);
3668 memset(va, 0xff, PAGE_SIZE);
3669 kunmap(vmx_io_bitmap_b);
3670
3671 va = kmap(vmx_msr_bitmap);
3672 memset(va, 0xff, PAGE_SIZE);
3673 kunmap(vmx_msr_bitmap);
3674
3675 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3676
3677 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3678 if (r)
3679 goto out2;
3680
3681 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3682 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3683 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3684 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3685 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3686
3687 if (vm_need_ept()) {
3688 bypass_guest_pf = 0;
3689 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3690 VMX_EPT_WRITABLE_MASK);
3691 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3692 VMX_EPT_EXECUTABLE_MASK,
3693 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3694 kvm_enable_tdp();
3695 } else
3696 kvm_disable_tdp();
3697
3698 if (bypass_guest_pf)
3699 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3700
3701 ept_sync_global();
3702
3703 return 0;
3704
3705 out2:
3706 __free_page(vmx_msr_bitmap);
3707 out1:
3708 __free_page(vmx_io_bitmap_b);
3709 out:
3710 __free_page(vmx_io_bitmap_a);
3711 return r;
3712 }
3713
3714 static void __exit vmx_exit(void)
3715 {
3716 __free_page(vmx_msr_bitmap);
3717 __free_page(vmx_io_bitmap_b);
3718 __free_page(vmx_io_bitmap_a);
3719
3720 kvm_exit();
3721 }
3722
3723 module_init(vmx_init)
3724 module_exit(vmx_exit)
Support for the Chinese Samsung S3C2440 based development boards