2 * linux/arch/arm/plat-omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Multichannel mode not supported.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
28 #include <mach/mcbsp.h>
30 struct omap_mcbsp
**mcbsp_ptr
;
33 void omap_mcbsp_write(void __iomem
*io_base
, u16 reg
, u32 val
)
35 if (cpu_class_is_omap1() || cpu_is_omap2420())
36 __raw_writew((u16
)val
, io_base
+ reg
);
38 __raw_writel(val
, io_base
+ reg
);
41 int omap_mcbsp_read(void __iomem
*io_base
, u16 reg
)
43 if (cpu_class_is_omap1() || cpu_is_omap2420())
44 return __raw_readw(io_base
+ reg
);
46 return __raw_readl(io_base
+ reg
);
49 #define OMAP_MCBSP_READ(base, reg) \
50 omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
51 #define OMAP_MCBSP_WRITE(base, reg, val) \
52 omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
54 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
55 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
57 static void omap_mcbsp_dump_reg(u8 id
)
59 struct omap_mcbsp
*mcbsp
= id_to_mcbsp_ptr(id
);
61 dev_dbg(mcbsp
->dev
, "**** McBSP%d regs ****\n", mcbsp
->id
);
62 dev_dbg(mcbsp
->dev
, "DRR2: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp
->io_base
, DRR2
));
64 dev_dbg(mcbsp
->dev
, "DRR1: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp
->io_base
, DRR1
));
66 dev_dbg(mcbsp
->dev
, "DXR2: 0x%04x\n",
67 OMAP_MCBSP_READ(mcbsp
->io_base
, DXR2
));
68 dev_dbg(mcbsp
->dev
, "DXR1: 0x%04x\n",
69 OMAP_MCBSP_READ(mcbsp
->io_base
, DXR1
));
70 dev_dbg(mcbsp
->dev
, "SPCR2: 0x%04x\n",
71 OMAP_MCBSP_READ(mcbsp
->io_base
, SPCR2
));
72 dev_dbg(mcbsp
->dev
, "SPCR1: 0x%04x\n",
73 OMAP_MCBSP_READ(mcbsp
->io_base
, SPCR1
));
74 dev_dbg(mcbsp
->dev
, "RCR2: 0x%04x\n",
75 OMAP_MCBSP_READ(mcbsp
->io_base
, RCR2
));
76 dev_dbg(mcbsp
->dev
, "RCR1: 0x%04x\n",
77 OMAP_MCBSP_READ(mcbsp
->io_base
, RCR1
));
78 dev_dbg(mcbsp
->dev
, "XCR2: 0x%04x\n",
79 OMAP_MCBSP_READ(mcbsp
->io_base
, XCR2
));
80 dev_dbg(mcbsp
->dev
, "XCR1: 0x%04x\n",
81 OMAP_MCBSP_READ(mcbsp
->io_base
, XCR1
));
82 dev_dbg(mcbsp
->dev
, "SRGR2: 0x%04x\n",
83 OMAP_MCBSP_READ(mcbsp
->io_base
, SRGR2
));
84 dev_dbg(mcbsp
->dev
, "SRGR1: 0x%04x\n",
85 OMAP_MCBSP_READ(mcbsp
->io_base
, SRGR1
));
86 dev_dbg(mcbsp
->dev
, "PCR0: 0x%04x\n",
87 OMAP_MCBSP_READ(mcbsp
->io_base
, PCR0
));
88 dev_dbg(mcbsp
->dev
, "***********************\n");
91 static irqreturn_t
omap_mcbsp_tx_irq_handler(int irq
, void *dev_id
)
93 struct omap_mcbsp
*mcbsp_tx
= dev_id
;
95 dev_dbg(mcbsp_tx
->dev
, "TX IRQ callback : 0x%x\n",
96 OMAP_MCBSP_READ(mcbsp_tx
->io_base
, SPCR2
));
98 complete(&mcbsp_tx
->tx_irq_completion
);
103 static irqreturn_t
omap_mcbsp_rx_irq_handler(int irq
, void *dev_id
)
105 struct omap_mcbsp
*mcbsp_rx
= dev_id
;
107 dev_dbg(mcbsp_rx
->dev
, "RX IRQ callback : 0x%x\n",
108 OMAP_MCBSP_READ(mcbsp_rx
->io_base
, SPCR2
));
110 complete(&mcbsp_rx
->rx_irq_completion
);
115 static void omap_mcbsp_tx_dma_callback(int lch
, u16 ch_status
, void *data
)
117 struct omap_mcbsp
*mcbsp_dma_tx
= data
;
119 dev_dbg(mcbsp_dma_tx
->dev
, "TX DMA callback : 0x%x\n",
120 OMAP_MCBSP_READ(mcbsp_dma_tx
->io_base
, SPCR2
));
122 /* We can free the channels */
123 omap_free_dma(mcbsp_dma_tx
->dma_tx_lch
);
124 mcbsp_dma_tx
->dma_tx_lch
= -1;
126 complete(&mcbsp_dma_tx
->tx_dma_completion
);
129 static void omap_mcbsp_rx_dma_callback(int lch
, u16 ch_status
, void *data
)
131 struct omap_mcbsp
*mcbsp_dma_rx
= data
;
133 dev_dbg(mcbsp_dma_rx
->dev
, "RX DMA callback : 0x%x\n",
134 OMAP_MCBSP_READ(mcbsp_dma_rx
->io_base
, SPCR2
));
136 /* We can free the channels */
137 omap_free_dma(mcbsp_dma_rx
->dma_rx_lch
);
138 mcbsp_dma_rx
->dma_rx_lch
= -1;
140 complete(&mcbsp_dma_rx
->rx_dma_completion
);
144 * omap_mcbsp_config simply write a config to the
146 * You either call this function or set the McBSP registers
147 * by yourself before calling omap_mcbsp_start().
149 void omap_mcbsp_config(unsigned int id
, const struct omap_mcbsp_reg_cfg
*config
)
151 struct omap_mcbsp
*mcbsp
;
152 void __iomem
*io_base
;
154 if (!omap_mcbsp_check_valid_id(id
)) {
155 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
158 mcbsp
= id_to_mcbsp_ptr(id
);
160 io_base
= mcbsp
->io_base
;
161 dev_dbg(mcbsp
->dev
, "Configuring McBSP%d phys_base: 0x%08lx\n",
162 mcbsp
->id
, mcbsp
->phys_base
);
164 /* We write the given config */
165 OMAP_MCBSP_WRITE(io_base
, SPCR2
, config
->spcr2
);
166 OMAP_MCBSP_WRITE(io_base
, SPCR1
, config
->spcr1
);
167 OMAP_MCBSP_WRITE(io_base
, RCR2
, config
->rcr2
);
168 OMAP_MCBSP_WRITE(io_base
, RCR1
, config
->rcr1
);
169 OMAP_MCBSP_WRITE(io_base
, XCR2
, config
->xcr2
);
170 OMAP_MCBSP_WRITE(io_base
, XCR1
, config
->xcr1
);
171 OMAP_MCBSP_WRITE(io_base
, SRGR2
, config
->srgr2
);
172 OMAP_MCBSP_WRITE(io_base
, SRGR1
, config
->srgr1
);
173 OMAP_MCBSP_WRITE(io_base
, MCR2
, config
->mcr2
);
174 OMAP_MCBSP_WRITE(io_base
, MCR1
, config
->mcr1
);
175 OMAP_MCBSP_WRITE(io_base
, PCR0
, config
->pcr0
);
177 EXPORT_SYMBOL(omap_mcbsp_config
);
180 * We can choose between IRQ based or polled IO.
181 * This needs to be called before omap_mcbsp_request().
183 int omap_mcbsp_set_io_type(unsigned int id
, omap_mcbsp_io_type_t io_type
)
185 struct omap_mcbsp
*mcbsp
;
187 if (!omap_mcbsp_check_valid_id(id
)) {
188 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
191 mcbsp
= id_to_mcbsp_ptr(id
);
193 spin_lock(&mcbsp
->lock
);
196 dev_err(mcbsp
->dev
, "McBSP%d is currently in use\n",
198 spin_unlock(&mcbsp
->lock
);
202 mcbsp
->io_type
= io_type
;
204 spin_unlock(&mcbsp
->lock
);
208 EXPORT_SYMBOL(omap_mcbsp_set_io_type
);
210 int omap_mcbsp_request(unsigned int id
)
212 struct omap_mcbsp
*mcbsp
;
215 if (!omap_mcbsp_check_valid_id(id
)) {
216 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
219 mcbsp
= id_to_mcbsp_ptr(id
);
221 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->request
)
222 mcbsp
->pdata
->ops
->request(id
);
224 clk_enable(mcbsp
->clk
);
226 spin_lock(&mcbsp
->lock
);
228 dev_err(mcbsp
->dev
, "McBSP%d is currently in use\n",
230 spin_unlock(&mcbsp
->lock
);
235 spin_unlock(&mcbsp
->lock
);
238 * Make sure that transmitter, receiver and sample-rate generator are
239 * not running before activating IRQs.
241 OMAP_MCBSP_WRITE(mcbsp
->io_base
, SPCR1
, 0);
242 OMAP_MCBSP_WRITE(mcbsp
->io_base
, SPCR2
, 0);
244 if (mcbsp
->io_type
== OMAP_MCBSP_IRQ_IO
) {
245 /* We need to get IRQs here */
246 init_completion(&mcbsp
->tx_irq_completion
);
247 err
= request_irq(mcbsp
->tx_irq
, omap_mcbsp_tx_irq_handler
,
248 0, "McBSP", (void *)mcbsp
);
250 dev_err(mcbsp
->dev
, "Unable to request TX IRQ %d "
251 "for McBSP%d\n", mcbsp
->tx_irq
,
256 init_completion(&mcbsp
->rx_irq_completion
);
257 err
= request_irq(mcbsp
->rx_irq
, omap_mcbsp_rx_irq_handler
,
258 0, "McBSP", (void *)mcbsp
);
260 dev_err(mcbsp
->dev
, "Unable to request RX IRQ %d "
261 "for McBSP%d\n", mcbsp
->rx_irq
,
263 free_irq(mcbsp
->tx_irq
, (void *)mcbsp
);
270 EXPORT_SYMBOL(omap_mcbsp_request
);
272 void omap_mcbsp_free(unsigned int id
)
274 struct omap_mcbsp
*mcbsp
;
276 if (!omap_mcbsp_check_valid_id(id
)) {
277 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
280 mcbsp
= id_to_mcbsp_ptr(id
);
282 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->free
)
283 mcbsp
->pdata
->ops
->free(id
);
285 clk_disable(mcbsp
->clk
);
287 spin_lock(&mcbsp
->lock
);
289 dev_err(mcbsp
->dev
, "McBSP%d was not reserved\n",
291 spin_unlock(&mcbsp
->lock
);
296 spin_unlock(&mcbsp
->lock
);
298 if (mcbsp
->io_type
== OMAP_MCBSP_IRQ_IO
) {
300 free_irq(mcbsp
->rx_irq
, (void *)mcbsp
);
301 free_irq(mcbsp
->tx_irq
, (void *)mcbsp
);
304 EXPORT_SYMBOL(omap_mcbsp_free
);
307 * Here we start the McBSP, by enabling the sample
308 * generator, both transmitter and receivers,
309 * and the frame sync.
311 void omap_mcbsp_start(unsigned int id
)
313 struct omap_mcbsp
*mcbsp
;
314 void __iomem
*io_base
;
317 if (!omap_mcbsp_check_valid_id(id
)) {
318 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
321 mcbsp
= id_to_mcbsp_ptr(id
);
322 io_base
= mcbsp
->io_base
;
324 mcbsp
->rx_word_length
= (OMAP_MCBSP_READ(io_base
, RCR1
) >> 5) & 0x7;
325 mcbsp
->tx_word_length
= (OMAP_MCBSP_READ(io_base
, XCR1
) >> 5) & 0x7;
327 /* Start the sample generator */
328 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
329 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
| (1 << 6));
331 /* Enable transmitter and receiver */
332 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
333 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
| 1);
335 w
= OMAP_MCBSP_READ(io_base
, SPCR1
);
336 OMAP_MCBSP_WRITE(io_base
, SPCR1
, w
| 1);
340 /* Start frame sync */
341 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
342 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
| (1 << 7));
344 /* Dump McBSP Regs */
345 omap_mcbsp_dump_reg(id
);
347 EXPORT_SYMBOL(omap_mcbsp_start
);
349 void omap_mcbsp_stop(unsigned int id
)
351 struct omap_mcbsp
*mcbsp
;
352 void __iomem
*io_base
;
355 if (!omap_mcbsp_check_valid_id(id
)) {
356 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
360 mcbsp
= id_to_mcbsp_ptr(id
);
361 io_base
= mcbsp
->io_base
;
363 /* Reset transmitter */
364 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
365 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
& ~(1));
368 w
= OMAP_MCBSP_READ(io_base
, SPCR1
);
369 OMAP_MCBSP_WRITE(io_base
, SPCR1
, w
& ~(1));
371 /* Reset the sample rate generator */
372 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
373 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
& ~(1 << 6));
375 EXPORT_SYMBOL(omap_mcbsp_stop
);
377 /* polled mcbsp i/o operations */
378 int omap_mcbsp_pollwrite(unsigned int id
, u16 buf
)
380 struct omap_mcbsp
*mcbsp
;
383 if (!omap_mcbsp_check_valid_id(id
)) {
384 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
388 mcbsp
= id_to_mcbsp_ptr(id
);
389 base
= mcbsp
->io_base
;
391 writew(buf
, base
+ OMAP_MCBSP_REG_DXR1
);
392 /* if frame sync error - clear the error */
393 if (readw(base
+ OMAP_MCBSP_REG_SPCR2
) & XSYNC_ERR
) {
395 writew(readw(base
+ OMAP_MCBSP_REG_SPCR2
) & (~XSYNC_ERR
),
396 base
+ OMAP_MCBSP_REG_SPCR2
);
400 /* wait for transmit confirmation */
402 while (!(readw(base
+ OMAP_MCBSP_REG_SPCR2
) & XRDY
)) {
403 if (attemps
++ > 1000) {
404 writew(readw(base
+ OMAP_MCBSP_REG_SPCR2
) &
406 base
+ OMAP_MCBSP_REG_SPCR2
);
408 writew(readw(base
+ OMAP_MCBSP_REG_SPCR2
) |
410 base
+ OMAP_MCBSP_REG_SPCR2
);
412 dev_err(mcbsp
->dev
, "Could not write to"
413 " McBSP%d Register\n", mcbsp
->id
);
421 EXPORT_SYMBOL(omap_mcbsp_pollwrite
);
423 int omap_mcbsp_pollread(unsigned int id
, u16
*buf
)
425 struct omap_mcbsp
*mcbsp
;
428 if (!omap_mcbsp_check_valid_id(id
)) {
429 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
432 mcbsp
= id_to_mcbsp_ptr(id
);
434 base
= mcbsp
->io_base
;
435 /* if frame sync error - clear the error */
436 if (readw(base
+ OMAP_MCBSP_REG_SPCR1
) & RSYNC_ERR
) {
438 writew(readw(base
+ OMAP_MCBSP_REG_SPCR1
) & (~RSYNC_ERR
),
439 base
+ OMAP_MCBSP_REG_SPCR1
);
443 /* wait for recieve confirmation */
445 while (!(readw(base
+ OMAP_MCBSP_REG_SPCR1
) & RRDY
)) {
446 if (attemps
++ > 1000) {
447 writew(readw(base
+ OMAP_MCBSP_REG_SPCR1
) &
449 base
+ OMAP_MCBSP_REG_SPCR1
);
451 writew(readw(base
+ OMAP_MCBSP_REG_SPCR1
) |
453 base
+ OMAP_MCBSP_REG_SPCR1
);
455 dev_err(mcbsp
->dev
, "Could not read from"
456 " McBSP%d Register\n", mcbsp
->id
);
461 *buf
= readw(base
+ OMAP_MCBSP_REG_DRR1
);
465 EXPORT_SYMBOL(omap_mcbsp_pollread
);
468 * IRQ based word transmission.
470 void omap_mcbsp_xmit_word(unsigned int id
, u32 word
)
472 struct omap_mcbsp
*mcbsp
;
473 void __iomem
*io_base
;
474 omap_mcbsp_word_length word_length
;
476 if (!omap_mcbsp_check_valid_id(id
)) {
477 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
481 mcbsp
= id_to_mcbsp_ptr(id
);
482 io_base
= mcbsp
->io_base
;
483 word_length
= mcbsp
->tx_word_length
;
485 wait_for_completion(&mcbsp
->tx_irq_completion
);
487 if (word_length
> OMAP_MCBSP_WORD_16
)
488 OMAP_MCBSP_WRITE(io_base
, DXR2
, word
>> 16);
489 OMAP_MCBSP_WRITE(io_base
, DXR1
, word
& 0xffff);
491 EXPORT_SYMBOL(omap_mcbsp_xmit_word
);
493 u32
omap_mcbsp_recv_word(unsigned int id
)
495 struct omap_mcbsp
*mcbsp
;
496 void __iomem
*io_base
;
497 u16 word_lsb
, word_msb
= 0;
498 omap_mcbsp_word_length word_length
;
500 if (!omap_mcbsp_check_valid_id(id
)) {
501 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
504 mcbsp
= id_to_mcbsp_ptr(id
);
506 word_length
= mcbsp
->rx_word_length
;
507 io_base
= mcbsp
->io_base
;
509 wait_for_completion(&mcbsp
->rx_irq_completion
);
511 if (word_length
> OMAP_MCBSP_WORD_16
)
512 word_msb
= OMAP_MCBSP_READ(io_base
, DRR2
);
513 word_lsb
= OMAP_MCBSP_READ(io_base
, DRR1
);
515 return (word_lsb
| (word_msb
<< 16));
517 EXPORT_SYMBOL(omap_mcbsp_recv_word
);
519 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id
, u32 word
)
521 struct omap_mcbsp
*mcbsp
;
522 void __iomem
*io_base
;
523 omap_mcbsp_word_length tx_word_length
;
524 omap_mcbsp_word_length rx_word_length
;
525 u16 spcr2
, spcr1
, attempts
= 0, word_lsb
, word_msb
= 0;
527 if (!omap_mcbsp_check_valid_id(id
)) {
528 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
531 mcbsp
= id_to_mcbsp_ptr(id
);
532 io_base
= mcbsp
->io_base
;
533 tx_word_length
= mcbsp
->tx_word_length
;
534 rx_word_length
= mcbsp
->rx_word_length
;
536 if (tx_word_length
!= rx_word_length
)
539 /* First we wait for the transmitter to be ready */
540 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
541 while (!(spcr2
& XRDY
)) {
542 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
543 if (attempts
++ > 1000) {
544 /* We must reset the transmitter */
545 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
& (~XRST
));
547 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
| XRST
);
549 dev_err(mcbsp
->dev
, "McBSP%d transmitter not "
550 "ready\n", mcbsp
->id
);
555 /* Now we can push the data */
556 if (tx_word_length
> OMAP_MCBSP_WORD_16
)
557 OMAP_MCBSP_WRITE(io_base
, DXR2
, word
>> 16);
558 OMAP_MCBSP_WRITE(io_base
, DXR1
, word
& 0xffff);
560 /* We wait for the receiver to be ready */
561 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
562 while (!(spcr1
& RRDY
)) {
563 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
564 if (attempts
++ > 1000) {
565 /* We must reset the receiver */
566 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
& (~RRST
));
568 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
| RRST
);
570 dev_err(mcbsp
->dev
, "McBSP%d receiver not "
571 "ready\n", mcbsp
->id
);
576 /* Receiver is ready, let's read the dummy data */
577 if (rx_word_length
> OMAP_MCBSP_WORD_16
)
578 word_msb
= OMAP_MCBSP_READ(io_base
, DRR2
);
579 word_lsb
= OMAP_MCBSP_READ(io_base
, DRR1
);
583 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll
);
585 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id
, u32
*word
)
587 struct omap_mcbsp
*mcbsp
;
589 void __iomem
*io_base
;
590 omap_mcbsp_word_length tx_word_length
;
591 omap_mcbsp_word_length rx_word_length
;
592 u16 spcr2
, spcr1
, attempts
= 0, word_lsb
, word_msb
= 0;
594 if (!omap_mcbsp_check_valid_id(id
)) {
595 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
599 mcbsp
= id_to_mcbsp_ptr(id
);
600 io_base
= mcbsp
->io_base
;
602 tx_word_length
= mcbsp
->tx_word_length
;
603 rx_word_length
= mcbsp
->rx_word_length
;
605 if (tx_word_length
!= rx_word_length
)
608 /* First we wait for the transmitter to be ready */
609 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
610 while (!(spcr2
& XRDY
)) {
611 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
612 if (attempts
++ > 1000) {
613 /* We must reset the transmitter */
614 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
& (~XRST
));
616 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
| XRST
);
618 dev_err(mcbsp
->dev
, "McBSP%d transmitter not "
619 "ready\n", mcbsp
->id
);
624 /* We first need to enable the bus clock */
625 if (tx_word_length
> OMAP_MCBSP_WORD_16
)
626 OMAP_MCBSP_WRITE(io_base
, DXR2
, clock_word
>> 16);
627 OMAP_MCBSP_WRITE(io_base
, DXR1
, clock_word
& 0xffff);
629 /* We wait for the receiver to be ready */
630 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
631 while (!(spcr1
& RRDY
)) {
632 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
633 if (attempts
++ > 1000) {
634 /* We must reset the receiver */
635 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
& (~RRST
));
637 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
| RRST
);
639 dev_err(mcbsp
->dev
, "McBSP%d receiver not "
640 "ready\n", mcbsp
->id
);
645 /* Receiver is ready, there is something for us */
646 if (rx_word_length
> OMAP_MCBSP_WORD_16
)
647 word_msb
= OMAP_MCBSP_READ(io_base
, DRR2
);
648 word_lsb
= OMAP_MCBSP_READ(io_base
, DRR1
);
650 word
[0] = (word_lsb
| (word_msb
<< 16));
654 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll
);
657 * Simple DMA based buffer rx/tx routines.
658 * Nothing fancy, just a single buffer tx/rx through DMA.
659 * The DMA resources are released once the transfer is done.
660 * For anything fancier, you should use your own customized DMA
661 * routines and callbacks.
663 int omap_mcbsp_xmit_buffer(unsigned int id
, dma_addr_t buffer
,
666 struct omap_mcbsp
*mcbsp
;
672 if (!omap_mcbsp_check_valid_id(id
)) {
673 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
676 mcbsp
= id_to_mcbsp_ptr(id
);
678 if (omap_request_dma(mcbsp
->dma_tx_sync
, "McBSP TX",
679 omap_mcbsp_tx_dma_callback
,
682 dev_err(mcbsp
->dev
, " Unable to request DMA channel for "
683 "McBSP%d TX. Trying IRQ based TX\n",
687 mcbsp
->dma_tx_lch
= dma_tx_ch
;
689 dev_err(mcbsp
->dev
, "McBSP%d TX DMA on channel %d\n", mcbsp
->id
,
692 init_completion(&mcbsp
->tx_dma_completion
);
694 if (cpu_class_is_omap1()) {
695 src_port
= OMAP_DMA_PORT_TIPB
;
696 dest_port
= OMAP_DMA_PORT_EMIFF
;
698 if (cpu_class_is_omap2())
699 sync_dev
= mcbsp
->dma_tx_sync
;
701 omap_set_dma_transfer_params(mcbsp
->dma_tx_lch
,
702 OMAP_DMA_DATA_TYPE_S16
,
704 OMAP_DMA_SYNC_ELEMENT
,
707 omap_set_dma_dest_params(mcbsp
->dma_tx_lch
,
709 OMAP_DMA_AMODE_CONSTANT
,
710 mcbsp
->phys_base
+ OMAP_MCBSP_REG_DXR1
,
713 omap_set_dma_src_params(mcbsp
->dma_tx_lch
,
715 OMAP_DMA_AMODE_POST_INC
,
719 omap_start_dma(mcbsp
->dma_tx_lch
);
720 wait_for_completion(&mcbsp
->tx_dma_completion
);
724 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer
);
726 int omap_mcbsp_recv_buffer(unsigned int id
, dma_addr_t buffer
,
729 struct omap_mcbsp
*mcbsp
;
735 if (!omap_mcbsp_check_valid_id(id
)) {
736 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
739 mcbsp
= id_to_mcbsp_ptr(id
);
741 if (omap_request_dma(mcbsp
->dma_rx_sync
, "McBSP RX",
742 omap_mcbsp_rx_dma_callback
,
745 dev_err(mcbsp
->dev
, "Unable to request DMA channel for "
746 "McBSP%d RX. Trying IRQ based RX\n",
750 mcbsp
->dma_rx_lch
= dma_rx_ch
;
752 dev_err(mcbsp
->dev
, "McBSP%d RX DMA on channel %d\n", mcbsp
->id
,
755 init_completion(&mcbsp
->rx_dma_completion
);
757 if (cpu_class_is_omap1()) {
758 src_port
= OMAP_DMA_PORT_TIPB
;
759 dest_port
= OMAP_DMA_PORT_EMIFF
;
761 if (cpu_class_is_omap2())
762 sync_dev
= mcbsp
->dma_rx_sync
;
764 omap_set_dma_transfer_params(mcbsp
->dma_rx_lch
,
765 OMAP_DMA_DATA_TYPE_S16
,
767 OMAP_DMA_SYNC_ELEMENT
,
770 omap_set_dma_src_params(mcbsp
->dma_rx_lch
,
772 OMAP_DMA_AMODE_CONSTANT
,
773 mcbsp
->phys_base
+ OMAP_MCBSP_REG_DRR1
,
776 omap_set_dma_dest_params(mcbsp
->dma_rx_lch
,
778 OMAP_DMA_AMODE_POST_INC
,
782 omap_start_dma(mcbsp
->dma_rx_lch
);
783 wait_for_completion(&mcbsp
->rx_dma_completion
);
787 EXPORT_SYMBOL(omap_mcbsp_recv_buffer
);
791 * Since SPI setup is much simpler than the generic McBSP one,
792 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
793 * Once this is done, you can call omap_mcbsp_start().
795 void omap_mcbsp_set_spi_mode(unsigned int id
,
796 const struct omap_mcbsp_spi_cfg
*spi_cfg
)
798 struct omap_mcbsp
*mcbsp
;
799 struct omap_mcbsp_reg_cfg mcbsp_cfg
;
801 if (!omap_mcbsp_check_valid_id(id
)) {
802 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
805 mcbsp
= id_to_mcbsp_ptr(id
);
807 memset(&mcbsp_cfg
, 0, sizeof(struct omap_mcbsp_reg_cfg
));
809 /* SPI has only one frame */
810 mcbsp_cfg
.rcr1
|= (RWDLEN1(spi_cfg
->word_length
) | RFRLEN1(0));
811 mcbsp_cfg
.xcr1
|= (XWDLEN1(spi_cfg
->word_length
) | XFRLEN1(0));
813 /* Clock stop mode */
814 if (spi_cfg
->clk_stp_mode
== OMAP_MCBSP_CLK_STP_MODE_NO_DELAY
)
815 mcbsp_cfg
.spcr1
|= (1 << 12);
817 mcbsp_cfg
.spcr1
|= (3 << 11);
819 /* Set clock parities */
820 if (spi_cfg
->rx_clock_polarity
== OMAP_MCBSP_CLK_RISING
)
821 mcbsp_cfg
.pcr0
|= CLKRP
;
823 mcbsp_cfg
.pcr0
&= ~CLKRP
;
825 if (spi_cfg
->tx_clock_polarity
== OMAP_MCBSP_CLK_RISING
)
826 mcbsp_cfg
.pcr0
&= ~CLKXP
;
828 mcbsp_cfg
.pcr0
|= CLKXP
;
830 /* Set SCLKME to 0 and CLKSM to 1 */
831 mcbsp_cfg
.pcr0
&= ~SCLKME
;
832 mcbsp_cfg
.srgr2
|= CLKSM
;
835 if (spi_cfg
->fsx_polarity
== OMAP_MCBSP_FS_ACTIVE_HIGH
)
836 mcbsp_cfg
.pcr0
&= ~FSXP
;
838 mcbsp_cfg
.pcr0
|= FSXP
;
840 if (spi_cfg
->spi_mode
== OMAP_MCBSP_SPI_MASTER
) {
841 mcbsp_cfg
.pcr0
|= CLKXM
;
842 mcbsp_cfg
.srgr1
|= CLKGDV(spi_cfg
->clk_div
- 1);
843 mcbsp_cfg
.pcr0
|= FSXM
;
844 mcbsp_cfg
.srgr2
&= ~FSGM
;
845 mcbsp_cfg
.xcr2
|= XDATDLY(1);
846 mcbsp_cfg
.rcr2
|= RDATDLY(1);
848 mcbsp_cfg
.pcr0
&= ~CLKXM
;
849 mcbsp_cfg
.srgr1
|= CLKGDV(1);
850 mcbsp_cfg
.pcr0
&= ~FSXM
;
851 mcbsp_cfg
.xcr2
&= ~XDATDLY(3);
852 mcbsp_cfg
.rcr2
&= ~RDATDLY(3);
855 mcbsp_cfg
.xcr2
&= ~XPHASE
;
856 mcbsp_cfg
.rcr2
&= ~RPHASE
;
858 omap_mcbsp_config(id
, &mcbsp_cfg
);
860 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode
);
863 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
864 * 730 has only 2 McBSP, and both of them are MPU peripherals.
866 static int __devinit
omap_mcbsp_probe(struct platform_device
*pdev
)
868 struct omap_mcbsp_platform_data
*pdata
= pdev
->dev
.platform_data
;
869 struct omap_mcbsp
*mcbsp
;
870 int id
= pdev
->id
- 1;
874 dev_err(&pdev
->dev
, "McBSP device initialized without"
880 dev_dbg(&pdev
->dev
, "Initializing OMAP McBSP (%d).\n", pdev
->id
);
882 if (id
>= omap_mcbsp_count
) {
883 dev_err(&pdev
->dev
, "Invalid McBSP device id (%d)\n", id
);
888 mcbsp
= kzalloc(sizeof(struct omap_mcbsp
), GFP_KERNEL
);
893 mcbsp_ptr
[id
] = mcbsp
;
895 spin_lock_init(&mcbsp
->lock
);
898 mcbsp
->dma_tx_lch
= -1;
899 mcbsp
->dma_rx_lch
= -1;
901 mcbsp
->phys_base
= pdata
->phys_base
;
902 mcbsp
->io_base
= ioremap(pdata
->phys_base
, SZ_4K
);
903 if (!mcbsp
->io_base
) {
908 /* Default I/O is IRQ based */
909 mcbsp
->io_type
= OMAP_MCBSP_IRQ_IO
;
910 mcbsp
->tx_irq
= pdata
->tx_irq
;
911 mcbsp
->rx_irq
= pdata
->rx_irq
;
912 mcbsp
->dma_rx_sync
= pdata
->dma_rx_sync
;
913 mcbsp
->dma_tx_sync
= pdata
->dma_tx_sync
;
916 mcbsp
->clk
= clk_get(&pdev
->dev
, pdata
->clk_name
);
917 if (IS_ERR(mcbsp
->clk
)) {
919 "Invalid clock configuration for McBSP%d.\n",
921 ret
= PTR_ERR(mcbsp
->clk
);
925 mcbsp
->pdata
= pdata
;
926 mcbsp
->dev
= &pdev
->dev
;
927 platform_set_drvdata(pdev
, mcbsp
);
931 iounmap(mcbsp
->io_base
);
938 static int __devexit
omap_mcbsp_remove(struct platform_device
*pdev
)
940 struct omap_mcbsp
*mcbsp
= platform_get_drvdata(pdev
);
942 platform_set_drvdata(pdev
, NULL
);
945 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&&
946 mcbsp
->pdata
->ops
->free
)
947 mcbsp
->pdata
->ops
->free(mcbsp
->id
);
949 clk_disable(mcbsp
->clk
);
952 iounmap(mcbsp
->io_base
);
962 static struct platform_driver omap_mcbsp_driver
= {
963 .probe
= omap_mcbsp_probe
,
964 .remove
= __devexit_p(omap_mcbsp_remove
),
966 .name
= "omap-mcbsp",
970 int __init
omap_mcbsp_init(void)
972 /* Register the McBSP driver */
973 return platform_driver_register(&omap_mcbsp_driver
);