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e1000e: enable new 82567V-3 device
[linux-2.6/mini2440.git] / drivers / net / tg3.c
blobdcc1c23aab81b889b6a8bc24be0f829a2f856651
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0 0
59 #define BAR_2 2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.102"
72 #define DRV_MODULE_RELDATE "September 1, 2009"
73
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90 #define TG3_TX_TIMEOUT (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105 #define TG3_RSS_INDIR_TBL_SIZE 128
106
107 /* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
112 */
113 #define TG3_RX_RCB_RING_SIZE(tp) \
114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
116
117 #define TG3_TX_RING_SIZE 512
118 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119
120 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_RING_SIZE)
122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
125 TG3_RX_RCB_RING_SIZE(tp))
126 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 TG3_TX_RING_SIZE)
128 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129
130 #define TG3_DMA_BYTE_ENAB 64
131
132 #define TG3_RX_STD_DMA_SZ 1536
133 #define TG3_RX_JMB_DMA_SZ 9046
134
135 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136
137 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139
140 /* minimum number of free TX descriptors required to wake up TX process */
141 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
142
143 #define TG3_RAW_IP_ALIGN 2
144
145 /* number of ETHTOOL_GSTATS u64's */
146 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
147
148 #define TG3_NUM_TEST 6
149
150 #define FIRMWARE_TG3 "tigon/tg3.bin"
151 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
152 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
153
154 static char version[] __devinitdata =
155 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
156
157 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
158 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
159 MODULE_LICENSE("GPL");
160 MODULE_VERSION(DRV_MODULE_VERSION);
161 MODULE_FIRMWARE(FIRMWARE_TG3);
162 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
163 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
164
165 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
166
167 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
168 module_param(tg3_debug, int, 0);
169 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
170
171 static struct pci_device_id tg3_pci_tbl[] = {
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
238 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
239 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
242 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
243 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
244 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
245 {}
246 };
247
248 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
249
250 static const struct {
251 const char string[ETH_GSTRING_LEN];
252 } ethtool_stats_keys[TG3_NUM_STATS] = {
253 { "rx_octets" },
254 { "rx_fragments" },
255 { "rx_ucast_packets" },
256 { "rx_mcast_packets" },
257 { "rx_bcast_packets" },
258 { "rx_fcs_errors" },
259 { "rx_align_errors" },
260 { "rx_xon_pause_rcvd" },
261 { "rx_xoff_pause_rcvd" },
262 { "rx_mac_ctrl_rcvd" },
263 { "rx_xoff_entered" },
264 { "rx_frame_too_long_errors" },
265 { "rx_jabbers" },
266 { "rx_undersize_packets" },
267 { "rx_in_length_errors" },
268 { "rx_out_length_errors" },
269 { "rx_64_or_less_octet_packets" },
270 { "rx_65_to_127_octet_packets" },
271 { "rx_128_to_255_octet_packets" },
272 { "rx_256_to_511_octet_packets" },
273 { "rx_512_to_1023_octet_packets" },
274 { "rx_1024_to_1522_octet_packets" },
275 { "rx_1523_to_2047_octet_packets" },
276 { "rx_2048_to_4095_octet_packets" },
277 { "rx_4096_to_8191_octet_packets" },
278 { "rx_8192_to_9022_octet_packets" },
279
280 { "tx_octets" },
281 { "tx_collisions" },
282
283 { "tx_xon_sent" },
284 { "tx_xoff_sent" },
285 { "tx_flow_control" },
286 { "tx_mac_errors" },
287 { "tx_single_collisions" },
288 { "tx_mult_collisions" },
289 { "tx_deferred" },
290 { "tx_excessive_collisions" },
291 { "tx_late_collisions" },
292 { "tx_collide_2times" },
293 { "tx_collide_3times" },
294 { "tx_collide_4times" },
295 { "tx_collide_5times" },
296 { "tx_collide_6times" },
297 { "tx_collide_7times" },
298 { "tx_collide_8times" },
299 { "tx_collide_9times" },
300 { "tx_collide_10times" },
301 { "tx_collide_11times" },
302 { "tx_collide_12times" },
303 { "tx_collide_13times" },
304 { "tx_collide_14times" },
305 { "tx_collide_15times" },
306 { "tx_ucast_packets" },
307 { "tx_mcast_packets" },
308 { "tx_bcast_packets" },
309 { "tx_carrier_sense_errors" },
310 { "tx_discards" },
311 { "tx_errors" },
312
313 { "dma_writeq_full" },
314 { "dma_write_prioq_full" },
315 { "rxbds_empty" },
316 { "rx_discards" },
317 { "rx_errors" },
318 { "rx_threshold_hit" },
319
320 { "dma_readq_full" },
321 { "dma_read_prioq_full" },
322 { "tx_comp_queue_full" },
323
324 { "ring_set_send_prod_index" },
325 { "ring_status_update" },
326 { "nic_irqs" },
327 { "nic_avoided_irqs" },
328 { "nic_tx_threshold_hit" }
329 };
330
331 static const struct {
332 const char string[ETH_GSTRING_LEN];
333 } ethtool_test_keys[TG3_NUM_TEST] = {
334 { "nvram test (online) " },
335 { "link test (online) " },
336 { "register test (offline)" },
337 { "memory test (offline)" },
338 { "loopback test (offline)" },
339 { "interrupt test (offline)" },
340 };
341
342 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
343 {
344 writel(val, tp->regs + off);
345 }
346
347 static u32 tg3_read32(struct tg3 *tp, u32 off)
348 {
349 return (readl(tp->regs + off));
350 }
351
352 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
353 {
354 writel(val, tp->aperegs + off);
355 }
356
357 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
358 {
359 return (readl(tp->aperegs + off));
360 }
361
362 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
363 {
364 unsigned long flags;
365
366 spin_lock_irqsave(&tp->indirect_lock, flags);
367 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
368 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
369 spin_unlock_irqrestore(&tp->indirect_lock, flags);
370 }
371
372 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
373 {
374 writel(val, tp->regs + off);
375 readl(tp->regs + off);
376 }
377
378 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
379 {
380 unsigned long flags;
381 u32 val;
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
385 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
386 spin_unlock_irqrestore(&tp->indirect_lock, flags);
387 return val;
388 }
389
390 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
391 {
392 unsigned long flags;
393
394 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
395 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
396 TG3_64BIT_REG_LOW, val);
397 return;
398 }
399 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
400 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
401 TG3_64BIT_REG_LOW, val);
402 return;
403 }
404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409
410 /* In indirect mode when disabling interrupts, we also need
411 * to clear the interrupt bit in the GRC local ctrl register.
412 */
413 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
414 (val == 0x1)) {
415 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
416 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
417 }
418 }
419
420 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
421 {
422 unsigned long flags;
423 u32 val;
424
425 spin_lock_irqsave(&tp->indirect_lock, flags);
426 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
427 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
428 spin_unlock_irqrestore(&tp->indirect_lock, flags);
429 return val;
430 }
431
432 /* usec_wait specifies the wait time in usec when writing to certain registers
433 * where it is unsafe to read back the register without some delay.
434 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
435 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
436 */
437 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
438 {
439 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
440 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
441 /* Non-posted methods */
442 tp->write32(tp, off, val);
443 else {
444 /* Posted method */
445 tg3_write32(tp, off, val);
446 if (usec_wait)
447 udelay(usec_wait);
448 tp->read32(tp, off);
449 }
450 /* Wait again after the read for the posted method to guarantee that
451 * the wait time is met.
452 */
453 if (usec_wait)
454 udelay(usec_wait);
455 }
456
457 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
458 {
459 tp->write32_mbox(tp, off, val);
460 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
461 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
462 tp->read32_mbox(tp, off);
463 }
464
465 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
466 {
467 void __iomem *mbox = tp->regs + off;
468 writel(val, mbox);
469 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
470 writel(val, mbox);
471 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
472 readl(mbox);
473 }
474
475 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
476 {
477 return (readl(tp->regs + off + GRCMBOX_BASE));
478 }
479
480 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
481 {
482 writel(val, tp->regs + off + GRCMBOX_BASE);
483 }
484
485 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
486 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
487 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
488 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
489 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
490
491 #define tw32(reg,val) tp->write32(tp, reg, val)
492 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
493 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
494 #define tr32(reg) tp->read32(tp, reg)
495
496 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
497 {
498 unsigned long flags;
499
500 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
501 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
502 return;
503
504 spin_lock_irqsave(&tp->indirect_lock, flags);
505 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
506 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
507 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
508
509 /* Always leave this as zero. */
510 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
511 } else {
512 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
513 tw32_f(TG3PCI_MEM_WIN_DATA, val);
514
515 /* Always leave this as zero. */
516 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
517 }
518 spin_unlock_irqrestore(&tp->indirect_lock, flags);
519 }
520
521 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
522 {
523 unsigned long flags;
524
525 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
526 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
527 *val = 0;
528 return;
529 }
530
531 spin_lock_irqsave(&tp->indirect_lock, flags);
532 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
533 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
534 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
535
536 /* Always leave this as zero. */
537 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
538 } else {
539 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
540 *val = tr32(TG3PCI_MEM_WIN_DATA);
541
542 /* Always leave this as zero. */
543 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
544 }
545 spin_unlock_irqrestore(&tp->indirect_lock, flags);
546 }
547
548 static void tg3_ape_lock_init(struct tg3 *tp)
549 {
550 int i;
551
552 /* Make sure the driver hasn't any stale locks. */
553 for (i = 0; i < 8; i++)
554 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
555 APE_LOCK_GRANT_DRIVER);
556 }
557
558 static int tg3_ape_lock(struct tg3 *tp, int locknum)
559 {
560 int i, off;
561 int ret = 0;
562 u32 status;
563
564 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
565 return 0;
566
567 switch (locknum) {
568 case TG3_APE_LOCK_GRC:
569 case TG3_APE_LOCK_MEM:
570 break;
571 default:
572 return -EINVAL;
573 }
574
575 off = 4 * locknum;
576
577 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
578
579 /* Wait for up to 1 millisecond to acquire lock. */
580 for (i = 0; i < 100; i++) {
581 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
582 if (status == APE_LOCK_GRANT_DRIVER)
583 break;
584 udelay(10);
585 }
586
587 if (status != APE_LOCK_GRANT_DRIVER) {
588 /* Revoke the lock request. */
589 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
590 APE_LOCK_GRANT_DRIVER);
591
592 ret = -EBUSY;
593 }
594
595 return ret;
596 }
597
598 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
599 {
600 int off;
601
602 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
603 return;
604
605 switch (locknum) {
606 case TG3_APE_LOCK_GRC:
607 case TG3_APE_LOCK_MEM:
608 break;
609 default:
610 return;
611 }
612
613 off = 4 * locknum;
614 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
615 }
616
617 static void tg3_disable_ints(struct tg3 *tp)
618 {
619 int i;
620
621 tw32(TG3PCI_MISC_HOST_CTRL,
622 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
623 for (i = 0; i < tp->irq_max; i++)
624 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
625 }
626
627 static void tg3_enable_ints(struct tg3 *tp)
628 {
629 int i;
630 u32 coal_now = 0;
631
632 tp->irq_sync = 0;
633 wmb();
634
635 tw32(TG3PCI_MISC_HOST_CTRL,
636 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
637
638 for (i = 0; i < tp->irq_cnt; i++) {
639 struct tg3_napi *tnapi = &tp->napi[i];
640 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
641 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
642 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
643
644 coal_now |= tnapi->coal_now;
645 }
646
647 /* Force an initial interrupt */
648 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
649 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
650 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
651 else
652 tw32(HOSTCC_MODE, tp->coalesce_mode |
653 HOSTCC_MODE_ENABLE | coal_now);
654 }
655
656 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
657 {
658 struct tg3 *tp = tnapi->tp;
659 struct tg3_hw_status *sblk = tnapi->hw_status;
660 unsigned int work_exists = 0;
661
662 /* check for phy events */
663 if (!(tp->tg3_flags &
664 (TG3_FLAG_USE_LINKCHG_REG |
665 TG3_FLAG_POLL_SERDES))) {
666 if (sblk->status & SD_STATUS_LINK_CHG)
667 work_exists = 1;
668 }
669 /* check for RX/TX work to do */
670 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
671 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
672 work_exists = 1;
673
674 return work_exists;
675 }
676
677 /* tg3_int_reenable
678 * similar to tg3_enable_ints, but it accurately determines whether there
679 * is new work pending and can return without flushing the PIO write
680 * which reenables interrupts
681 */
682 static void tg3_int_reenable(struct tg3_napi *tnapi)
683 {
684 struct tg3 *tp = tnapi->tp;
685
686 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
687 mmiowb();
688
689 /* When doing tagged status, this work check is unnecessary.
690 * The last_tag we write above tells the chip which piece of
691 * work we've completed.
692 */
693 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
694 tg3_has_work(tnapi))
695 tw32(HOSTCC_MODE, tp->coalesce_mode |
696 HOSTCC_MODE_ENABLE | tnapi->coal_now);
697 }
698
699 static void tg3_napi_disable(struct tg3 *tp)
700 {
701 int i;
702
703 for (i = tp->irq_cnt - 1; i >= 0; i--)
704 napi_disable(&tp->napi[i].napi);
705 }
706
707 static void tg3_napi_enable(struct tg3 *tp)
708 {
709 int i;
710
711 for (i = 0; i < tp->irq_cnt; i++)
712 napi_enable(&tp->napi[i].napi);
713 }
714
715 static inline void tg3_netif_stop(struct tg3 *tp)
716 {
717 tp->dev->trans_start = jiffies; /* prevent tx timeout */
718 tg3_napi_disable(tp);
719 netif_tx_disable(tp->dev);
720 }
721
722 static inline void tg3_netif_start(struct tg3 *tp)
723 {
724 /* NOTE: unconditional netif_tx_wake_all_queues is only
725 * appropriate so long as all callers are assured to
726 * have free tx slots (such as after tg3_init_hw)
727 */
728 netif_tx_wake_all_queues(tp->dev);
729
730 tg3_napi_enable(tp);
731 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
732 tg3_enable_ints(tp);
733 }
734
735 static void tg3_switch_clocks(struct tg3 *tp)
736 {
737 u32 clock_ctrl;
738 u32 orig_clock_ctrl;
739
740 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
741 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
742 return;
743
744 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
745
746 orig_clock_ctrl = clock_ctrl;
747 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
748 CLOCK_CTRL_CLKRUN_OENABLE |
749 0x1f);
750 tp->pci_clock_ctrl = clock_ctrl;
751
752 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
753 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
754 tw32_wait_f(TG3PCI_CLOCK_CTRL,
755 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
756 }
757 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
758 tw32_wait_f(TG3PCI_CLOCK_CTRL,
759 clock_ctrl |
760 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
761 40);
762 tw32_wait_f(TG3PCI_CLOCK_CTRL,
763 clock_ctrl | (CLOCK_CTRL_ALTCLK),
764 40);
765 }
766 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
767 }
768
769 #define PHY_BUSY_LOOPS 5000
770
771 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
772 {
773 u32 frame_val;
774 unsigned int loops;
775 int ret;
776
777 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
778 tw32_f(MAC_MI_MODE,
779 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
780 udelay(80);
781 }
782
783 *val = 0x0;
784
785 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
786 MI_COM_PHY_ADDR_MASK);
787 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
788 MI_COM_REG_ADDR_MASK);
789 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
790
791 tw32_f(MAC_MI_COM, frame_val);
792
793 loops = PHY_BUSY_LOOPS;
794 while (loops != 0) {
795 udelay(10);
796 frame_val = tr32(MAC_MI_COM);
797
798 if ((frame_val & MI_COM_BUSY) == 0) {
799 udelay(5);
800 frame_val = tr32(MAC_MI_COM);
801 break;
802 }
803 loops -= 1;
804 }
805
806 ret = -EBUSY;
807 if (loops != 0) {
808 *val = frame_val & MI_COM_DATA_MASK;
809 ret = 0;
810 }
811
812 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
813 tw32_f(MAC_MI_MODE, tp->mi_mode);
814 udelay(80);
815 }
816
817 return ret;
818 }
819
820 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
821 {
822 u32 frame_val;
823 unsigned int loops;
824 int ret;
825
826 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
827 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
828 return 0;
829
830 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
831 tw32_f(MAC_MI_MODE,
832 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
833 udelay(80);
834 }
835
836 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
837 MI_COM_PHY_ADDR_MASK);
838 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
839 MI_COM_REG_ADDR_MASK);
840 frame_val |= (val & MI_COM_DATA_MASK);
841 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
842
843 tw32_f(MAC_MI_COM, frame_val);
844
845 loops = PHY_BUSY_LOOPS;
846 while (loops != 0) {
847 udelay(10);
848 frame_val = tr32(MAC_MI_COM);
849 if ((frame_val & MI_COM_BUSY) == 0) {
850 udelay(5);
851 frame_val = tr32(MAC_MI_COM);
852 break;
853 }
854 loops -= 1;
855 }
856
857 ret = -EBUSY;
858 if (loops != 0)
859 ret = 0;
860
861 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
862 tw32_f(MAC_MI_MODE, tp->mi_mode);
863 udelay(80);
864 }
865
866 return ret;
867 }
868
869 static int tg3_bmcr_reset(struct tg3 *tp)
870 {
871 u32 phy_control;
872 int limit, err;
873
874 /* OK, reset it, and poll the BMCR_RESET bit until it
875 * clears or we time out.
876 */
877 phy_control = BMCR_RESET;
878 err = tg3_writephy(tp, MII_BMCR, phy_control);
879 if (err != 0)
880 return -EBUSY;
881
882 limit = 5000;
883 while (limit--) {
884 err = tg3_readphy(tp, MII_BMCR, &phy_control);
885 if (err != 0)
886 return -EBUSY;
887
888 if ((phy_control & BMCR_RESET) == 0) {
889 udelay(40);
890 break;
891 }
892 udelay(10);
893 }
894 if (limit < 0)
895 return -EBUSY;
896
897 return 0;
898 }
899
900 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
901 {
902 struct tg3 *tp = bp->priv;
903 u32 val;
904
905 spin_lock_bh(&tp->lock);
906
907 if (tg3_readphy(tp, reg, &val))
908 val = -EIO;
909
910 spin_unlock_bh(&tp->lock);
911
912 return val;
913 }
914
915 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
916 {
917 struct tg3 *tp = bp->priv;
918 u32 ret = 0;
919
920 spin_lock_bh(&tp->lock);
921
922 if (tg3_writephy(tp, reg, val))
923 ret = -EIO;
924
925 spin_unlock_bh(&tp->lock);
926
927 return ret;
928 }
929
930 static int tg3_mdio_reset(struct mii_bus *bp)
931 {
932 return 0;
933 }
934
935 static void tg3_mdio_config_5785(struct tg3 *tp)
936 {
937 u32 val;
938 struct phy_device *phydev;
939
940 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
941 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
942 case TG3_PHY_ID_BCM50610:
943 val = MAC_PHYCFG2_50610_LED_MODES;
944 break;
945 case TG3_PHY_ID_BCMAC131:
946 val = MAC_PHYCFG2_AC131_LED_MODES;
947 break;
948 case TG3_PHY_ID_RTL8211C:
949 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
950 break;
951 case TG3_PHY_ID_RTL8201E:
952 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
953 break;
954 default:
955 return;
956 }
957
958 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
959 tw32(MAC_PHYCFG2, val);
960
961 val = tr32(MAC_PHYCFG1);
962 val &= ~(MAC_PHYCFG1_RGMII_INT |
963 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
964 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
965 tw32(MAC_PHYCFG1, val);
966
967 return;
968 }
969
970 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
971 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
972 MAC_PHYCFG2_FMODE_MASK_MASK |
973 MAC_PHYCFG2_GMODE_MASK_MASK |
974 MAC_PHYCFG2_ACT_MASK_MASK |
975 MAC_PHYCFG2_QUAL_MASK_MASK |
976 MAC_PHYCFG2_INBAND_ENABLE;
977
978 tw32(MAC_PHYCFG2, val);
979
980 val = tr32(MAC_PHYCFG1);
981 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
982 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
983 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
984 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
985 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
986 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
987 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
988 }
989 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
990 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
991 tw32(MAC_PHYCFG1, val);
992
993 val = tr32(MAC_EXT_RGMII_MODE);
994 val &= ~(MAC_RGMII_MODE_RX_INT_B |
995 MAC_RGMII_MODE_RX_QUALITY |
996 MAC_RGMII_MODE_RX_ACTIVITY |
997 MAC_RGMII_MODE_RX_ENG_DET |
998 MAC_RGMII_MODE_TX_ENABLE |
999 MAC_RGMII_MODE_TX_LOWPWR |
1000 MAC_RGMII_MODE_TX_RESET);
1001 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1002 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1003 val |= MAC_RGMII_MODE_RX_INT_B |
1004 MAC_RGMII_MODE_RX_QUALITY |
1005 MAC_RGMII_MODE_RX_ACTIVITY |
1006 MAC_RGMII_MODE_RX_ENG_DET;
1007 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1008 val |= MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET;
1011 }
1012 tw32(MAC_EXT_RGMII_MODE, val);
1013 }
1014
1015 static void tg3_mdio_start(struct tg3 *tp)
1016 {
1017 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1018 tw32_f(MAC_MI_MODE, tp->mi_mode);
1019 udelay(80);
1020
1021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1022 u32 funcnum, is_serdes;
1023
1024 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1025 if (funcnum)
1026 tp->phy_addr = 2;
1027 else
1028 tp->phy_addr = 1;
1029
1030 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1031 if (is_serdes)
1032 tp->phy_addr += 7;
1033 } else
1034 tp->phy_addr = PHY_ADDR;
1035
1036 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1037 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1038 tg3_mdio_config_5785(tp);
1039 }
1040
1041 static int tg3_mdio_init(struct tg3 *tp)
1042 {
1043 int i;
1044 u32 reg;
1045 struct phy_device *phydev;
1046
1047 tg3_mdio_start(tp);
1048
1049 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1050 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1051 return 0;
1052
1053 tp->mdio_bus = mdiobus_alloc();
1054 if (tp->mdio_bus == NULL)
1055 return -ENOMEM;
1056
1057 tp->mdio_bus->name = "tg3 mdio bus";
1058 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1059 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1060 tp->mdio_bus->priv = tp;
1061 tp->mdio_bus->parent = &tp->pdev->dev;
1062 tp->mdio_bus->read = &tg3_mdio_read;
1063 tp->mdio_bus->write = &tg3_mdio_write;
1064 tp->mdio_bus->reset = &tg3_mdio_reset;
1065 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1066 tp->mdio_bus->irq = &tp->mdio_irq[0];
1067
1068 for (i = 0; i < PHY_MAX_ADDR; i++)
1069 tp->mdio_bus->irq[i] = PHY_POLL;
1070
1071 /* The bus registration will look for all the PHYs on the mdio bus.
1072 * Unfortunately, it does not ensure the PHY is powered up before
1073 * accessing the PHY ID registers. A chip reset is the
1074 * quickest way to bring the device back to an operational state..
1075 */
1076 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1077 tg3_bmcr_reset(tp);
1078
1079 i = mdiobus_register(tp->mdio_bus);
1080 if (i) {
1081 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1082 tp->dev->name, i);
1083 mdiobus_free(tp->mdio_bus);
1084 return i;
1085 }
1086
1087 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1088
1089 if (!phydev || !phydev->drv) {
1090 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1091 mdiobus_unregister(tp->mdio_bus);
1092 mdiobus_free(tp->mdio_bus);
1093 return -ENODEV;
1094 }
1095
1096 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1097 case TG3_PHY_ID_BCM57780:
1098 phydev->interface = PHY_INTERFACE_MODE_GMII;
1099 break;
1100 case TG3_PHY_ID_BCM50610:
1101 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1102 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1103 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1104 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1105 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1106 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1107 /* fallthru */
1108 case TG3_PHY_ID_RTL8211C:
1109 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1110 break;
1111 case TG3_PHY_ID_RTL8201E:
1112 case TG3_PHY_ID_BCMAC131:
1113 phydev->interface = PHY_INTERFACE_MODE_MII;
1114 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1115 break;
1116 }
1117
1118 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1119
1120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1121 tg3_mdio_config_5785(tp);
1122
1123 return 0;
1124 }
1125
1126 static void tg3_mdio_fini(struct tg3 *tp)
1127 {
1128 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1129 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1130 mdiobus_unregister(tp->mdio_bus);
1131 mdiobus_free(tp->mdio_bus);
1132 }
1133 }
1134
1135 /* tp->lock is held. */
1136 static inline void tg3_generate_fw_event(struct tg3 *tp)
1137 {
1138 u32 val;
1139
1140 val = tr32(GRC_RX_CPU_EVENT);
1141 val |= GRC_RX_CPU_DRIVER_EVENT;
1142 tw32_f(GRC_RX_CPU_EVENT, val);
1143
1144 tp->last_event_jiffies = jiffies;
1145 }
1146
1147 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1148
1149 /* tp->lock is held. */
1150 static void tg3_wait_for_event_ack(struct tg3 *tp)
1151 {
1152 int i;
1153 unsigned int delay_cnt;
1154 long time_remain;
1155
1156 /* If enough time has passed, no wait is necessary. */
1157 time_remain = (long)(tp->last_event_jiffies + 1 +
1158 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1159 (long)jiffies;
1160 if (time_remain < 0)
1161 return;
1162
1163 /* Check if we can shorten the wait time. */
1164 delay_cnt = jiffies_to_usecs(time_remain);
1165 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1166 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1167 delay_cnt = (delay_cnt >> 3) + 1;
1168
1169 for (i = 0; i < delay_cnt; i++) {
1170 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1171 break;
1172 udelay(8);
1173 }
1174 }
1175
1176 /* tp->lock is held. */
1177 static void tg3_ump_link_report(struct tg3 *tp)
1178 {
1179 u32 reg;
1180 u32 val;
1181
1182 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1183 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1184 return;
1185
1186 tg3_wait_for_event_ack(tp);
1187
1188 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1189
1190 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1191
1192 val = 0;
1193 if (!tg3_readphy(tp, MII_BMCR, &reg))
1194 val = reg << 16;
1195 if (!tg3_readphy(tp, MII_BMSR, &reg))
1196 val |= (reg & 0xffff);
1197 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1198
1199 val = 0;
1200 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1201 val = reg << 16;
1202 if (!tg3_readphy(tp, MII_LPA, &reg))
1203 val |= (reg & 0xffff);
1204 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1205
1206 val = 0;
1207 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1208 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1209 val = reg << 16;
1210 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1211 val |= (reg & 0xffff);
1212 }
1213 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1214
1215 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1216 val = reg << 16;
1217 else
1218 val = 0;
1219 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1220
1221 tg3_generate_fw_event(tp);
1222 }
1223
1224 static void tg3_link_report(struct tg3 *tp)
1225 {
1226 if (!netif_carrier_ok(tp->dev)) {
1227 if (netif_msg_link(tp))
1228 printk(KERN_INFO PFX "%s: Link is down.\n",
1229 tp->dev->name);
1230 tg3_ump_link_report(tp);
1231 } else if (netif_msg_link(tp)) {
1232 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1233 tp->dev->name,
1234 (tp->link_config.active_speed == SPEED_1000 ?
1235 1000 :
1236 (tp->link_config.active_speed == SPEED_100 ?
1237 100 : 10)),
1238 (tp->link_config.active_duplex == DUPLEX_FULL ?
1239 "full" : "half"));
1240
1241 printk(KERN_INFO PFX
1242 "%s: Flow control is %s for TX and %s for RX.\n",
1243 tp->dev->name,
1244 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1245 "on" : "off",
1246 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1247 "on" : "off");
1248 tg3_ump_link_report(tp);
1249 }
1250 }
1251
1252 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1253 {
1254 u16 miireg;
1255
1256 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1257 miireg = ADVERTISE_PAUSE_CAP;
1258 else if (flow_ctrl & FLOW_CTRL_TX)
1259 miireg = ADVERTISE_PAUSE_ASYM;
1260 else if (flow_ctrl & FLOW_CTRL_RX)
1261 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1262 else
1263 miireg = 0;
1264
1265 return miireg;
1266 }
1267
1268 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1269 {
1270 u16 miireg;
1271
1272 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1273 miireg = ADVERTISE_1000XPAUSE;
1274 else if (flow_ctrl & FLOW_CTRL_TX)
1275 miireg = ADVERTISE_1000XPSE_ASYM;
1276 else if (flow_ctrl & FLOW_CTRL_RX)
1277 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1278 else
1279 miireg = 0;
1280
1281 return miireg;
1282 }
1283
1284 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1285 {
1286 u8 cap = 0;
1287
1288 if (lcladv & ADVERTISE_1000XPAUSE) {
1289 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1290 if (rmtadv & LPA_1000XPAUSE)
1291 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1292 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1293 cap = FLOW_CTRL_RX;
1294 } else {
1295 if (rmtadv & LPA_1000XPAUSE)
1296 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1297 }
1298 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1299 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1300 cap = FLOW_CTRL_TX;
1301 }
1302
1303 return cap;
1304 }
1305
1306 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1307 {
1308 u8 autoneg;
1309 u8 flowctrl = 0;
1310 u32 old_rx_mode = tp->rx_mode;
1311 u32 old_tx_mode = tp->tx_mode;
1312
1313 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1314 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1315 else
1316 autoneg = tp->link_config.autoneg;
1317
1318 if (autoneg == AUTONEG_ENABLE &&
1319 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1320 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1321 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1322 else
1323 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1324 } else
1325 flowctrl = tp->link_config.flowctrl;
1326
1327 tp->link_config.active_flowctrl = flowctrl;
1328
1329 if (flowctrl & FLOW_CTRL_RX)
1330 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1331 else
1332 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1333
1334 if (old_rx_mode != tp->rx_mode)
1335 tw32_f(MAC_RX_MODE, tp->rx_mode);
1336
1337 if (flowctrl & FLOW_CTRL_TX)
1338 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1339 else
1340 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1341
1342 if (old_tx_mode != tp->tx_mode)
1343 tw32_f(MAC_TX_MODE, tp->tx_mode);
1344 }
1345
1346 static void tg3_adjust_link(struct net_device *dev)
1347 {
1348 u8 oldflowctrl, linkmesg = 0;
1349 u32 mac_mode, lcl_adv, rmt_adv;
1350 struct tg3 *tp = netdev_priv(dev);
1351 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1352
1353 spin_lock_bh(&tp->lock);
1354
1355 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1356 MAC_MODE_HALF_DUPLEX);
1357
1358 oldflowctrl = tp->link_config.active_flowctrl;
1359
1360 if (phydev->link) {
1361 lcl_adv = 0;
1362 rmt_adv = 0;
1363
1364 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1365 mac_mode |= MAC_MODE_PORT_MODE_MII;
1366 else
1367 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1368
1369 if (phydev->duplex == DUPLEX_HALF)
1370 mac_mode |= MAC_MODE_HALF_DUPLEX;
1371 else {
1372 lcl_adv = tg3_advert_flowctrl_1000T(
1373 tp->link_config.flowctrl);
1374
1375 if (phydev->pause)
1376 rmt_adv = LPA_PAUSE_CAP;
1377 if (phydev->asym_pause)
1378 rmt_adv |= LPA_PAUSE_ASYM;
1379 }
1380
1381 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1382 } else
1383 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1384
1385 if (mac_mode != tp->mac_mode) {
1386 tp->mac_mode = mac_mode;
1387 tw32_f(MAC_MODE, tp->mac_mode);
1388 udelay(40);
1389 }
1390
1391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1392 if (phydev->speed == SPEED_10)
1393 tw32(MAC_MI_STAT,
1394 MAC_MI_STAT_10MBPS_MODE |
1395 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1396 else
1397 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1398 }
1399
1400 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1401 tw32(MAC_TX_LENGTHS,
1402 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1403 (6 << TX_LENGTHS_IPG_SHIFT) |
1404 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1405 else
1406 tw32(MAC_TX_LENGTHS,
1407 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1408 (6 << TX_LENGTHS_IPG_SHIFT) |
1409 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1410
1411 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1412 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1413 phydev->speed != tp->link_config.active_speed ||
1414 phydev->duplex != tp->link_config.active_duplex ||
1415 oldflowctrl != tp->link_config.active_flowctrl)
1416 linkmesg = 1;
1417
1418 tp->link_config.active_speed = phydev->speed;
1419 tp->link_config.active_duplex = phydev->duplex;
1420
1421 spin_unlock_bh(&tp->lock);
1422
1423 if (linkmesg)
1424 tg3_link_report(tp);
1425 }
1426
1427 static int tg3_phy_init(struct tg3 *tp)
1428 {
1429 struct phy_device *phydev;
1430
1431 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1432 return 0;
1433
1434 /* Bring the PHY back to a known state. */
1435 tg3_bmcr_reset(tp);
1436
1437 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1438
1439 /* Attach the MAC to the PHY. */
1440 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1441 phydev->dev_flags, phydev->interface);
1442 if (IS_ERR(phydev)) {
1443 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1444 return PTR_ERR(phydev);
1445 }
1446
1447 /* Mask with MAC supported features. */
1448 switch (phydev->interface) {
1449 case PHY_INTERFACE_MODE_GMII:
1450 case PHY_INTERFACE_MODE_RGMII:
1451 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1452 phydev->supported &= (PHY_GBIT_FEATURES |
1453 SUPPORTED_Pause |
1454 SUPPORTED_Asym_Pause);
1455 break;
1456 }
1457 /* fallthru */
1458 case PHY_INTERFACE_MODE_MII:
1459 phydev->supported &= (PHY_BASIC_FEATURES |
1460 SUPPORTED_Pause |
1461 SUPPORTED_Asym_Pause);
1462 break;
1463 default:
1464 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1465 return -EINVAL;
1466 }
1467
1468 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1469
1470 phydev->advertising = phydev->supported;
1471
1472 return 0;
1473 }
1474
1475 static void tg3_phy_start(struct tg3 *tp)
1476 {
1477 struct phy_device *phydev;
1478
1479 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1480 return;
1481
1482 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1483
1484 if (tp->link_config.phy_is_low_power) {
1485 tp->link_config.phy_is_low_power = 0;
1486 phydev->speed = tp->link_config.orig_speed;
1487 phydev->duplex = tp->link_config.orig_duplex;
1488 phydev->autoneg = tp->link_config.orig_autoneg;
1489 phydev->advertising = tp->link_config.orig_advertising;
1490 }
1491
1492 phy_start(phydev);
1493
1494 phy_start_aneg(phydev);
1495 }
1496
1497 static void tg3_phy_stop(struct tg3 *tp)
1498 {
1499 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1500 return;
1501
1502 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1503 }
1504
1505 static void tg3_phy_fini(struct tg3 *tp)
1506 {
1507 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1508 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1509 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1510 }
1511 }
1512
1513 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1514 {
1515 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1516 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1517 }
1518
1519 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1520 {
1521 u32 phytest;
1522
1523 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1524 u32 phy;
1525
1526 tg3_writephy(tp, MII_TG3_FET_TEST,
1527 phytest | MII_TG3_FET_SHADOW_EN);
1528 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1529 if (enable)
1530 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1531 else
1532 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1533 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1534 }
1535 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1536 }
1537 }
1538
1539 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1540 {
1541 u32 reg;
1542
1543 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1544 return;
1545
1546 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1547 tg3_phy_fet_toggle_apd(tp, enable);
1548 return;
1549 }
1550
1551 reg = MII_TG3_MISC_SHDW_WREN |
1552 MII_TG3_MISC_SHDW_SCR5_SEL |
1553 MII_TG3_MISC_SHDW_SCR5_LPED |
1554 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1555 MII_TG3_MISC_SHDW_SCR5_SDTL |
1556 MII_TG3_MISC_SHDW_SCR5_C125OE;
1557 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1558 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1559
1560 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1561
1562
1563 reg = MII_TG3_MISC_SHDW_WREN |
1564 MII_TG3_MISC_SHDW_APD_SEL |
1565 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1566 if (enable)
1567 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1568
1569 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1570 }
1571
1572 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1573 {
1574 u32 phy;
1575
1576 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1577 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1578 return;
1579
1580 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1581 u32 ephy;
1582
1583 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1584 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1585
1586 tg3_writephy(tp, MII_TG3_FET_TEST,
1587 ephy | MII_TG3_FET_SHADOW_EN);
1588 if (!tg3_readphy(tp, reg, &phy)) {
1589 if (enable)
1590 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1591 else
1592 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1593 tg3_writephy(tp, reg, phy);
1594 }
1595 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1596 }
1597 } else {
1598 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1599 MII_TG3_AUXCTL_SHDWSEL_MISC;
1600 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1601 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1602 if (enable)
1603 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1604 else
1605 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1606 phy |= MII_TG3_AUXCTL_MISC_WREN;
1607 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1608 }
1609 }
1610 }
1611
1612 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1613 {
1614 u32 val;
1615
1616 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1617 return;
1618
1619 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1620 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1621 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1622 (val | (1 << 15) | (1 << 4)));
1623 }
1624
1625 static void tg3_phy_apply_otp(struct tg3 *tp)
1626 {
1627 u32 otp, phy;
1628
1629 if (!tp->phy_otp)
1630 return;
1631
1632 otp = tp->phy_otp;
1633
1634 /* Enable SM_DSP clock and tx 6dB coding. */
1635 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1636 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1637 MII_TG3_AUXCTL_ACTL_TX_6DB;
1638 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1639
1640 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1641 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1642 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1643
1644 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1645 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1646 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1647
1648 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1649 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1650 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1651
1652 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1653 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1654
1655 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1656 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1657
1658 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1659 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1660 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1661
1662 /* Turn off SM_DSP clock. */
1663 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1664 MII_TG3_AUXCTL_ACTL_TX_6DB;
1665 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1666 }
1667
1668 static int tg3_wait_macro_done(struct tg3 *tp)
1669 {
1670 int limit = 100;
1671
1672 while (limit--) {
1673 u32 tmp32;
1674
1675 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1676 if ((tmp32 & 0x1000) == 0)
1677 break;
1678 }
1679 }
1680 if (limit < 0)
1681 return -EBUSY;
1682
1683 return 0;
1684 }
1685
1686 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1687 {
1688 static const u32 test_pat[4][6] = {
1689 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1690 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1691 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1692 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1693 };
1694 int chan;
1695
1696 for (chan = 0; chan < 4; chan++) {
1697 int i;
1698
1699 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1700 (chan * 0x2000) | 0x0200);
1701 tg3_writephy(tp, 0x16, 0x0002);
1702
1703 for (i = 0; i < 6; i++)
1704 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1705 test_pat[chan][i]);
1706
1707 tg3_writephy(tp, 0x16, 0x0202);
1708 if (tg3_wait_macro_done(tp)) {
1709 *resetp = 1;
1710 return -EBUSY;
1711 }
1712
1713 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1714 (chan * 0x2000) | 0x0200);
1715 tg3_writephy(tp, 0x16, 0x0082);
1716 if (tg3_wait_macro_done(tp)) {
1717 *resetp = 1;
1718 return -EBUSY;
1719 }
1720
1721 tg3_writephy(tp, 0x16, 0x0802);
1722 if (tg3_wait_macro_done(tp)) {
1723 *resetp = 1;
1724 return -EBUSY;
1725 }
1726
1727 for (i = 0; i < 6; i += 2) {
1728 u32 low, high;
1729
1730 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1731 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1732 tg3_wait_macro_done(tp)) {
1733 *resetp = 1;
1734 return -EBUSY;
1735 }
1736 low &= 0x7fff;
1737 high &= 0x000f;
1738 if (low != test_pat[chan][i] ||
1739 high != test_pat[chan][i+1]) {
1740 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1741 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1742 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1743
1744 return -EBUSY;
1745 }
1746 }
1747 }
1748
1749 return 0;
1750 }
1751
1752 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1753 {
1754 int chan;
1755
1756 for (chan = 0; chan < 4; chan++) {
1757 int i;
1758
1759 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1760 (chan * 0x2000) | 0x0200);
1761 tg3_writephy(tp, 0x16, 0x0002);
1762 for (i = 0; i < 6; i++)
1763 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1764 tg3_writephy(tp, 0x16, 0x0202);
1765 if (tg3_wait_macro_done(tp))
1766 return -EBUSY;
1767 }
1768
1769 return 0;
1770 }
1771
1772 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1773 {
1774 u32 reg32, phy9_orig;
1775 int retries, do_phy_reset, err;
1776
1777 retries = 10;
1778 do_phy_reset = 1;
1779 do {
1780 if (do_phy_reset) {
1781 err = tg3_bmcr_reset(tp);
1782 if (err)
1783 return err;
1784 do_phy_reset = 0;
1785 }
1786
1787 /* Disable transmitter and interrupt. */
1788 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1789 continue;
1790
1791 reg32 |= 0x3000;
1792 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1793
1794 /* Set full-duplex, 1000 mbps. */
1795 tg3_writephy(tp, MII_BMCR,
1796 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1797
1798 /* Set to master mode. */
1799 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1800 continue;
1801
1802 tg3_writephy(tp, MII_TG3_CTRL,
1803 (MII_TG3_CTRL_AS_MASTER |
1804 MII_TG3_CTRL_ENABLE_AS_MASTER));
1805
1806 /* Enable SM_DSP_CLOCK and 6dB. */
1807 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1808
1809 /* Block the PHY control access. */
1810 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1811 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1812
1813 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1814 if (!err)
1815 break;
1816 } while (--retries);
1817
1818 err = tg3_phy_reset_chanpat(tp);
1819 if (err)
1820 return err;
1821
1822 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1823 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1824
1825 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1826 tg3_writephy(tp, 0x16, 0x0000);
1827
1828 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1829 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1830 /* Set Extended packet length bit for jumbo frames */
1831 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1832 }
1833 else {
1834 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1835 }
1836
1837 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1838
1839 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1840 reg32 &= ~0x3000;
1841 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1842 } else if (!err)
1843 err = -EBUSY;
1844
1845 return err;
1846 }
1847
1848 /* This will reset the tigon3 PHY if there is no valid
1849 * link unless the FORCE argument is non-zero.
1850 */
1851 static int tg3_phy_reset(struct tg3 *tp)
1852 {
1853 u32 cpmuctrl;
1854 u32 phy_status;
1855 int err;
1856
1857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1858 u32 val;
1859
1860 val = tr32(GRC_MISC_CFG);
1861 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1862 udelay(40);
1863 }
1864 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1865 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1866 if (err != 0)
1867 return -EBUSY;
1868
1869 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1870 netif_carrier_off(tp->dev);
1871 tg3_link_report(tp);
1872 }
1873
1874 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1875 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1876 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1877 err = tg3_phy_reset_5703_4_5(tp);
1878 if (err)
1879 return err;
1880 goto out;
1881 }
1882
1883 cpmuctrl = 0;
1884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1885 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1886 cpmuctrl = tr32(TG3_CPMU_CTRL);
1887 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1888 tw32(TG3_CPMU_CTRL,
1889 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1890 }
1891
1892 err = tg3_bmcr_reset(tp);
1893 if (err)
1894 return err;
1895
1896 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1897 u32 phy;
1898
1899 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1900 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1901
1902 tw32(TG3_CPMU_CTRL, cpmuctrl);
1903 }
1904
1905 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1906 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1907 u32 val;
1908
1909 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1910 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1911 CPMU_LSPD_1000MB_MACCLK_12_5) {
1912 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1913 udelay(40);
1914 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1915 }
1916 }
1917
1918 tg3_phy_apply_otp(tp);
1919
1920 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1921 tg3_phy_toggle_apd(tp, true);
1922 else
1923 tg3_phy_toggle_apd(tp, false);
1924
1925 out:
1926 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1927 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1928 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1929 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1930 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1931 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1932 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1933 }
1934 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1935 tg3_writephy(tp, 0x1c, 0x8d68);
1936 tg3_writephy(tp, 0x1c, 0x8d68);
1937 }
1938 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1939 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1940 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1941 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1942 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1943 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1944 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1945 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1946 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1947 }
1948 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1949 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1950 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1951 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1952 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1953 tg3_writephy(tp, MII_TG3_TEST1,
1954 MII_TG3_TEST1_TRIM_EN | 0x4);
1955 } else
1956 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1957 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1958 }
1959 /* Set Extended packet length bit (bit 14) on all chips that */
1960 /* support jumbo frames */
1961 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1962 /* Cannot do read-modify-write on 5401 */
1963 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1964 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1965 u32 phy_reg;
1966
1967 /* Set bit 14 with read-modify-write to preserve other bits */
1968 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1969 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1970 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1971 }
1972
1973 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1974 * jumbo frames transmission.
1975 */
1976 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1977 u32 phy_reg;
1978
1979 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1980 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1981 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1982 }
1983
1984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1985 /* adjust output voltage */
1986 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
1987 }
1988
1989 tg3_phy_toggle_automdix(tp, 1);
1990 tg3_phy_set_wirespeed(tp);
1991 return 0;
1992 }
1993
1994 static void tg3_frob_aux_power(struct tg3 *tp)
1995 {
1996 struct tg3 *tp_peer = tp;
1997
1998 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1999 return;
2000
2001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2003 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2004 struct net_device *dev_peer;
2005
2006 dev_peer = pci_get_drvdata(tp->pdev_peer);
2007 /* remove_one() may have been run on the peer. */
2008 if (!dev_peer)
2009 tp_peer = tp;
2010 else
2011 tp_peer = netdev_priv(dev_peer);
2012 }
2013
2014 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2015 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2016 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2017 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2020 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2021 (GRC_LCLCTRL_GPIO_OE0 |
2022 GRC_LCLCTRL_GPIO_OE1 |
2023 GRC_LCLCTRL_GPIO_OE2 |
2024 GRC_LCLCTRL_GPIO_OUTPUT0 |
2025 GRC_LCLCTRL_GPIO_OUTPUT1),
2026 100);
2027 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2028 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2029 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2030 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2031 GRC_LCLCTRL_GPIO_OE1 |
2032 GRC_LCLCTRL_GPIO_OE2 |
2033 GRC_LCLCTRL_GPIO_OUTPUT0 |
2034 GRC_LCLCTRL_GPIO_OUTPUT1 |
2035 tp->grc_local_ctrl;
2036 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2037
2038 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2039 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2040
2041 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2042 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2043 } else {
2044 u32 no_gpio2;
2045 u32 grc_local_ctrl = 0;
2046
2047 if (tp_peer != tp &&
2048 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2049 return;
2050
2051 /* Workaround to prevent overdrawing Amps. */
2052 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2053 ASIC_REV_5714) {
2054 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2055 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2056 grc_local_ctrl, 100);
2057 }
2058
2059 /* On 5753 and variants, GPIO2 cannot be used. */
2060 no_gpio2 = tp->nic_sram_data_cfg &
2061 NIC_SRAM_DATA_CFG_NO_GPIO2;
2062
2063 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2064 GRC_LCLCTRL_GPIO_OE1 |
2065 GRC_LCLCTRL_GPIO_OE2 |
2066 GRC_LCLCTRL_GPIO_OUTPUT1 |
2067 GRC_LCLCTRL_GPIO_OUTPUT2;
2068 if (no_gpio2) {
2069 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2070 GRC_LCLCTRL_GPIO_OUTPUT2);
2071 }
2072 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2073 grc_local_ctrl, 100);
2074
2075 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2076
2077 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2078 grc_local_ctrl, 100);
2079
2080 if (!no_gpio2) {
2081 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2082 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2083 grc_local_ctrl, 100);
2084 }
2085 }
2086 } else {
2087 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2088 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2089 if (tp_peer != tp &&
2090 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2091 return;
2092
2093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094 (GRC_LCLCTRL_GPIO_OE1 |
2095 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2096
2097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2098 GRC_LCLCTRL_GPIO_OE1, 100);
2099
2100 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2101 (GRC_LCLCTRL_GPIO_OE1 |
2102 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2103 }
2104 }
2105 }
2106
2107 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2108 {
2109 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2110 return 1;
2111 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2112 if (speed != SPEED_10)
2113 return 1;
2114 } else if (speed == SPEED_10)
2115 return 1;
2116
2117 return 0;
2118 }
2119
2120 static int tg3_setup_phy(struct tg3 *, int);
2121
2122 #define RESET_KIND_SHUTDOWN 0
2123 #define RESET_KIND_INIT 1
2124 #define RESET_KIND_SUSPEND 2
2125
2126 static void tg3_write_sig_post_reset(struct tg3 *, int);
2127 static int tg3_halt_cpu(struct tg3 *, u32);
2128
2129 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2130 {
2131 u32 val;
2132
2133 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2135 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2136 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2137
2138 sg_dig_ctrl |=
2139 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2140 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2141 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2142 }
2143 return;
2144 }
2145
2146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2147 tg3_bmcr_reset(tp);
2148 val = tr32(GRC_MISC_CFG);
2149 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2150 udelay(40);
2151 return;
2152 } else if (do_low_power) {
2153 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2154 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2155
2156 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2157 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2158 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2159 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2160 MII_TG3_AUXCTL_PCTL_VREG_11V);
2161 }
2162
2163 /* The PHY should not be powered down on some chips because
2164 * of bugs.
2165 */
2166 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2167 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2168 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2169 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2170 return;
2171
2172 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2173 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2174 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2175 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2176 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2177 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2178 }
2179
2180 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2181 }
2182
2183 /* tp->lock is held. */
2184 static int tg3_nvram_lock(struct tg3 *tp)
2185 {
2186 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2187 int i;
2188
2189 if (tp->nvram_lock_cnt == 0) {
2190 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2191 for (i = 0; i < 8000; i++) {
2192 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2193 break;
2194 udelay(20);
2195 }
2196 if (i == 8000) {
2197 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2198 return -ENODEV;
2199 }
2200 }
2201 tp->nvram_lock_cnt++;
2202 }
2203 return 0;
2204 }
2205
2206 /* tp->lock is held. */
2207 static void tg3_nvram_unlock(struct tg3 *tp)
2208 {
2209 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2210 if (tp->nvram_lock_cnt > 0)
2211 tp->nvram_lock_cnt--;
2212 if (tp->nvram_lock_cnt == 0)
2213 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2214 }
2215 }
2216
2217 /* tp->lock is held. */
2218 static void tg3_enable_nvram_access(struct tg3 *tp)
2219 {
2220 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2221 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2222 u32 nvaccess = tr32(NVRAM_ACCESS);
2223
2224 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2225 }
2226 }
2227
2228 /* tp->lock is held. */
2229 static void tg3_disable_nvram_access(struct tg3 *tp)
2230 {
2231 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2232 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
2233 u32 nvaccess = tr32(NVRAM_ACCESS);
2234
2235 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2236 }
2237 }
2238
2239 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2240 u32 offset, u32 *val)
2241 {
2242 u32 tmp;
2243 int i;
2244
2245 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2246 return -EINVAL;
2247
2248 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2249 EEPROM_ADDR_DEVID_MASK |
2250 EEPROM_ADDR_READ);
2251 tw32(GRC_EEPROM_ADDR,
2252 tmp |
2253 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2254 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2255 EEPROM_ADDR_ADDR_MASK) |
2256 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2257
2258 for (i = 0; i < 1000; i++) {
2259 tmp = tr32(GRC_EEPROM_ADDR);
2260
2261 if (tmp & EEPROM_ADDR_COMPLETE)
2262 break;
2263 msleep(1);
2264 }
2265 if (!(tmp & EEPROM_ADDR_COMPLETE))
2266 return -EBUSY;
2267
2268 tmp = tr32(GRC_EEPROM_DATA);
2269
2270 /*
2271 * The data will always be opposite the native endian
2272 * format. Perform a blind byteswap to compensate.
2273 */
2274 *val = swab32(tmp);
2275
2276 return 0;
2277 }
2278
2279 #define NVRAM_CMD_TIMEOUT 10000
2280
2281 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2282 {
2283 int i;
2284
2285 tw32(NVRAM_CMD, nvram_cmd);
2286 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2287 udelay(10);
2288 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2289 udelay(10);
2290 break;
2291 }
2292 }
2293
2294 if (i == NVRAM_CMD_TIMEOUT)
2295 return -EBUSY;
2296
2297 return 0;
2298 }
2299
2300 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2301 {
2302 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2303 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2304 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2305 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2306 (tp->nvram_jedecnum == JEDEC_ATMEL))
2307
2308 addr = ((addr / tp->nvram_pagesize) <<
2309 ATMEL_AT45DB0X1B_PAGE_POS) +
2310 (addr % tp->nvram_pagesize);
2311
2312 return addr;
2313 }
2314
2315 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2316 {
2317 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2318 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2319 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2320 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2321 (tp->nvram_jedecnum == JEDEC_ATMEL))
2322
2323 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2324 tp->nvram_pagesize) +
2325 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2326
2327 return addr;
2328 }
2329
2330 /* NOTE: Data read in from NVRAM is byteswapped according to
2331 * the byteswapping settings for all other register accesses.
2332 * tg3 devices are BE devices, so on a BE machine, the data
2333 * returned will be exactly as it is seen in NVRAM. On a LE
2334 * machine, the 32-bit value will be byteswapped.
2335 */
2336 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2337 {
2338 int ret;
2339
2340 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2341 return tg3_nvram_read_using_eeprom(tp, offset, val);
2342
2343 offset = tg3_nvram_phys_addr(tp, offset);
2344
2345 if (offset > NVRAM_ADDR_MSK)
2346 return -EINVAL;
2347
2348 ret = tg3_nvram_lock(tp);
2349 if (ret)
2350 return ret;
2351
2352 tg3_enable_nvram_access(tp);
2353
2354 tw32(NVRAM_ADDR, offset);
2355 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2356 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2357
2358 if (ret == 0)
2359 *val = tr32(NVRAM_RDDATA);
2360
2361 tg3_disable_nvram_access(tp);
2362
2363 tg3_nvram_unlock(tp);
2364
2365 return ret;
2366 }
2367
2368 /* Ensures NVRAM data is in bytestream format. */
2369 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2370 {
2371 u32 v;
2372 int res = tg3_nvram_read(tp, offset, &v);
2373 if (!res)
2374 *val = cpu_to_be32(v);
2375 return res;
2376 }
2377
2378 /* tp->lock is held. */
2379 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2380 {
2381 u32 addr_high, addr_low;
2382 int i;
2383
2384 addr_high = ((tp->dev->dev_addr[0] << 8) |
2385 tp->dev->dev_addr[1]);
2386 addr_low = ((tp->dev->dev_addr[2] << 24) |
2387 (tp->dev->dev_addr[3] << 16) |
2388 (tp->dev->dev_addr[4] << 8) |
2389 (tp->dev->dev_addr[5] << 0));
2390 for (i = 0; i < 4; i++) {
2391 if (i == 1 && skip_mac_1)
2392 continue;
2393 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2394 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2395 }
2396
2397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2398 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2399 for (i = 0; i < 12; i++) {
2400 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2401 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2402 }
2403 }
2404
2405 addr_high = (tp->dev->dev_addr[0] +
2406 tp->dev->dev_addr[1] +
2407 tp->dev->dev_addr[2] +
2408 tp->dev->dev_addr[3] +
2409 tp->dev->dev_addr[4] +
2410 tp->dev->dev_addr[5]) &
2411 TX_BACKOFF_SEED_MASK;
2412 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2413 }
2414
2415 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2416 {
2417 u32 misc_host_ctrl;
2418 bool device_should_wake, do_low_power;
2419
2420 /* Make sure register accesses (indirect or otherwise)
2421 * will function correctly.
2422 */
2423 pci_write_config_dword(tp->pdev,
2424 TG3PCI_MISC_HOST_CTRL,
2425 tp->misc_host_ctrl);
2426
2427 switch (state) {
2428 case PCI_D0:
2429 pci_enable_wake(tp->pdev, state, false);
2430 pci_set_power_state(tp->pdev, PCI_D0);
2431
2432 /* Switch out of Vaux if it is a NIC */
2433 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2434 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2435
2436 return 0;
2437
2438 case PCI_D1:
2439 case PCI_D2:
2440 case PCI_D3hot:
2441 break;
2442
2443 default:
2444 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2445 tp->dev->name, state);
2446 return -EINVAL;
2447 }
2448
2449 /* Restore the CLKREQ setting. */
2450 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2451 u16 lnkctl;
2452
2453 pci_read_config_word(tp->pdev,
2454 tp->pcie_cap + PCI_EXP_LNKCTL,
2455 &lnkctl);
2456 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2457 pci_write_config_word(tp->pdev,
2458 tp->pcie_cap + PCI_EXP_LNKCTL,
2459 lnkctl);
2460 }
2461
2462 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2463 tw32(TG3PCI_MISC_HOST_CTRL,
2464 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2465
2466 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2467 device_may_wakeup(&tp->pdev->dev) &&
2468 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2469
2470 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2471 do_low_power = false;
2472 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2473 !tp->link_config.phy_is_low_power) {
2474 struct phy_device *phydev;
2475 u32 phyid, advertising;
2476
2477 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2478
2479 tp->link_config.phy_is_low_power = 1;
2480
2481 tp->link_config.orig_speed = phydev->speed;
2482 tp->link_config.orig_duplex = phydev->duplex;
2483 tp->link_config.orig_autoneg = phydev->autoneg;
2484 tp->link_config.orig_advertising = phydev->advertising;
2485
2486 advertising = ADVERTISED_TP |
2487 ADVERTISED_Pause |
2488 ADVERTISED_Autoneg |
2489 ADVERTISED_10baseT_Half;
2490
2491 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2492 device_should_wake) {
2493 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2494 advertising |=
2495 ADVERTISED_100baseT_Half |
2496 ADVERTISED_100baseT_Full |
2497 ADVERTISED_10baseT_Full;
2498 else
2499 advertising |= ADVERTISED_10baseT_Full;
2500 }
2501
2502 phydev->advertising = advertising;
2503
2504 phy_start_aneg(phydev);
2505
2506 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2507 if (phyid != TG3_PHY_ID_BCMAC131) {
2508 phyid &= TG3_PHY_OUI_MASK;
2509 if (phyid == TG3_PHY_OUI_1 ||
2510 phyid == TG3_PHY_OUI_2 ||
2511 phyid == TG3_PHY_OUI_3)
2512 do_low_power = true;
2513 }
2514 }
2515 } else {
2516 do_low_power = true;
2517
2518 if (tp->link_config.phy_is_low_power == 0) {
2519 tp->link_config.phy_is_low_power = 1;
2520 tp->link_config.orig_speed = tp->link_config.speed;
2521 tp->link_config.orig_duplex = tp->link_config.duplex;
2522 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2523 }
2524
2525 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2526 tp->link_config.speed = SPEED_10;
2527 tp->link_config.duplex = DUPLEX_HALF;
2528 tp->link_config.autoneg = AUTONEG_ENABLE;
2529 tg3_setup_phy(tp, 0);
2530 }
2531 }
2532
2533 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2534 u32 val;
2535
2536 val = tr32(GRC_VCPU_EXT_CTRL);
2537 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2538 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2539 int i;
2540 u32 val;
2541
2542 for (i = 0; i < 200; i++) {
2543 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2544 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2545 break;
2546 msleep(1);
2547 }
2548 }
2549 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2550 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2551 WOL_DRV_STATE_SHUTDOWN |
2552 WOL_DRV_WOL |
2553 WOL_SET_MAGIC_PKT);
2554
2555 if (device_should_wake) {
2556 u32 mac_mode;
2557
2558 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2559 if (do_low_power) {
2560 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2561 udelay(40);
2562 }
2563
2564 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2565 mac_mode = MAC_MODE_PORT_MODE_GMII;
2566 else
2567 mac_mode = MAC_MODE_PORT_MODE_MII;
2568
2569 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2570 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2571 ASIC_REV_5700) {
2572 u32 speed = (tp->tg3_flags &
2573 TG3_FLAG_WOL_SPEED_100MB) ?
2574 SPEED_100 : SPEED_10;
2575 if (tg3_5700_link_polarity(tp, speed))
2576 mac_mode |= MAC_MODE_LINK_POLARITY;
2577 else
2578 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2579 }
2580 } else {
2581 mac_mode = MAC_MODE_PORT_MODE_TBI;
2582 }
2583
2584 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2585 tw32(MAC_LED_CTRL, tp->led_ctrl);
2586
2587 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2588 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2589 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2590 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2591 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2592 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2593
2594 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2595 mac_mode |= tp->mac_mode &
2596 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2597 if (mac_mode & MAC_MODE_APE_TX_EN)
2598 mac_mode |= MAC_MODE_TDE_ENABLE;
2599 }
2600
2601 tw32_f(MAC_MODE, mac_mode);
2602 udelay(100);
2603
2604 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2605 udelay(10);
2606 }
2607
2608 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2609 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2610 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2611 u32 base_val;
2612
2613 base_val = tp->pci_clock_ctrl;
2614 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2615 CLOCK_CTRL_TXCLK_DISABLE);
2616
2617 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2618 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2619 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2620 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2621 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2622 /* do nothing */
2623 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2624 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2625 u32 newbits1, newbits2;
2626
2627 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2628 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2629 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2630 CLOCK_CTRL_TXCLK_DISABLE |
2631 CLOCK_CTRL_ALTCLK);
2632 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2633 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2634 newbits1 = CLOCK_CTRL_625_CORE;
2635 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2636 } else {
2637 newbits1 = CLOCK_CTRL_ALTCLK;
2638 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2639 }
2640
2641 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2642 40);
2643
2644 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2645 40);
2646
2647 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2648 u32 newbits3;
2649
2650 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2651 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2652 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2653 CLOCK_CTRL_TXCLK_DISABLE |
2654 CLOCK_CTRL_44MHZ_CORE);
2655 } else {
2656 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2657 }
2658
2659 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2660 tp->pci_clock_ctrl | newbits3, 40);
2661 }
2662 }
2663
2664 if (!(device_should_wake) &&
2665 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2666 tg3_power_down_phy(tp, do_low_power);
2667
2668 tg3_frob_aux_power(tp);
2669
2670 /* Workaround for unstable PLL clock */
2671 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2672 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2673 u32 val = tr32(0x7d00);
2674
2675 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2676 tw32(0x7d00, val);
2677 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2678 int err;
2679
2680 err = tg3_nvram_lock(tp);
2681 tg3_halt_cpu(tp, RX_CPU_BASE);
2682 if (!err)
2683 tg3_nvram_unlock(tp);
2684 }
2685 }
2686
2687 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2688
2689 if (device_should_wake)
2690 pci_enable_wake(tp->pdev, state, true);
2691
2692 /* Finally, set the new power state. */
2693 pci_set_power_state(tp->pdev, state);
2694
2695 return 0;
2696 }
2697
2698 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2699 {
2700 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2701 case MII_TG3_AUX_STAT_10HALF:
2702 *speed = SPEED_10;
2703 *duplex = DUPLEX_HALF;
2704 break;
2705
2706 case MII_TG3_AUX_STAT_10FULL:
2707 *speed = SPEED_10;
2708 *duplex = DUPLEX_FULL;
2709 break;
2710
2711 case MII_TG3_AUX_STAT_100HALF:
2712 *speed = SPEED_100;
2713 *duplex = DUPLEX_HALF;
2714 break;
2715
2716 case MII_TG3_AUX_STAT_100FULL:
2717 *speed = SPEED_100;
2718 *duplex = DUPLEX_FULL;
2719 break;
2720
2721 case MII_TG3_AUX_STAT_1000HALF:
2722 *speed = SPEED_1000;
2723 *duplex = DUPLEX_HALF;
2724 break;
2725
2726 case MII_TG3_AUX_STAT_1000FULL:
2727 *speed = SPEED_1000;
2728 *duplex = DUPLEX_FULL;
2729 break;
2730
2731 default:
2732 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2733 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2734 SPEED_10;
2735 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2736 DUPLEX_HALF;
2737 break;
2738 }
2739 *speed = SPEED_INVALID;
2740 *duplex = DUPLEX_INVALID;
2741 break;
2742 }
2743 }
2744
2745 static void tg3_phy_copper_begin(struct tg3 *tp)
2746 {
2747 u32 new_adv;
2748 int i;
2749
2750 if (tp->link_config.phy_is_low_power) {
2751 /* Entering low power mode. Disable gigabit and
2752 * 100baseT advertisements.
2753 */
2754 tg3_writephy(tp, MII_TG3_CTRL, 0);
2755
2756 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2757 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2758 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2759 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2760
2761 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2762 } else if (tp->link_config.speed == SPEED_INVALID) {
2763 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2764 tp->link_config.advertising &=
2765 ~(ADVERTISED_1000baseT_Half |
2766 ADVERTISED_1000baseT_Full);
2767
2768 new_adv = ADVERTISE_CSMA;
2769 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2770 new_adv |= ADVERTISE_10HALF;
2771 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2772 new_adv |= ADVERTISE_10FULL;
2773 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2774 new_adv |= ADVERTISE_100HALF;
2775 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2776 new_adv |= ADVERTISE_100FULL;
2777
2778 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2779
2780 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2781
2782 if (tp->link_config.advertising &
2783 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2784 new_adv = 0;
2785 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2786 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2787 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2788 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2789 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2790 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2791 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2792 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2793 MII_TG3_CTRL_ENABLE_AS_MASTER);
2794 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2795 } else {
2796 tg3_writephy(tp, MII_TG3_CTRL, 0);
2797 }
2798 } else {
2799 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2800 new_adv |= ADVERTISE_CSMA;
2801
2802 /* Asking for a specific link mode. */
2803 if (tp->link_config.speed == SPEED_1000) {
2804 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2805
2806 if (tp->link_config.duplex == DUPLEX_FULL)
2807 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2808 else
2809 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2810 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2811 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2812 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2813 MII_TG3_CTRL_ENABLE_AS_MASTER);
2814 } else {
2815 if (tp->link_config.speed == SPEED_100) {
2816 if (tp->link_config.duplex == DUPLEX_FULL)
2817 new_adv |= ADVERTISE_100FULL;
2818 else
2819 new_adv |= ADVERTISE_100HALF;
2820 } else {
2821 if (tp->link_config.duplex == DUPLEX_FULL)
2822 new_adv |= ADVERTISE_10FULL;
2823 else
2824 new_adv |= ADVERTISE_10HALF;
2825 }
2826 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2827
2828 new_adv = 0;
2829 }
2830
2831 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2832 }
2833
2834 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2835 tp->link_config.speed != SPEED_INVALID) {
2836 u32 bmcr, orig_bmcr;
2837
2838 tp->link_config.active_speed = tp->link_config.speed;
2839 tp->link_config.active_duplex = tp->link_config.duplex;
2840
2841 bmcr = 0;
2842 switch (tp->link_config.speed) {
2843 default:
2844 case SPEED_10:
2845 break;
2846
2847 case SPEED_100:
2848 bmcr |= BMCR_SPEED100;
2849 break;
2850
2851 case SPEED_1000:
2852 bmcr |= TG3_BMCR_SPEED1000;
2853 break;
2854 }
2855
2856 if (tp->link_config.duplex == DUPLEX_FULL)
2857 bmcr |= BMCR_FULLDPLX;
2858
2859 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2860 (bmcr != orig_bmcr)) {
2861 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2862 for (i = 0; i < 1500; i++) {
2863 u32 tmp;
2864
2865 udelay(10);
2866 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2867 tg3_readphy(tp, MII_BMSR, &tmp))
2868 continue;
2869 if (!(tmp & BMSR_LSTATUS)) {
2870 udelay(40);
2871 break;
2872 }
2873 }
2874 tg3_writephy(tp, MII_BMCR, bmcr);
2875 udelay(40);
2876 }
2877 } else {
2878 tg3_writephy(tp, MII_BMCR,
2879 BMCR_ANENABLE | BMCR_ANRESTART);
2880 }
2881 }
2882
2883 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2884 {
2885 int err;
2886
2887 /* Turn off tap power management. */
2888 /* Set Extended packet length bit */
2889 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2890
2891 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2892 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2893
2894 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2895 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2896
2897 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2898 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2899
2900 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2901 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2902
2903 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2904 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2905
2906 udelay(40);
2907
2908 return err;
2909 }
2910
2911 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2912 {
2913 u32 adv_reg, all_mask = 0;
2914
2915 if (mask & ADVERTISED_10baseT_Half)
2916 all_mask |= ADVERTISE_10HALF;
2917 if (mask & ADVERTISED_10baseT_Full)
2918 all_mask |= ADVERTISE_10FULL;
2919 if (mask & ADVERTISED_100baseT_Half)
2920 all_mask |= ADVERTISE_100HALF;
2921 if (mask & ADVERTISED_100baseT_Full)
2922 all_mask |= ADVERTISE_100FULL;
2923
2924 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2925 return 0;
2926
2927 if ((adv_reg & all_mask) != all_mask)
2928 return 0;
2929 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2930 u32 tg3_ctrl;
2931
2932 all_mask = 0;
2933 if (mask & ADVERTISED_1000baseT_Half)
2934 all_mask |= ADVERTISE_1000HALF;
2935 if (mask & ADVERTISED_1000baseT_Full)
2936 all_mask |= ADVERTISE_1000FULL;
2937
2938 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2939 return 0;
2940
2941 if ((tg3_ctrl & all_mask) != all_mask)
2942 return 0;
2943 }
2944 return 1;
2945 }
2946
2947 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2948 {
2949 u32 curadv, reqadv;
2950
2951 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2952 return 1;
2953
2954 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2955 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2956
2957 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2958 if (curadv != reqadv)
2959 return 0;
2960
2961 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2962 tg3_readphy(tp, MII_LPA, rmtadv);
2963 } else {
2964 /* Reprogram the advertisement register, even if it
2965 * does not affect the current link. If the link
2966 * gets renegotiated in the future, we can save an
2967 * additional renegotiation cycle by advertising
2968 * it correctly in the first place.
2969 */
2970 if (curadv != reqadv) {
2971 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2972 ADVERTISE_PAUSE_ASYM);
2973 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2974 }
2975 }
2976
2977 return 1;
2978 }
2979
2980 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2981 {
2982 int current_link_up;
2983 u32 bmsr, dummy;
2984 u32 lcl_adv, rmt_adv;
2985 u16 current_speed;
2986 u8 current_duplex;
2987 int i, err;
2988
2989 tw32(MAC_EVENT, 0);
2990
2991 tw32_f(MAC_STATUS,
2992 (MAC_STATUS_SYNC_CHANGED |
2993 MAC_STATUS_CFG_CHANGED |
2994 MAC_STATUS_MI_COMPLETION |
2995 MAC_STATUS_LNKSTATE_CHANGED));
2996 udelay(40);
2997
2998 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2999 tw32_f(MAC_MI_MODE,
3000 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3001 udelay(80);
3002 }
3003
3004 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3005
3006 /* Some third-party PHYs need to be reset on link going
3007 * down.
3008 */
3009 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3012 netif_carrier_ok(tp->dev)) {
3013 tg3_readphy(tp, MII_BMSR, &bmsr);
3014 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3015 !(bmsr & BMSR_LSTATUS))
3016 force_reset = 1;
3017 }
3018 if (force_reset)
3019 tg3_phy_reset(tp);
3020
3021 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3022 tg3_readphy(tp, MII_BMSR, &bmsr);
3023 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3024 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3025 bmsr = 0;
3026
3027 if (!(bmsr & BMSR_LSTATUS)) {
3028 err = tg3_init_5401phy_dsp(tp);
3029 if (err)
3030 return err;
3031
3032 tg3_readphy(tp, MII_BMSR, &bmsr);
3033 for (i = 0; i < 1000; i++) {
3034 udelay(10);
3035 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3036 (bmsr & BMSR_LSTATUS)) {
3037 udelay(40);
3038 break;
3039 }
3040 }
3041
3042 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3043 !(bmsr & BMSR_LSTATUS) &&
3044 tp->link_config.active_speed == SPEED_1000) {
3045 err = tg3_phy_reset(tp);
3046 if (!err)
3047 err = tg3_init_5401phy_dsp(tp);
3048 if (err)
3049 return err;
3050 }
3051 }
3052 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3053 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3054 /* 5701 {A0,B0} CRC bug workaround */
3055 tg3_writephy(tp, 0x15, 0x0a75);
3056 tg3_writephy(tp, 0x1c, 0x8c68);
3057 tg3_writephy(tp, 0x1c, 0x8d68);
3058 tg3_writephy(tp, 0x1c, 0x8c68);
3059 }
3060
3061 /* Clear pending interrupts... */
3062 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3063 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3064
3065 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3066 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3067 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3068 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3069
3070 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3071 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3072 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3073 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3074 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3075 else
3076 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3077 }
3078
3079 current_link_up = 0;
3080 current_speed = SPEED_INVALID;
3081 current_duplex = DUPLEX_INVALID;
3082
3083 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3084 u32 val;
3085
3086 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3087 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3088 if (!(val & (1 << 10))) {
3089 val |= (1 << 10);
3090 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3091 goto relink;
3092 }
3093 }
3094
3095 bmsr = 0;
3096 for (i = 0; i < 100; i++) {
3097 tg3_readphy(tp, MII_BMSR, &bmsr);
3098 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3099 (bmsr & BMSR_LSTATUS))
3100 break;
3101 udelay(40);
3102 }
3103
3104 if (bmsr & BMSR_LSTATUS) {
3105 u32 aux_stat, bmcr;
3106
3107 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3108 for (i = 0; i < 2000; i++) {
3109 udelay(10);
3110 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3111 aux_stat)
3112 break;
3113 }
3114
3115 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3116 &current_speed,
3117 &current_duplex);
3118
3119 bmcr = 0;
3120 for (i = 0; i < 200; i++) {
3121 tg3_readphy(tp, MII_BMCR, &bmcr);
3122 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3123 continue;
3124 if (bmcr && bmcr != 0x7fff)
3125 break;
3126 udelay(10);
3127 }
3128
3129 lcl_adv = 0;
3130 rmt_adv = 0;
3131
3132 tp->link_config.active_speed = current_speed;
3133 tp->link_config.active_duplex = current_duplex;
3134
3135 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3136 if ((bmcr & BMCR_ANENABLE) &&
3137 tg3_copper_is_advertising_all(tp,
3138 tp->link_config.advertising)) {
3139 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3140 &rmt_adv))
3141 current_link_up = 1;
3142 }
3143 } else {
3144 if (!(bmcr & BMCR_ANENABLE) &&
3145 tp->link_config.speed == current_speed &&
3146 tp->link_config.duplex == current_duplex &&
3147 tp->link_config.flowctrl ==
3148 tp->link_config.active_flowctrl) {
3149 current_link_up = 1;
3150 }
3151 }
3152
3153 if (current_link_up == 1 &&
3154 tp->link_config.active_duplex == DUPLEX_FULL)
3155 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3156 }
3157
3158 relink:
3159 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3160 u32 tmp;
3161
3162 tg3_phy_copper_begin(tp);
3163
3164 tg3_readphy(tp, MII_BMSR, &tmp);
3165 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3166 (tmp & BMSR_LSTATUS))
3167 current_link_up = 1;
3168 }
3169
3170 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3171 if (current_link_up == 1) {
3172 if (tp->link_config.active_speed == SPEED_100 ||
3173 tp->link_config.active_speed == SPEED_10)
3174 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3175 else
3176 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3177 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3178 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3179 else
3180 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3181
3182 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3183 if (tp->link_config.active_duplex == DUPLEX_HALF)
3184 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3185
3186 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3187 if (current_link_up == 1 &&
3188 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3189 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3190 else
3191 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3192 }
3193
3194 /* ??? Without this setting Netgear GA302T PHY does not
3195 * ??? send/receive packets...
3196 */
3197 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3198 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3199 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3200 tw32_f(MAC_MI_MODE, tp->mi_mode);
3201 udelay(80);
3202 }
3203
3204 tw32_f(MAC_MODE, tp->mac_mode);
3205 udelay(40);
3206
3207 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3208 /* Polled via timer. */
3209 tw32_f(MAC_EVENT, 0);
3210 } else {
3211 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3212 }
3213 udelay(40);
3214
3215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3216 current_link_up == 1 &&
3217 tp->link_config.active_speed == SPEED_1000 &&
3218 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3219 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3220 udelay(120);
3221 tw32_f(MAC_STATUS,
3222 (MAC_STATUS_SYNC_CHANGED |
3223 MAC_STATUS_CFG_CHANGED));
3224 udelay(40);
3225 tg3_write_mem(tp,
3226 NIC_SRAM_FIRMWARE_MBOX,
3227 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3228 }
3229
3230 /* Prevent send BD corruption. */
3231 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3232 u16 oldlnkctl, newlnkctl;
3233
3234 pci_read_config_word(tp->pdev,
3235 tp->pcie_cap + PCI_EXP_LNKCTL,
3236 &oldlnkctl);
3237 if (tp->link_config.active_speed == SPEED_100 ||
3238 tp->link_config.active_speed == SPEED_10)
3239 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3240 else
3241 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3242 if (newlnkctl != oldlnkctl)
3243 pci_write_config_word(tp->pdev,
3244 tp->pcie_cap + PCI_EXP_LNKCTL,
3245 newlnkctl);
3246 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3247 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3248 if (tp->link_config.active_speed == SPEED_100 ||
3249 tp->link_config.active_speed == SPEED_10)
3250 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3251 else
3252 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3253 if (newreg != oldreg)
3254 tw32(TG3_PCIE_LNKCTL, newreg);
3255 }
3256
3257 if (current_link_up != netif_carrier_ok(tp->dev)) {
3258 if (current_link_up)
3259 netif_carrier_on(tp->dev);
3260 else
3261 netif_carrier_off(tp->dev);
3262 tg3_link_report(tp);
3263 }
3264
3265 return 0;
3266 }
3267
3268 struct tg3_fiber_aneginfo {
3269 int state;
3270 #define ANEG_STATE_UNKNOWN 0
3271 #define ANEG_STATE_AN_ENABLE 1
3272 #define ANEG_STATE_RESTART_INIT 2
3273 #define ANEG_STATE_RESTART 3
3274 #define ANEG_STATE_DISABLE_LINK_OK 4
3275 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3276 #define ANEG_STATE_ABILITY_DETECT 6
3277 #define ANEG_STATE_ACK_DETECT_INIT 7
3278 #define ANEG_STATE_ACK_DETECT 8
3279 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3280 #define ANEG_STATE_COMPLETE_ACK 10
3281 #define ANEG_STATE_IDLE_DETECT_INIT 11
3282 #define ANEG_STATE_IDLE_DETECT 12
3283 #define ANEG_STATE_LINK_OK 13
3284 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3285 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3286
3287 u32 flags;
3288 #define MR_AN_ENABLE 0x00000001
3289 #define MR_RESTART_AN 0x00000002
3290 #define MR_AN_COMPLETE 0x00000004
3291 #define MR_PAGE_RX 0x00000008
3292 #define MR_NP_LOADED 0x00000010
3293 #define MR_TOGGLE_TX 0x00000020
3294 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3295 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3296 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3297 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3298 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3299 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3300 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3301 #define MR_TOGGLE_RX 0x00002000
3302 #define MR_NP_RX 0x00004000
3303
3304 #define MR_LINK_OK 0x80000000
3305
3306 unsigned long link_time, cur_time;
3307
3308 u32 ability_match_cfg;
3309 int ability_match_count;
3310
3311 char ability_match, idle_match, ack_match;
3312
3313 u32 txconfig, rxconfig;
3314 #define ANEG_CFG_NP 0x00000080
3315 #define ANEG_CFG_ACK 0x00000040
3316 #define ANEG_CFG_RF2 0x00000020
3317 #define ANEG_CFG_RF1 0x00000010
3318 #define ANEG_CFG_PS2 0x00000001
3319 #define ANEG_CFG_PS1 0x00008000
3320 #define ANEG_CFG_HD 0x00004000
3321 #define ANEG_CFG_FD 0x00002000
3322 #define ANEG_CFG_INVAL 0x00001f06
3323
3324 };
3325 #define ANEG_OK 0
3326 #define ANEG_DONE 1
3327 #define ANEG_TIMER_ENAB 2
3328 #define ANEG_FAILED -1
3329
3330 #define ANEG_STATE_SETTLE_TIME 10000
3331
3332 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3333 struct tg3_fiber_aneginfo *ap)
3334 {
3335 u16 flowctrl;
3336 unsigned long delta;
3337 u32 rx_cfg_reg;
3338 int ret;
3339
3340 if (ap->state == ANEG_STATE_UNKNOWN) {
3341 ap->rxconfig = 0;
3342 ap->link_time = 0;
3343 ap->cur_time = 0;
3344 ap->ability_match_cfg = 0;
3345 ap->ability_match_count = 0;
3346 ap->ability_match = 0;
3347 ap->idle_match = 0;
3348 ap->ack_match = 0;
3349 }
3350 ap->cur_time++;
3351
3352 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3353 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3354
3355 if (rx_cfg_reg != ap->ability_match_cfg) {
3356 ap->ability_match_cfg = rx_cfg_reg;
3357 ap->ability_match = 0;
3358 ap->ability_match_count = 0;
3359 } else {
3360 if (++ap->ability_match_count > 1) {
3361 ap->ability_match = 1;
3362 ap->ability_match_cfg = rx_cfg_reg;
3363 }
3364 }
3365 if (rx_cfg_reg & ANEG_CFG_ACK)
3366 ap->ack_match = 1;
3367 else
3368 ap->ack_match = 0;
3369
3370 ap->idle_match = 0;
3371 } else {
3372 ap->idle_match = 1;
3373 ap->ability_match_cfg = 0;
3374 ap->ability_match_count = 0;
3375 ap->ability_match = 0;
3376 ap->ack_match = 0;
3377
3378 rx_cfg_reg = 0;
3379 }
3380
3381 ap->rxconfig = rx_cfg_reg;
3382 ret = ANEG_OK;
3383
3384 switch(ap->state) {
3385 case ANEG_STATE_UNKNOWN:
3386 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3387 ap->state = ANEG_STATE_AN_ENABLE;
3388
3389 /* fallthru */
3390 case ANEG_STATE_AN_ENABLE:
3391 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3392 if (ap->flags & MR_AN_ENABLE) {
3393 ap->link_time = 0;
3394 ap->cur_time = 0;
3395 ap->ability_match_cfg = 0;
3396 ap->ability_match_count = 0;
3397 ap->ability_match = 0;
3398 ap->idle_match = 0;
3399 ap->ack_match = 0;
3400
3401 ap->state = ANEG_STATE_RESTART_INIT;
3402 } else {
3403 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3404 }
3405 break;
3406
3407 case ANEG_STATE_RESTART_INIT:
3408 ap->link_time = ap->cur_time;
3409 ap->flags &= ~(MR_NP_LOADED);
3410 ap->txconfig = 0;
3411 tw32(MAC_TX_AUTO_NEG, 0);
3412 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3413 tw32_f(MAC_MODE, tp->mac_mode);
3414 udelay(40);
3415
3416 ret = ANEG_TIMER_ENAB;
3417 ap->state = ANEG_STATE_RESTART;
3418
3419 /* fallthru */
3420 case ANEG_STATE_RESTART:
3421 delta = ap->cur_time - ap->link_time;
3422 if (delta > ANEG_STATE_SETTLE_TIME) {
3423 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3424 } else {
3425 ret = ANEG_TIMER_ENAB;
3426 }
3427 break;
3428
3429 case ANEG_STATE_DISABLE_LINK_OK:
3430 ret = ANEG_DONE;
3431 break;
3432
3433 case ANEG_STATE_ABILITY_DETECT_INIT:
3434 ap->flags &= ~(MR_TOGGLE_TX);
3435 ap->txconfig = ANEG_CFG_FD;
3436 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3437 if (flowctrl & ADVERTISE_1000XPAUSE)
3438 ap->txconfig |= ANEG_CFG_PS1;
3439 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3440 ap->txconfig |= ANEG_CFG_PS2;
3441 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3442 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3443 tw32_f(MAC_MODE, tp->mac_mode);
3444 udelay(40);
3445
3446 ap->state = ANEG_STATE_ABILITY_DETECT;
3447 break;
3448
3449 case ANEG_STATE_ABILITY_DETECT:
3450 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3451 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3452 }
3453 break;
3454
3455 case ANEG_STATE_ACK_DETECT_INIT:
3456 ap->txconfig |= ANEG_CFG_ACK;
3457 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3458 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3459 tw32_f(MAC_MODE, tp->mac_mode);
3460 udelay(40);
3461
3462 ap->state = ANEG_STATE_ACK_DETECT;
3463
3464 /* fallthru */
3465 case ANEG_STATE_ACK_DETECT:
3466 if (ap->ack_match != 0) {
3467 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3468 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3469 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3470 } else {
3471 ap->state = ANEG_STATE_AN_ENABLE;
3472 }
3473 } else if (ap->ability_match != 0 &&
3474 ap->rxconfig == 0) {
3475 ap->state = ANEG_STATE_AN_ENABLE;
3476 }
3477 break;
3478
3479 case ANEG_STATE_COMPLETE_ACK_INIT:
3480 if (ap->rxconfig & ANEG_CFG_INVAL) {
3481 ret = ANEG_FAILED;
3482 break;
3483 }
3484 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3485 MR_LP_ADV_HALF_DUPLEX |
3486 MR_LP_ADV_SYM_PAUSE |
3487 MR_LP_ADV_ASYM_PAUSE |
3488 MR_LP_ADV_REMOTE_FAULT1 |
3489 MR_LP_ADV_REMOTE_FAULT2 |
3490 MR_LP_ADV_NEXT_PAGE |
3491 MR_TOGGLE_RX |
3492 MR_NP_RX);
3493 if (ap->rxconfig & ANEG_CFG_FD)
3494 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3495 if (ap->rxconfig & ANEG_CFG_HD)
3496 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3497 if (ap->rxconfig & ANEG_CFG_PS1)
3498 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3499 if (ap->rxconfig & ANEG_CFG_PS2)
3500 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3501 if (ap->rxconfig & ANEG_CFG_RF1)
3502 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3503 if (ap->rxconfig & ANEG_CFG_RF2)
3504 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3505 if (ap->rxconfig & ANEG_CFG_NP)
3506 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3507
3508 ap->link_time = ap->cur_time;
3509
3510 ap->flags ^= (MR_TOGGLE_TX);
3511 if (ap->rxconfig & 0x0008)
3512 ap->flags |= MR_TOGGLE_RX;
3513 if (ap->rxconfig & ANEG_CFG_NP)
3514 ap->flags |= MR_NP_RX;
3515 ap->flags |= MR_PAGE_RX;
3516
3517 ap->state = ANEG_STATE_COMPLETE_ACK;
3518 ret = ANEG_TIMER_ENAB;
3519 break;
3520
3521 case ANEG_STATE_COMPLETE_ACK:
3522 if (ap->ability_match != 0 &&
3523 ap->rxconfig == 0) {
3524 ap->state = ANEG_STATE_AN_ENABLE;
3525 break;
3526 }
3527 delta = ap->cur_time - ap->link_time;
3528 if (delta > ANEG_STATE_SETTLE_TIME) {
3529 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3530 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3531 } else {
3532 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3533 !(ap->flags & MR_NP_RX)) {
3534 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3535 } else {
3536 ret = ANEG_FAILED;
3537 }
3538 }
3539 }
3540 break;
3541
3542 case ANEG_STATE_IDLE_DETECT_INIT:
3543 ap->link_time = ap->cur_time;
3544 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3545 tw32_f(MAC_MODE, tp->mac_mode);
3546 udelay(40);
3547
3548 ap->state = ANEG_STATE_IDLE_DETECT;
3549 ret = ANEG_TIMER_ENAB;
3550 break;
3551
3552 case ANEG_STATE_IDLE_DETECT:
3553 if (ap->ability_match != 0 &&
3554 ap->rxconfig == 0) {
3555 ap->state = ANEG_STATE_AN_ENABLE;
3556 break;
3557 }
3558 delta = ap->cur_time - ap->link_time;
3559 if (delta > ANEG_STATE_SETTLE_TIME) {
3560 /* XXX another gem from the Broadcom driver :( */
3561 ap->state = ANEG_STATE_LINK_OK;
3562 }
3563 break;
3564
3565 case ANEG_STATE_LINK_OK:
3566 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3567 ret = ANEG_DONE;
3568 break;
3569
3570 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3571 /* ??? unimplemented */
3572 break;
3573
3574 case ANEG_STATE_NEXT_PAGE_WAIT:
3575 /* ??? unimplemented */
3576 break;
3577
3578 default:
3579 ret = ANEG_FAILED;
3580 break;
3581 }
3582
3583 return ret;
3584 }
3585
3586 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3587 {
3588 int res = 0;
3589 struct tg3_fiber_aneginfo aninfo;
3590 int status = ANEG_FAILED;
3591 unsigned int tick;
3592 u32 tmp;
3593
3594 tw32_f(MAC_TX_AUTO_NEG, 0);
3595
3596 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3597 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3598 udelay(40);
3599
3600 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3601 udelay(40);
3602
3603 memset(&aninfo, 0, sizeof(aninfo));
3604 aninfo.flags |= MR_AN_ENABLE;
3605 aninfo.state = ANEG_STATE_UNKNOWN;
3606 aninfo.cur_time = 0;
3607 tick = 0;
3608 while (++tick < 195000) {
3609 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3610 if (status == ANEG_DONE || status == ANEG_FAILED)
3611 break;
3612
3613 udelay(1);
3614 }
3615
3616 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3617 tw32_f(MAC_MODE, tp->mac_mode);
3618 udelay(40);
3619
3620 *txflags = aninfo.txconfig;
3621 *rxflags = aninfo.flags;
3622
3623 if (status == ANEG_DONE &&
3624 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3625 MR_LP_ADV_FULL_DUPLEX)))
3626 res = 1;
3627
3628 return res;
3629 }
3630
3631 static void tg3_init_bcm8002(struct tg3 *tp)
3632 {
3633 u32 mac_status = tr32(MAC_STATUS);
3634 int i;
3635
3636 /* Reset when initting first time or we have a link. */
3637 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3638 !(mac_status & MAC_STATUS_PCS_SYNCED))
3639 return;
3640
3641 /* Set PLL lock range. */
3642 tg3_writephy(tp, 0x16, 0x8007);
3643
3644 /* SW reset */
3645 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3646
3647 /* Wait for reset to complete. */
3648 /* XXX schedule_timeout() ... */
3649 for (i = 0; i < 500; i++)
3650 udelay(10);
3651
3652 /* Config mode; select PMA/Ch 1 regs. */
3653 tg3_writephy(tp, 0x10, 0x8411);
3654
3655 /* Enable auto-lock and comdet, select txclk for tx. */
3656 tg3_writephy(tp, 0x11, 0x0a10);
3657
3658 tg3_writephy(tp, 0x18, 0x00a0);
3659 tg3_writephy(tp, 0x16, 0x41ff);
3660
3661 /* Assert and deassert POR. */
3662 tg3_writephy(tp, 0x13, 0x0400);
3663 udelay(40);
3664 tg3_writephy(tp, 0x13, 0x0000);
3665
3666 tg3_writephy(tp, 0x11, 0x0a50);
3667 udelay(40);
3668 tg3_writephy(tp, 0x11, 0x0a10);
3669
3670 /* Wait for signal to stabilize */
3671 /* XXX schedule_timeout() ... */
3672 for (i = 0; i < 15000; i++)
3673 udelay(10);
3674
3675 /* Deselect the channel register so we can read the PHYID
3676 * later.
3677 */
3678 tg3_writephy(tp, 0x10, 0x8011);
3679 }
3680
3681 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3682 {
3683 u16 flowctrl;
3684 u32 sg_dig_ctrl, sg_dig_status;
3685 u32 serdes_cfg, expected_sg_dig_ctrl;
3686 int workaround, port_a;
3687 int current_link_up;
3688
3689 serdes_cfg = 0;
3690 expected_sg_dig_ctrl = 0;
3691 workaround = 0;
3692 port_a = 1;
3693 current_link_up = 0;
3694
3695 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3696 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3697 workaround = 1;
3698 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3699 port_a = 0;
3700
3701 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3702 /* preserve bits 20-23 for voltage regulator */
3703 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3704 }
3705
3706 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3707
3708 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3709 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3710 if (workaround) {
3711 u32 val = serdes_cfg;
3712
3713 if (port_a)
3714 val |= 0xc010000;
3715 else
3716 val |= 0x4010000;
3717 tw32_f(MAC_SERDES_CFG, val);
3718 }
3719
3720 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3721 }
3722 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3723 tg3_setup_flow_control(tp, 0, 0);
3724 current_link_up = 1;
3725 }
3726 goto out;
3727 }
3728
3729 /* Want auto-negotiation. */
3730 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3731
3732 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3733 if (flowctrl & ADVERTISE_1000XPAUSE)
3734 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3735 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3736 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3737
3738 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3739 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3740 tp->serdes_counter &&
3741 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3742 MAC_STATUS_RCVD_CFG)) ==
3743 MAC_STATUS_PCS_SYNCED)) {
3744 tp->serdes_counter--;
3745 current_link_up = 1;
3746 goto out;
3747 }
3748 restart_autoneg:
3749 if (workaround)
3750 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3751 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3752 udelay(5);
3753 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3754
3755 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3756 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3757 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3758 MAC_STATUS_SIGNAL_DET)) {
3759 sg_dig_status = tr32(SG_DIG_STATUS);
3760 mac_status = tr32(MAC_STATUS);
3761
3762 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3763 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3764 u32 local_adv = 0, remote_adv = 0;
3765
3766 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3767 local_adv |= ADVERTISE_1000XPAUSE;
3768 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3769 local_adv |= ADVERTISE_1000XPSE_ASYM;
3770
3771 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3772 remote_adv |= LPA_1000XPAUSE;
3773 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3774 remote_adv |= LPA_1000XPAUSE_ASYM;
3775
3776 tg3_setup_flow_control(tp, local_adv, remote_adv);
3777 current_link_up = 1;
3778 tp->serdes_counter = 0;
3779 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3780 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3781 if (tp->serdes_counter)
3782 tp->serdes_counter--;
3783 else {
3784 if (workaround) {
3785 u32 val = serdes_cfg;
3786
3787 if (port_a)
3788 val |= 0xc010000;
3789 else
3790 val |= 0x4010000;
3791
3792 tw32_f(MAC_SERDES_CFG, val);
3793 }
3794
3795 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3796 udelay(40);
3797
3798 /* Link parallel detection - link is up */
3799 /* only if we have PCS_SYNC and not */
3800 /* receiving config code words */
3801 mac_status = tr32(MAC_STATUS);
3802 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3803 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3804 tg3_setup_flow_control(tp, 0, 0);
3805 current_link_up = 1;
3806 tp->tg3_flags2 |=
3807 TG3_FLG2_PARALLEL_DETECT;
3808 tp->serdes_counter =
3809 SERDES_PARALLEL_DET_TIMEOUT;
3810 } else
3811 goto restart_autoneg;
3812 }
3813 }
3814 } else {
3815 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3816 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3817 }
3818
3819 out:
3820 return current_link_up;
3821 }
3822
3823 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3824 {
3825 int current_link_up = 0;
3826
3827 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3828 goto out;
3829
3830 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3831 u32 txflags, rxflags;
3832 int i;
3833
3834 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3835 u32 local_adv = 0, remote_adv = 0;
3836
3837 if (txflags & ANEG_CFG_PS1)
3838 local_adv |= ADVERTISE_1000XPAUSE;
3839 if (txflags & ANEG_CFG_PS2)
3840 local_adv |= ADVERTISE_1000XPSE_ASYM;
3841
3842 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3843 remote_adv |= LPA_1000XPAUSE;
3844 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3845 remote_adv |= LPA_1000XPAUSE_ASYM;
3846
3847 tg3_setup_flow_control(tp, local_adv, remote_adv);
3848
3849 current_link_up = 1;
3850 }
3851 for (i = 0; i < 30; i++) {
3852 udelay(20);
3853 tw32_f(MAC_STATUS,
3854 (MAC_STATUS_SYNC_CHANGED |
3855 MAC_STATUS_CFG_CHANGED));
3856 udelay(40);
3857 if ((tr32(MAC_STATUS) &
3858 (MAC_STATUS_SYNC_CHANGED |
3859 MAC_STATUS_CFG_CHANGED)) == 0)
3860 break;
3861 }
3862
3863 mac_status = tr32(MAC_STATUS);
3864 if (current_link_up == 0 &&
3865 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3866 !(mac_status & MAC_STATUS_RCVD_CFG))
3867 current_link_up = 1;
3868 } else {
3869 tg3_setup_flow_control(tp, 0, 0);
3870
3871 /* Forcing 1000FD link up. */
3872 current_link_up = 1;
3873
3874 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3875 udelay(40);
3876
3877 tw32_f(MAC_MODE, tp->mac_mode);
3878 udelay(40);
3879 }
3880
3881 out:
3882 return current_link_up;
3883 }
3884
3885 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3886 {
3887 u32 orig_pause_cfg;
3888 u16 orig_active_speed;
3889 u8 orig_active_duplex;
3890 u32 mac_status;
3891 int current_link_up;
3892 int i;
3893
3894 orig_pause_cfg = tp->link_config.active_flowctrl;
3895 orig_active_speed = tp->link_config.active_speed;
3896 orig_active_duplex = tp->link_config.active_duplex;
3897
3898 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3899 netif_carrier_ok(tp->dev) &&
3900 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3901 mac_status = tr32(MAC_STATUS);
3902 mac_status &= (MAC_STATUS_PCS_SYNCED |
3903 MAC_STATUS_SIGNAL_DET |
3904 MAC_STATUS_CFG_CHANGED |
3905 MAC_STATUS_RCVD_CFG);
3906 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3907 MAC_STATUS_SIGNAL_DET)) {
3908 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3909 MAC_STATUS_CFG_CHANGED));
3910 return 0;
3911 }
3912 }
3913
3914 tw32_f(MAC_TX_AUTO_NEG, 0);
3915
3916 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3917 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3918 tw32_f(MAC_MODE, tp->mac_mode);
3919 udelay(40);
3920
3921 if (tp->phy_id == PHY_ID_BCM8002)
3922 tg3_init_bcm8002(tp);
3923
3924 /* Enable link change event even when serdes polling. */
3925 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3926 udelay(40);
3927
3928 current_link_up = 0;
3929 mac_status = tr32(MAC_STATUS);
3930
3931 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3932 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3933 else
3934 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3935
3936 tp->napi[0].hw_status->status =
3937 (SD_STATUS_UPDATED |
3938 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3939
3940 for (i = 0; i < 100; i++) {
3941 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3942 MAC_STATUS_CFG_CHANGED));
3943 udelay(5);
3944 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3945 MAC_STATUS_CFG_CHANGED |
3946 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3947 break;
3948 }
3949
3950 mac_status = tr32(MAC_STATUS);
3951 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3952 current_link_up = 0;
3953 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3954 tp->serdes_counter == 0) {
3955 tw32_f(MAC_MODE, (tp->mac_mode |
3956 MAC_MODE_SEND_CONFIGS));
3957 udelay(1);
3958 tw32_f(MAC_MODE, tp->mac_mode);
3959 }
3960 }
3961
3962 if (current_link_up == 1) {
3963 tp->link_config.active_speed = SPEED_1000;
3964 tp->link_config.active_duplex = DUPLEX_FULL;
3965 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3966 LED_CTRL_LNKLED_OVERRIDE |
3967 LED_CTRL_1000MBPS_ON));
3968 } else {
3969 tp->link_config.active_speed = SPEED_INVALID;
3970 tp->link_config.active_duplex = DUPLEX_INVALID;
3971 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3972 LED_CTRL_LNKLED_OVERRIDE |
3973 LED_CTRL_TRAFFIC_OVERRIDE));
3974 }
3975
3976 if (current_link_up != netif_carrier_ok(tp->dev)) {
3977 if (current_link_up)
3978 netif_carrier_on(tp->dev);
3979 else
3980 netif_carrier_off(tp->dev);
3981 tg3_link_report(tp);
3982 } else {
3983 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3984 if (orig_pause_cfg != now_pause_cfg ||
3985 orig_active_speed != tp->link_config.active_speed ||
3986 orig_active_duplex != tp->link_config.active_duplex)
3987 tg3_link_report(tp);
3988 }
3989
3990 return 0;
3991 }
3992
3993 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3994 {
3995 int current_link_up, err = 0;
3996 u32 bmsr, bmcr;
3997 u16 current_speed;
3998 u8 current_duplex;
3999 u32 local_adv, remote_adv;
4000
4001 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4002 tw32_f(MAC_MODE, tp->mac_mode);
4003 udelay(40);
4004
4005 tw32(MAC_EVENT, 0);
4006
4007 tw32_f(MAC_STATUS,
4008 (MAC_STATUS_SYNC_CHANGED |
4009 MAC_STATUS_CFG_CHANGED |
4010 MAC_STATUS_MI_COMPLETION |
4011 MAC_STATUS_LNKSTATE_CHANGED));
4012 udelay(40);
4013
4014 if (force_reset)
4015 tg3_phy_reset(tp);
4016
4017 current_link_up = 0;
4018 current_speed = SPEED_INVALID;
4019 current_duplex = DUPLEX_INVALID;
4020
4021 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4022 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4023 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4024 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4025 bmsr |= BMSR_LSTATUS;
4026 else
4027 bmsr &= ~BMSR_LSTATUS;
4028 }
4029
4030 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4031
4032 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4033 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4034 /* do nothing, just check for link up at the end */
4035 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4036 u32 adv, new_adv;
4037
4038 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4039 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4040 ADVERTISE_1000XPAUSE |
4041 ADVERTISE_1000XPSE_ASYM |
4042 ADVERTISE_SLCT);
4043
4044 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4045
4046 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4047 new_adv |= ADVERTISE_1000XHALF;
4048 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4049 new_adv |= ADVERTISE_1000XFULL;
4050
4051 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4052 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4053 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4054 tg3_writephy(tp, MII_BMCR, bmcr);
4055
4056 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4057 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4058 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4059
4060 return err;
4061 }
4062 } else {
4063 u32 new_bmcr;
4064
4065 bmcr &= ~BMCR_SPEED1000;
4066 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4067
4068 if (tp->link_config.duplex == DUPLEX_FULL)
4069 new_bmcr |= BMCR_FULLDPLX;
4070
4071 if (new_bmcr != bmcr) {
4072 /* BMCR_SPEED1000 is a reserved bit that needs
4073 * to be set on write.
4074 */
4075 new_bmcr |= BMCR_SPEED1000;
4076
4077 /* Force a linkdown */
4078 if (netif_carrier_ok(tp->dev)) {
4079 u32 adv;
4080
4081 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4082 adv &= ~(ADVERTISE_1000XFULL |
4083 ADVERTISE_1000XHALF |
4084 ADVERTISE_SLCT);
4085 tg3_writephy(tp, MII_ADVERTISE, adv);
4086 tg3_writephy(tp, MII_BMCR, bmcr |
4087 BMCR_ANRESTART |
4088 BMCR_ANENABLE);
4089 udelay(10);
4090 netif_carrier_off(tp->dev);
4091 }
4092 tg3_writephy(tp, MII_BMCR, new_bmcr);
4093 bmcr = new_bmcr;
4094 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4095 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4096 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4097 ASIC_REV_5714) {
4098 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4099 bmsr |= BMSR_LSTATUS;
4100 else
4101 bmsr &= ~BMSR_LSTATUS;
4102 }
4103 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4104 }
4105 }
4106
4107 if (bmsr & BMSR_LSTATUS) {
4108 current_speed = SPEED_1000;
4109 current_link_up = 1;
4110 if (bmcr & BMCR_FULLDPLX)
4111 current_duplex = DUPLEX_FULL;
4112 else
4113 current_duplex = DUPLEX_HALF;
4114
4115 local_adv = 0;
4116 remote_adv = 0;
4117
4118 if (bmcr & BMCR_ANENABLE) {
4119 u32 common;
4120
4121 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4122 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4123 common = local_adv & remote_adv;
4124 if (common & (ADVERTISE_1000XHALF |
4125 ADVERTISE_1000XFULL)) {
4126 if (common & ADVERTISE_1000XFULL)
4127 current_duplex = DUPLEX_FULL;
4128 else
4129 current_duplex = DUPLEX_HALF;
4130 }
4131 else
4132 current_link_up = 0;
4133 }
4134 }
4135
4136 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4137 tg3_setup_flow_control(tp, local_adv, remote_adv);
4138
4139 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4140 if (tp->link_config.active_duplex == DUPLEX_HALF)
4141 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4142
4143 tw32_f(MAC_MODE, tp->mac_mode);
4144 udelay(40);
4145
4146 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4147
4148 tp->link_config.active_speed = current_speed;
4149 tp->link_config.active_duplex = current_duplex;
4150
4151 if (current_link_up != netif_carrier_ok(tp->dev)) {
4152 if (current_link_up)
4153 netif_carrier_on(tp->dev);
4154 else {
4155 netif_carrier_off(tp->dev);
4156 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4157 }
4158 tg3_link_report(tp);
4159 }
4160 return err;
4161 }
4162
4163 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4164 {
4165 if (tp->serdes_counter) {
4166 /* Give autoneg time to complete. */
4167 tp->serdes_counter--;
4168 return;
4169 }
4170 if (!netif_carrier_ok(tp->dev) &&
4171 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4172 u32 bmcr;
4173
4174 tg3_readphy(tp, MII_BMCR, &bmcr);
4175 if (bmcr & BMCR_ANENABLE) {
4176 u32 phy1, phy2;
4177
4178 /* Select shadow register 0x1f */
4179 tg3_writephy(tp, 0x1c, 0x7c00);
4180 tg3_readphy(tp, 0x1c, &phy1);
4181
4182 /* Select expansion interrupt status register */
4183 tg3_writephy(tp, 0x17, 0x0f01);
4184 tg3_readphy(tp, 0x15, &phy2);
4185 tg3_readphy(tp, 0x15, &phy2);
4186
4187 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4188 /* We have signal detect and not receiving
4189 * config code words, link is up by parallel
4190 * detection.
4191 */
4192
4193 bmcr &= ~BMCR_ANENABLE;
4194 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4195 tg3_writephy(tp, MII_BMCR, bmcr);
4196 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4197 }
4198 }
4199 }
4200 else if (netif_carrier_ok(tp->dev) &&
4201 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4202 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4203 u32 phy2;
4204
4205 /* Select expansion interrupt status register */
4206 tg3_writephy(tp, 0x17, 0x0f01);
4207 tg3_readphy(tp, 0x15, &phy2);
4208 if (phy2 & 0x20) {
4209 u32 bmcr;
4210
4211 /* Config code words received, turn on autoneg. */
4212 tg3_readphy(tp, MII_BMCR, &bmcr);
4213 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4214
4215 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4216
4217 }
4218 }
4219 }
4220
4221 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4222 {
4223 int err;
4224
4225 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4226 err = tg3_setup_fiber_phy(tp, force_reset);
4227 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4228 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4229 } else {
4230 err = tg3_setup_copper_phy(tp, force_reset);
4231 }
4232
4233 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4234 u32 val, scale;
4235
4236 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4237 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4238 scale = 65;
4239 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4240 scale = 6;
4241 else
4242 scale = 12;
4243
4244 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4245 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4246 tw32(GRC_MISC_CFG, val);
4247 }
4248
4249 if (tp->link_config.active_speed == SPEED_1000 &&
4250 tp->link_config.active_duplex == DUPLEX_HALF)
4251 tw32(MAC_TX_LENGTHS,
4252 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4253 (6 << TX_LENGTHS_IPG_SHIFT) |
4254 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4255 else
4256 tw32(MAC_TX_LENGTHS,
4257 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4258 (6 << TX_LENGTHS_IPG_SHIFT) |
4259 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4260
4261 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4262 if (netif_carrier_ok(tp->dev)) {
4263 tw32(HOSTCC_STAT_COAL_TICKS,
4264 tp->coal.stats_block_coalesce_usecs);
4265 } else {
4266 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4267 }
4268 }
4269
4270 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4271 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4272 if (!netif_carrier_ok(tp->dev))
4273 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4274 tp->pwrmgmt_thresh;
4275 else
4276 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4277 tw32(PCIE_PWR_MGMT_THRESH, val);
4278 }
4279
4280 return err;
4281 }
4282
4283 /* This is called whenever we suspect that the system chipset is re-
4284 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4285 * is bogus tx completions. We try to recover by setting the
4286 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4287 * in the workqueue.
4288 */
4289 static void tg3_tx_recover(struct tg3 *tp)
4290 {
4291 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4292 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4293
4294 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4295 "mapped I/O cycles to the network device, attempting to "
4296 "recover. Please report the problem to the driver maintainer "
4297 "and include system chipset information.\n", tp->dev->name);
4298
4299 spin_lock(&tp->lock);
4300 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4301 spin_unlock(&tp->lock);
4302 }
4303
4304 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4305 {
4306 smp_mb();
4307 return tnapi->tx_pending -
4308 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4309 }
4310
4311 /* Tigon3 never reports partial packet sends. So we do not
4312 * need special logic to handle SKBs that have not had all
4313 * of their frags sent yet, like SunGEM does.
4314 */
4315 static void tg3_tx(struct tg3_napi *tnapi)
4316 {
4317 struct tg3 *tp = tnapi->tp;
4318 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4319 u32 sw_idx = tnapi->tx_cons;
4320 struct netdev_queue *txq;
4321 int index = tnapi - tp->napi;
4322
4323 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
4324 index--;
4325
4326 txq = netdev_get_tx_queue(tp->dev, index);
4327
4328 while (sw_idx != hw_idx) {
4329 struct tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
4330 struct sk_buff *skb = ri->skb;
4331 int i, tx_bug = 0;
4332
4333 if (unlikely(skb == NULL)) {
4334 tg3_tx_recover(tp);
4335 return;
4336 }
4337
4338 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4339
4340 ri->skb = NULL;
4341
4342 sw_idx = NEXT_TX(sw_idx);
4343
4344 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4345 ri = &tnapi->tx_buffers[sw_idx];
4346 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4347 tx_bug = 1;
4348 sw_idx = NEXT_TX(sw_idx);
4349 }
4350
4351 dev_kfree_skb(skb);
4352
4353 if (unlikely(tx_bug)) {
4354 tg3_tx_recover(tp);
4355 return;
4356 }
4357 }
4358
4359 tnapi->tx_cons = sw_idx;
4360
4361 /* Need to make the tx_cons update visible to tg3_start_xmit()
4362 * before checking for netif_queue_stopped(). Without the
4363 * memory barrier, there is a small possibility that tg3_start_xmit()
4364 * will miss it and cause the queue to be stopped forever.
4365 */
4366 smp_mb();
4367
4368 if (unlikely(netif_tx_queue_stopped(txq) &&
4369 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4370 __netif_tx_lock(txq, smp_processor_id());
4371 if (netif_tx_queue_stopped(txq) &&
4372 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4373 netif_tx_wake_queue(txq);
4374 __netif_tx_unlock(txq);
4375 }
4376 }
4377
4378 /* Returns size of skb allocated or < 0 on error.
4379 *
4380 * We only need to fill in the address because the other members
4381 * of the RX descriptor are invariant, see tg3_init_rings.
4382 *
4383 * Note the purposeful assymetry of cpu vs. chip accesses. For
4384 * posting buffers we only dirty the first cache line of the RX
4385 * descriptor (containing the address). Whereas for the RX status
4386 * buffers the cpu only reads the last cacheline of the RX descriptor
4387 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4388 */
4389 static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
4390 int src_idx, u32 dest_idx_unmasked)
4391 {
4392 struct tg3 *tp = tnapi->tp;
4393 struct tg3_rx_buffer_desc *desc;
4394 struct ring_info *map, *src_map;
4395 struct sk_buff *skb;
4396 dma_addr_t mapping;
4397 int skb_size, dest_idx;
4398 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4399
4400 src_map = NULL;
4401 switch (opaque_key) {
4402 case RXD_OPAQUE_RING_STD:
4403 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4404 desc = &tpr->rx_std[dest_idx];
4405 map = &tpr->rx_std_buffers[dest_idx];
4406 if (src_idx >= 0)
4407 src_map = &tpr->rx_std_buffers[src_idx];
4408 skb_size = tp->rx_pkt_map_sz;
4409 break;
4410
4411 case RXD_OPAQUE_RING_JUMBO:
4412 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4413 desc = &tpr->rx_jmb[dest_idx].std;
4414 map = &tpr->rx_jmb_buffers[dest_idx];
4415 if (src_idx >= 0)
4416 src_map = &tpr->rx_jmb_buffers[src_idx];
4417 skb_size = TG3_RX_JMB_MAP_SZ;
4418 break;
4419
4420 default:
4421 return -EINVAL;
4422 }
4423
4424 /* Do not overwrite any of the map or rp information
4425 * until we are sure we can commit to a new buffer.
4426 *
4427 * Callers depend upon this behavior and assume that
4428 * we leave everything unchanged if we fail.
4429 */
4430 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4431 if (skb == NULL)
4432 return -ENOMEM;
4433
4434 skb_reserve(skb, tp->rx_offset);
4435
4436 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4437 PCI_DMA_FROMDEVICE);
4438
4439 map->skb = skb;
4440 pci_unmap_addr_set(map, mapping, mapping);
4441
4442 if (src_map != NULL)
4443 src_map->skb = NULL;
4444
4445 desc->addr_hi = ((u64)mapping >> 32);
4446 desc->addr_lo = ((u64)mapping & 0xffffffff);
4447
4448 return skb_size;
4449 }
4450
4451 /* We only need to move over in the address because the other
4452 * members of the RX descriptor are invariant. See notes above
4453 * tg3_alloc_rx_skb for full details.
4454 */
4455 static void tg3_recycle_rx(struct tg3_napi *tnapi, u32 opaque_key,
4456 int src_idx, u32 dest_idx_unmasked)
4457 {
4458 struct tg3 *tp = tnapi->tp;
4459 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4460 struct ring_info *src_map, *dest_map;
4461 int dest_idx;
4462 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4463
4464 switch (opaque_key) {
4465 case RXD_OPAQUE_RING_STD:
4466 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4467 dest_desc = &tpr->rx_std[dest_idx];
4468 dest_map = &tpr->rx_std_buffers[dest_idx];
4469 src_desc = &tpr->rx_std[src_idx];
4470 src_map = &tpr->rx_std_buffers[src_idx];
4471 break;
4472
4473 case RXD_OPAQUE_RING_JUMBO:
4474 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4475 dest_desc = &tpr->rx_jmb[dest_idx].std;
4476 dest_map = &tpr->rx_jmb_buffers[dest_idx];
4477 src_desc = &tpr->rx_jmb[src_idx].std;
4478 src_map = &tpr->rx_jmb_buffers[src_idx];
4479 break;
4480
4481 default:
4482 return;
4483 }
4484
4485 dest_map->skb = src_map->skb;
4486 pci_unmap_addr_set(dest_map, mapping,
4487 pci_unmap_addr(src_map, mapping));
4488 dest_desc->addr_hi = src_desc->addr_hi;
4489 dest_desc->addr_lo = src_desc->addr_lo;
4490
4491 src_map->skb = NULL;
4492 }
4493
4494 /* The RX ring scheme is composed of multiple rings which post fresh
4495 * buffers to the chip, and one special ring the chip uses to report
4496 * status back to the host.
4497 *
4498 * The special ring reports the status of received packets to the
4499 * host. The chip does not write into the original descriptor the
4500 * RX buffer was obtained from. The chip simply takes the original
4501 * descriptor as provided by the host, updates the status and length
4502 * field, then writes this into the next status ring entry.
4503 *
4504 * Each ring the host uses to post buffers to the chip is described
4505 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4506 * it is first placed into the on-chip ram. When the packet's length
4507 * is known, it walks down the TG3_BDINFO entries to select the ring.
4508 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4509 * which is within the range of the new packet's length is chosen.
4510 *
4511 * The "separate ring for rx status" scheme may sound queer, but it makes
4512 * sense from a cache coherency perspective. If only the host writes
4513 * to the buffer post rings, and only the chip writes to the rx status
4514 * rings, then cache lines never move beyond shared-modified state.
4515 * If both the host and chip were to write into the same ring, cache line
4516 * eviction could occur since both entities want it in an exclusive state.
4517 */
4518 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4519 {
4520 struct tg3 *tp = tnapi->tp;
4521 u32 work_mask, rx_std_posted = 0;
4522 u32 sw_idx = tnapi->rx_rcb_ptr;
4523 u16 hw_idx;
4524 int received;
4525 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4526
4527 hw_idx = *(tnapi->rx_rcb_prod_idx);
4528 /*
4529 * We need to order the read of hw_idx and the read of
4530 * the opaque cookie.
4531 */
4532 rmb();
4533 work_mask = 0;
4534 received = 0;
4535 while (sw_idx != hw_idx && budget > 0) {
4536 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4537 unsigned int len;
4538 struct sk_buff *skb;
4539 dma_addr_t dma_addr;
4540 u32 opaque_key, desc_idx, *post_ptr;
4541
4542 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4543 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4544 if (opaque_key == RXD_OPAQUE_RING_STD) {
4545 struct ring_info *ri = &tpr->rx_std_buffers[desc_idx];
4546 dma_addr = pci_unmap_addr(ri, mapping);
4547 skb = ri->skb;
4548 post_ptr = &tpr->rx_std_ptr;
4549 rx_std_posted++;
4550 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4551 struct ring_info *ri = &tpr->rx_jmb_buffers[desc_idx];
4552 dma_addr = pci_unmap_addr(ri, mapping);
4553 skb = ri->skb;
4554 post_ptr = &tpr->rx_jmb_ptr;
4555 } else
4556 goto next_pkt_nopost;
4557
4558 work_mask |= opaque_key;
4559
4560 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4561 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4562 drop_it:
4563 tg3_recycle_rx(tnapi, opaque_key,
4564 desc_idx, *post_ptr);
4565 drop_it_no_recycle:
4566 /* Other statistics kept track of by card. */
4567 tp->net_stats.rx_dropped++;
4568 goto next_pkt;
4569 }
4570
4571 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4572 ETH_FCS_LEN;
4573
4574 if (len > RX_COPY_THRESHOLD
4575 && tp->rx_offset == NET_IP_ALIGN
4576 /* rx_offset will likely not equal NET_IP_ALIGN
4577 * if this is a 5701 card running in PCI-X mode
4578 * [see tg3_get_invariants()]
4579 */
4580 ) {
4581 int skb_size;
4582
4583 skb_size = tg3_alloc_rx_skb(tnapi, opaque_key,
4584 desc_idx, *post_ptr);
4585 if (skb_size < 0)
4586 goto drop_it;
4587
4588 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4589 PCI_DMA_FROMDEVICE);
4590
4591 skb_put(skb, len);
4592 } else {
4593 struct sk_buff *copy_skb;
4594
4595 tg3_recycle_rx(tnapi, opaque_key,
4596 desc_idx, *post_ptr);
4597
4598 copy_skb = netdev_alloc_skb(tp->dev,
4599 len + TG3_RAW_IP_ALIGN);
4600 if (copy_skb == NULL)
4601 goto drop_it_no_recycle;
4602
4603 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4604 skb_put(copy_skb, len);
4605 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4606 skb_copy_from_linear_data(skb, copy_skb->data, len);
4607 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4608
4609 /* We'll reuse the original ring buffer. */
4610 skb = copy_skb;
4611 }
4612
4613 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4614 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4615 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4616 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4617 skb->ip_summed = CHECKSUM_UNNECESSARY;
4618 else
4619 skb->ip_summed = CHECKSUM_NONE;
4620
4621 skb->protocol = eth_type_trans(skb, tp->dev);
4622
4623 if (len > (tp->dev->mtu + ETH_HLEN) &&
4624 skb->protocol != htons(ETH_P_8021Q)) {
4625 dev_kfree_skb(skb);
4626 goto next_pkt;
4627 }
4628
4629 #if TG3_VLAN_TAG_USED
4630 if (tp->vlgrp != NULL &&
4631 desc->type_flags & RXD_FLAG_VLAN) {
4632 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4633 desc->err_vlan & RXD_VLAN_MASK, skb);
4634 } else
4635 #endif
4636 napi_gro_receive(&tnapi->napi, skb);
4637
4638 received++;
4639 budget--;
4640
4641 next_pkt:
4642 (*post_ptr)++;
4643
4644 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4645 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4646
4647 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4648 TG3_64BIT_REG_LOW, idx);
4649 work_mask &= ~RXD_OPAQUE_RING_STD;
4650 rx_std_posted = 0;
4651 }
4652 next_pkt_nopost:
4653 sw_idx++;
4654 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4655
4656 /* Refresh hw_idx to see if there is new work */
4657 if (sw_idx == hw_idx) {
4658 hw_idx = *(tnapi->rx_rcb_prod_idx);
4659 rmb();
4660 }
4661 }
4662
4663 /* ACK the status ring. */
4664 tnapi->rx_rcb_ptr = sw_idx;
4665 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4666
4667 /* Refill RX ring(s). */
4668 if (work_mask & RXD_OPAQUE_RING_STD) {
4669 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE;
4670 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4671 sw_idx);
4672 }
4673 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4674 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE;
4675 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4676 sw_idx);
4677 }
4678 mmiowb();
4679
4680 return received;
4681 }
4682
4683 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4684 {
4685 struct tg3 *tp = tnapi->tp;
4686 struct tg3_hw_status *sblk = tnapi->hw_status;
4687
4688 /* handle link change and other phy events */
4689 if (!(tp->tg3_flags &
4690 (TG3_FLAG_USE_LINKCHG_REG |
4691 TG3_FLAG_POLL_SERDES))) {
4692 if (sblk->status & SD_STATUS_LINK_CHG) {
4693 sblk->status = SD_STATUS_UPDATED |
4694 (sblk->status & ~SD_STATUS_LINK_CHG);
4695 spin_lock(&tp->lock);
4696 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4697 tw32_f(MAC_STATUS,
4698 (MAC_STATUS_SYNC_CHANGED |
4699 MAC_STATUS_CFG_CHANGED |
4700 MAC_STATUS_MI_COMPLETION |
4701 MAC_STATUS_LNKSTATE_CHANGED));
4702 udelay(40);
4703 } else
4704 tg3_setup_phy(tp, 0);
4705 spin_unlock(&tp->lock);
4706 }
4707 }
4708
4709 /* run TX completion thread */
4710 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4711 tg3_tx(tnapi);
4712 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4713 return work_done;
4714 }
4715
4716 /* run RX thread, within the bounds set by NAPI.
4717 * All RX "locking" is done by ensuring outside
4718 * code synchronizes with tg3->napi.poll()
4719 */
4720 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4721 work_done += tg3_rx(tnapi, budget - work_done);
4722
4723 return work_done;
4724 }
4725
4726 static int tg3_poll(struct napi_struct *napi, int budget)
4727 {
4728 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4729 struct tg3 *tp = tnapi->tp;
4730 int work_done = 0;
4731 struct tg3_hw_status *sblk = tnapi->hw_status;
4732
4733 while (1) {
4734 work_done = tg3_poll_work(tnapi, work_done, budget);
4735
4736 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4737 goto tx_recovery;
4738
4739 if (unlikely(work_done >= budget))
4740 break;
4741
4742 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4743 /* tp->last_tag is used in tg3_int_reenable() below
4744 * to tell the hw how much work has been processed,
4745 * so we must read it before checking for more work.
4746 */
4747 tnapi->last_tag = sblk->status_tag;
4748 tnapi->last_irq_tag = tnapi->last_tag;
4749 rmb();
4750 } else
4751 sblk->status &= ~SD_STATUS_UPDATED;
4752
4753 if (likely(!tg3_has_work(tnapi))) {
4754 napi_complete(napi);
4755 tg3_int_reenable(tnapi);
4756 break;
4757 }
4758 }
4759
4760 return work_done;
4761
4762 tx_recovery:
4763 /* work_done is guaranteed to be less than budget. */
4764 napi_complete(napi);
4765 schedule_work(&tp->reset_task);
4766 return work_done;
4767 }
4768
4769 static void tg3_irq_quiesce(struct tg3 *tp)
4770 {
4771 int i;
4772
4773 BUG_ON(tp->irq_sync);
4774
4775 tp->irq_sync = 1;
4776 smp_mb();
4777
4778 for (i = 0; i < tp->irq_cnt; i++)
4779 synchronize_irq(tp->napi[i].irq_vec);
4780 }
4781
4782 static inline int tg3_irq_sync(struct tg3 *tp)
4783 {
4784 return tp->irq_sync;
4785 }
4786
4787 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4788 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4789 * with as well. Most of the time, this is not necessary except when
4790 * shutting down the device.
4791 */
4792 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4793 {
4794 spin_lock_bh(&tp->lock);
4795 if (irq_sync)
4796 tg3_irq_quiesce(tp);
4797 }
4798
4799 static inline void tg3_full_unlock(struct tg3 *tp)
4800 {
4801 spin_unlock_bh(&tp->lock);
4802 }
4803
4804 /* One-shot MSI handler - Chip automatically disables interrupt
4805 * after sending MSI so driver doesn't have to do it.
4806 */
4807 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4808 {
4809 struct tg3_napi *tnapi = dev_id;
4810 struct tg3 *tp = tnapi->tp;
4811
4812 prefetch(tnapi->hw_status);
4813 if (tnapi->rx_rcb)
4814 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4815
4816 if (likely(!tg3_irq_sync(tp)))
4817 napi_schedule(&tnapi->napi);
4818
4819 return IRQ_HANDLED;
4820 }
4821
4822 /* MSI ISR - No need to check for interrupt sharing and no need to
4823 * flush status block and interrupt mailbox. PCI ordering rules
4824 * guarantee that MSI will arrive after the status block.
4825 */
4826 static irqreturn_t tg3_msi(int irq, void *dev_id)
4827 {
4828 struct tg3_napi *tnapi = dev_id;
4829 struct tg3 *tp = tnapi->tp;
4830
4831 prefetch(tnapi->hw_status);
4832 if (tnapi->rx_rcb)
4833 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4834 /*
4835 * Writing any value to intr-mbox-0 clears PCI INTA# and
4836 * chip-internal interrupt pending events.
4837 * Writing non-zero to intr-mbox-0 additional tells the
4838 * NIC to stop sending us irqs, engaging "in-intr-handler"
4839 * event coalescing.
4840 */
4841 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4842 if (likely(!tg3_irq_sync(tp)))
4843 napi_schedule(&tnapi->napi);
4844
4845 return IRQ_RETVAL(1);
4846 }
4847
4848 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4849 {
4850 struct tg3_napi *tnapi = dev_id;
4851 struct tg3 *tp = tnapi->tp;
4852 struct tg3_hw_status *sblk = tnapi->hw_status;
4853 unsigned int handled = 1;
4854
4855 /* In INTx mode, it is possible for the interrupt to arrive at
4856 * the CPU before the status block posted prior to the interrupt.
4857 * Reading the PCI State register will confirm whether the
4858 * interrupt is ours and will flush the status block.
4859 */
4860 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4861 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4862 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4863 handled = 0;
4864 goto out;
4865 }
4866 }
4867
4868 /*
4869 * Writing any value to intr-mbox-0 clears PCI INTA# and
4870 * chip-internal interrupt pending events.
4871 * Writing non-zero to intr-mbox-0 additional tells the
4872 * NIC to stop sending us irqs, engaging "in-intr-handler"
4873 * event coalescing.
4874 *
4875 * Flush the mailbox to de-assert the IRQ immediately to prevent
4876 * spurious interrupts. The flush impacts performance but
4877 * excessive spurious interrupts can be worse in some cases.
4878 */
4879 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4880 if (tg3_irq_sync(tp))
4881 goto out;
4882 sblk->status &= ~SD_STATUS_UPDATED;
4883 if (likely(tg3_has_work(tnapi))) {
4884 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4885 napi_schedule(&tnapi->napi);
4886 } else {
4887 /* No work, shared interrupt perhaps? re-enable
4888 * interrupts, and flush that PCI write
4889 */
4890 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4891 0x00000000);
4892 }
4893 out:
4894 return IRQ_RETVAL(handled);
4895 }
4896
4897 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4898 {
4899 struct tg3_napi *tnapi = dev_id;
4900 struct tg3 *tp = tnapi->tp;
4901 struct tg3_hw_status *sblk = tnapi->hw_status;
4902 unsigned int handled = 1;
4903
4904 /* In INTx mode, it is possible for the interrupt to arrive at
4905 * the CPU before the status block posted prior to the interrupt.
4906 * Reading the PCI State register will confirm whether the
4907 * interrupt is ours and will flush the status block.
4908 */
4909 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4910 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4911 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4912 handled = 0;
4913 goto out;
4914 }
4915 }
4916
4917 /*
4918 * writing any value to intr-mbox-0 clears PCI INTA# and
4919 * chip-internal interrupt pending events.
4920 * writing non-zero to intr-mbox-0 additional tells the
4921 * NIC to stop sending us irqs, engaging "in-intr-handler"
4922 * event coalescing.
4923 *
4924 * Flush the mailbox to de-assert the IRQ immediately to prevent
4925 * spurious interrupts. The flush impacts performance but
4926 * excessive spurious interrupts can be worse in some cases.
4927 */
4928 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4929
4930 /*
4931 * In a shared interrupt configuration, sometimes other devices'
4932 * interrupts will scream. We record the current status tag here
4933 * so that the above check can report that the screaming interrupts
4934 * are unhandled. Eventually they will be silenced.
4935 */
4936 tnapi->last_irq_tag = sblk->status_tag;
4937
4938 if (tg3_irq_sync(tp))
4939 goto out;
4940
4941 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
4942
4943 napi_schedule(&tnapi->napi);
4944
4945 out:
4946 return IRQ_RETVAL(handled);
4947 }
4948
4949 /* ISR for interrupt test */
4950 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4951 {
4952 struct tg3_napi *tnapi = dev_id;
4953 struct tg3 *tp = tnapi->tp;
4954 struct tg3_hw_status *sblk = tnapi->hw_status;
4955
4956 if ((sblk->status & SD_STATUS_UPDATED) ||
4957 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4958 tg3_disable_ints(tp);
4959 return IRQ_RETVAL(1);
4960 }
4961 return IRQ_RETVAL(0);
4962 }
4963
4964 static int tg3_init_hw(struct tg3 *, int);
4965 static int tg3_halt(struct tg3 *, int, int);
4966
4967 /* Restart hardware after configuration changes, self-test, etc.
4968 * Invoked with tp->lock held.
4969 */
4970 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4971 __releases(tp->lock)
4972 __acquires(tp->lock)
4973 {
4974 int err;
4975
4976 err = tg3_init_hw(tp, reset_phy);
4977 if (err) {
4978 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4979 "aborting.\n", tp->dev->name);
4980 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4981 tg3_full_unlock(tp);
4982 del_timer_sync(&tp->timer);
4983 tp->irq_sync = 0;
4984 tg3_napi_enable(tp);
4985 dev_close(tp->dev);
4986 tg3_full_lock(tp, 0);
4987 }
4988 return err;
4989 }
4990
4991 #ifdef CONFIG_NET_POLL_CONTROLLER
4992 static void tg3_poll_controller(struct net_device *dev)
4993 {
4994 int i;
4995 struct tg3 *tp = netdev_priv(dev);
4996
4997 for (i = 0; i < tp->irq_cnt; i++)
4998 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
4999 }
5000 #endif
5001
5002 static void tg3_reset_task(struct work_struct *work)
5003 {
5004 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5005 int err;
5006 unsigned int restart_timer;
5007
5008 tg3_full_lock(tp, 0);
5009
5010 if (!netif_running(tp->dev)) {
5011 tg3_full_unlock(tp);
5012 return;
5013 }
5014
5015 tg3_full_unlock(tp);
5016
5017 tg3_phy_stop(tp);
5018
5019 tg3_netif_stop(tp);
5020
5021 tg3_full_lock(tp, 1);
5022
5023 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5024 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5025
5026 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5027 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5028 tp->write32_rx_mbox = tg3_write_flush_reg32;
5029 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5030 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5031 }
5032
5033 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5034 err = tg3_init_hw(tp, 1);
5035 if (err)
5036 goto out;
5037
5038 tg3_netif_start(tp);
5039
5040 if (restart_timer)
5041 mod_timer(&tp->timer, jiffies + 1);
5042
5043 out:
5044 tg3_full_unlock(tp);
5045
5046 if (!err)
5047 tg3_phy_start(tp);
5048 }
5049
5050 static void tg3_dump_short_state(struct tg3 *tp)
5051 {
5052 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5053 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5054 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5055 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5056 }
5057
5058 static void tg3_tx_timeout(struct net_device *dev)
5059 {
5060 struct tg3 *tp = netdev_priv(dev);
5061
5062 if (netif_msg_tx_err(tp)) {
5063 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5064 dev->name);
5065 tg3_dump_short_state(tp);
5066 }
5067
5068 schedule_work(&tp->reset_task);
5069 }
5070
5071 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5072 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5073 {
5074 u32 base = (u32) mapping & 0xffffffff;
5075
5076 return ((base > 0xffffdcc0) &&
5077 (base + len + 8 < base));
5078 }
5079
5080 /* Test for DMA addresses > 40-bit */
5081 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5082 int len)
5083 {
5084 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5085 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5086 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5087 return 0;
5088 #else
5089 return 0;
5090 #endif
5091 }
5092
5093 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5094
5095 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5096 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
5097 u32 last_plus_one, u32 *start,
5098 u32 base_flags, u32 mss)
5099 {
5100 struct tg3_napi *tnapi = &tp->napi[0];
5101 struct sk_buff *new_skb;
5102 dma_addr_t new_addr = 0;
5103 u32 entry = *start;
5104 int i, ret = 0;
5105
5106 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5107 new_skb = skb_copy(skb, GFP_ATOMIC);
5108 else {
5109 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5110
5111 new_skb = skb_copy_expand(skb,
5112 skb_headroom(skb) + more_headroom,
5113 skb_tailroom(skb), GFP_ATOMIC);
5114 }
5115
5116 if (!new_skb) {
5117 ret = -1;
5118 } else {
5119 /* New SKB is guaranteed to be linear. */
5120 entry = *start;
5121 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
5122 new_addr = skb_shinfo(new_skb)->dma_head;
5123
5124 /* Make sure new skb does not cross any 4G boundaries.
5125 * Drop the packet if it does.
5126 */
5127 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
5128 if (!ret)
5129 skb_dma_unmap(&tp->pdev->dev, new_skb,
5130 DMA_TO_DEVICE);
5131 ret = -1;
5132 dev_kfree_skb(new_skb);
5133 new_skb = NULL;
5134 } else {
5135 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5136 base_flags, 1 | (mss << 1));
5137 *start = NEXT_TX(entry);
5138 }
5139 }
5140
5141 /* Now clean up the sw ring entries. */
5142 i = 0;
5143 while (entry != last_plus_one) {
5144 if (i == 0)
5145 tnapi->tx_buffers[entry].skb = new_skb;
5146 else
5147 tnapi->tx_buffers[entry].skb = NULL;
5148 entry = NEXT_TX(entry);
5149 i++;
5150 }
5151
5152 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5153 dev_kfree_skb(skb);
5154
5155 return ret;
5156 }
5157
5158 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5159 dma_addr_t mapping, int len, u32 flags,
5160 u32 mss_and_is_end)
5161 {
5162 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5163 int is_end = (mss_and_is_end & 0x1);
5164 u32 mss = (mss_and_is_end >> 1);
5165 u32 vlan_tag = 0;
5166
5167 if (is_end)
5168 flags |= TXD_FLAG_END;
5169 if (flags & TXD_FLAG_VLAN) {
5170 vlan_tag = flags >> 16;
5171 flags &= 0xffff;
5172 }
5173 vlan_tag |= (mss << TXD_MSS_SHIFT);
5174
5175 txd->addr_hi = ((u64) mapping >> 32);
5176 txd->addr_lo = ((u64) mapping & 0xffffffff);
5177 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5178 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5179 }
5180
5181 /* hard_start_xmit for devices that don't have any bugs and
5182 * support TG3_FLG2_HW_TSO_2 only.
5183 */
5184 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5185 struct net_device *dev)
5186 {
5187 struct tg3 *tp = netdev_priv(dev);
5188 u32 len, entry, base_flags, mss;
5189 struct skb_shared_info *sp;
5190 dma_addr_t mapping;
5191 struct tg3_napi *tnapi;
5192 struct netdev_queue *txq;
5193
5194 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5195 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5196 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
5197 tnapi++;
5198
5199 /* We are running in BH disabled context with netif_tx_lock
5200 * and TX reclaim runs via tp->napi.poll inside of a software
5201 * interrupt. Furthermore, IRQ processing runs lockless so we have
5202 * no IRQ context deadlocks to worry about either. Rejoice!
5203 */
5204 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5205 if (!netif_tx_queue_stopped(txq)) {
5206 netif_tx_stop_queue(txq);
5207
5208 /* This is a hard error, log it. */
5209 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5210 "queue awake!\n", dev->name);
5211 }
5212 return NETDEV_TX_BUSY;
5213 }
5214
5215 entry = tnapi->tx_prod;
5216 base_flags = 0;
5217 mss = 0;
5218 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5219 int tcp_opt_len, ip_tcp_len;
5220 u32 hdrlen;
5221
5222 if (skb_header_cloned(skb) &&
5223 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5224 dev_kfree_skb(skb);
5225 goto out_unlock;
5226 }
5227
5228 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5229 hdrlen = skb_headlen(skb) - ETH_HLEN;
5230 else {
5231 struct iphdr *iph = ip_hdr(skb);
5232
5233 tcp_opt_len = tcp_optlen(skb);
5234 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5235
5236 iph->check = 0;
5237 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5238 hdrlen = ip_tcp_len + tcp_opt_len;
5239 }
5240
5241 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
5242 mss |= (hdrlen & 0xc) << 12;
5243 if (hdrlen & 0x10)
5244 base_flags |= 0x00000010;
5245 base_flags |= (hdrlen & 0x3e0) << 5;
5246 } else
5247 mss |= hdrlen << 9;
5248
5249 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5250 TXD_FLAG_CPU_POST_DMA);
5251
5252 tcp_hdr(skb)->check = 0;
5253
5254 }
5255 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5256 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5257 #if TG3_VLAN_TAG_USED
5258 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5259 base_flags |= (TXD_FLAG_VLAN |
5260 (vlan_tx_tag_get(skb) << 16));
5261 #endif
5262
5263 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5264 dev_kfree_skb(skb);
5265 goto out_unlock;
5266 }
5267
5268 sp = skb_shinfo(skb);
5269
5270 mapping = sp->dma_head;
5271
5272 tnapi->tx_buffers[entry].skb = skb;
5273
5274 len = skb_headlen(skb);
5275
5276 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
5277 !mss && skb->len > ETH_DATA_LEN)
5278 base_flags |= TXD_FLAG_JMB_PKT;
5279
5280 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5281 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5282
5283 entry = NEXT_TX(entry);
5284
5285 /* Now loop through additional data fragments, and queue them. */
5286 if (skb_shinfo(skb)->nr_frags > 0) {
5287 unsigned int i, last;
5288
5289 last = skb_shinfo(skb)->nr_frags - 1;
5290 for (i = 0; i <= last; i++) {
5291 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5292
5293 len = frag->size;
5294 mapping = sp->dma_maps[i];
5295 tnapi->tx_buffers[entry].skb = NULL;
5296
5297 tg3_set_txd(tnapi, entry, mapping, len,
5298 base_flags, (i == last) | (mss << 1));
5299
5300 entry = NEXT_TX(entry);
5301 }
5302 }
5303
5304 /* Packets are ready, update Tx producer idx local and on card. */
5305 tw32_tx_mbox(tnapi->prodmbox, entry);
5306
5307 tnapi->tx_prod = entry;
5308 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5309 netif_tx_stop_queue(txq);
5310 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5311 netif_tx_wake_queue(txq);
5312 }
5313
5314 out_unlock:
5315 mmiowb();
5316
5317 return NETDEV_TX_OK;
5318 }
5319
5320 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5321 struct net_device *);
5322
5323 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5324 * TSO header is greater than 80 bytes.
5325 */
5326 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5327 {
5328 struct sk_buff *segs, *nskb;
5329 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5330
5331 /* Estimate the number of fragments in the worst case */
5332 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5333 netif_stop_queue(tp->dev);
5334 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5335 return NETDEV_TX_BUSY;
5336
5337 netif_wake_queue(tp->dev);
5338 }
5339
5340 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5341 if (IS_ERR(segs))
5342 goto tg3_tso_bug_end;
5343
5344 do {
5345 nskb = segs;
5346 segs = segs->next;
5347 nskb->next = NULL;
5348 tg3_start_xmit_dma_bug(nskb, tp->dev);
5349 } while (segs);
5350
5351 tg3_tso_bug_end:
5352 dev_kfree_skb(skb);
5353
5354 return NETDEV_TX_OK;
5355 }
5356
5357 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5358 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5359 */
5360 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5361 struct net_device *dev)
5362 {
5363 struct tg3 *tp = netdev_priv(dev);
5364 u32 len, entry, base_flags, mss;
5365 struct skb_shared_info *sp;
5366 int would_hit_hwbug;
5367 dma_addr_t mapping;
5368 struct tg3_napi *tnapi = &tp->napi[0];
5369
5370 len = skb_headlen(skb);
5371
5372 /* We are running in BH disabled context with netif_tx_lock
5373 * and TX reclaim runs via tp->napi.poll inside of a software
5374 * interrupt. Furthermore, IRQ processing runs lockless so we have
5375 * no IRQ context deadlocks to worry about either. Rejoice!
5376 */
5377 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5378 if (!netif_queue_stopped(dev)) {
5379 netif_stop_queue(dev);
5380
5381 /* This is a hard error, log it. */
5382 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5383 "queue awake!\n", dev->name);
5384 }
5385 return NETDEV_TX_BUSY;
5386 }
5387
5388 entry = tnapi->tx_prod;
5389 base_flags = 0;
5390 if (skb->ip_summed == CHECKSUM_PARTIAL)
5391 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5392 mss = 0;
5393 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5394 struct iphdr *iph;
5395 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5396
5397 if (skb_header_cloned(skb) &&
5398 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5399 dev_kfree_skb(skb);
5400 goto out_unlock;
5401 }
5402
5403 tcp_opt_len = tcp_optlen(skb);
5404 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5405
5406 hdr_len = ip_tcp_len + tcp_opt_len;
5407 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5408 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5409 return (tg3_tso_bug(tp, skb));
5410
5411 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5412 TXD_FLAG_CPU_POST_DMA);
5413
5414 iph = ip_hdr(skb);
5415 iph->check = 0;
5416 iph->tot_len = htons(mss + hdr_len);
5417 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5418 tcp_hdr(skb)->check = 0;
5419 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5420 } else
5421 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5422 iph->daddr, 0,
5423 IPPROTO_TCP,
5424 0);
5425
5426 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5427 mss |= hdr_len << 9;
5428 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5429 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5430 if (tcp_opt_len || iph->ihl > 5) {
5431 int tsflags;
5432
5433 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5434 mss |= (tsflags << 11);
5435 }
5436 } else {
5437 if (tcp_opt_len || iph->ihl > 5) {
5438 int tsflags;
5439
5440 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5441 base_flags |= tsflags << 12;
5442 }
5443 }
5444 }
5445 #if TG3_VLAN_TAG_USED
5446 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5447 base_flags |= (TXD_FLAG_VLAN |
5448 (vlan_tx_tag_get(skb) << 16));
5449 #endif
5450
5451 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5452 dev_kfree_skb(skb);
5453 goto out_unlock;
5454 }
5455
5456 sp = skb_shinfo(skb);
5457
5458 mapping = sp->dma_head;
5459
5460 tnapi->tx_buffers[entry].skb = skb;
5461
5462 would_hit_hwbug = 0;
5463
5464 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5465 would_hit_hwbug = 1;
5466
5467 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5468 would_hit_hwbug = 1;
5469 else if (tg3_4g_overflow_test(mapping, len))
5470 would_hit_hwbug = 1;
5471
5472 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5473 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5474
5475 entry = NEXT_TX(entry);
5476
5477 /* Now loop through additional data fragments, and queue them. */
5478 if (skb_shinfo(skb)->nr_frags > 0) {
5479 unsigned int i, last;
5480
5481 last = skb_shinfo(skb)->nr_frags - 1;
5482 for (i = 0; i <= last; i++) {
5483 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5484
5485 len = frag->size;
5486 mapping = sp->dma_maps[i];
5487
5488 tnapi->tx_buffers[entry].skb = NULL;
5489
5490 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5491 len <= 8)
5492 would_hit_hwbug = 1;
5493
5494 if (tg3_4g_overflow_test(mapping, len))
5495 would_hit_hwbug = 1;
5496
5497 if (tg3_40bit_overflow_test(tp, mapping, len))
5498 would_hit_hwbug = 1;
5499
5500 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5501 tg3_set_txd(tnapi, entry, mapping, len,
5502 base_flags, (i == last)|(mss << 1));
5503 else
5504 tg3_set_txd(tnapi, entry, mapping, len,
5505 base_flags, (i == last));
5506
5507 entry = NEXT_TX(entry);
5508 }
5509 }
5510
5511 if (would_hit_hwbug) {
5512 u32 last_plus_one = entry;
5513 u32 start;
5514
5515 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5516 start &= (TG3_TX_RING_SIZE - 1);
5517
5518 /* If the workaround fails due to memory/mapping
5519 * failure, silently drop this packet.
5520 */
5521 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5522 &start, base_flags, mss))
5523 goto out_unlock;
5524
5525 entry = start;
5526 }
5527
5528 /* Packets are ready, update Tx producer idx local and on card. */
5529 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, entry);
5530
5531 tnapi->tx_prod = entry;
5532 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5533 netif_stop_queue(dev);
5534 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5535 netif_wake_queue(tp->dev);
5536 }
5537
5538 out_unlock:
5539 mmiowb();
5540
5541 return NETDEV_TX_OK;
5542 }
5543
5544 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5545 int new_mtu)
5546 {
5547 dev->mtu = new_mtu;
5548
5549 if (new_mtu > ETH_DATA_LEN) {
5550 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5551 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5552 ethtool_op_set_tso(dev, 0);
5553 }
5554 else
5555 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5556 } else {
5557 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5558 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5559 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5560 }
5561 }
5562
5563 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5564 {
5565 struct tg3 *tp = netdev_priv(dev);
5566 int err;
5567
5568 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5569 return -EINVAL;
5570
5571 if (!netif_running(dev)) {
5572 /* We'll just catch it later when the
5573 * device is up'd.
5574 */
5575 tg3_set_mtu(dev, tp, new_mtu);
5576 return 0;
5577 }
5578
5579 tg3_phy_stop(tp);
5580
5581 tg3_netif_stop(tp);
5582
5583 tg3_full_lock(tp, 1);
5584
5585 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5586
5587 tg3_set_mtu(dev, tp, new_mtu);
5588
5589 err = tg3_restart_hw(tp, 0);
5590
5591 if (!err)
5592 tg3_netif_start(tp);
5593
5594 tg3_full_unlock(tp);
5595
5596 if (!err)
5597 tg3_phy_start(tp);
5598
5599 return err;
5600 }
5601
5602 static void tg3_rx_prodring_free(struct tg3 *tp,
5603 struct tg3_rx_prodring_set *tpr)
5604 {
5605 int i;
5606 struct ring_info *rxp;
5607
5608 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5609 rxp = &tpr->rx_std_buffers[i];
5610
5611 if (rxp->skb == NULL)
5612 continue;
5613
5614 pci_unmap_single(tp->pdev,
5615 pci_unmap_addr(rxp, mapping),
5616 tp->rx_pkt_map_sz,
5617 PCI_DMA_FROMDEVICE);
5618 dev_kfree_skb_any(rxp->skb);
5619 rxp->skb = NULL;
5620 }
5621
5622 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5623 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5624 rxp = &tpr->rx_jmb_buffers[i];
5625
5626 if (rxp->skb == NULL)
5627 continue;
5628
5629 pci_unmap_single(tp->pdev,
5630 pci_unmap_addr(rxp, mapping),
5631 TG3_RX_JMB_MAP_SZ,
5632 PCI_DMA_FROMDEVICE);
5633 dev_kfree_skb_any(rxp->skb);
5634 rxp->skb = NULL;
5635 }
5636 }
5637 }
5638
5639 /* Initialize tx/rx rings for packet processing.
5640 *
5641 * The chip has been shut down and the driver detached from
5642 * the networking, so no interrupts or new tx packets will
5643 * end up in the driver. tp->{tx,}lock are held and thus
5644 * we may not sleep.
5645 */
5646 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5647 struct tg3_rx_prodring_set *tpr)
5648 {
5649 u32 i, rx_pkt_dma_sz;
5650 struct tg3_napi *tnapi = &tp->napi[0];
5651
5652 /* Zero out all descriptors. */
5653 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5654
5655 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5656 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5657 tp->dev->mtu > ETH_DATA_LEN)
5658 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5659 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5660
5661 /* Initialize invariants of the rings, we only set this
5662 * stuff once. This works because the card does not
5663 * write into the rx buffer posting rings.
5664 */
5665 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5666 struct tg3_rx_buffer_desc *rxd;
5667
5668 rxd = &tpr->rx_std[i];
5669 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
5670 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5671 rxd->opaque = (RXD_OPAQUE_RING_STD |
5672 (i << RXD_OPAQUE_INDEX_SHIFT));
5673 }
5674
5675 /* Now allocate fresh SKBs for each rx ring. */
5676 for (i = 0; i < tp->rx_pending; i++) {
5677 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5678 printk(KERN_WARNING PFX
5679 "%s: Using a smaller RX standard ring, "
5680 "only %d out of %d buffers were allocated "
5681 "successfully.\n",
5682 tp->dev->name, i, tp->rx_pending);
5683 if (i == 0)
5684 goto initfail;
5685 tp->rx_pending = i;
5686 break;
5687 }
5688 }
5689
5690 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
5691 goto done;
5692
5693 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
5694
5695 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5696 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5697 struct tg3_rx_buffer_desc *rxd;
5698
5699 rxd = &tpr->rx_jmb[i].std;
5700 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
5701 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5702 RXD_FLAG_JUMBO;
5703 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5704 (i << RXD_OPAQUE_INDEX_SHIFT));
5705 }
5706
5707 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5708 if (tg3_alloc_rx_skb(tnapi, RXD_OPAQUE_RING_JUMBO,
5709 -1, i) < 0) {
5710 printk(KERN_WARNING PFX
5711 "%s: Using a smaller RX jumbo ring, "
5712 "only %d out of %d buffers were "
5713 "allocated successfully.\n",
5714 tp->dev->name, i, tp->rx_jumbo_pending);
5715 if (i == 0)
5716 goto initfail;
5717 tp->rx_jumbo_pending = i;
5718 break;
5719 }
5720 }
5721 }
5722
5723 done:
5724 return 0;
5725
5726 initfail:
5727 tg3_rx_prodring_free(tp, tpr);
5728 return -ENOMEM;
5729 }
5730
5731 static void tg3_rx_prodring_fini(struct tg3 *tp,
5732 struct tg3_rx_prodring_set *tpr)
5733 {
5734 kfree(tpr->rx_std_buffers);
5735 tpr->rx_std_buffers = NULL;
5736 kfree(tpr->rx_jmb_buffers);
5737 tpr->rx_jmb_buffers = NULL;
5738 if (tpr->rx_std) {
5739 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5740 tpr->rx_std, tpr->rx_std_mapping);
5741 tpr->rx_std = NULL;
5742 }
5743 if (tpr->rx_jmb) {
5744 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5745 tpr->rx_jmb, tpr->rx_jmb_mapping);
5746 tpr->rx_jmb = NULL;
5747 }
5748 }
5749
5750 static int tg3_rx_prodring_init(struct tg3 *tp,
5751 struct tg3_rx_prodring_set *tpr)
5752 {
5753 tpr->rx_std_buffers = kzalloc(sizeof(struct ring_info) *
5754 TG3_RX_RING_SIZE, GFP_KERNEL);
5755 if (!tpr->rx_std_buffers)
5756 return -ENOMEM;
5757
5758 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5759 &tpr->rx_std_mapping);
5760 if (!tpr->rx_std)
5761 goto err_out;
5762
5763 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5764 tpr->rx_jmb_buffers = kzalloc(sizeof(struct ring_info) *
5765 TG3_RX_JUMBO_RING_SIZE,
5766 GFP_KERNEL);
5767 if (!tpr->rx_jmb_buffers)
5768 goto err_out;
5769
5770 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
5771 TG3_RX_JUMBO_RING_BYTES,
5772 &tpr->rx_jmb_mapping);
5773 if (!tpr->rx_jmb)
5774 goto err_out;
5775 }
5776
5777 return 0;
5778
5779 err_out:
5780 tg3_rx_prodring_fini(tp, tpr);
5781 return -ENOMEM;
5782 }
5783
5784 /* Free up pending packets in all rx/tx rings.
5785 *
5786 * The chip has been shut down and the driver detached from
5787 * the networking, so no interrupts or new tx packets will
5788 * end up in the driver. tp->{tx,}lock is not held and we are not
5789 * in an interrupt context and thus may sleep.
5790 */
5791 static void tg3_free_rings(struct tg3 *tp)
5792 {
5793 int i, j;
5794
5795 for (j = 0; j < tp->irq_cnt; j++) {
5796 struct tg3_napi *tnapi = &tp->napi[j];
5797
5798 if (!tnapi->tx_buffers)
5799 continue;
5800
5801 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5802 struct tx_ring_info *txp;
5803 struct sk_buff *skb;
5804
5805 txp = &tnapi->tx_buffers[i];
5806 skb = txp->skb;
5807
5808 if (skb == NULL) {
5809 i++;
5810 continue;
5811 }
5812
5813 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5814
5815 txp->skb = NULL;
5816
5817 i += skb_shinfo(skb)->nr_frags + 1;
5818
5819 dev_kfree_skb_any(skb);
5820 }
5821 }
5822
5823 tg3_rx_prodring_free(tp, &tp->prodring[0]);
5824 }
5825
5826 /* Initialize tx/rx rings for packet processing.
5827 *
5828 * The chip has been shut down and the driver detached from
5829 * the networking, so no interrupts or new tx packets will
5830 * end up in the driver. tp->{tx,}lock are held and thus
5831 * we may not sleep.
5832 */
5833 static int tg3_init_rings(struct tg3 *tp)
5834 {
5835 int i;
5836
5837 /* Free up all the SKBs. */
5838 tg3_free_rings(tp);
5839
5840 for (i = 0; i < tp->irq_cnt; i++) {
5841 struct tg3_napi *tnapi = &tp->napi[i];
5842
5843 tnapi->last_tag = 0;
5844 tnapi->last_irq_tag = 0;
5845 tnapi->hw_status->status = 0;
5846 tnapi->hw_status->status_tag = 0;
5847 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5848
5849 tnapi->tx_prod = 0;
5850 tnapi->tx_cons = 0;
5851 if (tnapi->tx_ring)
5852 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
5853
5854 tnapi->rx_rcb_ptr = 0;
5855 if (tnapi->rx_rcb)
5856 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5857 }
5858
5859 return tg3_rx_prodring_alloc(tp, &tp->prodring[0]);
5860 }
5861
5862 /*
5863 * Must not be invoked with interrupt sources disabled and
5864 * the hardware shutdown down.
5865 */
5866 static void tg3_free_consistent(struct tg3 *tp)
5867 {
5868 int i;
5869
5870 for (i = 0; i < tp->irq_cnt; i++) {
5871 struct tg3_napi *tnapi = &tp->napi[i];
5872
5873 if (tnapi->tx_ring) {
5874 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5875 tnapi->tx_ring, tnapi->tx_desc_mapping);
5876 tnapi->tx_ring = NULL;
5877 }
5878
5879 kfree(tnapi->tx_buffers);
5880 tnapi->tx_buffers = NULL;
5881
5882 if (tnapi->rx_rcb) {
5883 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5884 tnapi->rx_rcb,
5885 tnapi->rx_rcb_mapping);
5886 tnapi->rx_rcb = NULL;
5887 }
5888
5889 if (tnapi->hw_status) {
5890 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5891 tnapi->hw_status,
5892 tnapi->status_mapping);
5893 tnapi->hw_status = NULL;
5894 }
5895 }
5896
5897 if (tp->hw_stats) {
5898 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5899 tp->hw_stats, tp->stats_mapping);
5900 tp->hw_stats = NULL;
5901 }
5902
5903 tg3_rx_prodring_fini(tp, &tp->prodring[0]);
5904 }
5905
5906 /*
5907 * Must not be invoked with interrupt sources disabled and
5908 * the hardware shutdown down. Can sleep.
5909 */
5910 static int tg3_alloc_consistent(struct tg3 *tp)
5911 {
5912 int i;
5913
5914 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5915 return -ENOMEM;
5916
5917 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5918 sizeof(struct tg3_hw_stats),
5919 &tp->stats_mapping);
5920 if (!tp->hw_stats)
5921 goto err_out;
5922
5923 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5924
5925 for (i = 0; i < tp->irq_cnt; i++) {
5926 struct tg3_napi *tnapi = &tp->napi[i];
5927 struct tg3_hw_status *sblk;
5928
5929 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5930 TG3_HW_STATUS_SIZE,
5931 &tnapi->status_mapping);
5932 if (!tnapi->hw_status)
5933 goto err_out;
5934
5935 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5936 sblk = tnapi->hw_status;
5937
5938 /*
5939 * When RSS is enabled, the status block format changes
5940 * slightly. The "rx_jumbo_consumer", "reserved",
5941 * and "rx_mini_consumer" members get mapped to the
5942 * other three rx return ring producer indexes.
5943 */
5944 switch (i) {
5945 default:
5946 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
5947 break;
5948 case 2:
5949 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
5950 break;
5951 case 3:
5952 tnapi->rx_rcb_prod_idx = &sblk->reserved;
5953 break;
5954 case 4:
5955 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
5956 break;
5957 }
5958
5959 /*
5960 * If multivector RSS is enabled, vector 0 does not handle
5961 * rx or tx interrupts. Don't allocate any resources for it.
5962 */
5963 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
5964 continue;
5965
5966 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
5967 TG3_RX_RCB_RING_BYTES(tp),
5968 &tnapi->rx_rcb_mapping);
5969 if (!tnapi->rx_rcb)
5970 goto err_out;
5971
5972 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5973
5974 tnapi->tx_buffers = kzalloc(sizeof(struct tx_ring_info) *
5975 TG3_TX_RING_SIZE, GFP_KERNEL);
5976 if (!tnapi->tx_buffers)
5977 goto err_out;
5978
5979 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
5980 TG3_TX_RING_BYTES,
5981 &tnapi->tx_desc_mapping);
5982 if (!tnapi->tx_ring)
5983 goto err_out;
5984 }
5985
5986 return 0;
5987
5988 err_out:
5989 tg3_free_consistent(tp);
5990 return -ENOMEM;
5991 }
5992
5993 #define MAX_WAIT_CNT 1000
5994
5995 /* To stop a block, clear the enable bit and poll till it
5996 * clears. tp->lock is held.
5997 */
5998 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5999 {
6000 unsigned int i;
6001 u32 val;
6002
6003 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6004 switch (ofs) {
6005 case RCVLSC_MODE:
6006 case DMAC_MODE:
6007 case MBFREE_MODE:
6008 case BUFMGR_MODE:
6009 case MEMARB_MODE:
6010 /* We can't enable/disable these bits of the
6011 * 5705/5750, just say success.
6012 */
6013 return 0;
6014
6015 default:
6016 break;
6017 }
6018 }
6019
6020 val = tr32(ofs);
6021 val &= ~enable_bit;
6022 tw32_f(ofs, val);
6023
6024 for (i = 0; i < MAX_WAIT_CNT; i++) {
6025 udelay(100);
6026 val = tr32(ofs);
6027 if ((val & enable_bit) == 0)
6028 break;
6029 }
6030
6031 if (i == MAX_WAIT_CNT && !silent) {
6032 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6033 "ofs=%lx enable_bit=%x\n",
6034 ofs, enable_bit);
6035 return -ENODEV;
6036 }
6037
6038 return 0;
6039 }
6040
6041 /* tp->lock is held. */
6042 static int tg3_abort_hw(struct tg3 *tp, int silent)
6043 {
6044 int i, err;
6045
6046 tg3_disable_ints(tp);
6047
6048 tp->rx_mode &= ~RX_MODE_ENABLE;
6049 tw32_f(MAC_RX_MODE, tp->rx_mode);
6050 udelay(10);
6051
6052 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6053 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6054 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6055 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6056 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6057 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6058
6059 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6060 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6061 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6062 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6063 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6064 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6065 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6066
6067 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6068 tw32_f(MAC_MODE, tp->mac_mode);
6069 udelay(40);
6070
6071 tp->tx_mode &= ~TX_MODE_ENABLE;
6072 tw32_f(MAC_TX_MODE, tp->tx_mode);
6073
6074 for (i = 0; i < MAX_WAIT_CNT; i++) {
6075 udelay(100);
6076 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6077 break;
6078 }
6079 if (i >= MAX_WAIT_CNT) {
6080 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6081 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6082 tp->dev->name, tr32(MAC_TX_MODE));
6083 err |= -ENODEV;
6084 }
6085
6086 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6087 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6088 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6089
6090 tw32(FTQ_RESET, 0xffffffff);
6091 tw32(FTQ_RESET, 0x00000000);
6092
6093 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6094 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6095
6096 for (i = 0; i < tp->irq_cnt; i++) {
6097 struct tg3_napi *tnapi = &tp->napi[i];
6098 if (tnapi->hw_status)
6099 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6100 }
6101 if (tp->hw_stats)
6102 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6103
6104 return err;
6105 }
6106
6107 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6108 {
6109 int i;
6110 u32 apedata;
6111
6112 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6113 if (apedata != APE_SEG_SIG_MAGIC)
6114 return;
6115
6116 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6117 if (!(apedata & APE_FW_STATUS_READY))
6118 return;
6119
6120 /* Wait for up to 1 millisecond for APE to service previous event. */
6121 for (i = 0; i < 10; i++) {
6122 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6123 return;
6124
6125 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6126
6127 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6128 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6129 event | APE_EVENT_STATUS_EVENT_PENDING);
6130
6131 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6132
6133 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6134 break;
6135
6136 udelay(100);
6137 }
6138
6139 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6140 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6141 }
6142
6143 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6144 {
6145 u32 event;
6146 u32 apedata;
6147
6148 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6149 return;
6150
6151 switch (kind) {
6152 case RESET_KIND_INIT:
6153 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6154 APE_HOST_SEG_SIG_MAGIC);
6155 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6156 APE_HOST_SEG_LEN_MAGIC);
6157 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6158 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6159 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6160 APE_HOST_DRIVER_ID_MAGIC);
6161 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6162 APE_HOST_BEHAV_NO_PHYLOCK);
6163
6164 event = APE_EVENT_STATUS_STATE_START;
6165 break;
6166 case RESET_KIND_SHUTDOWN:
6167 /* With the interface we are currently using,
6168 * APE does not track driver state. Wiping
6169 * out the HOST SEGMENT SIGNATURE forces
6170 * the APE to assume OS absent status.
6171 */
6172 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6173
6174 event = APE_EVENT_STATUS_STATE_UNLOAD;
6175 break;
6176 case RESET_KIND_SUSPEND:
6177 event = APE_EVENT_STATUS_STATE_SUSPEND;
6178 break;
6179 default:
6180 return;
6181 }
6182
6183 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6184
6185 tg3_ape_send_event(tp, event);
6186 }
6187
6188 /* tp->lock is held. */
6189 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6190 {
6191 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6192 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6193
6194 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6195 switch (kind) {
6196 case RESET_KIND_INIT:
6197 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6198 DRV_STATE_START);
6199 break;
6200
6201 case RESET_KIND_SHUTDOWN:
6202 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6203 DRV_STATE_UNLOAD);
6204 break;
6205
6206 case RESET_KIND_SUSPEND:
6207 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6208 DRV_STATE_SUSPEND);
6209 break;
6210
6211 default:
6212 break;
6213 }
6214 }
6215
6216 if (kind == RESET_KIND_INIT ||
6217 kind == RESET_KIND_SUSPEND)
6218 tg3_ape_driver_state_change(tp, kind);
6219 }
6220
6221 /* tp->lock is held. */
6222 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6223 {
6224 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6225 switch (kind) {
6226 case RESET_KIND_INIT:
6227 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6228 DRV_STATE_START_DONE);
6229 break;
6230
6231 case RESET_KIND_SHUTDOWN:
6232 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6233 DRV_STATE_UNLOAD_DONE);
6234 break;
6235
6236 default:
6237 break;
6238 }
6239 }
6240
6241 if (kind == RESET_KIND_SHUTDOWN)
6242 tg3_ape_driver_state_change(tp, kind);
6243 }
6244
6245 /* tp->lock is held. */
6246 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6247 {
6248 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6249 switch (kind) {
6250 case RESET_KIND_INIT:
6251 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6252 DRV_STATE_START);
6253 break;
6254
6255 case RESET_KIND_SHUTDOWN:
6256 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6257 DRV_STATE_UNLOAD);
6258 break;
6259
6260 case RESET_KIND_SUSPEND:
6261 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6262 DRV_STATE_SUSPEND);
6263 break;
6264
6265 default:
6266 break;
6267 }
6268 }
6269 }
6270
6271 static int tg3_poll_fw(struct tg3 *tp)
6272 {
6273 int i;
6274 u32 val;
6275
6276 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6277 /* Wait up to 20ms for init done. */
6278 for (i = 0; i < 200; i++) {
6279 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6280 return 0;
6281 udelay(100);
6282 }
6283 return -ENODEV;
6284 }
6285
6286 /* Wait for firmware initialization to complete. */
6287 for (i = 0; i < 100000; i++) {
6288 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6289 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6290 break;
6291 udelay(10);
6292 }
6293
6294 /* Chip might not be fitted with firmware. Some Sun onboard
6295 * parts are configured like that. So don't signal the timeout
6296 * of the above loop as an error, but do report the lack of
6297 * running firmware once.
6298 */
6299 if (i >= 100000 &&
6300 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6301 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6302
6303 printk(KERN_INFO PFX "%s: No firmware running.\n",
6304 tp->dev->name);
6305 }
6306
6307 return 0;
6308 }
6309
6310 /* Save PCI command register before chip reset */
6311 static void tg3_save_pci_state(struct tg3 *tp)
6312 {
6313 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6314 }
6315
6316 /* Restore PCI state after chip reset */
6317 static void tg3_restore_pci_state(struct tg3 *tp)
6318 {
6319 u32 val;
6320
6321 /* Re-enable indirect register accesses. */
6322 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6323 tp->misc_host_ctrl);
6324
6325 /* Set MAX PCI retry to zero. */
6326 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6327 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6328 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6329 val |= PCISTATE_RETRY_SAME_DMA;
6330 /* Allow reads and writes to the APE register and memory space. */
6331 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6332 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6333 PCISTATE_ALLOW_APE_SHMEM_WR;
6334 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6335
6336 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6337
6338 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6339 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6340 pcie_set_readrq(tp->pdev, 4096);
6341 else {
6342 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6343 tp->pci_cacheline_sz);
6344 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6345 tp->pci_lat_timer);
6346 }
6347 }
6348
6349 /* Make sure PCI-X relaxed ordering bit is clear. */
6350 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6351 u16 pcix_cmd;
6352
6353 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6354 &pcix_cmd);
6355 pcix_cmd &= ~PCI_X_CMD_ERO;
6356 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6357 pcix_cmd);
6358 }
6359
6360 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6361
6362 /* Chip reset on 5780 will reset MSI enable bit,
6363 * so need to restore it.
6364 */
6365 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6366 u16 ctrl;
6367
6368 pci_read_config_word(tp->pdev,
6369 tp->msi_cap + PCI_MSI_FLAGS,
6370 &ctrl);
6371 pci_write_config_word(tp->pdev,
6372 tp->msi_cap + PCI_MSI_FLAGS,
6373 ctrl | PCI_MSI_FLAGS_ENABLE);
6374 val = tr32(MSGINT_MODE);
6375 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6376 }
6377 }
6378 }
6379
6380 static void tg3_stop_fw(struct tg3 *);
6381
6382 /* tp->lock is held. */
6383 static int tg3_chip_reset(struct tg3 *tp)
6384 {
6385 u32 val;
6386 void (*write_op)(struct tg3 *, u32, u32);
6387 int i, err;
6388
6389 tg3_nvram_lock(tp);
6390
6391 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6392
6393 /* No matching tg3_nvram_unlock() after this because
6394 * chip reset below will undo the nvram lock.
6395 */
6396 tp->nvram_lock_cnt = 0;
6397
6398 /* GRC_MISC_CFG core clock reset will clear the memory
6399 * enable bit in PCI register 4 and the MSI enable bit
6400 * on some chips, so we save relevant registers here.
6401 */
6402 tg3_save_pci_state(tp);
6403
6404 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6405 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6406 tw32(GRC_FASTBOOT_PC, 0);
6407
6408 /*
6409 * We must avoid the readl() that normally takes place.
6410 * It locks machines, causes machine checks, and other
6411 * fun things. So, temporarily disable the 5701
6412 * hardware workaround, while we do the reset.
6413 */
6414 write_op = tp->write32;
6415 if (write_op == tg3_write_flush_reg32)
6416 tp->write32 = tg3_write32;
6417
6418 /* Prevent the irq handler from reading or writing PCI registers
6419 * during chip reset when the memory enable bit in the PCI command
6420 * register may be cleared. The chip does not generate interrupt
6421 * at this time, but the irq handler may still be called due to irq
6422 * sharing or irqpoll.
6423 */
6424 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6425 for (i = 0; i < tp->irq_cnt; i++) {
6426 struct tg3_napi *tnapi = &tp->napi[i];
6427 if (tnapi->hw_status) {
6428 tnapi->hw_status->status = 0;
6429 tnapi->hw_status->status_tag = 0;
6430 }
6431 tnapi->last_tag = 0;
6432 tnapi->last_irq_tag = 0;
6433 }
6434 smp_mb();
6435
6436 for (i = 0; i < tp->irq_cnt; i++)
6437 synchronize_irq(tp->napi[i].irq_vec);
6438
6439 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6440 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6441 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6442 }
6443
6444 /* do the reset */
6445 val = GRC_MISC_CFG_CORECLK_RESET;
6446
6447 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6448 if (tr32(0x7e2c) == 0x60) {
6449 tw32(0x7e2c, 0x20);
6450 }
6451 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6452 tw32(GRC_MISC_CFG, (1 << 29));
6453 val |= (1 << 29);
6454 }
6455 }
6456
6457 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6458 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6459 tw32(GRC_VCPU_EXT_CTRL,
6460 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6461 }
6462
6463 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6464 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6465 tw32(GRC_MISC_CFG, val);
6466
6467 /* restore 5701 hardware bug workaround write method */
6468 tp->write32 = write_op;
6469
6470 /* Unfortunately, we have to delay before the PCI read back.
6471 * Some 575X chips even will not respond to a PCI cfg access
6472 * when the reset command is given to the chip.
6473 *
6474 * How do these hardware designers expect things to work
6475 * properly if the PCI write is posted for a long period
6476 * of time? It is always necessary to have some method by
6477 * which a register read back can occur to push the write
6478 * out which does the reset.
6479 *
6480 * For most tg3 variants the trick below was working.
6481 * Ho hum...
6482 */
6483 udelay(120);
6484
6485 /* Flush PCI posted writes. The normal MMIO registers
6486 * are inaccessible at this time so this is the only
6487 * way to make this reliably (actually, this is no longer
6488 * the case, see above). I tried to use indirect
6489 * register read/write but this upset some 5701 variants.
6490 */
6491 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6492
6493 udelay(120);
6494
6495 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6496 u16 val16;
6497
6498 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6499 int i;
6500 u32 cfg_val;
6501
6502 /* Wait for link training to complete. */
6503 for (i = 0; i < 5000; i++)
6504 udelay(100);
6505
6506 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6507 pci_write_config_dword(tp->pdev, 0xc4,
6508 cfg_val | (1 << 15));
6509 }
6510
6511 /* Clear the "no snoop" and "relaxed ordering" bits. */
6512 pci_read_config_word(tp->pdev,
6513 tp->pcie_cap + PCI_EXP_DEVCTL,
6514 &val16);
6515 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6516 PCI_EXP_DEVCTL_NOSNOOP_EN);
6517 /*
6518 * Older PCIe devices only support the 128 byte
6519 * MPS setting. Enforce the restriction.
6520 */
6521 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6522 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6523 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6524 pci_write_config_word(tp->pdev,
6525 tp->pcie_cap + PCI_EXP_DEVCTL,
6526 val16);
6527
6528 pcie_set_readrq(tp->pdev, 4096);
6529
6530 /* Clear error status */
6531 pci_write_config_word(tp->pdev,
6532 tp->pcie_cap + PCI_EXP_DEVSTA,
6533 PCI_EXP_DEVSTA_CED |
6534 PCI_EXP_DEVSTA_NFED |
6535 PCI_EXP_DEVSTA_FED |
6536 PCI_EXP_DEVSTA_URD);
6537 }
6538
6539 tg3_restore_pci_state(tp);
6540
6541 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6542
6543 val = 0;
6544 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6545 val = tr32(MEMARB_MODE);
6546 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6547
6548 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6549 tg3_stop_fw(tp);
6550 tw32(0x5000, 0x400);
6551 }
6552
6553 tw32(GRC_MODE, tp->grc_mode);
6554
6555 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6556 val = tr32(0xc4);
6557
6558 tw32(0xc4, val | (1 << 15));
6559 }
6560
6561 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6562 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6563 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6564 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6565 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6566 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6567 }
6568
6569 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6570 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6571 tw32_f(MAC_MODE, tp->mac_mode);
6572 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6573 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6574 tw32_f(MAC_MODE, tp->mac_mode);
6575 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6576 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6577 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6578 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6579 tw32_f(MAC_MODE, tp->mac_mode);
6580 } else
6581 tw32_f(MAC_MODE, 0);
6582 udelay(40);
6583
6584 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6585
6586 err = tg3_poll_fw(tp);
6587 if (err)
6588 return err;
6589
6590 tg3_mdio_start(tp);
6591
6592 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6593 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6594 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6595 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
6596 val = tr32(0x7c00);
6597
6598 tw32(0x7c00, val | (1 << 25));
6599 }
6600
6601 /* Reprobe ASF enable state. */
6602 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6603 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6604 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6605 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6606 u32 nic_cfg;
6607
6608 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6609 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6610 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6611 tp->last_event_jiffies = jiffies;
6612 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6613 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6614 }
6615 }
6616
6617 return 0;
6618 }
6619
6620 /* tp->lock is held. */
6621 static void tg3_stop_fw(struct tg3 *tp)
6622 {
6623 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6624 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6625 /* Wait for RX cpu to ACK the previous event. */
6626 tg3_wait_for_event_ack(tp);
6627
6628 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6629
6630 tg3_generate_fw_event(tp);
6631
6632 /* Wait for RX cpu to ACK this event. */
6633 tg3_wait_for_event_ack(tp);
6634 }
6635 }
6636
6637 /* tp->lock is held. */
6638 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6639 {
6640 int err;
6641
6642 tg3_stop_fw(tp);
6643
6644 tg3_write_sig_pre_reset(tp, kind);
6645
6646 tg3_abort_hw(tp, silent);
6647 err = tg3_chip_reset(tp);
6648
6649 __tg3_set_mac_addr(tp, 0);
6650
6651 tg3_write_sig_legacy(tp, kind);
6652 tg3_write_sig_post_reset(tp, kind);
6653
6654 if (err)
6655 return err;
6656
6657 return 0;
6658 }
6659
6660 #define RX_CPU_SCRATCH_BASE 0x30000
6661 #define RX_CPU_SCRATCH_SIZE 0x04000
6662 #define TX_CPU_SCRATCH_BASE 0x34000
6663 #define TX_CPU_SCRATCH_SIZE 0x04000
6664
6665 /* tp->lock is held. */
6666 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6667 {
6668 int i;
6669
6670 BUG_ON(offset == TX_CPU_BASE &&
6671 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6672
6673 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6674 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6675
6676 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6677 return 0;
6678 }
6679 if (offset == RX_CPU_BASE) {
6680 for (i = 0; i < 10000; i++) {
6681 tw32(offset + CPU_STATE, 0xffffffff);
6682 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6683 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6684 break;
6685 }
6686
6687 tw32(offset + CPU_STATE, 0xffffffff);
6688 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6689 udelay(10);
6690 } else {
6691 for (i = 0; i < 10000; i++) {
6692 tw32(offset + CPU_STATE, 0xffffffff);
6693 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6694 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6695 break;
6696 }
6697 }
6698
6699 if (i >= 10000) {
6700 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6701 "and %s CPU\n",
6702 tp->dev->name,
6703 (offset == RX_CPU_BASE ? "RX" : "TX"));
6704 return -ENODEV;
6705 }
6706
6707 /* Clear firmware's nvram arbitration. */
6708 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6709 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6710 return 0;
6711 }
6712
6713 struct fw_info {
6714 unsigned int fw_base;
6715 unsigned int fw_len;
6716 const __be32 *fw_data;
6717 };
6718
6719 /* tp->lock is held. */
6720 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6721 int cpu_scratch_size, struct fw_info *info)
6722 {
6723 int err, lock_err, i;
6724 void (*write_op)(struct tg3 *, u32, u32);
6725
6726 if (cpu_base == TX_CPU_BASE &&
6727 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6728 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6729 "TX cpu firmware on %s which is 5705.\n",
6730 tp->dev->name);
6731 return -EINVAL;
6732 }
6733
6734 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6735 write_op = tg3_write_mem;
6736 else
6737 write_op = tg3_write_indirect_reg32;
6738
6739 /* It is possible that bootcode is still loading at this point.
6740 * Get the nvram lock first before halting the cpu.
6741 */
6742 lock_err = tg3_nvram_lock(tp);
6743 err = tg3_halt_cpu(tp, cpu_base);
6744 if (!lock_err)
6745 tg3_nvram_unlock(tp);
6746 if (err)
6747 goto out;
6748
6749 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6750 write_op(tp, cpu_scratch_base + i, 0);
6751 tw32(cpu_base + CPU_STATE, 0xffffffff);
6752 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6753 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6754 write_op(tp, (cpu_scratch_base +
6755 (info->fw_base & 0xffff) +
6756 (i * sizeof(u32))),
6757 be32_to_cpu(info->fw_data[i]));
6758
6759 err = 0;
6760
6761 out:
6762 return err;
6763 }
6764
6765 /* tp->lock is held. */
6766 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6767 {
6768 struct fw_info info;
6769 const __be32 *fw_data;
6770 int err, i;
6771
6772 fw_data = (void *)tp->fw->data;
6773
6774 /* Firmware blob starts with version numbers, followed by
6775 start address and length. We are setting complete length.
6776 length = end_address_of_bss - start_address_of_text.
6777 Remainder is the blob to be loaded contiguously
6778 from start address. */
6779
6780 info.fw_base = be32_to_cpu(fw_data[1]);
6781 info.fw_len = tp->fw->size - 12;
6782 info.fw_data = &fw_data[3];
6783
6784 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6785 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6786 &info);
6787 if (err)
6788 return err;
6789
6790 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6791 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6792 &info);
6793 if (err)
6794 return err;
6795
6796 /* Now startup only the RX cpu. */
6797 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6798 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6799
6800 for (i = 0; i < 5; i++) {
6801 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6802 break;
6803 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6804 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6805 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6806 udelay(1000);
6807 }
6808 if (i >= 5) {
6809 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6810 "to set RX CPU PC, is %08x should be %08x\n",
6811 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6812 info.fw_base);
6813 return -ENODEV;
6814 }
6815 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6816 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6817
6818 return 0;
6819 }
6820
6821 /* 5705 needs a special version of the TSO firmware. */
6822
6823 /* tp->lock is held. */
6824 static int tg3_load_tso_firmware(struct tg3 *tp)
6825 {
6826 struct fw_info info;
6827 const __be32 *fw_data;
6828 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6829 int err, i;
6830
6831 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6832 return 0;
6833
6834 fw_data = (void *)tp->fw->data;
6835
6836 /* Firmware blob starts with version numbers, followed by
6837 start address and length. We are setting complete length.
6838 length = end_address_of_bss - start_address_of_text.
6839 Remainder is the blob to be loaded contiguously
6840 from start address. */
6841
6842 info.fw_base = be32_to_cpu(fw_data[1]);
6843 cpu_scratch_size = tp->fw_len;
6844 info.fw_len = tp->fw->size - 12;
6845 info.fw_data = &fw_data[3];
6846
6847 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6848 cpu_base = RX_CPU_BASE;
6849 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6850 } else {
6851 cpu_base = TX_CPU_BASE;
6852 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6853 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6854 }
6855
6856 err = tg3_load_firmware_cpu(tp, cpu_base,
6857 cpu_scratch_base, cpu_scratch_size,
6858 &info);
6859 if (err)
6860 return err;
6861
6862 /* Now startup the cpu. */
6863 tw32(cpu_base + CPU_STATE, 0xffffffff);
6864 tw32_f(cpu_base + CPU_PC, info.fw_base);
6865
6866 for (i = 0; i < 5; i++) {
6867 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6868 break;
6869 tw32(cpu_base + CPU_STATE, 0xffffffff);
6870 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6871 tw32_f(cpu_base + CPU_PC, info.fw_base);
6872 udelay(1000);
6873 }
6874 if (i >= 5) {
6875 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6876 "to set CPU PC, is %08x should be %08x\n",
6877 tp->dev->name, tr32(cpu_base + CPU_PC),
6878 info.fw_base);
6879 return -ENODEV;
6880 }
6881 tw32(cpu_base + CPU_STATE, 0xffffffff);
6882 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6883 return 0;
6884 }
6885
6886
6887 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6888 {
6889 struct tg3 *tp = netdev_priv(dev);
6890 struct sockaddr *addr = p;
6891 int err = 0, skip_mac_1 = 0;
6892
6893 if (!is_valid_ether_addr(addr->sa_data))
6894 return -EINVAL;
6895
6896 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6897
6898 if (!netif_running(dev))
6899 return 0;
6900
6901 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6902 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6903
6904 addr0_high = tr32(MAC_ADDR_0_HIGH);
6905 addr0_low = tr32(MAC_ADDR_0_LOW);
6906 addr1_high = tr32(MAC_ADDR_1_HIGH);
6907 addr1_low = tr32(MAC_ADDR_1_LOW);
6908
6909 /* Skip MAC addr 1 if ASF is using it. */
6910 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6911 !(addr1_high == 0 && addr1_low == 0))
6912 skip_mac_1 = 1;
6913 }
6914 spin_lock_bh(&tp->lock);
6915 __tg3_set_mac_addr(tp, skip_mac_1);
6916 spin_unlock_bh(&tp->lock);
6917
6918 return err;
6919 }
6920
6921 /* tp->lock is held. */
6922 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6923 dma_addr_t mapping, u32 maxlen_flags,
6924 u32 nic_addr)
6925 {
6926 tg3_write_mem(tp,
6927 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6928 ((u64) mapping >> 32));
6929 tg3_write_mem(tp,
6930 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6931 ((u64) mapping & 0xffffffff));
6932 tg3_write_mem(tp,
6933 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6934 maxlen_flags);
6935
6936 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6937 tg3_write_mem(tp,
6938 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6939 nic_addr);
6940 }
6941
6942 static void __tg3_set_rx_mode(struct net_device *);
6943 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6944 {
6945 int i;
6946
6947 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
6948 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6949 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6950 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6951
6952 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6953 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6954 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6955 } else {
6956 tw32(HOSTCC_TXCOL_TICKS, 0);
6957 tw32(HOSTCC_TXMAX_FRAMES, 0);
6958 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
6959
6960 tw32(HOSTCC_RXCOL_TICKS, 0);
6961 tw32(HOSTCC_RXMAX_FRAMES, 0);
6962 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
6963 }
6964
6965 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6966 u32 val = ec->stats_block_coalesce_usecs;
6967
6968 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6969 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6970
6971 if (!netif_carrier_ok(tp->dev))
6972 val = 0;
6973
6974 tw32(HOSTCC_STAT_COAL_TICKS, val);
6975 }
6976
6977 for (i = 0; i < tp->irq_cnt - 1; i++) {
6978 u32 reg;
6979
6980 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
6981 tw32(reg, ec->rx_coalesce_usecs);
6982 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
6983 tw32(reg, ec->tx_coalesce_usecs);
6984 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
6985 tw32(reg, ec->rx_max_coalesced_frames);
6986 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
6987 tw32(reg, ec->tx_max_coalesced_frames);
6988 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
6989 tw32(reg, ec->rx_max_coalesced_frames_irq);
6990 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
6991 tw32(reg, ec->tx_max_coalesced_frames_irq);
6992 }
6993
6994 for (; i < tp->irq_max - 1; i++) {
6995 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
6996 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
6997 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
6998 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
6999 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7000 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7001 }
7002 }
7003
7004 /* tp->lock is held. */
7005 static void tg3_rings_reset(struct tg3 *tp)
7006 {
7007 int i;
7008 u32 stblk, txrcb, rxrcb, limit;
7009 struct tg3_napi *tnapi = &tp->napi[0];
7010
7011 /* Disable all transmit rings but the first. */
7012 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7013 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7014 else
7015 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7016
7017 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7018 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7019 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7020 BDINFO_FLAGS_DISABLED);
7021
7022
7023 /* Disable all receive return rings but the first. */
7024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7025 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7026 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7027 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7028 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7029 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7030 else
7031 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7032
7033 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7034 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7035 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7036 BDINFO_FLAGS_DISABLED);
7037
7038 /* Disable interrupts */
7039 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7040
7041 /* Zero mailbox registers. */
7042 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7043 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7044 tp->napi[i].tx_prod = 0;
7045 tp->napi[i].tx_cons = 0;
7046 tw32_mailbox(tp->napi[i].prodmbox, 0);
7047 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7048 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7049 }
7050 } else {
7051 tp->napi[0].tx_prod = 0;
7052 tp->napi[0].tx_cons = 0;
7053 tw32_mailbox(tp->napi[0].prodmbox, 0);
7054 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7055 }
7056
7057 /* Make sure the NIC-based send BD rings are disabled. */
7058 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7059 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7060 for (i = 0; i < 16; i++)
7061 tw32_tx_mbox(mbox + i * 8, 0);
7062 }
7063
7064 txrcb = NIC_SRAM_SEND_RCB;
7065 rxrcb = NIC_SRAM_RCV_RET_RCB;
7066
7067 /* Clear status block in ram. */
7068 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7069
7070 /* Set status block DMA address */
7071 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7072 ((u64) tnapi->status_mapping >> 32));
7073 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7074 ((u64) tnapi->status_mapping & 0xffffffff));
7075
7076 if (tnapi->tx_ring) {
7077 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7078 (TG3_TX_RING_SIZE <<
7079 BDINFO_FLAGS_MAXLEN_SHIFT),
7080 NIC_SRAM_TX_BUFFER_DESC);
7081 txrcb += TG3_BDINFO_SIZE;
7082 }
7083
7084 if (tnapi->rx_rcb) {
7085 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7086 (TG3_RX_RCB_RING_SIZE(tp) <<
7087 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7088 rxrcb += TG3_BDINFO_SIZE;
7089 }
7090
7091 stblk = HOSTCC_STATBLCK_RING1;
7092
7093 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7094 u64 mapping = (u64)tnapi->status_mapping;
7095 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7096 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7097
7098 /* Clear status block in ram. */
7099 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7100
7101 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7102 (TG3_TX_RING_SIZE <<
7103 BDINFO_FLAGS_MAXLEN_SHIFT),
7104 NIC_SRAM_TX_BUFFER_DESC);
7105
7106 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7107 (TG3_RX_RCB_RING_SIZE(tp) <<
7108 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7109
7110 stblk += 8;
7111 txrcb += TG3_BDINFO_SIZE;
7112 rxrcb += TG3_BDINFO_SIZE;
7113 }
7114 }
7115
7116 /* tp->lock is held. */
7117 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7118 {
7119 u32 val, rdmac_mode;
7120 int i, err, limit;
7121 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7122
7123 tg3_disable_ints(tp);
7124
7125 tg3_stop_fw(tp);
7126
7127 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7128
7129 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7130 tg3_abort_hw(tp, 1);
7131 }
7132
7133 if (reset_phy &&
7134 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7135 tg3_phy_reset(tp);
7136
7137 err = tg3_chip_reset(tp);
7138 if (err)
7139 return err;
7140
7141 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7142
7143 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7144 val = tr32(TG3_CPMU_CTRL);
7145 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7146 tw32(TG3_CPMU_CTRL, val);
7147
7148 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7149 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7150 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7151 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7152
7153 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7154 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7155 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7156 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7157
7158 val = tr32(TG3_CPMU_HST_ACC);
7159 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7160 val |= CPMU_HST_ACC_MACCLK_6_25;
7161 tw32(TG3_CPMU_HST_ACC, val);
7162 }
7163
7164 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7165 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7166 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7167 PCIE_PWR_MGMT_L1_THRESH_4MS;
7168 tw32(PCIE_PWR_MGMT_THRESH, val);
7169
7170 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7171 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7172
7173 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7174 }
7175
7176 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
7177 val = tr32(TG3_PCIE_LNKCTL);
7178 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
7179 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7180 else
7181 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7182 tw32(TG3_PCIE_LNKCTL, val);
7183 }
7184
7185 /* This works around an issue with Athlon chipsets on
7186 * B3 tigon3 silicon. This bit has no effect on any
7187 * other revision. But do not set this on PCI Express
7188 * chips and don't even touch the clocks if the CPMU is present.
7189 */
7190 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7191 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7192 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7193 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7194 }
7195
7196 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7197 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7198 val = tr32(TG3PCI_PCISTATE);
7199 val |= PCISTATE_RETRY_SAME_DMA;
7200 tw32(TG3PCI_PCISTATE, val);
7201 }
7202
7203 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7204 /* Allow reads and writes to the
7205 * APE register and memory space.
7206 */
7207 val = tr32(TG3PCI_PCISTATE);
7208 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7209 PCISTATE_ALLOW_APE_SHMEM_WR;
7210 tw32(TG3PCI_PCISTATE, val);
7211 }
7212
7213 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7214 /* Enable some hw fixes. */
7215 val = tr32(TG3PCI_MSI_DATA);
7216 val |= (1 << 26) | (1 << 28) | (1 << 29);
7217 tw32(TG3PCI_MSI_DATA, val);
7218 }
7219
7220 /* Descriptor ring init may make accesses to the
7221 * NIC SRAM area to setup the TX descriptors, so we
7222 * can only do this after the hardware has been
7223 * successfully reset.
7224 */
7225 err = tg3_init_rings(tp);
7226 if (err)
7227 return err;
7228
7229 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7230 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7231 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
7232 /* This value is determined during the probe time DMA
7233 * engine test, tg3_test_dma.
7234 */
7235 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7236 }
7237
7238 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7239 GRC_MODE_4X_NIC_SEND_RINGS |
7240 GRC_MODE_NO_TX_PHDR_CSUM |
7241 GRC_MODE_NO_RX_PHDR_CSUM);
7242 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7243
7244 /* Pseudo-header checksum is done by hardware logic and not
7245 * the offload processers, so make the chip do the pseudo-
7246 * header checksums on receive. For transmit it is more
7247 * convenient to do the pseudo-header checksum in software
7248 * as Linux does that on transmit for us in all cases.
7249 */
7250 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7251
7252 tw32(GRC_MODE,
7253 tp->grc_mode |
7254 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7255
7256 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7257 val = tr32(GRC_MISC_CFG);
7258 val &= ~0xff;
7259 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7260 tw32(GRC_MISC_CFG, val);
7261
7262 /* Initialize MBUF/DESC pool. */
7263 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7264 /* Do nothing. */
7265 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7266 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7267 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7268 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7269 else
7270 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7271 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7272 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7273 }
7274 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7275 int fw_len;
7276
7277 fw_len = tp->fw_len;
7278 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7279 tw32(BUFMGR_MB_POOL_ADDR,
7280 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7281 tw32(BUFMGR_MB_POOL_SIZE,
7282 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7283 }
7284
7285 if (tp->dev->mtu <= ETH_DATA_LEN) {
7286 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7287 tp->bufmgr_config.mbuf_read_dma_low_water);
7288 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7289 tp->bufmgr_config.mbuf_mac_rx_low_water);
7290 tw32(BUFMGR_MB_HIGH_WATER,
7291 tp->bufmgr_config.mbuf_high_water);
7292 } else {
7293 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7294 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7295 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7296 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7297 tw32(BUFMGR_MB_HIGH_WATER,
7298 tp->bufmgr_config.mbuf_high_water_jumbo);
7299 }
7300 tw32(BUFMGR_DMA_LOW_WATER,
7301 tp->bufmgr_config.dma_low_water);
7302 tw32(BUFMGR_DMA_HIGH_WATER,
7303 tp->bufmgr_config.dma_high_water);
7304
7305 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7306 for (i = 0; i < 2000; i++) {
7307 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7308 break;
7309 udelay(10);
7310 }
7311 if (i >= 2000) {
7312 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7313 tp->dev->name);
7314 return -ENODEV;
7315 }
7316
7317 /* Setup replenish threshold. */
7318 val = tp->rx_pending / 8;
7319 if (val == 0)
7320 val = 1;
7321 else if (val > tp->rx_std_max_post)
7322 val = tp->rx_std_max_post;
7323 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7324 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7325 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7326
7327 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7328 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7329 }
7330
7331 tw32(RCVBDI_STD_THRESH, val);
7332
7333 /* Initialize TG3_BDINFO's at:
7334 * RCVDBDI_STD_BD: standard eth size rx ring
7335 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7336 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7337 *
7338 * like so:
7339 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7340 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7341 * ring attribute flags
7342 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7343 *
7344 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7345 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7346 *
7347 * The size of each ring is fixed in the firmware, but the location is
7348 * configurable.
7349 */
7350 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7351 ((u64) tpr->rx_std_mapping >> 32));
7352 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7353 ((u64) tpr->rx_std_mapping & 0xffffffff));
7354 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7355 NIC_SRAM_RX_BUFFER_DESC);
7356
7357 /* Disable the mini ring */
7358 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7359 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7360 BDINFO_FLAGS_DISABLED);
7361
7362 /* Program the jumbo buffer descriptor ring control
7363 * blocks on those devices that have them.
7364 */
7365 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7366 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7367 /* Setup replenish threshold. */
7368 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7369
7370 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7371 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7372 ((u64) tpr->rx_jmb_mapping >> 32));
7373 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7374 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7375 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7376 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7377 BDINFO_FLAGS_USE_EXT_RECV);
7378 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7379 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7380 } else {
7381 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7382 BDINFO_FLAGS_DISABLED);
7383 }
7384
7385 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7386 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7387 (RX_STD_MAX_SIZE << 2);
7388 else
7389 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7390 } else
7391 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7392
7393 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7394
7395 tpr->rx_std_ptr = tp->rx_pending;
7396 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7397 tpr->rx_std_ptr);
7398
7399 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7400 tp->rx_jumbo_pending : 0;
7401 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7402 tpr->rx_jmb_ptr);
7403
7404 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7405 tw32(STD_REPLENISH_LWM, 32);
7406 tw32(JMB_REPLENISH_LWM, 16);
7407 }
7408
7409 tg3_rings_reset(tp);
7410
7411 /* Initialize MAC address and backoff seed. */
7412 __tg3_set_mac_addr(tp, 0);
7413
7414 /* MTU + ethernet header + FCS + optional VLAN tag */
7415 tw32(MAC_RX_MTU_SIZE,
7416 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7417
7418 /* The slot time is changed by tg3_setup_phy if we
7419 * run at gigabit with half duplex.
7420 */
7421 tw32(MAC_TX_LENGTHS,
7422 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7423 (6 << TX_LENGTHS_IPG_SHIFT) |
7424 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7425
7426 /* Receive rules. */
7427 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7428 tw32(RCVLPC_CONFIG, 0x0181);
7429
7430 /* Calculate RDMAC_MODE setting early, we need it to determine
7431 * the RCVLPC_STATE_ENABLE mask.
7432 */
7433 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7434 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7435 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7436 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7437 RDMAC_MODE_LNGREAD_ENAB);
7438
7439 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7440 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7441 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7442 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7443 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7444 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7445
7446 /* If statement applies to 5705 and 5750 PCI devices only */
7447 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7448 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7449 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7450 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7451 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7452 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7453 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7454 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7455 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7456 }
7457 }
7458
7459 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7460 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7461
7462 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7463 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7464
7465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7466 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7467 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7468
7469 /* Receive/send statistics. */
7470 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7471 val = tr32(RCVLPC_STATS_ENABLE);
7472 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7473 tw32(RCVLPC_STATS_ENABLE, val);
7474 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7475 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7476 val = tr32(RCVLPC_STATS_ENABLE);
7477 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7478 tw32(RCVLPC_STATS_ENABLE, val);
7479 } else {
7480 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7481 }
7482 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7483 tw32(SNDDATAI_STATSENAB, 0xffffff);
7484 tw32(SNDDATAI_STATSCTRL,
7485 (SNDDATAI_SCTRL_ENABLE |
7486 SNDDATAI_SCTRL_FASTUPD));
7487
7488 /* Setup host coalescing engine. */
7489 tw32(HOSTCC_MODE, 0);
7490 for (i = 0; i < 2000; i++) {
7491 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7492 break;
7493 udelay(10);
7494 }
7495
7496 __tg3_set_coalesce(tp, &tp->coal);
7497
7498 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7499 /* Status/statistics block address. See tg3_timer,
7500 * the tg3_periodic_fetch_stats call there, and
7501 * tg3_get_stats to see how this works for 5705/5750 chips.
7502 */
7503 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7504 ((u64) tp->stats_mapping >> 32));
7505 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7506 ((u64) tp->stats_mapping & 0xffffffff));
7507 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7508
7509 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7510
7511 /* Clear statistics and status block memory areas */
7512 for (i = NIC_SRAM_STATS_BLK;
7513 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7514 i += sizeof(u32)) {
7515 tg3_write_mem(tp, i, 0);
7516 udelay(40);
7517 }
7518 }
7519
7520 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7521
7522 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7523 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7524 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7525 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7526
7527 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7528 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7529 /* reset to prevent losing 1st rx packet intermittently */
7530 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7531 udelay(10);
7532 }
7533
7534 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7535 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7536 else
7537 tp->mac_mode = 0;
7538 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7539 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7540 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7541 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7542 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7543 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7544 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7545 udelay(40);
7546
7547 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7548 * If TG3_FLG2_IS_NIC is zero, we should read the
7549 * register to preserve the GPIO settings for LOMs. The GPIOs,
7550 * whether used as inputs or outputs, are set by boot code after
7551 * reset.
7552 */
7553 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7554 u32 gpio_mask;
7555
7556 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7557 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7558 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7559
7560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7561 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7562 GRC_LCLCTRL_GPIO_OUTPUT3;
7563
7564 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7565 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7566
7567 tp->grc_local_ctrl &= ~gpio_mask;
7568 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7569
7570 /* GPIO1 must be driven high for eeprom write protect */
7571 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7572 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7573 GRC_LCLCTRL_GPIO_OUTPUT1);
7574 }
7575 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7576 udelay(100);
7577
7578 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7579 val = tr32(MSGINT_MODE);
7580 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7581 tw32(MSGINT_MODE, val);
7582 }
7583
7584 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7585 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7586 udelay(40);
7587 }
7588
7589 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7590 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7591 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7592 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7593 WDMAC_MODE_LNGREAD_ENAB);
7594
7595 /* If statement applies to 5705 and 5750 PCI devices only */
7596 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7597 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7598 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7599 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
7600 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7601 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7602 /* nothing */
7603 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7604 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7605 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7606 val |= WDMAC_MODE_RX_ACCEL;
7607 }
7608 }
7609
7610 /* Enable host coalescing bug fix */
7611 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7612 val |= WDMAC_MODE_STATUS_TAG_FIX;
7613
7614 tw32_f(WDMAC_MODE, val);
7615 udelay(40);
7616
7617 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7618 u16 pcix_cmd;
7619
7620 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7621 &pcix_cmd);
7622 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7623 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7624 pcix_cmd |= PCI_X_CMD_READ_2K;
7625 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7626 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7627 pcix_cmd |= PCI_X_CMD_READ_2K;
7628 }
7629 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7630 pcix_cmd);
7631 }
7632
7633 tw32_f(RDMAC_MODE, rdmac_mode);
7634 udelay(40);
7635
7636 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7637 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7638 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7639
7640 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7641 tw32(SNDDATAC_MODE,
7642 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7643 else
7644 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7645
7646 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7647 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7648 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7649 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7650 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7651 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7652 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
7653 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
7654 val |= SNDBDI_MODE_MULTI_TXQ_EN;
7655 tw32(SNDBDI_MODE, val);
7656 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7657
7658 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7659 err = tg3_load_5701_a0_firmware_fix(tp);
7660 if (err)
7661 return err;
7662 }
7663
7664 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7665 err = tg3_load_tso_firmware(tp);
7666 if (err)
7667 return err;
7668 }
7669
7670 tp->tx_mode = TX_MODE_ENABLE;
7671 tw32_f(MAC_TX_MODE, tp->tx_mode);
7672 udelay(100);
7673
7674 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
7675 u32 reg = MAC_RSS_INDIR_TBL_0;
7676 u8 *ent = (u8 *)&val;
7677
7678 /* Setup the indirection table */
7679 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
7680 int idx = i % sizeof(val);
7681
7682 ent[idx] = i % (tp->irq_cnt - 1);
7683 if (idx == sizeof(val) - 1) {
7684 tw32(reg, val);
7685 reg += 4;
7686 }
7687 }
7688
7689 /* Setup the "secret" hash key. */
7690 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
7691 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
7692 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
7693 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
7694 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
7695 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
7696 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
7697 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
7698 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
7699 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
7700 }
7701
7702 tp->rx_mode = RX_MODE_ENABLE;
7703 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7704 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7705
7706 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
7707 tp->rx_mode |= RX_MODE_RSS_ENABLE |
7708 RX_MODE_RSS_ITBL_HASH_BITS_7 |
7709 RX_MODE_RSS_IPV6_HASH_EN |
7710 RX_MODE_RSS_TCP_IPV6_HASH_EN |
7711 RX_MODE_RSS_IPV4_HASH_EN |
7712 RX_MODE_RSS_TCP_IPV4_HASH_EN;
7713
7714 tw32_f(MAC_RX_MODE, tp->rx_mode);
7715 udelay(10);
7716
7717 tw32(MAC_LED_CTRL, tp->led_ctrl);
7718
7719 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7720 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7721 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7722 udelay(10);
7723 }
7724 tw32_f(MAC_RX_MODE, tp->rx_mode);
7725 udelay(10);
7726
7727 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7728 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7729 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7730 /* Set drive transmission level to 1.2V */
7731 /* only if the signal pre-emphasis bit is not set */
7732 val = tr32(MAC_SERDES_CFG);
7733 val &= 0xfffff000;
7734 val |= 0x880;
7735 tw32(MAC_SERDES_CFG, val);
7736 }
7737 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7738 tw32(MAC_SERDES_CFG, 0x616000);
7739 }
7740
7741 /* Prevent chip from dropping frames when flow control
7742 * is enabled.
7743 */
7744 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7745
7746 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7747 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7748 /* Use hardware link auto-negotiation */
7749 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7750 }
7751
7752 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7753 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7754 u32 tmp;
7755
7756 tmp = tr32(SERDES_RX_CTRL);
7757 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7758 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7759 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7760 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7761 }
7762
7763 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7764 if (tp->link_config.phy_is_low_power) {
7765 tp->link_config.phy_is_low_power = 0;
7766 tp->link_config.speed = tp->link_config.orig_speed;
7767 tp->link_config.duplex = tp->link_config.orig_duplex;
7768 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7769 }
7770
7771 err = tg3_setup_phy(tp, 0);
7772 if (err)
7773 return err;
7774
7775 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7776 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
7777 u32 tmp;
7778
7779 /* Clear CRC stats. */
7780 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7781 tg3_writephy(tp, MII_TG3_TEST1,
7782 tmp | MII_TG3_TEST1_CRC_EN);
7783 tg3_readphy(tp, 0x14, &tmp);
7784 }
7785 }
7786 }
7787
7788 __tg3_set_rx_mode(tp->dev);
7789
7790 /* Initialize receive rules. */
7791 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7792 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7793 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7794 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7795
7796 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7797 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7798 limit = 8;
7799 else
7800 limit = 16;
7801 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7802 limit -= 4;
7803 switch (limit) {
7804 case 16:
7805 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7806 case 15:
7807 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7808 case 14:
7809 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7810 case 13:
7811 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7812 case 12:
7813 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7814 case 11:
7815 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7816 case 10:
7817 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7818 case 9:
7819 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7820 case 8:
7821 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7822 case 7:
7823 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7824 case 6:
7825 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7826 case 5:
7827 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7828 case 4:
7829 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7830 case 3:
7831 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7832 case 2:
7833 case 1:
7834
7835 default:
7836 break;
7837 }
7838
7839 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7840 /* Write our heartbeat update interval to APE. */
7841 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7842 APE_HOST_HEARTBEAT_INT_DISABLE);
7843
7844 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7845
7846 return 0;
7847 }
7848
7849 /* Called at device open time to get the chip ready for
7850 * packet processing. Invoked with tp->lock held.
7851 */
7852 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7853 {
7854 tg3_switch_clocks(tp);
7855
7856 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7857
7858 return tg3_reset_hw(tp, reset_phy);
7859 }
7860
7861 #define TG3_STAT_ADD32(PSTAT, REG) \
7862 do { u32 __val = tr32(REG); \
7863 (PSTAT)->low += __val; \
7864 if ((PSTAT)->low < __val) \
7865 (PSTAT)->high += 1; \
7866 } while (0)
7867
7868 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7869 {
7870 struct tg3_hw_stats *sp = tp->hw_stats;
7871
7872 if (!netif_carrier_ok(tp->dev))
7873 return;
7874
7875 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7876 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7877 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7878 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7879 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7880 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7881 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7882 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7883 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7884 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7885 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7886 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7887 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7888
7889 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7890 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7891 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7892 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7893 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7894 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7895 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7896 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7897 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7898 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7899 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7900 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7901 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7902 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7903
7904 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7905 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7906 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7907 }
7908
7909 static void tg3_timer(unsigned long __opaque)
7910 {
7911 struct tg3 *tp = (struct tg3 *) __opaque;
7912
7913 if (tp->irq_sync)
7914 goto restart_timer;
7915
7916 spin_lock(&tp->lock);
7917
7918 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7919 /* All of this garbage is because when using non-tagged
7920 * IRQ status the mailbox/status_block protocol the chip
7921 * uses with the cpu is race prone.
7922 */
7923 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7924 tw32(GRC_LOCAL_CTRL,
7925 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7926 } else {
7927 tw32(HOSTCC_MODE, tp->coalesce_mode |
7928 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
7929 }
7930
7931 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7932 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7933 spin_unlock(&tp->lock);
7934 schedule_work(&tp->reset_task);
7935 return;
7936 }
7937 }
7938
7939 /* This part only runs once per second. */
7940 if (!--tp->timer_counter) {
7941 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7942 tg3_periodic_fetch_stats(tp);
7943
7944 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7945 u32 mac_stat;
7946 int phy_event;
7947
7948 mac_stat = tr32(MAC_STATUS);
7949
7950 phy_event = 0;
7951 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7952 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7953 phy_event = 1;
7954 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7955 phy_event = 1;
7956
7957 if (phy_event)
7958 tg3_setup_phy(tp, 0);
7959 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7960 u32 mac_stat = tr32(MAC_STATUS);
7961 int need_setup = 0;
7962
7963 if (netif_carrier_ok(tp->dev) &&
7964 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7965 need_setup = 1;
7966 }
7967 if (! netif_carrier_ok(tp->dev) &&
7968 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7969 MAC_STATUS_SIGNAL_DET))) {
7970 need_setup = 1;
7971 }
7972 if (need_setup) {
7973 if (!tp->serdes_counter) {
7974 tw32_f(MAC_MODE,
7975 (tp->mac_mode &
7976 ~MAC_MODE_PORT_MODE_MASK));
7977 udelay(40);
7978 tw32_f(MAC_MODE, tp->mac_mode);
7979 udelay(40);
7980 }
7981 tg3_setup_phy(tp, 0);
7982 }
7983 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7984 tg3_serdes_parallel_detect(tp);
7985
7986 tp->timer_counter = tp->timer_multiplier;
7987 }
7988
7989 /* Heartbeat is only sent once every 2 seconds.
7990 *
7991 * The heartbeat is to tell the ASF firmware that the host
7992 * driver is still alive. In the event that the OS crashes,
7993 * ASF needs to reset the hardware to free up the FIFO space
7994 * that may be filled with rx packets destined for the host.
7995 * If the FIFO is full, ASF will no longer function properly.
7996 *
7997 * Unintended resets have been reported on real time kernels
7998 * where the timer doesn't run on time. Netpoll will also have
7999 * same problem.
8000 *
8001 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8002 * to check the ring condition when the heartbeat is expiring
8003 * before doing the reset. This will prevent most unintended
8004 * resets.
8005 */
8006 if (!--tp->asf_counter) {
8007 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8008 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8009 tg3_wait_for_event_ack(tp);
8010
8011 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8012 FWCMD_NICDRV_ALIVE3);
8013 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8014 /* 5 seconds timeout */
8015 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8016
8017 tg3_generate_fw_event(tp);
8018 }
8019 tp->asf_counter = tp->asf_multiplier;
8020 }
8021
8022 spin_unlock(&tp->lock);
8023
8024 restart_timer:
8025 tp->timer.expires = jiffies + tp->timer_offset;
8026 add_timer(&tp->timer);
8027 }
8028
8029 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8030 {
8031 irq_handler_t fn;
8032 unsigned long flags;
8033 char *name;
8034 struct tg3_napi *tnapi = &tp->napi[irq_num];
8035
8036 if (tp->irq_cnt == 1)
8037 name = tp->dev->name;
8038 else {
8039 name = &tnapi->irq_lbl[0];
8040 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8041 name[IFNAMSIZ-1] = 0;
8042 }
8043
8044 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8045 fn = tg3_msi;
8046 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8047 fn = tg3_msi_1shot;
8048 flags = IRQF_SAMPLE_RANDOM;
8049 } else {
8050 fn = tg3_interrupt;
8051 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8052 fn = tg3_interrupt_tagged;
8053 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8054 }
8055
8056 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8057 }
8058
8059 static int tg3_test_interrupt(struct tg3 *tp)
8060 {
8061 struct tg3_napi *tnapi = &tp->napi[0];
8062 struct net_device *dev = tp->dev;
8063 int err, i, intr_ok = 0;
8064 u32 val;
8065
8066 if (!netif_running(dev))
8067 return -ENODEV;
8068
8069 tg3_disable_ints(tp);
8070
8071 free_irq(tnapi->irq_vec, tnapi);
8072
8073 /*
8074 * Turn off MSI one shot mode. Otherwise this test has no
8075 * observable way to know whether the interrupt was delivered.
8076 */
8077 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8078 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8079 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8080 tw32(MSGINT_MODE, val);
8081 }
8082
8083 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8084 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8085 if (err)
8086 return err;
8087
8088 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8089 tg3_enable_ints(tp);
8090
8091 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8092 tnapi->coal_now);
8093
8094 for (i = 0; i < 5; i++) {
8095 u32 int_mbox, misc_host_ctrl;
8096
8097 int_mbox = tr32_mailbox(tnapi->int_mbox);
8098 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8099
8100 if ((int_mbox != 0) ||
8101 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8102 intr_ok = 1;
8103 break;
8104 }
8105
8106 msleep(10);
8107 }
8108
8109 tg3_disable_ints(tp);
8110
8111 free_irq(tnapi->irq_vec, tnapi);
8112
8113 err = tg3_request_irq(tp, 0);
8114
8115 if (err)
8116 return err;
8117
8118 if (intr_ok) {
8119 /* Reenable MSI one shot mode. */
8120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
8121 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8122 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8123 tw32(MSGINT_MODE, val);
8124 }
8125 return 0;
8126 }
8127
8128 return -EIO;
8129 }
8130
8131 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8132 * successfully restored
8133 */
8134 static int tg3_test_msi(struct tg3 *tp)
8135 {
8136 int err;
8137 u16 pci_cmd;
8138
8139 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8140 return 0;
8141
8142 /* Turn off SERR reporting in case MSI terminates with Master
8143 * Abort.
8144 */
8145 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8146 pci_write_config_word(tp->pdev, PCI_COMMAND,
8147 pci_cmd & ~PCI_COMMAND_SERR);
8148
8149 err = tg3_test_interrupt(tp);
8150
8151 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8152
8153 if (!err)
8154 return 0;
8155
8156 /* other failures */
8157 if (err != -EIO)
8158 return err;
8159
8160 /* MSI test failed, go back to INTx mode */
8161 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8162 "switching to INTx mode. Please report this failure to "
8163 "the PCI maintainer and include system chipset information.\n",
8164 tp->dev->name);
8165
8166 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8167
8168 pci_disable_msi(tp->pdev);
8169
8170 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8171
8172 err = tg3_request_irq(tp, 0);
8173 if (err)
8174 return err;
8175
8176 /* Need to reset the chip because the MSI cycle may have terminated
8177 * with Master Abort.
8178 */
8179 tg3_full_lock(tp, 1);
8180
8181 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8182 err = tg3_init_hw(tp, 1);
8183
8184 tg3_full_unlock(tp);
8185
8186 if (err)
8187 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8188
8189 return err;
8190 }
8191
8192 static int tg3_request_firmware(struct tg3 *tp)
8193 {
8194 const __be32 *fw_data;
8195
8196 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8197 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8198 tp->dev->name, tp->fw_needed);
8199 return -ENOENT;
8200 }
8201
8202 fw_data = (void *)tp->fw->data;
8203
8204 /* Firmware blob starts with version numbers, followed by
8205 * start address and _full_ length including BSS sections
8206 * (which must be longer than the actual data, of course
8207 */
8208
8209 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8210 if (tp->fw_len < (tp->fw->size - 12)) {
8211 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8212 tp->dev->name, tp->fw_len, tp->fw_needed);
8213 release_firmware(tp->fw);
8214 tp->fw = NULL;
8215 return -EINVAL;
8216 }
8217
8218 /* We no longer need firmware; we have it. */
8219 tp->fw_needed = NULL;
8220 return 0;
8221 }
8222
8223 static bool tg3_enable_msix(struct tg3 *tp)
8224 {
8225 int i, rc, cpus = num_online_cpus();
8226 struct msix_entry msix_ent[tp->irq_max];
8227
8228 if (cpus == 1)
8229 /* Just fallback to the simpler MSI mode. */
8230 return false;
8231
8232 /*
8233 * We want as many rx rings enabled as there are cpus.
8234 * The first MSIX vector only deals with link interrupts, etc,
8235 * so we add one to the number of vectors we are requesting.
8236 */
8237 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8238
8239 for (i = 0; i < tp->irq_max; i++) {
8240 msix_ent[i].entry = i;
8241 msix_ent[i].vector = 0;
8242 }
8243
8244 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8245 if (rc != 0) {
8246 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8247 return false;
8248 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8249 return false;
8250 printk(KERN_NOTICE
8251 "%s: Requested %d MSI-X vectors, received %d\n",
8252 tp->dev->name, tp->irq_cnt, rc);
8253 tp->irq_cnt = rc;
8254 }
8255
8256 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8257
8258 for (i = 0; i < tp->irq_max; i++)
8259 tp->napi[i].irq_vec = msix_ent[i].vector;
8260
8261 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8262
8263 return true;
8264 }
8265
8266 static void tg3_ints_init(struct tg3 *tp)
8267 {
8268 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8269 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8270 /* All MSI supporting chips should support tagged
8271 * status. Assert that this is the case.
8272 */
8273 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8274 "Not using MSI.\n", tp->dev->name);
8275 goto defcfg;
8276 }
8277
8278 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8279 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8280 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8281 pci_enable_msi(tp->pdev) == 0)
8282 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8283
8284 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8285 u32 msi_mode = tr32(MSGINT_MODE);
8286 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8287 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8288 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8289 }
8290 defcfg:
8291 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8292 tp->irq_cnt = 1;
8293 tp->napi[0].irq_vec = tp->pdev->irq;
8294 tp->dev->real_num_tx_queues = 1;
8295 }
8296 }
8297
8298 static void tg3_ints_fini(struct tg3 *tp)
8299 {
8300 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8301 pci_disable_msix(tp->pdev);
8302 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8303 pci_disable_msi(tp->pdev);
8304 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8305 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8306 }
8307
8308 static int tg3_open(struct net_device *dev)
8309 {
8310 struct tg3 *tp = netdev_priv(dev);
8311 int i, err;
8312
8313 if (tp->fw_needed) {
8314 err = tg3_request_firmware(tp);
8315 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8316 if (err)
8317 return err;
8318 } else if (err) {
8319 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8320 tp->dev->name);
8321 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8322 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8323 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8324 tp->dev->name);
8325 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8326 }
8327 }
8328
8329 netif_carrier_off(tp->dev);
8330
8331 err = tg3_set_power_state(tp, PCI_D0);
8332 if (err)
8333 return err;
8334
8335 tg3_full_lock(tp, 0);
8336
8337 tg3_disable_ints(tp);
8338 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8339
8340 tg3_full_unlock(tp);
8341
8342 /*
8343 * Setup interrupts first so we know how
8344 * many NAPI resources to allocate
8345 */
8346 tg3_ints_init(tp);
8347
8348 /* The placement of this call is tied
8349 * to the setup and use of Host TX descriptors.
8350 */
8351 err = tg3_alloc_consistent(tp);
8352 if (err)
8353 goto err_out1;
8354
8355 tg3_napi_enable(tp);
8356
8357 for (i = 0; i < tp->irq_cnt; i++) {
8358 struct tg3_napi *tnapi = &tp->napi[i];
8359 err = tg3_request_irq(tp, i);
8360 if (err) {
8361 for (i--; i >= 0; i--)
8362 free_irq(tnapi->irq_vec, tnapi);
8363 break;
8364 }
8365 }
8366
8367 if (err)
8368 goto err_out2;
8369
8370 tg3_full_lock(tp, 0);
8371
8372 err = tg3_init_hw(tp, 1);
8373 if (err) {
8374 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8375 tg3_free_rings(tp);
8376 } else {
8377 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8378 tp->timer_offset = HZ;
8379 else
8380 tp->timer_offset = HZ / 10;
8381
8382 BUG_ON(tp->timer_offset > HZ);
8383 tp->timer_counter = tp->timer_multiplier =
8384 (HZ / tp->timer_offset);
8385 tp->asf_counter = tp->asf_multiplier =
8386 ((HZ / tp->timer_offset) * 2);
8387
8388 init_timer(&tp->timer);
8389 tp->timer.expires = jiffies + tp->timer_offset;
8390 tp->timer.data = (unsigned long) tp;
8391 tp->timer.function = tg3_timer;
8392 }
8393
8394 tg3_full_unlock(tp);
8395
8396 if (err)
8397 goto err_out3;
8398
8399 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8400 err = tg3_test_msi(tp);
8401
8402 if (err) {
8403 tg3_full_lock(tp, 0);
8404 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8405 tg3_free_rings(tp);
8406 tg3_full_unlock(tp);
8407
8408 goto err_out2;
8409 }
8410
8411 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8412 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8413 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8414 u32 val = tr32(PCIE_TRANSACTION_CFG);
8415
8416 tw32(PCIE_TRANSACTION_CFG,
8417 val | PCIE_TRANS_CFG_1SHOT_MSI);
8418 }
8419 }
8420
8421 tg3_phy_start(tp);
8422
8423 tg3_full_lock(tp, 0);
8424
8425 add_timer(&tp->timer);
8426 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8427 tg3_enable_ints(tp);
8428
8429 tg3_full_unlock(tp);
8430
8431 netif_tx_start_all_queues(dev);
8432
8433 return 0;
8434
8435 err_out3:
8436 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8437 struct tg3_napi *tnapi = &tp->napi[i];
8438 free_irq(tnapi->irq_vec, tnapi);
8439 }
8440
8441 err_out2:
8442 tg3_napi_disable(tp);
8443 tg3_free_consistent(tp);
8444
8445 err_out1:
8446 tg3_ints_fini(tp);
8447 return err;
8448 }
8449
8450 #if 0
8451 /*static*/ void tg3_dump_state(struct tg3 *tp)
8452 {
8453 u32 val32, val32_2, val32_3, val32_4, val32_5;
8454 u16 val16;
8455 int i;
8456 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8457
8458 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8459 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8460 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8461 val16, val32);
8462
8463 /* MAC block */
8464 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8465 tr32(MAC_MODE), tr32(MAC_STATUS));
8466 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8467 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8468 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8469 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8470 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8471 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8472
8473 /* Send data initiator control block */
8474 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8475 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8476 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8477 tr32(SNDDATAI_STATSCTRL));
8478
8479 /* Send data completion control block */
8480 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8481
8482 /* Send BD ring selector block */
8483 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8484 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8485
8486 /* Send BD initiator control block */
8487 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8488 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8489
8490 /* Send BD completion control block */
8491 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8492
8493 /* Receive list placement control block */
8494 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8495 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8496 printk(" RCVLPC_STATSCTRL[%08x]\n",
8497 tr32(RCVLPC_STATSCTRL));
8498
8499 /* Receive data and receive BD initiator control block */
8500 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8501 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8502
8503 /* Receive data completion control block */
8504 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8505 tr32(RCVDCC_MODE));
8506
8507 /* Receive BD initiator control block */
8508 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8509 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8510
8511 /* Receive BD completion control block */
8512 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8513 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8514
8515 /* Receive list selector control block */
8516 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8517 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8518
8519 /* Mbuf cluster free block */
8520 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8521 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8522
8523 /* Host coalescing control block */
8524 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8525 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8526 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8527 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8528 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8529 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8530 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8531 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8532 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8533 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8534 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8535 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8536
8537 /* Memory arbiter control block */
8538 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8539 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8540
8541 /* Buffer manager control block */
8542 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8543 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8544 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8545 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8546 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8547 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8548 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8549 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8550
8551 /* Read DMA control block */
8552 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8553 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8554
8555 /* Write DMA control block */
8556 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8557 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8558
8559 /* DMA completion block */
8560 printk("DEBUG: DMAC_MODE[%08x]\n",
8561 tr32(DMAC_MODE));
8562
8563 /* GRC block */
8564 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8565 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8566 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8567 tr32(GRC_LOCAL_CTRL));
8568
8569 /* TG3_BDINFOs */
8570 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8571 tr32(RCVDBDI_JUMBO_BD + 0x0),
8572 tr32(RCVDBDI_JUMBO_BD + 0x4),
8573 tr32(RCVDBDI_JUMBO_BD + 0x8),
8574 tr32(RCVDBDI_JUMBO_BD + 0xc));
8575 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8576 tr32(RCVDBDI_STD_BD + 0x0),
8577 tr32(RCVDBDI_STD_BD + 0x4),
8578 tr32(RCVDBDI_STD_BD + 0x8),
8579 tr32(RCVDBDI_STD_BD + 0xc));
8580 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8581 tr32(RCVDBDI_MINI_BD + 0x0),
8582 tr32(RCVDBDI_MINI_BD + 0x4),
8583 tr32(RCVDBDI_MINI_BD + 0x8),
8584 tr32(RCVDBDI_MINI_BD + 0xc));
8585
8586 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8587 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8588 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8589 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8590 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8591 val32, val32_2, val32_3, val32_4);
8592
8593 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8594 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8595 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8596 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8597 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8598 val32, val32_2, val32_3, val32_4);
8599
8600 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8601 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8602 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8603 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8604 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8605 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8606 val32, val32_2, val32_3, val32_4, val32_5);
8607
8608 /* SW status block */
8609 printk(KERN_DEBUG
8610 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8611 sblk->status,
8612 sblk->status_tag,
8613 sblk->rx_jumbo_consumer,
8614 sblk->rx_consumer,
8615 sblk->rx_mini_consumer,
8616 sblk->idx[0].rx_producer,
8617 sblk->idx[0].tx_consumer);
8618
8619 /* SW statistics block */
8620 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8621 ((u32 *)tp->hw_stats)[0],
8622 ((u32 *)tp->hw_stats)[1],
8623 ((u32 *)tp->hw_stats)[2],
8624 ((u32 *)tp->hw_stats)[3]);
8625
8626 /* Mailboxes */
8627 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8628 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8629 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8630 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8631 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8632
8633 /* NIC side send descriptors. */
8634 for (i = 0; i < 6; i++) {
8635 unsigned long txd;
8636
8637 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8638 + (i * sizeof(struct tg3_tx_buffer_desc));
8639 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8640 i,
8641 readl(txd + 0x0), readl(txd + 0x4),
8642 readl(txd + 0x8), readl(txd + 0xc));
8643 }
8644
8645 /* NIC side RX descriptors. */
8646 for (i = 0; i < 6; i++) {
8647 unsigned long rxd;
8648
8649 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8650 + (i * sizeof(struct tg3_rx_buffer_desc));
8651 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8652 i,
8653 readl(rxd + 0x0), readl(rxd + 0x4),
8654 readl(rxd + 0x8), readl(rxd + 0xc));
8655 rxd += (4 * sizeof(u32));
8656 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8657 i,
8658 readl(rxd + 0x0), readl(rxd + 0x4),
8659 readl(rxd + 0x8), readl(rxd + 0xc));
8660 }
8661
8662 for (i = 0; i < 6; i++) {
8663 unsigned long rxd;
8664
8665 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8666 + (i * sizeof(struct tg3_rx_buffer_desc));
8667 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8668 i,
8669 readl(rxd + 0x0), readl(rxd + 0x4),
8670 readl(rxd + 0x8), readl(rxd + 0xc));
8671 rxd += (4 * sizeof(u32));
8672 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8673 i,
8674 readl(rxd + 0x0), readl(rxd + 0x4),
8675 readl(rxd + 0x8), readl(rxd + 0xc));
8676 }
8677 }
8678 #endif
8679
8680 static struct net_device_stats *tg3_get_stats(struct net_device *);
8681 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8682
8683 static int tg3_close(struct net_device *dev)
8684 {
8685 int i;
8686 struct tg3 *tp = netdev_priv(dev);
8687
8688 tg3_napi_disable(tp);
8689 cancel_work_sync(&tp->reset_task);
8690
8691 netif_tx_stop_all_queues(dev);
8692
8693 del_timer_sync(&tp->timer);
8694
8695 tg3_phy_stop(tp);
8696
8697 tg3_full_lock(tp, 1);
8698 #if 0
8699 tg3_dump_state(tp);
8700 #endif
8701
8702 tg3_disable_ints(tp);
8703
8704 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8705 tg3_free_rings(tp);
8706 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8707
8708 tg3_full_unlock(tp);
8709
8710 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8711 struct tg3_napi *tnapi = &tp->napi[i];
8712 free_irq(tnapi->irq_vec, tnapi);
8713 }
8714
8715 tg3_ints_fini(tp);
8716
8717 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8718 sizeof(tp->net_stats_prev));
8719 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8720 sizeof(tp->estats_prev));
8721
8722 tg3_free_consistent(tp);
8723
8724 tg3_set_power_state(tp, PCI_D3hot);
8725
8726 netif_carrier_off(tp->dev);
8727
8728 return 0;
8729 }
8730
8731 static inline unsigned long get_stat64(tg3_stat64_t *val)
8732 {
8733 unsigned long ret;
8734
8735 #if (BITS_PER_LONG == 32)
8736 ret = val->low;
8737 #else
8738 ret = ((u64)val->high << 32) | ((u64)val->low);
8739 #endif
8740 return ret;
8741 }
8742
8743 static inline u64 get_estat64(tg3_stat64_t *val)
8744 {
8745 return ((u64)val->high << 32) | ((u64)val->low);
8746 }
8747
8748 static unsigned long calc_crc_errors(struct tg3 *tp)
8749 {
8750 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8751
8752 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8753 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8754 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8755 u32 val;
8756
8757 spin_lock_bh(&tp->lock);
8758 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8759 tg3_writephy(tp, MII_TG3_TEST1,
8760 val | MII_TG3_TEST1_CRC_EN);
8761 tg3_readphy(tp, 0x14, &val);
8762 } else
8763 val = 0;
8764 spin_unlock_bh(&tp->lock);
8765
8766 tp->phy_crc_errors += val;
8767
8768 return tp->phy_crc_errors;
8769 }
8770
8771 return get_stat64(&hw_stats->rx_fcs_errors);
8772 }
8773
8774 #define ESTAT_ADD(member) \
8775 estats->member = old_estats->member + \
8776 get_estat64(&hw_stats->member)
8777
8778 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8779 {
8780 struct tg3_ethtool_stats *estats = &tp->estats;
8781 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8782 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8783
8784 if (!hw_stats)
8785 return old_estats;
8786
8787 ESTAT_ADD(rx_octets);
8788 ESTAT_ADD(rx_fragments);
8789 ESTAT_ADD(rx_ucast_packets);
8790 ESTAT_ADD(rx_mcast_packets);
8791 ESTAT_ADD(rx_bcast_packets);
8792 ESTAT_ADD(rx_fcs_errors);
8793 ESTAT_ADD(rx_align_errors);
8794 ESTAT_ADD(rx_xon_pause_rcvd);
8795 ESTAT_ADD(rx_xoff_pause_rcvd);
8796 ESTAT_ADD(rx_mac_ctrl_rcvd);
8797 ESTAT_ADD(rx_xoff_entered);
8798 ESTAT_ADD(rx_frame_too_long_errors);
8799 ESTAT_ADD(rx_jabbers);
8800 ESTAT_ADD(rx_undersize_packets);
8801 ESTAT_ADD(rx_in_length_errors);
8802 ESTAT_ADD(rx_out_length_errors);
8803 ESTAT_ADD(rx_64_or_less_octet_packets);
8804 ESTAT_ADD(rx_65_to_127_octet_packets);
8805 ESTAT_ADD(rx_128_to_255_octet_packets);
8806 ESTAT_ADD(rx_256_to_511_octet_packets);
8807 ESTAT_ADD(rx_512_to_1023_octet_packets);
8808 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8809 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8810 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8811 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8812 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8813
8814 ESTAT_ADD(tx_octets);
8815 ESTAT_ADD(tx_collisions);
8816 ESTAT_ADD(tx_xon_sent);
8817 ESTAT_ADD(tx_xoff_sent);
8818 ESTAT_ADD(tx_flow_control);
8819 ESTAT_ADD(tx_mac_errors);
8820 ESTAT_ADD(tx_single_collisions);
8821 ESTAT_ADD(tx_mult_collisions);
8822 ESTAT_ADD(tx_deferred);
8823 ESTAT_ADD(tx_excessive_collisions);
8824 ESTAT_ADD(tx_late_collisions);
8825 ESTAT_ADD(tx_collide_2times);
8826 ESTAT_ADD(tx_collide_3times);
8827 ESTAT_ADD(tx_collide_4times);
8828 ESTAT_ADD(tx_collide_5times);
8829 ESTAT_ADD(tx_collide_6times);
8830 ESTAT_ADD(tx_collide_7times);
8831 ESTAT_ADD(tx_collide_8times);
8832 ESTAT_ADD(tx_collide_9times);
8833 ESTAT_ADD(tx_collide_10times);
8834 ESTAT_ADD(tx_collide_11times);
8835 ESTAT_ADD(tx_collide_12times);
8836 ESTAT_ADD(tx_collide_13times);
8837 ESTAT_ADD(tx_collide_14times);
8838 ESTAT_ADD(tx_collide_15times);
8839 ESTAT_ADD(tx_ucast_packets);
8840 ESTAT_ADD(tx_mcast_packets);
8841 ESTAT_ADD(tx_bcast_packets);
8842 ESTAT_ADD(tx_carrier_sense_errors);
8843 ESTAT_ADD(tx_discards);
8844 ESTAT_ADD(tx_errors);
8845
8846 ESTAT_ADD(dma_writeq_full);
8847 ESTAT_ADD(dma_write_prioq_full);
8848 ESTAT_ADD(rxbds_empty);
8849 ESTAT_ADD(rx_discards);
8850 ESTAT_ADD(rx_errors);
8851 ESTAT_ADD(rx_threshold_hit);
8852
8853 ESTAT_ADD(dma_readq_full);
8854 ESTAT_ADD(dma_read_prioq_full);
8855 ESTAT_ADD(tx_comp_queue_full);
8856
8857 ESTAT_ADD(ring_set_send_prod_index);
8858 ESTAT_ADD(ring_status_update);
8859 ESTAT_ADD(nic_irqs);
8860 ESTAT_ADD(nic_avoided_irqs);
8861 ESTAT_ADD(nic_tx_threshold_hit);
8862
8863 return estats;
8864 }
8865
8866 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8867 {
8868 struct tg3 *tp = netdev_priv(dev);
8869 struct net_device_stats *stats = &tp->net_stats;
8870 struct net_device_stats *old_stats = &tp->net_stats_prev;
8871 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8872
8873 if (!hw_stats)
8874 return old_stats;
8875
8876 stats->rx_packets = old_stats->rx_packets +
8877 get_stat64(&hw_stats->rx_ucast_packets) +
8878 get_stat64(&hw_stats->rx_mcast_packets) +
8879 get_stat64(&hw_stats->rx_bcast_packets);
8880
8881 stats->tx_packets = old_stats->tx_packets +
8882 get_stat64(&hw_stats->tx_ucast_packets) +
8883 get_stat64(&hw_stats->tx_mcast_packets) +
8884 get_stat64(&hw_stats->tx_bcast_packets);
8885
8886 stats->rx_bytes = old_stats->rx_bytes +
8887 get_stat64(&hw_stats->rx_octets);
8888 stats->tx_bytes = old_stats->tx_bytes +
8889 get_stat64(&hw_stats->tx_octets);
8890
8891 stats->rx_errors = old_stats->rx_errors +
8892 get_stat64(&hw_stats->rx_errors);
8893 stats->tx_errors = old_stats->tx_errors +
8894 get_stat64(&hw_stats->tx_errors) +
8895 get_stat64(&hw_stats->tx_mac_errors) +
8896 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8897 get_stat64(&hw_stats->tx_discards);
8898
8899 stats->multicast = old_stats->multicast +
8900 get_stat64(&hw_stats->rx_mcast_packets);
8901 stats->collisions = old_stats->collisions +
8902 get_stat64(&hw_stats->tx_collisions);
8903
8904 stats->rx_length_errors = old_stats->rx_length_errors +
8905 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8906 get_stat64(&hw_stats->rx_undersize_packets);
8907
8908 stats->rx_over_errors = old_stats->rx_over_errors +
8909 get_stat64(&hw_stats->rxbds_empty);
8910 stats->rx_frame_errors = old_stats->rx_frame_errors +
8911 get_stat64(&hw_stats->rx_align_errors);
8912 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8913 get_stat64(&hw_stats->tx_discards);
8914 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8915 get_stat64(&hw_stats->tx_carrier_sense_errors);
8916
8917 stats->rx_crc_errors = old_stats->rx_crc_errors +
8918 calc_crc_errors(tp);
8919
8920 stats->rx_missed_errors = old_stats->rx_missed_errors +
8921 get_stat64(&hw_stats->rx_discards);
8922
8923 return stats;
8924 }
8925
8926 static inline u32 calc_crc(unsigned char *buf, int len)
8927 {
8928 u32 reg;
8929 u32 tmp;
8930 int j, k;
8931
8932 reg = 0xffffffff;
8933
8934 for (j = 0; j < len; j++) {
8935 reg ^= buf[j];
8936
8937 for (k = 0; k < 8; k++) {
8938 tmp = reg & 0x01;
8939
8940 reg >>= 1;
8941
8942 if (tmp) {
8943 reg ^= 0xedb88320;
8944 }
8945 }
8946 }
8947
8948 return ~reg;
8949 }
8950
8951 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8952 {
8953 /* accept or reject all multicast frames */
8954 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8955 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8956 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8957 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8958 }
8959
8960 static void __tg3_set_rx_mode(struct net_device *dev)
8961 {
8962 struct tg3 *tp = netdev_priv(dev);
8963 u32 rx_mode;
8964
8965 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8966 RX_MODE_KEEP_VLAN_TAG);
8967
8968 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8969 * flag clear.
8970 */
8971 #if TG3_VLAN_TAG_USED
8972 if (!tp->vlgrp &&
8973 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8974 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8975 #else
8976 /* By definition, VLAN is disabled always in this
8977 * case.
8978 */
8979 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8980 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8981 #endif
8982
8983 if (dev->flags & IFF_PROMISC) {
8984 /* Promiscuous mode. */
8985 rx_mode |= RX_MODE_PROMISC;
8986 } else if (dev->flags & IFF_ALLMULTI) {
8987 /* Accept all multicast. */
8988 tg3_set_multi (tp, 1);
8989 } else if (dev->mc_count < 1) {
8990 /* Reject all multicast. */
8991 tg3_set_multi (tp, 0);
8992 } else {
8993 /* Accept one or more multicast(s). */
8994 struct dev_mc_list *mclist;
8995 unsigned int i;
8996 u32 mc_filter[4] = { 0, };
8997 u32 regidx;
8998 u32 bit;
8999 u32 crc;
9000
9001 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9002 i++, mclist = mclist->next) {
9003
9004 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9005 bit = ~crc & 0x7f;
9006 regidx = (bit & 0x60) >> 5;
9007 bit &= 0x1f;
9008 mc_filter[regidx] |= (1 << bit);
9009 }
9010
9011 tw32(MAC_HASH_REG_0, mc_filter[0]);
9012 tw32(MAC_HASH_REG_1, mc_filter[1]);
9013 tw32(MAC_HASH_REG_2, mc_filter[2]);
9014 tw32(MAC_HASH_REG_3, mc_filter[3]);
9015 }
9016
9017 if (rx_mode != tp->rx_mode) {
9018 tp->rx_mode = rx_mode;
9019 tw32_f(MAC_RX_MODE, rx_mode);
9020 udelay(10);
9021 }
9022 }
9023
9024 static void tg3_set_rx_mode(struct net_device *dev)
9025 {
9026 struct tg3 *tp = netdev_priv(dev);
9027
9028 if (!netif_running(dev))
9029 return;
9030
9031 tg3_full_lock(tp, 0);
9032 __tg3_set_rx_mode(dev);
9033 tg3_full_unlock(tp);
9034 }
9035
9036 #define TG3_REGDUMP_LEN (32 * 1024)
9037
9038 static int tg3_get_regs_len(struct net_device *dev)
9039 {
9040 return TG3_REGDUMP_LEN;
9041 }
9042
9043 static void tg3_get_regs(struct net_device *dev,
9044 struct ethtool_regs *regs, void *_p)
9045 {
9046 u32 *p = _p;
9047 struct tg3 *tp = netdev_priv(dev);
9048 u8 *orig_p = _p;
9049 int i;
9050
9051 regs->version = 0;
9052
9053 memset(p, 0, TG3_REGDUMP_LEN);
9054
9055 if (tp->link_config.phy_is_low_power)
9056 return;
9057
9058 tg3_full_lock(tp, 0);
9059
9060 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9061 #define GET_REG32_LOOP(base,len) \
9062 do { p = (u32 *)(orig_p + (base)); \
9063 for (i = 0; i < len; i += 4) \
9064 __GET_REG32((base) + i); \
9065 } while (0)
9066 #define GET_REG32_1(reg) \
9067 do { p = (u32 *)(orig_p + (reg)); \
9068 __GET_REG32((reg)); \
9069 } while (0)
9070
9071 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9072 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9073 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9074 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9075 GET_REG32_1(SNDDATAC_MODE);
9076 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9077 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9078 GET_REG32_1(SNDBDC_MODE);
9079 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9080 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9081 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9082 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9083 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9084 GET_REG32_1(RCVDCC_MODE);
9085 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9086 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9087 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9088 GET_REG32_1(MBFREE_MODE);
9089 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9090 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9091 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9092 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9093 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9094 GET_REG32_1(RX_CPU_MODE);
9095 GET_REG32_1(RX_CPU_STATE);
9096 GET_REG32_1(RX_CPU_PGMCTR);
9097 GET_REG32_1(RX_CPU_HWBKPT);
9098 GET_REG32_1(TX_CPU_MODE);
9099 GET_REG32_1(TX_CPU_STATE);
9100 GET_REG32_1(TX_CPU_PGMCTR);
9101 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9102 GET_REG32_LOOP(FTQ_RESET, 0x120);
9103 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9104 GET_REG32_1(DMAC_MODE);
9105 GET_REG32_LOOP(GRC_MODE, 0x4c);
9106 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9107 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9108
9109 #undef __GET_REG32
9110 #undef GET_REG32_LOOP
9111 #undef GET_REG32_1
9112
9113 tg3_full_unlock(tp);
9114 }
9115
9116 static int tg3_get_eeprom_len(struct net_device *dev)
9117 {
9118 struct tg3 *tp = netdev_priv(dev);
9119
9120 return tp->nvram_size;
9121 }
9122
9123 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9124 {
9125 struct tg3 *tp = netdev_priv(dev);
9126 int ret;
9127 u8 *pd;
9128 u32 i, offset, len, b_offset, b_count;
9129 __be32 val;
9130
9131 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9132 return -EINVAL;
9133
9134 if (tp->link_config.phy_is_low_power)
9135 return -EAGAIN;
9136
9137 offset = eeprom->offset;
9138 len = eeprom->len;
9139 eeprom->len = 0;
9140
9141 eeprom->magic = TG3_EEPROM_MAGIC;
9142
9143 if (offset & 3) {
9144 /* adjustments to start on required 4 byte boundary */
9145 b_offset = offset & 3;
9146 b_count = 4 - b_offset;
9147 if (b_count > len) {
9148 /* i.e. offset=1 len=2 */
9149 b_count = len;
9150 }
9151 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9152 if (ret)
9153 return ret;
9154 memcpy(data, ((char*)&val) + b_offset, b_count);
9155 len -= b_count;
9156 offset += b_count;
9157 eeprom->len += b_count;
9158 }
9159
9160 /* read bytes upto the last 4 byte boundary */
9161 pd = &data[eeprom->len];
9162 for (i = 0; i < (len - (len & 3)); i += 4) {
9163 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9164 if (ret) {
9165 eeprom->len += i;
9166 return ret;
9167 }
9168 memcpy(pd + i, &val, 4);
9169 }
9170 eeprom->len += i;
9171
9172 if (len & 3) {
9173 /* read last bytes not ending on 4 byte boundary */
9174 pd = &data[eeprom->len];
9175 b_count = len & 3;
9176 b_offset = offset + len - b_count;
9177 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9178 if (ret)
9179 return ret;
9180 memcpy(pd, &val, b_count);
9181 eeprom->len += b_count;
9182 }
9183 return 0;
9184 }
9185
9186 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9187
9188 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9189 {
9190 struct tg3 *tp = netdev_priv(dev);
9191 int ret;
9192 u32 offset, len, b_offset, odd_len;
9193 u8 *buf;
9194 __be32 start, end;
9195
9196 if (tp->link_config.phy_is_low_power)
9197 return -EAGAIN;
9198
9199 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9200 eeprom->magic != TG3_EEPROM_MAGIC)
9201 return -EINVAL;
9202
9203 offset = eeprom->offset;
9204 len = eeprom->len;
9205
9206 if ((b_offset = (offset & 3))) {
9207 /* adjustments to start on required 4 byte boundary */
9208 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9209 if (ret)
9210 return ret;
9211 len += b_offset;
9212 offset &= ~3;
9213 if (len < 4)
9214 len = 4;
9215 }
9216
9217 odd_len = 0;
9218 if (len & 3) {
9219 /* adjustments to end on required 4 byte boundary */
9220 odd_len = 1;
9221 len = (len + 3) & ~3;
9222 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9223 if (ret)
9224 return ret;
9225 }
9226
9227 buf = data;
9228 if (b_offset || odd_len) {
9229 buf = kmalloc(len, GFP_KERNEL);
9230 if (!buf)
9231 return -ENOMEM;
9232 if (b_offset)
9233 memcpy(buf, &start, 4);
9234 if (odd_len)
9235 memcpy(buf+len-4, &end, 4);
9236 memcpy(buf + b_offset, data, eeprom->len);
9237 }
9238
9239 ret = tg3_nvram_write_block(tp, offset, len, buf);
9240
9241 if (buf != data)
9242 kfree(buf);
9243
9244 return ret;
9245 }
9246
9247 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9248 {
9249 struct tg3 *tp = netdev_priv(dev);
9250
9251 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9252 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9253 return -EAGAIN;
9254 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9255 }
9256
9257 cmd->supported = (SUPPORTED_Autoneg);
9258
9259 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9260 cmd->supported |= (SUPPORTED_1000baseT_Half |
9261 SUPPORTED_1000baseT_Full);
9262
9263 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9264 cmd->supported |= (SUPPORTED_100baseT_Half |
9265 SUPPORTED_100baseT_Full |
9266 SUPPORTED_10baseT_Half |
9267 SUPPORTED_10baseT_Full |
9268 SUPPORTED_TP);
9269 cmd->port = PORT_TP;
9270 } else {
9271 cmd->supported |= SUPPORTED_FIBRE;
9272 cmd->port = PORT_FIBRE;
9273 }
9274
9275 cmd->advertising = tp->link_config.advertising;
9276 if (netif_running(dev)) {
9277 cmd->speed = tp->link_config.active_speed;
9278 cmd->duplex = tp->link_config.active_duplex;
9279 }
9280 cmd->phy_address = tp->phy_addr;
9281 cmd->transceiver = XCVR_INTERNAL;
9282 cmd->autoneg = tp->link_config.autoneg;
9283 cmd->maxtxpkt = 0;
9284 cmd->maxrxpkt = 0;
9285 return 0;
9286 }
9287
9288 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9289 {
9290 struct tg3 *tp = netdev_priv(dev);
9291
9292 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9293 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9294 return -EAGAIN;
9295 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
9296 }
9297
9298 if (cmd->autoneg != AUTONEG_ENABLE &&
9299 cmd->autoneg != AUTONEG_DISABLE)
9300 return -EINVAL;
9301
9302 if (cmd->autoneg == AUTONEG_DISABLE &&
9303 cmd->duplex != DUPLEX_FULL &&
9304 cmd->duplex != DUPLEX_HALF)
9305 return -EINVAL;
9306
9307 if (cmd->autoneg == AUTONEG_ENABLE) {
9308 u32 mask = ADVERTISED_Autoneg |
9309 ADVERTISED_Pause |
9310 ADVERTISED_Asym_Pause;
9311
9312 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9313 mask |= ADVERTISED_1000baseT_Half |
9314 ADVERTISED_1000baseT_Full;
9315
9316 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9317 mask |= ADVERTISED_100baseT_Half |
9318 ADVERTISED_100baseT_Full |
9319 ADVERTISED_10baseT_Half |
9320 ADVERTISED_10baseT_Full |
9321 ADVERTISED_TP;
9322 else
9323 mask |= ADVERTISED_FIBRE;
9324
9325 if (cmd->advertising & ~mask)
9326 return -EINVAL;
9327
9328 mask &= (ADVERTISED_1000baseT_Half |
9329 ADVERTISED_1000baseT_Full |
9330 ADVERTISED_100baseT_Half |
9331 ADVERTISED_100baseT_Full |
9332 ADVERTISED_10baseT_Half |
9333 ADVERTISED_10baseT_Full);
9334
9335 cmd->advertising &= mask;
9336 } else {
9337 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9338 if (cmd->speed != SPEED_1000)
9339 return -EINVAL;
9340
9341 if (cmd->duplex != DUPLEX_FULL)
9342 return -EINVAL;
9343 } else {
9344 if (cmd->speed != SPEED_100 &&
9345 cmd->speed != SPEED_10)
9346 return -EINVAL;
9347 }
9348 }
9349
9350 tg3_full_lock(tp, 0);
9351
9352 tp->link_config.autoneg = cmd->autoneg;
9353 if (cmd->autoneg == AUTONEG_ENABLE) {
9354 tp->link_config.advertising = (cmd->advertising |
9355 ADVERTISED_Autoneg);
9356 tp->link_config.speed = SPEED_INVALID;
9357 tp->link_config.duplex = DUPLEX_INVALID;
9358 } else {
9359 tp->link_config.advertising = 0;
9360 tp->link_config.speed = cmd->speed;
9361 tp->link_config.duplex = cmd->duplex;
9362 }
9363
9364 tp->link_config.orig_speed = tp->link_config.speed;
9365 tp->link_config.orig_duplex = tp->link_config.duplex;
9366 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9367
9368 if (netif_running(dev))
9369 tg3_setup_phy(tp, 1);
9370
9371 tg3_full_unlock(tp);
9372
9373 return 0;
9374 }
9375
9376 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9377 {
9378 struct tg3 *tp = netdev_priv(dev);
9379
9380 strcpy(info->driver, DRV_MODULE_NAME);
9381 strcpy(info->version, DRV_MODULE_VERSION);
9382 strcpy(info->fw_version, tp->fw_ver);
9383 strcpy(info->bus_info, pci_name(tp->pdev));
9384 }
9385
9386 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9387 {
9388 struct tg3 *tp = netdev_priv(dev);
9389
9390 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9391 device_can_wakeup(&tp->pdev->dev))
9392 wol->supported = WAKE_MAGIC;
9393 else
9394 wol->supported = 0;
9395 wol->wolopts = 0;
9396 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9397 device_can_wakeup(&tp->pdev->dev))
9398 wol->wolopts = WAKE_MAGIC;
9399 memset(&wol->sopass, 0, sizeof(wol->sopass));
9400 }
9401
9402 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9403 {
9404 struct tg3 *tp = netdev_priv(dev);
9405 struct device *dp = &tp->pdev->dev;
9406
9407 if (wol->wolopts & ~WAKE_MAGIC)
9408 return -EINVAL;
9409 if ((wol->wolopts & WAKE_MAGIC) &&
9410 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9411 return -EINVAL;
9412
9413 spin_lock_bh(&tp->lock);
9414 if (wol->wolopts & WAKE_MAGIC) {
9415 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9416 device_set_wakeup_enable(dp, true);
9417 } else {
9418 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9419 device_set_wakeup_enable(dp, false);
9420 }
9421 spin_unlock_bh(&tp->lock);
9422
9423 return 0;
9424 }
9425
9426 static u32 tg3_get_msglevel(struct net_device *dev)
9427 {
9428 struct tg3 *tp = netdev_priv(dev);
9429 return tp->msg_enable;
9430 }
9431
9432 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9433 {
9434 struct tg3 *tp = netdev_priv(dev);
9435 tp->msg_enable = value;
9436 }
9437
9438 static int tg3_set_tso(struct net_device *dev, u32 value)
9439 {
9440 struct tg3 *tp = netdev_priv(dev);
9441
9442 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9443 if (value)
9444 return -EINVAL;
9445 return 0;
9446 }
9447 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9448 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
9449 if (value) {
9450 dev->features |= NETIF_F_TSO6;
9451 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9452 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9453 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9454 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9455 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9456 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9457 dev->features |= NETIF_F_TSO_ECN;
9458 } else
9459 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9460 }
9461 return ethtool_op_set_tso(dev, value);
9462 }
9463
9464 static int tg3_nway_reset(struct net_device *dev)
9465 {
9466 struct tg3 *tp = netdev_priv(dev);
9467 int r;
9468
9469 if (!netif_running(dev))
9470 return -EAGAIN;
9471
9472 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9473 return -EINVAL;
9474
9475 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9476 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9477 return -EAGAIN;
9478 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
9479 } else {
9480 u32 bmcr;
9481
9482 spin_lock_bh(&tp->lock);
9483 r = -EINVAL;
9484 tg3_readphy(tp, MII_BMCR, &bmcr);
9485 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9486 ((bmcr & BMCR_ANENABLE) ||
9487 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9488 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9489 BMCR_ANENABLE);
9490 r = 0;
9491 }
9492 spin_unlock_bh(&tp->lock);
9493 }
9494
9495 return r;
9496 }
9497
9498 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9499 {
9500 struct tg3 *tp = netdev_priv(dev);
9501
9502 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9503 ering->rx_mini_max_pending = 0;
9504 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9505 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9506 else
9507 ering->rx_jumbo_max_pending = 0;
9508
9509 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9510
9511 ering->rx_pending = tp->rx_pending;
9512 ering->rx_mini_pending = 0;
9513 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9514 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9515 else
9516 ering->rx_jumbo_pending = 0;
9517
9518 ering->tx_pending = tp->napi[0].tx_pending;
9519 }
9520
9521 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9522 {
9523 struct tg3 *tp = netdev_priv(dev);
9524 int i, irq_sync = 0, err = 0;
9525
9526 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9527 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9528 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9529 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9530 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9531 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9532 return -EINVAL;
9533
9534 if (netif_running(dev)) {
9535 tg3_phy_stop(tp);
9536 tg3_netif_stop(tp);
9537 irq_sync = 1;
9538 }
9539
9540 tg3_full_lock(tp, irq_sync);
9541
9542 tp->rx_pending = ering->rx_pending;
9543
9544 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9545 tp->rx_pending > 63)
9546 tp->rx_pending = 63;
9547 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9548
9549 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9550 tp->napi[i].tx_pending = ering->tx_pending;
9551
9552 if (netif_running(dev)) {
9553 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9554 err = tg3_restart_hw(tp, 1);
9555 if (!err)
9556 tg3_netif_start(tp);
9557 }
9558
9559 tg3_full_unlock(tp);
9560
9561 if (irq_sync && !err)
9562 tg3_phy_start(tp);
9563
9564 return err;
9565 }
9566
9567 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9568 {
9569 struct tg3 *tp = netdev_priv(dev);
9570
9571 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9572
9573 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9574 epause->rx_pause = 1;
9575 else
9576 epause->rx_pause = 0;
9577
9578 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9579 epause->tx_pause = 1;
9580 else
9581 epause->tx_pause = 0;
9582 }
9583
9584 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9585 {
9586 struct tg3 *tp = netdev_priv(dev);
9587 int err = 0;
9588
9589 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9590 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9591 return -EAGAIN;
9592
9593 if (epause->autoneg) {
9594 u32 newadv;
9595 struct phy_device *phydev;
9596
9597 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
9598
9599 if (epause->rx_pause) {
9600 if (epause->tx_pause)
9601 newadv = ADVERTISED_Pause;
9602 else
9603 newadv = ADVERTISED_Pause |
9604 ADVERTISED_Asym_Pause;
9605 } else if (epause->tx_pause) {
9606 newadv = ADVERTISED_Asym_Pause;
9607 } else
9608 newadv = 0;
9609
9610 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9611 u32 oldadv = phydev->advertising &
9612 (ADVERTISED_Pause |
9613 ADVERTISED_Asym_Pause);
9614 if (oldadv != newadv) {
9615 phydev->advertising &=
9616 ~(ADVERTISED_Pause |
9617 ADVERTISED_Asym_Pause);
9618 phydev->advertising |= newadv;
9619 err = phy_start_aneg(phydev);
9620 }
9621 } else {
9622 tp->link_config.advertising &=
9623 ~(ADVERTISED_Pause |
9624 ADVERTISED_Asym_Pause);
9625 tp->link_config.advertising |= newadv;
9626 }
9627 } else {
9628 if (epause->rx_pause)
9629 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9630 else
9631 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9632
9633 if (epause->tx_pause)
9634 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9635 else
9636 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9637
9638 if (netif_running(dev))
9639 tg3_setup_flow_control(tp, 0, 0);
9640 }
9641 } else {
9642 int irq_sync = 0;
9643
9644 if (netif_running(dev)) {
9645 tg3_netif_stop(tp);
9646 irq_sync = 1;
9647 }
9648
9649 tg3_full_lock(tp, irq_sync);
9650
9651 if (epause->autoneg)
9652 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9653 else
9654 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9655 if (epause->rx_pause)
9656 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9657 else
9658 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9659 if (epause->tx_pause)
9660 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9661 else
9662 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9663
9664 if (netif_running(dev)) {
9665 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9666 err = tg3_restart_hw(tp, 1);
9667 if (!err)
9668 tg3_netif_start(tp);
9669 }
9670
9671 tg3_full_unlock(tp);
9672 }
9673
9674 return err;
9675 }
9676
9677 static u32 tg3_get_rx_csum(struct net_device *dev)
9678 {
9679 struct tg3 *tp = netdev_priv(dev);
9680 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9681 }
9682
9683 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9684 {
9685 struct tg3 *tp = netdev_priv(dev);
9686
9687 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9688 if (data != 0)
9689 return -EINVAL;
9690 return 0;
9691 }
9692
9693 spin_lock_bh(&tp->lock);
9694 if (data)
9695 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9696 else
9697 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9698 spin_unlock_bh(&tp->lock);
9699
9700 return 0;
9701 }
9702
9703 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9704 {
9705 struct tg3 *tp = netdev_priv(dev);
9706
9707 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9708 if (data != 0)
9709 return -EINVAL;
9710 return 0;
9711 }
9712
9713 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9714 ethtool_op_set_tx_ipv6_csum(dev, data);
9715 else
9716 ethtool_op_set_tx_csum(dev, data);
9717
9718 return 0;
9719 }
9720
9721 static int tg3_get_sset_count (struct net_device *dev, int sset)
9722 {
9723 switch (sset) {
9724 case ETH_SS_TEST:
9725 return TG3_NUM_TEST;
9726 case ETH_SS_STATS:
9727 return TG3_NUM_STATS;
9728 default:
9729 return -EOPNOTSUPP;
9730 }
9731 }
9732
9733 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9734 {
9735 switch (stringset) {
9736 case ETH_SS_STATS:
9737 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9738 break;
9739 case ETH_SS_TEST:
9740 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9741 break;
9742 default:
9743 WARN_ON(1); /* we need a WARN() */
9744 break;
9745 }
9746 }
9747
9748 static int tg3_phys_id(struct net_device *dev, u32 data)
9749 {
9750 struct tg3 *tp = netdev_priv(dev);
9751 int i;
9752
9753 if (!netif_running(tp->dev))
9754 return -EAGAIN;
9755
9756 if (data == 0)
9757 data = UINT_MAX / 2;
9758
9759 for (i = 0; i < (data * 2); i++) {
9760 if ((i % 2) == 0)
9761 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9762 LED_CTRL_1000MBPS_ON |
9763 LED_CTRL_100MBPS_ON |
9764 LED_CTRL_10MBPS_ON |
9765 LED_CTRL_TRAFFIC_OVERRIDE |
9766 LED_CTRL_TRAFFIC_BLINK |
9767 LED_CTRL_TRAFFIC_LED);
9768
9769 else
9770 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9771 LED_CTRL_TRAFFIC_OVERRIDE);
9772
9773 if (msleep_interruptible(500))
9774 break;
9775 }
9776 tw32(MAC_LED_CTRL, tp->led_ctrl);
9777 return 0;
9778 }
9779
9780 static void tg3_get_ethtool_stats (struct net_device *dev,
9781 struct ethtool_stats *estats, u64 *tmp_stats)
9782 {
9783 struct tg3 *tp = netdev_priv(dev);
9784 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9785 }
9786
9787 #define NVRAM_TEST_SIZE 0x100
9788 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9789 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9790 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9791 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9792 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9793
9794 static int tg3_test_nvram(struct tg3 *tp)
9795 {
9796 u32 csum, magic;
9797 __be32 *buf;
9798 int i, j, k, err = 0, size;
9799
9800 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9801 return 0;
9802
9803 if (tg3_nvram_read(tp, 0, &magic) != 0)
9804 return -EIO;
9805
9806 if (magic == TG3_EEPROM_MAGIC)
9807 size = NVRAM_TEST_SIZE;
9808 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9809 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9810 TG3_EEPROM_SB_FORMAT_1) {
9811 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9812 case TG3_EEPROM_SB_REVISION_0:
9813 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9814 break;
9815 case TG3_EEPROM_SB_REVISION_2:
9816 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9817 break;
9818 case TG3_EEPROM_SB_REVISION_3:
9819 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9820 break;
9821 default:
9822 return 0;
9823 }
9824 } else
9825 return 0;
9826 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9827 size = NVRAM_SELFBOOT_HW_SIZE;
9828 else
9829 return -EIO;
9830
9831 buf = kmalloc(size, GFP_KERNEL);
9832 if (buf == NULL)
9833 return -ENOMEM;
9834
9835 err = -EIO;
9836 for (i = 0, j = 0; i < size; i += 4, j++) {
9837 err = tg3_nvram_read_be32(tp, i, &buf[j]);
9838 if (err)
9839 break;
9840 }
9841 if (i < size)
9842 goto out;
9843
9844 /* Selfboot format */
9845 magic = be32_to_cpu(buf[0]);
9846 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9847 TG3_EEPROM_MAGIC_FW) {
9848 u8 *buf8 = (u8 *) buf, csum8 = 0;
9849
9850 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9851 TG3_EEPROM_SB_REVISION_2) {
9852 /* For rev 2, the csum doesn't include the MBA. */
9853 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9854 csum8 += buf8[i];
9855 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9856 csum8 += buf8[i];
9857 } else {
9858 for (i = 0; i < size; i++)
9859 csum8 += buf8[i];
9860 }
9861
9862 if (csum8 == 0) {
9863 err = 0;
9864 goto out;
9865 }
9866
9867 err = -EIO;
9868 goto out;
9869 }
9870
9871 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9872 TG3_EEPROM_MAGIC_HW) {
9873 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9874 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9875 u8 *buf8 = (u8 *) buf;
9876
9877 /* Separate the parity bits and the data bytes. */
9878 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9879 if ((i == 0) || (i == 8)) {
9880 int l;
9881 u8 msk;
9882
9883 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9884 parity[k++] = buf8[i] & msk;
9885 i++;
9886 }
9887 else if (i == 16) {
9888 int l;
9889 u8 msk;
9890
9891 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9892 parity[k++] = buf8[i] & msk;
9893 i++;
9894
9895 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9896 parity[k++] = buf8[i] & msk;
9897 i++;
9898 }
9899 data[j++] = buf8[i];
9900 }
9901
9902 err = -EIO;
9903 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9904 u8 hw8 = hweight8(data[i]);
9905
9906 if ((hw8 & 0x1) && parity[i])
9907 goto out;
9908 else if (!(hw8 & 0x1) && !parity[i])
9909 goto out;
9910 }
9911 err = 0;
9912 goto out;
9913 }
9914
9915 /* Bootstrap checksum at offset 0x10 */
9916 csum = calc_crc((unsigned char *) buf, 0x10);
9917 if (csum != be32_to_cpu(buf[0x10/4]))
9918 goto out;
9919
9920 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9921 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9922 if (csum != be32_to_cpu(buf[0xfc/4]))
9923 goto out;
9924
9925 err = 0;
9926
9927 out:
9928 kfree(buf);
9929 return err;
9930 }
9931
9932 #define TG3_SERDES_TIMEOUT_SEC 2
9933 #define TG3_COPPER_TIMEOUT_SEC 6
9934
9935 static int tg3_test_link(struct tg3 *tp)
9936 {
9937 int i, max;
9938
9939 if (!netif_running(tp->dev))
9940 return -ENODEV;
9941
9942 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9943 max = TG3_SERDES_TIMEOUT_SEC;
9944 else
9945 max = TG3_COPPER_TIMEOUT_SEC;
9946
9947 for (i = 0; i < max; i++) {
9948 if (netif_carrier_ok(tp->dev))
9949 return 0;
9950
9951 if (msleep_interruptible(1000))
9952 break;
9953 }
9954
9955 return -EIO;
9956 }
9957
9958 /* Only test the commonly used registers */
9959 static int tg3_test_registers(struct tg3 *tp)
9960 {
9961 int i, is_5705, is_5750;
9962 u32 offset, read_mask, write_mask, val, save_val, read_val;
9963 static struct {
9964 u16 offset;
9965 u16 flags;
9966 #define TG3_FL_5705 0x1
9967 #define TG3_FL_NOT_5705 0x2
9968 #define TG3_FL_NOT_5788 0x4
9969 #define TG3_FL_NOT_5750 0x8
9970 u32 read_mask;
9971 u32 write_mask;
9972 } reg_tbl[] = {
9973 /* MAC Control Registers */
9974 { MAC_MODE, TG3_FL_NOT_5705,
9975 0x00000000, 0x00ef6f8c },
9976 { MAC_MODE, TG3_FL_5705,
9977 0x00000000, 0x01ef6b8c },
9978 { MAC_STATUS, TG3_FL_NOT_5705,
9979 0x03800107, 0x00000000 },
9980 { MAC_STATUS, TG3_FL_5705,
9981 0x03800100, 0x00000000 },
9982 { MAC_ADDR_0_HIGH, 0x0000,
9983 0x00000000, 0x0000ffff },
9984 { MAC_ADDR_0_LOW, 0x0000,
9985 0x00000000, 0xffffffff },
9986 { MAC_RX_MTU_SIZE, 0x0000,
9987 0x00000000, 0x0000ffff },
9988 { MAC_TX_MODE, 0x0000,
9989 0x00000000, 0x00000070 },
9990 { MAC_TX_LENGTHS, 0x0000,
9991 0x00000000, 0x00003fff },
9992 { MAC_RX_MODE, TG3_FL_NOT_5705,
9993 0x00000000, 0x000007fc },
9994 { MAC_RX_MODE, TG3_FL_5705,
9995 0x00000000, 0x000007dc },
9996 { MAC_HASH_REG_0, 0x0000,
9997 0x00000000, 0xffffffff },
9998 { MAC_HASH_REG_1, 0x0000,
9999 0x00000000, 0xffffffff },
10000 { MAC_HASH_REG_2, 0x0000,
10001 0x00000000, 0xffffffff },
10002 { MAC_HASH_REG_3, 0x0000,
10003 0x00000000, 0xffffffff },
10004
10005 /* Receive Data and Receive BD Initiator Control Registers. */
10006 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10007 0x00000000, 0xffffffff },
10008 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10009 0x00000000, 0xffffffff },
10010 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10011 0x00000000, 0x00000003 },
10012 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10013 0x00000000, 0xffffffff },
10014 { RCVDBDI_STD_BD+0, 0x0000,
10015 0x00000000, 0xffffffff },
10016 { RCVDBDI_STD_BD+4, 0x0000,
10017 0x00000000, 0xffffffff },
10018 { RCVDBDI_STD_BD+8, 0x0000,
10019 0x00000000, 0xffff0002 },
10020 { RCVDBDI_STD_BD+0xc, 0x0000,
10021 0x00000000, 0xffffffff },
10022
10023 /* Receive BD Initiator Control Registers. */
10024 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10025 0x00000000, 0xffffffff },
10026 { RCVBDI_STD_THRESH, TG3_FL_5705,
10027 0x00000000, 0x000003ff },
10028 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10029 0x00000000, 0xffffffff },
10030
10031 /* Host Coalescing Control Registers. */
10032 { HOSTCC_MODE, TG3_FL_NOT_5705,
10033 0x00000000, 0x00000004 },
10034 { HOSTCC_MODE, TG3_FL_5705,
10035 0x00000000, 0x000000f6 },
10036 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10037 0x00000000, 0xffffffff },
10038 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10039 0x00000000, 0x000003ff },
10040 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10041 0x00000000, 0xffffffff },
10042 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10043 0x00000000, 0x000003ff },
10044 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10045 0x00000000, 0xffffffff },
10046 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10047 0x00000000, 0x000000ff },
10048 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10049 0x00000000, 0xffffffff },
10050 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10051 0x00000000, 0x000000ff },
10052 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10053 0x00000000, 0xffffffff },
10054 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10055 0x00000000, 0xffffffff },
10056 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10057 0x00000000, 0xffffffff },
10058 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10059 0x00000000, 0x000000ff },
10060 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10061 0x00000000, 0xffffffff },
10062 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10063 0x00000000, 0x000000ff },
10064 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10065 0x00000000, 0xffffffff },
10066 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10067 0x00000000, 0xffffffff },
10068 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10069 0x00000000, 0xffffffff },
10070 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10071 0x00000000, 0xffffffff },
10072 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10073 0x00000000, 0xffffffff },
10074 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10075 0xffffffff, 0x00000000 },
10076 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10077 0xffffffff, 0x00000000 },
10078
10079 /* Buffer Manager Control Registers. */
10080 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10081 0x00000000, 0x007fff80 },
10082 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10083 0x00000000, 0x007fffff },
10084 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10085 0x00000000, 0x0000003f },
10086 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10087 0x00000000, 0x000001ff },
10088 { BUFMGR_MB_HIGH_WATER, 0x0000,
10089 0x00000000, 0x000001ff },
10090 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10091 0xffffffff, 0x00000000 },
10092 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10093 0xffffffff, 0x00000000 },
10094
10095 /* Mailbox Registers */
10096 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10097 0x00000000, 0x000001ff },
10098 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10099 0x00000000, 0x000001ff },
10100 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10101 0x00000000, 0x000007ff },
10102 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10103 0x00000000, 0x000001ff },
10104
10105 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10106 };
10107
10108 is_5705 = is_5750 = 0;
10109 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10110 is_5705 = 1;
10111 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10112 is_5750 = 1;
10113 }
10114
10115 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10116 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10117 continue;
10118
10119 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10120 continue;
10121
10122 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10123 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10124 continue;
10125
10126 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10127 continue;
10128
10129 offset = (u32) reg_tbl[i].offset;
10130 read_mask = reg_tbl[i].read_mask;
10131 write_mask = reg_tbl[i].write_mask;
10132
10133 /* Save the original register content */
10134 save_val = tr32(offset);
10135
10136 /* Determine the read-only value. */
10137 read_val = save_val & read_mask;
10138
10139 /* Write zero to the register, then make sure the read-only bits
10140 * are not changed and the read/write bits are all zeros.
10141 */
10142 tw32(offset, 0);
10143
10144 val = tr32(offset);
10145
10146 /* Test the read-only and read/write bits. */
10147 if (((val & read_mask) != read_val) || (val & write_mask))
10148 goto out;
10149
10150 /* Write ones to all the bits defined by RdMask and WrMask, then
10151 * make sure the read-only bits are not changed and the
10152 * read/write bits are all ones.
10153 */
10154 tw32(offset, read_mask | write_mask);
10155
10156 val = tr32(offset);
10157
10158 /* Test the read-only bits. */
10159 if ((val & read_mask) != read_val)
10160 goto out;
10161
10162 /* Test the read/write bits. */
10163 if ((val & write_mask) != write_mask)
10164 goto out;
10165
10166 tw32(offset, save_val);
10167 }
10168
10169 return 0;
10170
10171 out:
10172 if (netif_msg_hw(tp))
10173 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10174 offset);
10175 tw32(offset, save_val);
10176 return -EIO;
10177 }
10178
10179 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10180 {
10181 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10182 int i;
10183 u32 j;
10184
10185 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10186 for (j = 0; j < len; j += 4) {
10187 u32 val;
10188
10189 tg3_write_mem(tp, offset + j, test_pattern[i]);
10190 tg3_read_mem(tp, offset + j, &val);
10191 if (val != test_pattern[i])
10192 return -EIO;
10193 }
10194 }
10195 return 0;
10196 }
10197
10198 static int tg3_test_memory(struct tg3 *tp)
10199 {
10200 static struct mem_entry {
10201 u32 offset;
10202 u32 len;
10203 } mem_tbl_570x[] = {
10204 { 0x00000000, 0x00b50},
10205 { 0x00002000, 0x1c000},
10206 { 0xffffffff, 0x00000}
10207 }, mem_tbl_5705[] = {
10208 { 0x00000100, 0x0000c},
10209 { 0x00000200, 0x00008},
10210 { 0x00004000, 0x00800},
10211 { 0x00006000, 0x01000},
10212 { 0x00008000, 0x02000},
10213 { 0x00010000, 0x0e000},
10214 { 0xffffffff, 0x00000}
10215 }, mem_tbl_5755[] = {
10216 { 0x00000200, 0x00008},
10217 { 0x00004000, 0x00800},
10218 { 0x00006000, 0x00800},
10219 { 0x00008000, 0x02000},
10220 { 0x00010000, 0x0c000},
10221 { 0xffffffff, 0x00000}
10222 }, mem_tbl_5906[] = {
10223 { 0x00000200, 0x00008},
10224 { 0x00004000, 0x00400},
10225 { 0x00006000, 0x00400},
10226 { 0x00008000, 0x01000},
10227 { 0x00010000, 0x01000},
10228 { 0xffffffff, 0x00000}
10229 };
10230 struct mem_entry *mem_tbl;
10231 int err = 0;
10232 int i;
10233
10234 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10235 mem_tbl = mem_tbl_5755;
10236 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10237 mem_tbl = mem_tbl_5906;
10238 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10239 mem_tbl = mem_tbl_5705;
10240 else
10241 mem_tbl = mem_tbl_570x;
10242
10243 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10244 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10245 mem_tbl[i].len)) != 0)
10246 break;
10247 }
10248
10249 return err;
10250 }
10251
10252 #define TG3_MAC_LOOPBACK 0
10253 #define TG3_PHY_LOOPBACK 1
10254
10255 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10256 {
10257 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10258 u32 desc_idx, coal_now;
10259 struct sk_buff *skb, *rx_skb;
10260 u8 *tx_data;
10261 dma_addr_t map;
10262 int num_pkts, tx_len, rx_len, i, err;
10263 struct tg3_rx_buffer_desc *desc;
10264 struct tg3_napi *tnapi, *rnapi;
10265 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10266
10267 if (tp->irq_cnt > 1) {
10268 tnapi = &tp->napi[1];
10269 rnapi = &tp->napi[1];
10270 } else {
10271 tnapi = &tp->napi[0];
10272 rnapi = &tp->napi[0];
10273 }
10274 coal_now = tnapi->coal_now | rnapi->coal_now;
10275
10276 if (loopback_mode == TG3_MAC_LOOPBACK) {
10277 /* HW errata - mac loopback fails in some cases on 5780.
10278 * Normal traffic and PHY loopback are not affected by
10279 * errata.
10280 */
10281 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10282 return 0;
10283
10284 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10285 MAC_MODE_PORT_INT_LPBACK;
10286 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10287 mac_mode |= MAC_MODE_LINK_POLARITY;
10288 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10289 mac_mode |= MAC_MODE_PORT_MODE_MII;
10290 else
10291 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10292 tw32(MAC_MODE, mac_mode);
10293 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10294 u32 val;
10295
10296 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10297 tg3_phy_fet_toggle_apd(tp, false);
10298 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10299 } else
10300 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10301
10302 tg3_phy_toggle_automdix(tp, 0);
10303
10304 tg3_writephy(tp, MII_BMCR, val);
10305 udelay(40);
10306
10307 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10308 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10309 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10310 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10311 mac_mode |= MAC_MODE_PORT_MODE_MII;
10312 } else
10313 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10314
10315 /* reset to prevent losing 1st rx packet intermittently */
10316 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10317 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10318 udelay(10);
10319 tw32_f(MAC_RX_MODE, tp->rx_mode);
10320 }
10321 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10322 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10323 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10324 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10325 mac_mode |= MAC_MODE_LINK_POLARITY;
10326 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10327 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10328 }
10329 tw32(MAC_MODE, mac_mode);
10330 }
10331 else
10332 return -EINVAL;
10333
10334 err = -EIO;
10335
10336 tx_len = 1514;
10337 skb = netdev_alloc_skb(tp->dev, tx_len);
10338 if (!skb)
10339 return -ENOMEM;
10340
10341 tx_data = skb_put(skb, tx_len);
10342 memcpy(tx_data, tp->dev->dev_addr, 6);
10343 memset(tx_data + 6, 0x0, 8);
10344
10345 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10346
10347 for (i = 14; i < tx_len; i++)
10348 tx_data[i] = (u8) (i & 0xff);
10349
10350 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10351
10352 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10353 rnapi->coal_now);
10354
10355 udelay(10);
10356
10357 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10358
10359 num_pkts = 0;
10360
10361 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10362
10363 tnapi->tx_prod++;
10364 num_pkts++;
10365
10366 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10367 tr32_mailbox(tnapi->prodmbox);
10368
10369 udelay(10);
10370
10371 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
10372 for (i = 0; i < 25; i++) {
10373 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10374 coal_now);
10375
10376 udelay(10);
10377
10378 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10379 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10380 if ((tx_idx == tnapi->tx_prod) &&
10381 (rx_idx == (rx_start_idx + num_pkts)))
10382 break;
10383 }
10384
10385 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10386 dev_kfree_skb(skb);
10387
10388 if (tx_idx != tnapi->tx_prod)
10389 goto out;
10390
10391 if (rx_idx != rx_start_idx + num_pkts)
10392 goto out;
10393
10394 desc = &rnapi->rx_rcb[rx_start_idx];
10395 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10396 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10397 if (opaque_key != RXD_OPAQUE_RING_STD)
10398 goto out;
10399
10400 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10401 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10402 goto out;
10403
10404 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10405 if (rx_len != tx_len)
10406 goto out;
10407
10408 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10409
10410 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10411 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10412
10413 for (i = 14; i < tx_len; i++) {
10414 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10415 goto out;
10416 }
10417 err = 0;
10418
10419 /* tg3_free_rings will unmap and free the rx_skb */
10420 out:
10421 return err;
10422 }
10423
10424 #define TG3_MAC_LOOPBACK_FAILED 1
10425 #define TG3_PHY_LOOPBACK_FAILED 2
10426 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10427 TG3_PHY_LOOPBACK_FAILED)
10428
10429 static int tg3_test_loopback(struct tg3 *tp)
10430 {
10431 int err = 0;
10432 u32 cpmuctrl = 0;
10433
10434 if (!netif_running(tp->dev))
10435 return TG3_LOOPBACK_FAILED;
10436
10437 err = tg3_reset_hw(tp, 1);
10438 if (err)
10439 return TG3_LOOPBACK_FAILED;
10440
10441 /* Turn off gphy autopowerdown. */
10442 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10443 tg3_phy_toggle_apd(tp, false);
10444
10445 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10446 int i;
10447 u32 status;
10448
10449 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10450
10451 /* Wait for up to 40 microseconds to acquire lock. */
10452 for (i = 0; i < 4; i++) {
10453 status = tr32(TG3_CPMU_MUTEX_GNT);
10454 if (status == CPMU_MUTEX_GNT_DRIVER)
10455 break;
10456 udelay(10);
10457 }
10458
10459 if (status != CPMU_MUTEX_GNT_DRIVER)
10460 return TG3_LOOPBACK_FAILED;
10461
10462 /* Turn off link-based power management. */
10463 cpmuctrl = tr32(TG3_CPMU_CTRL);
10464 tw32(TG3_CPMU_CTRL,
10465 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10466 CPMU_CTRL_LINK_AWARE_MODE));
10467 }
10468
10469 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10470 err |= TG3_MAC_LOOPBACK_FAILED;
10471
10472 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10473 tw32(TG3_CPMU_CTRL, cpmuctrl);
10474
10475 /* Release the mutex */
10476 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10477 }
10478
10479 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10480 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10481 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10482 err |= TG3_PHY_LOOPBACK_FAILED;
10483 }
10484
10485 /* Re-enable gphy autopowerdown. */
10486 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10487 tg3_phy_toggle_apd(tp, true);
10488
10489 return err;
10490 }
10491
10492 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10493 u64 *data)
10494 {
10495 struct tg3 *tp = netdev_priv(dev);
10496
10497 if (tp->link_config.phy_is_low_power)
10498 tg3_set_power_state(tp, PCI_D0);
10499
10500 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10501
10502 if (tg3_test_nvram(tp) != 0) {
10503 etest->flags |= ETH_TEST_FL_FAILED;
10504 data[0] = 1;
10505 }
10506 if (tg3_test_link(tp) != 0) {
10507 etest->flags |= ETH_TEST_FL_FAILED;
10508 data[1] = 1;
10509 }
10510 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10511 int err, err2 = 0, irq_sync = 0;
10512
10513 if (netif_running(dev)) {
10514 tg3_phy_stop(tp);
10515 tg3_netif_stop(tp);
10516 irq_sync = 1;
10517 }
10518
10519 tg3_full_lock(tp, irq_sync);
10520
10521 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10522 err = tg3_nvram_lock(tp);
10523 tg3_halt_cpu(tp, RX_CPU_BASE);
10524 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10525 tg3_halt_cpu(tp, TX_CPU_BASE);
10526 if (!err)
10527 tg3_nvram_unlock(tp);
10528
10529 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10530 tg3_phy_reset(tp);
10531
10532 if (tg3_test_registers(tp) != 0) {
10533 etest->flags |= ETH_TEST_FL_FAILED;
10534 data[2] = 1;
10535 }
10536 if (tg3_test_memory(tp) != 0) {
10537 etest->flags |= ETH_TEST_FL_FAILED;
10538 data[3] = 1;
10539 }
10540 if ((data[4] = tg3_test_loopback(tp)) != 0)
10541 etest->flags |= ETH_TEST_FL_FAILED;
10542
10543 tg3_full_unlock(tp);
10544
10545 if (tg3_test_interrupt(tp) != 0) {
10546 etest->flags |= ETH_TEST_FL_FAILED;
10547 data[5] = 1;
10548 }
10549
10550 tg3_full_lock(tp, 0);
10551
10552 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10553 if (netif_running(dev)) {
10554 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10555 err2 = tg3_restart_hw(tp, 1);
10556 if (!err2)
10557 tg3_netif_start(tp);
10558 }
10559
10560 tg3_full_unlock(tp);
10561
10562 if (irq_sync && !err2)
10563 tg3_phy_start(tp);
10564 }
10565 if (tp->link_config.phy_is_low_power)
10566 tg3_set_power_state(tp, PCI_D3hot);
10567
10568 }
10569
10570 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10571 {
10572 struct mii_ioctl_data *data = if_mii(ifr);
10573 struct tg3 *tp = netdev_priv(dev);
10574 int err;
10575
10576 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10577 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10578 return -EAGAIN;
10579 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
10580 }
10581
10582 switch(cmd) {
10583 case SIOCGMIIPHY:
10584 data->phy_id = tp->phy_addr;
10585
10586 /* fallthru */
10587 case SIOCGMIIREG: {
10588 u32 mii_regval;
10589
10590 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10591 break; /* We have no PHY */
10592
10593 if (tp->link_config.phy_is_low_power)
10594 return -EAGAIN;
10595
10596 spin_lock_bh(&tp->lock);
10597 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10598 spin_unlock_bh(&tp->lock);
10599
10600 data->val_out = mii_regval;
10601
10602 return err;
10603 }
10604
10605 case SIOCSMIIREG:
10606 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10607 break; /* We have no PHY */
10608
10609 if (tp->link_config.phy_is_low_power)
10610 return -EAGAIN;
10611
10612 spin_lock_bh(&tp->lock);
10613 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10614 spin_unlock_bh(&tp->lock);
10615
10616 return err;
10617
10618 default:
10619 /* do nothing */
10620 break;
10621 }
10622 return -EOPNOTSUPP;
10623 }
10624
10625 #if TG3_VLAN_TAG_USED
10626 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10627 {
10628 struct tg3 *tp = netdev_priv(dev);
10629
10630 if (!netif_running(dev)) {
10631 tp->vlgrp = grp;
10632 return;
10633 }
10634
10635 tg3_netif_stop(tp);
10636
10637 tg3_full_lock(tp, 0);
10638
10639 tp->vlgrp = grp;
10640
10641 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10642 __tg3_set_rx_mode(dev);
10643
10644 tg3_netif_start(tp);
10645
10646 tg3_full_unlock(tp);
10647 }
10648 #endif
10649
10650 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10651 {
10652 struct tg3 *tp = netdev_priv(dev);
10653
10654 memcpy(ec, &tp->coal, sizeof(*ec));
10655 return 0;
10656 }
10657
10658 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10659 {
10660 struct tg3 *tp = netdev_priv(dev);
10661 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10662 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10663
10664 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10665 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10666 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10667 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10668 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10669 }
10670
10671 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10672 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10673 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10674 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10675 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10676 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10677 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10678 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10679 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10680 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10681 return -EINVAL;
10682
10683 /* No rx interrupts will be generated if both are zero */
10684 if ((ec->rx_coalesce_usecs == 0) &&
10685 (ec->rx_max_coalesced_frames == 0))
10686 return -EINVAL;
10687
10688 /* No tx interrupts will be generated if both are zero */
10689 if ((ec->tx_coalesce_usecs == 0) &&
10690 (ec->tx_max_coalesced_frames == 0))
10691 return -EINVAL;
10692
10693 /* Only copy relevant parameters, ignore all others. */
10694 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10695 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10696 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10697 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10698 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10699 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10700 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10701 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10702 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10703
10704 if (netif_running(dev)) {
10705 tg3_full_lock(tp, 0);
10706 __tg3_set_coalesce(tp, &tp->coal);
10707 tg3_full_unlock(tp);
10708 }
10709 return 0;
10710 }
10711
10712 static const struct ethtool_ops tg3_ethtool_ops = {
10713 .get_settings = tg3_get_settings,
10714 .set_settings = tg3_set_settings,
10715 .get_drvinfo = tg3_get_drvinfo,
10716 .get_regs_len = tg3_get_regs_len,
10717 .get_regs = tg3_get_regs,
10718 .get_wol = tg3_get_wol,
10719 .set_wol = tg3_set_wol,
10720 .get_msglevel = tg3_get_msglevel,
10721 .set_msglevel = tg3_set_msglevel,
10722 .nway_reset = tg3_nway_reset,
10723 .get_link = ethtool_op_get_link,
10724 .get_eeprom_len = tg3_get_eeprom_len,
10725 .get_eeprom = tg3_get_eeprom,
10726 .set_eeprom = tg3_set_eeprom,
10727 .get_ringparam = tg3_get_ringparam,
10728 .set_ringparam = tg3_set_ringparam,
10729 .get_pauseparam = tg3_get_pauseparam,
10730 .set_pauseparam = tg3_set_pauseparam,
10731 .get_rx_csum = tg3_get_rx_csum,
10732 .set_rx_csum = tg3_set_rx_csum,
10733 .set_tx_csum = tg3_set_tx_csum,
10734 .set_sg = ethtool_op_set_sg,
10735 .set_tso = tg3_set_tso,
10736 .self_test = tg3_self_test,
10737 .get_strings = tg3_get_strings,
10738 .phys_id = tg3_phys_id,
10739 .get_ethtool_stats = tg3_get_ethtool_stats,
10740 .get_coalesce = tg3_get_coalesce,
10741 .set_coalesce = tg3_set_coalesce,
10742 .get_sset_count = tg3_get_sset_count,
10743 };
10744
10745 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10746 {
10747 u32 cursize, val, magic;
10748
10749 tp->nvram_size = EEPROM_CHIP_SIZE;
10750
10751 if (tg3_nvram_read(tp, 0, &magic) != 0)
10752 return;
10753
10754 if ((magic != TG3_EEPROM_MAGIC) &&
10755 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10756 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10757 return;
10758
10759 /*
10760 * Size the chip by reading offsets at increasing powers of two.
10761 * When we encounter our validation signature, we know the addressing
10762 * has wrapped around, and thus have our chip size.
10763 */
10764 cursize = 0x10;
10765
10766 while (cursize < tp->nvram_size) {
10767 if (tg3_nvram_read(tp, cursize, &val) != 0)
10768 return;
10769
10770 if (val == magic)
10771 break;
10772
10773 cursize <<= 1;
10774 }
10775
10776 tp->nvram_size = cursize;
10777 }
10778
10779 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10780 {
10781 u32 val;
10782
10783 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
10784 tg3_nvram_read(tp, 0, &val) != 0)
10785 return;
10786
10787 /* Selfboot format */
10788 if (val != TG3_EEPROM_MAGIC) {
10789 tg3_get_eeprom_size(tp);
10790 return;
10791 }
10792
10793 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10794 if (val != 0) {
10795 /* This is confusing. We want to operate on the
10796 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10797 * call will read from NVRAM and byteswap the data
10798 * according to the byteswapping settings for all
10799 * other register accesses. This ensures the data we
10800 * want will always reside in the lower 16-bits.
10801 * However, the data in NVRAM is in LE format, which
10802 * means the data from the NVRAM read will always be
10803 * opposite the endianness of the CPU. The 16-bit
10804 * byteswap then brings the data to CPU endianness.
10805 */
10806 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
10807 return;
10808 }
10809 }
10810 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10811 }
10812
10813 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10814 {
10815 u32 nvcfg1;
10816
10817 nvcfg1 = tr32(NVRAM_CFG1);
10818 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10819 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10820 } else {
10821 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10822 tw32(NVRAM_CFG1, nvcfg1);
10823 }
10824
10825 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10826 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10827 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10828 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10829 tp->nvram_jedecnum = JEDEC_ATMEL;
10830 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10831 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10832 break;
10833 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10834 tp->nvram_jedecnum = JEDEC_ATMEL;
10835 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10836 break;
10837 case FLASH_VENDOR_ATMEL_EEPROM:
10838 tp->nvram_jedecnum = JEDEC_ATMEL;
10839 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10840 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10841 break;
10842 case FLASH_VENDOR_ST:
10843 tp->nvram_jedecnum = JEDEC_ST;
10844 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10845 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10846 break;
10847 case FLASH_VENDOR_SAIFUN:
10848 tp->nvram_jedecnum = JEDEC_SAIFUN;
10849 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10850 break;
10851 case FLASH_VENDOR_SST_SMALL:
10852 case FLASH_VENDOR_SST_LARGE:
10853 tp->nvram_jedecnum = JEDEC_SST;
10854 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10855 break;
10856 }
10857 } else {
10858 tp->nvram_jedecnum = JEDEC_ATMEL;
10859 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10860 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10861 }
10862 }
10863
10864 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
10865 {
10866 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10867 case FLASH_5752PAGE_SIZE_256:
10868 tp->nvram_pagesize = 256;
10869 break;
10870 case FLASH_5752PAGE_SIZE_512:
10871 tp->nvram_pagesize = 512;
10872 break;
10873 case FLASH_5752PAGE_SIZE_1K:
10874 tp->nvram_pagesize = 1024;
10875 break;
10876 case FLASH_5752PAGE_SIZE_2K:
10877 tp->nvram_pagesize = 2048;
10878 break;
10879 case FLASH_5752PAGE_SIZE_4K:
10880 tp->nvram_pagesize = 4096;
10881 break;
10882 case FLASH_5752PAGE_SIZE_264:
10883 tp->nvram_pagesize = 264;
10884 break;
10885 case FLASH_5752PAGE_SIZE_528:
10886 tp->nvram_pagesize = 528;
10887 break;
10888 }
10889 }
10890
10891 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10892 {
10893 u32 nvcfg1;
10894
10895 nvcfg1 = tr32(NVRAM_CFG1);
10896
10897 /* NVRAM protection for TPM */
10898 if (nvcfg1 & (1 << 27))
10899 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10900
10901 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10902 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10903 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10904 tp->nvram_jedecnum = JEDEC_ATMEL;
10905 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10906 break;
10907 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10908 tp->nvram_jedecnum = JEDEC_ATMEL;
10909 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10910 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10911 break;
10912 case FLASH_5752VENDOR_ST_M45PE10:
10913 case FLASH_5752VENDOR_ST_M45PE20:
10914 case FLASH_5752VENDOR_ST_M45PE40:
10915 tp->nvram_jedecnum = JEDEC_ST;
10916 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10917 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10918 break;
10919 }
10920
10921 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10922 tg3_nvram_get_pagesize(tp, nvcfg1);
10923 } else {
10924 /* For eeprom, set pagesize to maximum eeprom size */
10925 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10926
10927 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10928 tw32(NVRAM_CFG1, nvcfg1);
10929 }
10930 }
10931
10932 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10933 {
10934 u32 nvcfg1, protect = 0;
10935
10936 nvcfg1 = tr32(NVRAM_CFG1);
10937
10938 /* NVRAM protection for TPM */
10939 if (nvcfg1 & (1 << 27)) {
10940 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10941 protect = 1;
10942 }
10943
10944 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10945 switch (nvcfg1) {
10946 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10947 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10948 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10949 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10950 tp->nvram_jedecnum = JEDEC_ATMEL;
10951 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10952 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10953 tp->nvram_pagesize = 264;
10954 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10955 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10956 tp->nvram_size = (protect ? 0x3e200 :
10957 TG3_NVRAM_SIZE_512KB);
10958 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10959 tp->nvram_size = (protect ? 0x1f200 :
10960 TG3_NVRAM_SIZE_256KB);
10961 else
10962 tp->nvram_size = (protect ? 0x1f200 :
10963 TG3_NVRAM_SIZE_128KB);
10964 break;
10965 case FLASH_5752VENDOR_ST_M45PE10:
10966 case FLASH_5752VENDOR_ST_M45PE20:
10967 case FLASH_5752VENDOR_ST_M45PE40:
10968 tp->nvram_jedecnum = JEDEC_ST;
10969 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10970 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10971 tp->nvram_pagesize = 256;
10972 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10973 tp->nvram_size = (protect ?
10974 TG3_NVRAM_SIZE_64KB :
10975 TG3_NVRAM_SIZE_128KB);
10976 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10977 tp->nvram_size = (protect ?
10978 TG3_NVRAM_SIZE_64KB :
10979 TG3_NVRAM_SIZE_256KB);
10980 else
10981 tp->nvram_size = (protect ?
10982 TG3_NVRAM_SIZE_128KB :
10983 TG3_NVRAM_SIZE_512KB);
10984 break;
10985 }
10986 }
10987
10988 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10989 {
10990 u32 nvcfg1;
10991
10992 nvcfg1 = tr32(NVRAM_CFG1);
10993
10994 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10995 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10996 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10997 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10998 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10999 tp->nvram_jedecnum = JEDEC_ATMEL;
11000 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11001 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11002
11003 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11004 tw32(NVRAM_CFG1, nvcfg1);
11005 break;
11006 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11007 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11008 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11009 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11010 tp->nvram_jedecnum = JEDEC_ATMEL;
11011 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11012 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11013 tp->nvram_pagesize = 264;
11014 break;
11015 case FLASH_5752VENDOR_ST_M45PE10:
11016 case FLASH_5752VENDOR_ST_M45PE20:
11017 case FLASH_5752VENDOR_ST_M45PE40:
11018 tp->nvram_jedecnum = JEDEC_ST;
11019 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11020 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11021 tp->nvram_pagesize = 256;
11022 break;
11023 }
11024 }
11025
11026 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11027 {
11028 u32 nvcfg1, protect = 0;
11029
11030 nvcfg1 = tr32(NVRAM_CFG1);
11031
11032 /* NVRAM protection for TPM */
11033 if (nvcfg1 & (1 << 27)) {
11034 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
11035 protect = 1;
11036 }
11037
11038 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11039 switch (nvcfg1) {
11040 case FLASH_5761VENDOR_ATMEL_ADB021D:
11041 case FLASH_5761VENDOR_ATMEL_ADB041D:
11042 case FLASH_5761VENDOR_ATMEL_ADB081D:
11043 case FLASH_5761VENDOR_ATMEL_ADB161D:
11044 case FLASH_5761VENDOR_ATMEL_MDB021D:
11045 case FLASH_5761VENDOR_ATMEL_MDB041D:
11046 case FLASH_5761VENDOR_ATMEL_MDB081D:
11047 case FLASH_5761VENDOR_ATMEL_MDB161D:
11048 tp->nvram_jedecnum = JEDEC_ATMEL;
11049 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11050 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11051 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11052 tp->nvram_pagesize = 256;
11053 break;
11054 case FLASH_5761VENDOR_ST_A_M45PE20:
11055 case FLASH_5761VENDOR_ST_A_M45PE40:
11056 case FLASH_5761VENDOR_ST_A_M45PE80:
11057 case FLASH_5761VENDOR_ST_A_M45PE16:
11058 case FLASH_5761VENDOR_ST_M_M45PE20:
11059 case FLASH_5761VENDOR_ST_M_M45PE40:
11060 case FLASH_5761VENDOR_ST_M_M45PE80:
11061 case FLASH_5761VENDOR_ST_M_M45PE16:
11062 tp->nvram_jedecnum = JEDEC_ST;
11063 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11064 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11065 tp->nvram_pagesize = 256;
11066 break;
11067 }
11068
11069 if (protect) {
11070 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11071 } else {
11072 switch (nvcfg1) {
11073 case FLASH_5761VENDOR_ATMEL_ADB161D:
11074 case FLASH_5761VENDOR_ATMEL_MDB161D:
11075 case FLASH_5761VENDOR_ST_A_M45PE16:
11076 case FLASH_5761VENDOR_ST_M_M45PE16:
11077 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11078 break;
11079 case FLASH_5761VENDOR_ATMEL_ADB081D:
11080 case FLASH_5761VENDOR_ATMEL_MDB081D:
11081 case FLASH_5761VENDOR_ST_A_M45PE80:
11082 case FLASH_5761VENDOR_ST_M_M45PE80:
11083 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11084 break;
11085 case FLASH_5761VENDOR_ATMEL_ADB041D:
11086 case FLASH_5761VENDOR_ATMEL_MDB041D:
11087 case FLASH_5761VENDOR_ST_A_M45PE40:
11088 case FLASH_5761VENDOR_ST_M_M45PE40:
11089 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11090 break;
11091 case FLASH_5761VENDOR_ATMEL_ADB021D:
11092 case FLASH_5761VENDOR_ATMEL_MDB021D:
11093 case FLASH_5761VENDOR_ST_A_M45PE20:
11094 case FLASH_5761VENDOR_ST_M_M45PE20:
11095 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11096 break;
11097 }
11098 }
11099 }
11100
11101 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11102 {
11103 tp->nvram_jedecnum = JEDEC_ATMEL;
11104 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11105 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11106 }
11107
11108 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11109 {
11110 u32 nvcfg1;
11111
11112 nvcfg1 = tr32(NVRAM_CFG1);
11113
11114 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11115 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11116 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11117 tp->nvram_jedecnum = JEDEC_ATMEL;
11118 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11119 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11120
11121 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11122 tw32(NVRAM_CFG1, nvcfg1);
11123 return;
11124 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11125 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11126 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11127 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11128 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11129 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11130 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11131 tp->nvram_jedecnum = JEDEC_ATMEL;
11132 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11133 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11134
11135 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11136 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11137 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11138 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11139 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11140 break;
11141 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11142 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11143 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11144 break;
11145 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11146 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11147 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11148 break;
11149 }
11150 break;
11151 case FLASH_5752VENDOR_ST_M45PE10:
11152 case FLASH_5752VENDOR_ST_M45PE20:
11153 case FLASH_5752VENDOR_ST_M45PE40:
11154 tp->nvram_jedecnum = JEDEC_ST;
11155 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11156 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11157
11158 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11159 case FLASH_5752VENDOR_ST_M45PE10:
11160 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11161 break;
11162 case FLASH_5752VENDOR_ST_M45PE20:
11163 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11164 break;
11165 case FLASH_5752VENDOR_ST_M45PE40:
11166 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11167 break;
11168 }
11169 break;
11170 default:
11171 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11172 return;
11173 }
11174
11175 tg3_nvram_get_pagesize(tp, nvcfg1);
11176 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11177 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11178 }
11179
11180
11181 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11182 {
11183 u32 nvcfg1;
11184
11185 nvcfg1 = tr32(NVRAM_CFG1);
11186
11187 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11188 case FLASH_5717VENDOR_ATMEL_EEPROM:
11189 case FLASH_5717VENDOR_MICRO_EEPROM:
11190 tp->nvram_jedecnum = JEDEC_ATMEL;
11191 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11192 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11193
11194 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11195 tw32(NVRAM_CFG1, nvcfg1);
11196 return;
11197 case FLASH_5717VENDOR_ATMEL_MDB011D:
11198 case FLASH_5717VENDOR_ATMEL_ADB011B:
11199 case FLASH_5717VENDOR_ATMEL_ADB011D:
11200 case FLASH_5717VENDOR_ATMEL_MDB021D:
11201 case FLASH_5717VENDOR_ATMEL_ADB021B:
11202 case FLASH_5717VENDOR_ATMEL_ADB021D:
11203 case FLASH_5717VENDOR_ATMEL_45USPT:
11204 tp->nvram_jedecnum = JEDEC_ATMEL;
11205 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11206 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11207
11208 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11209 case FLASH_5717VENDOR_ATMEL_MDB021D:
11210 case FLASH_5717VENDOR_ATMEL_ADB021B:
11211 case FLASH_5717VENDOR_ATMEL_ADB021D:
11212 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11213 break;
11214 default:
11215 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11216 break;
11217 }
11218 break;
11219 case FLASH_5717VENDOR_ST_M_M25PE10:
11220 case FLASH_5717VENDOR_ST_A_M25PE10:
11221 case FLASH_5717VENDOR_ST_M_M45PE10:
11222 case FLASH_5717VENDOR_ST_A_M45PE10:
11223 case FLASH_5717VENDOR_ST_M_M25PE20:
11224 case FLASH_5717VENDOR_ST_A_M25PE20:
11225 case FLASH_5717VENDOR_ST_M_M45PE20:
11226 case FLASH_5717VENDOR_ST_A_M45PE20:
11227 case FLASH_5717VENDOR_ST_25USPT:
11228 case FLASH_5717VENDOR_ST_45USPT:
11229 tp->nvram_jedecnum = JEDEC_ST;
11230 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11231 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11232
11233 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11234 case FLASH_5717VENDOR_ST_M_M25PE20:
11235 case FLASH_5717VENDOR_ST_A_M25PE20:
11236 case FLASH_5717VENDOR_ST_M_M45PE20:
11237 case FLASH_5717VENDOR_ST_A_M45PE20:
11238 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11239 break;
11240 default:
11241 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11242 break;
11243 }
11244 break;
11245 default:
11246 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11247 return;
11248 }
11249
11250 tg3_nvram_get_pagesize(tp, nvcfg1);
11251 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11252 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11253 }
11254
11255 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11256 static void __devinit tg3_nvram_init(struct tg3 *tp)
11257 {
11258 tw32_f(GRC_EEPROM_ADDR,
11259 (EEPROM_ADDR_FSM_RESET |
11260 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11261 EEPROM_ADDR_CLKPERD_SHIFT)));
11262
11263 msleep(1);
11264
11265 /* Enable seeprom accesses. */
11266 tw32_f(GRC_LOCAL_CTRL,
11267 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11268 udelay(100);
11269
11270 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11271 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11272 tp->tg3_flags |= TG3_FLAG_NVRAM;
11273
11274 if (tg3_nvram_lock(tp)) {
11275 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11276 "tg3_nvram_init failed.\n", tp->dev->name);
11277 return;
11278 }
11279 tg3_enable_nvram_access(tp);
11280
11281 tp->nvram_size = 0;
11282
11283 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11284 tg3_get_5752_nvram_info(tp);
11285 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11286 tg3_get_5755_nvram_info(tp);
11287 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11288 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11289 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11290 tg3_get_5787_nvram_info(tp);
11291 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11292 tg3_get_5761_nvram_info(tp);
11293 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11294 tg3_get_5906_nvram_info(tp);
11295 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11296 tg3_get_57780_nvram_info(tp);
11297 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11298 tg3_get_5717_nvram_info(tp);
11299 else
11300 tg3_get_nvram_info(tp);
11301
11302 if (tp->nvram_size == 0)
11303 tg3_get_nvram_size(tp);
11304
11305 tg3_disable_nvram_access(tp);
11306 tg3_nvram_unlock(tp);
11307
11308 } else {
11309 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11310
11311 tg3_get_eeprom_size(tp);
11312 }
11313 }
11314
11315 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11316 u32 offset, u32 len, u8 *buf)
11317 {
11318 int i, j, rc = 0;
11319 u32 val;
11320
11321 for (i = 0; i < len; i += 4) {
11322 u32 addr;
11323 __be32 data;
11324
11325 addr = offset + i;
11326
11327 memcpy(&data, buf + i, 4);
11328
11329 /*
11330 * The SEEPROM interface expects the data to always be opposite
11331 * the native endian format. We accomplish this by reversing
11332 * all the operations that would have been performed on the
11333 * data from a call to tg3_nvram_read_be32().
11334 */
11335 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11336
11337 val = tr32(GRC_EEPROM_ADDR);
11338 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11339
11340 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11341 EEPROM_ADDR_READ);
11342 tw32(GRC_EEPROM_ADDR, val |
11343 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11344 (addr & EEPROM_ADDR_ADDR_MASK) |
11345 EEPROM_ADDR_START |
11346 EEPROM_ADDR_WRITE);
11347
11348 for (j = 0; j < 1000; j++) {
11349 val = tr32(GRC_EEPROM_ADDR);
11350
11351 if (val & EEPROM_ADDR_COMPLETE)
11352 break;
11353 msleep(1);
11354 }
11355 if (!(val & EEPROM_ADDR_COMPLETE)) {
11356 rc = -EBUSY;
11357 break;
11358 }
11359 }
11360
11361 return rc;
11362 }
11363
11364 /* offset and length are dword aligned */
11365 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11366 u8 *buf)
11367 {
11368 int ret = 0;
11369 u32 pagesize = tp->nvram_pagesize;
11370 u32 pagemask = pagesize - 1;
11371 u32 nvram_cmd;
11372 u8 *tmp;
11373
11374 tmp = kmalloc(pagesize, GFP_KERNEL);
11375 if (tmp == NULL)
11376 return -ENOMEM;
11377
11378 while (len) {
11379 int j;
11380 u32 phy_addr, page_off, size;
11381
11382 phy_addr = offset & ~pagemask;
11383
11384 for (j = 0; j < pagesize; j += 4) {
11385 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11386 (__be32 *) (tmp + j));
11387 if (ret)
11388 break;
11389 }
11390 if (ret)
11391 break;
11392
11393 page_off = offset & pagemask;
11394 size = pagesize;
11395 if (len < size)
11396 size = len;
11397
11398 len -= size;
11399
11400 memcpy(tmp + page_off, buf, size);
11401
11402 offset = offset + (pagesize - page_off);
11403
11404 tg3_enable_nvram_access(tp);
11405
11406 /*
11407 * Before we can erase the flash page, we need
11408 * to issue a special "write enable" command.
11409 */
11410 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11411
11412 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11413 break;
11414
11415 /* Erase the target page */
11416 tw32(NVRAM_ADDR, phy_addr);
11417
11418 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11419 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11420
11421 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11422 break;
11423
11424 /* Issue another write enable to start the write. */
11425 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11426
11427 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11428 break;
11429
11430 for (j = 0; j < pagesize; j += 4) {
11431 __be32 data;
11432
11433 data = *((__be32 *) (tmp + j));
11434
11435 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11436
11437 tw32(NVRAM_ADDR, phy_addr + j);
11438
11439 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11440 NVRAM_CMD_WR;
11441
11442 if (j == 0)
11443 nvram_cmd |= NVRAM_CMD_FIRST;
11444 else if (j == (pagesize - 4))
11445 nvram_cmd |= NVRAM_CMD_LAST;
11446
11447 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11448 break;
11449 }
11450 if (ret)
11451 break;
11452 }
11453
11454 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11455 tg3_nvram_exec_cmd(tp, nvram_cmd);
11456
11457 kfree(tmp);
11458
11459 return ret;
11460 }
11461
11462 /* offset and length are dword aligned */
11463 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11464 u8 *buf)
11465 {
11466 int i, ret = 0;
11467
11468 for (i = 0; i < len; i += 4, offset += 4) {
11469 u32 page_off, phy_addr, nvram_cmd;
11470 __be32 data;
11471
11472 memcpy(&data, buf + i, 4);
11473 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11474
11475 page_off = offset % tp->nvram_pagesize;
11476
11477 phy_addr = tg3_nvram_phys_addr(tp, offset);
11478
11479 tw32(NVRAM_ADDR, phy_addr);
11480
11481 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11482
11483 if ((page_off == 0) || (i == 0))
11484 nvram_cmd |= NVRAM_CMD_FIRST;
11485 if (page_off == (tp->nvram_pagesize - 4))
11486 nvram_cmd |= NVRAM_CMD_LAST;
11487
11488 if (i == (len - 4))
11489 nvram_cmd |= NVRAM_CMD_LAST;
11490
11491 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11492 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11493 (tp->nvram_jedecnum == JEDEC_ST) &&
11494 (nvram_cmd & NVRAM_CMD_FIRST)) {
11495
11496 if ((ret = tg3_nvram_exec_cmd(tp,
11497 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11498 NVRAM_CMD_DONE)))
11499
11500 break;
11501 }
11502 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11503 /* We always do complete word writes to eeprom. */
11504 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11505 }
11506
11507 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11508 break;
11509 }
11510 return ret;
11511 }
11512
11513 /* offset and length are dword aligned */
11514 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11515 {
11516 int ret;
11517
11518 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11519 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11520 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11521 udelay(40);
11522 }
11523
11524 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11525 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11526 }
11527 else {
11528 u32 grc_mode;
11529
11530 ret = tg3_nvram_lock(tp);
11531 if (ret)
11532 return ret;
11533
11534 tg3_enable_nvram_access(tp);
11535 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11536 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11537 tw32(NVRAM_WRITE1, 0x406);
11538
11539 grc_mode = tr32(GRC_MODE);
11540 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11541
11542 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11543 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11544
11545 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11546 buf);
11547 }
11548 else {
11549 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11550 buf);
11551 }
11552
11553 grc_mode = tr32(GRC_MODE);
11554 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11555
11556 tg3_disable_nvram_access(tp);
11557 tg3_nvram_unlock(tp);
11558 }
11559
11560 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11561 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11562 udelay(40);
11563 }
11564
11565 return ret;
11566 }
11567
11568 struct subsys_tbl_ent {
11569 u16 subsys_vendor, subsys_devid;
11570 u32 phy_id;
11571 };
11572
11573 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11574 /* Broadcom boards. */
11575 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11576 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11577 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11578 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
11579 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11580 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11581 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
11582 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11583 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11584 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11585 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11586
11587 /* 3com boards. */
11588 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11589 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11590 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
11591 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11592 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11593
11594 /* DELL boards. */
11595 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11596 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11597 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11598 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11599
11600 /* Compaq boards. */
11601 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11602 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11603 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
11604 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11605 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11606
11607 /* IBM boards. */
11608 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11609 };
11610
11611 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11612 {
11613 int i;
11614
11615 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11616 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11617 tp->pdev->subsystem_vendor) &&
11618 (subsys_id_to_phy_id[i].subsys_devid ==
11619 tp->pdev->subsystem_device))
11620 return &subsys_id_to_phy_id[i];
11621 }
11622 return NULL;
11623 }
11624
11625 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11626 {
11627 u32 val;
11628 u16 pmcsr;
11629
11630 /* On some early chips the SRAM cannot be accessed in D3hot state,
11631 * so need make sure we're in D0.
11632 */
11633 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11634 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11635 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11636 msleep(1);
11637
11638 /* Make sure register accesses (indirect or otherwise)
11639 * will function correctly.
11640 */
11641 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11642 tp->misc_host_ctrl);
11643
11644 /* The memory arbiter has to be enabled in order for SRAM accesses
11645 * to succeed. Normally on powerup the tg3 chip firmware will make
11646 * sure it is enabled, but other entities such as system netboot
11647 * code might disable it.
11648 */
11649 val = tr32(MEMARB_MODE);
11650 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11651
11652 tp->phy_id = PHY_ID_INVALID;
11653 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11654
11655 /* Assume an onboard device and WOL capable by default. */
11656 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11657
11658 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11659 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11660 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11661 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11662 }
11663 val = tr32(VCPU_CFGSHDW);
11664 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11665 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11666 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11667 (val & VCPU_CFGSHDW_WOL_MAGPKT))
11668 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11669 goto done;
11670 }
11671
11672 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11673 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11674 u32 nic_cfg, led_cfg;
11675 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11676 int eeprom_phy_serdes = 0;
11677
11678 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11679 tp->nic_sram_data_cfg = nic_cfg;
11680
11681 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11682 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11683 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11684 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11685 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11686 (ver > 0) && (ver < 0x100))
11687 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11688
11689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11690 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11691
11692 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11693 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11694 eeprom_phy_serdes = 1;
11695
11696 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11697 if (nic_phy_id != 0) {
11698 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11699 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11700
11701 eeprom_phy_id = (id1 >> 16) << 10;
11702 eeprom_phy_id |= (id2 & 0xfc00) << 16;
11703 eeprom_phy_id |= (id2 & 0x03ff) << 0;
11704 } else
11705 eeprom_phy_id = 0;
11706
11707 tp->phy_id = eeprom_phy_id;
11708 if (eeprom_phy_serdes) {
11709 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11710 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11711 else
11712 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11713 }
11714
11715 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11716 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11717 SHASTA_EXT_LED_MODE_MASK);
11718 else
11719 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11720
11721 switch (led_cfg) {
11722 default:
11723 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11724 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11725 break;
11726
11727 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11728 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11729 break;
11730
11731 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11732 tp->led_ctrl = LED_CTRL_MODE_MAC;
11733
11734 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11735 * read on some older 5700/5701 bootcode.
11736 */
11737 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11738 ASIC_REV_5700 ||
11739 GET_ASIC_REV(tp->pci_chip_rev_id) ==
11740 ASIC_REV_5701)
11741 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11742
11743 break;
11744
11745 case SHASTA_EXT_LED_SHARED:
11746 tp->led_ctrl = LED_CTRL_MODE_SHARED;
11747 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11748 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11749 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11750 LED_CTRL_MODE_PHY_2);
11751 break;
11752
11753 case SHASTA_EXT_LED_MAC:
11754 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11755 break;
11756
11757 case SHASTA_EXT_LED_COMBO:
11758 tp->led_ctrl = LED_CTRL_MODE_COMBO;
11759 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11760 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11761 LED_CTRL_MODE_PHY_2);
11762 break;
11763
11764 }
11765
11766 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11767 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11768 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11769 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11770
11771 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11772 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11773
11774 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11775 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11776 if ((tp->pdev->subsystem_vendor ==
11777 PCI_VENDOR_ID_ARIMA) &&
11778 (tp->pdev->subsystem_device == 0x205a ||
11779 tp->pdev->subsystem_device == 0x2063))
11780 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11781 } else {
11782 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11783 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11784 }
11785
11786 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11787 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11788 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11789 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11790 }
11791
11792 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11793 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11794 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11795
11796 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11797 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11798 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11799
11800 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11801 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11802 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11803
11804 if (cfg2 & (1 << 17))
11805 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11806
11807 /* serdes signal pre-emphasis in register 0x590 set by */
11808 /* bootcode if bit 18 is set */
11809 if (cfg2 & (1 << 18))
11810 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11811
11812 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11813 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11814 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11815 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11816
11817 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11818 u32 cfg3;
11819
11820 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11821 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11822 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11823 }
11824
11825 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11826 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11827 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11828 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11829 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11830 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11831 }
11832 done:
11833 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11834 device_set_wakeup_enable(&tp->pdev->dev,
11835 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11836 }
11837
11838 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11839 {
11840 int i;
11841 u32 val;
11842
11843 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11844 tw32(OTP_CTRL, cmd);
11845
11846 /* Wait for up to 1 ms for command to execute. */
11847 for (i = 0; i < 100; i++) {
11848 val = tr32(OTP_STATUS);
11849 if (val & OTP_STATUS_CMD_DONE)
11850 break;
11851 udelay(10);
11852 }
11853
11854 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11855 }
11856
11857 /* Read the gphy configuration from the OTP region of the chip. The gphy
11858 * configuration is a 32-bit value that straddles the alignment boundary.
11859 * We do two 32-bit reads and then shift and merge the results.
11860 */
11861 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11862 {
11863 u32 bhalf_otp, thalf_otp;
11864
11865 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11866
11867 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11868 return 0;
11869
11870 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11871
11872 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11873 return 0;
11874
11875 thalf_otp = tr32(OTP_READ_DATA);
11876
11877 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11878
11879 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11880 return 0;
11881
11882 bhalf_otp = tr32(OTP_READ_DATA);
11883
11884 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11885 }
11886
11887 static int __devinit tg3_phy_probe(struct tg3 *tp)
11888 {
11889 u32 hw_phy_id_1, hw_phy_id_2;
11890 u32 hw_phy_id, hw_phy_id_masked;
11891 int err;
11892
11893 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11894 return tg3_phy_init(tp);
11895
11896 /* Reading the PHY ID register can conflict with ASF
11897 * firmware access to the PHY hardware.
11898 */
11899 err = 0;
11900 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11901 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11902 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11903 } else {
11904 /* Now read the physical PHY_ID from the chip and verify
11905 * that it is sane. If it doesn't look good, we fall back
11906 * to either the hard-coded table based PHY_ID and failing
11907 * that the value found in the eeprom area.
11908 */
11909 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11910 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11911
11912 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11913 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11914 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11915
11916 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11917 }
11918
11919 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11920 tp->phy_id = hw_phy_id;
11921 if (hw_phy_id_masked == PHY_ID_BCM8002)
11922 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11923 else
11924 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11925 } else {
11926 if (tp->phy_id != PHY_ID_INVALID) {
11927 /* Do nothing, phy ID already set up in
11928 * tg3_get_eeprom_hw_cfg().
11929 */
11930 } else {
11931 struct subsys_tbl_ent *p;
11932
11933 /* No eeprom signature? Try the hardcoded
11934 * subsys device table.
11935 */
11936 p = lookup_by_subsys(tp);
11937 if (!p)
11938 return -ENODEV;
11939
11940 tp->phy_id = p->phy_id;
11941 if (!tp->phy_id ||
11942 tp->phy_id == PHY_ID_BCM8002)
11943 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11944 }
11945 }
11946
11947 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11948 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11949 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11950 u32 bmsr, adv_reg, tg3_ctrl, mask;
11951
11952 tg3_readphy(tp, MII_BMSR, &bmsr);
11953 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11954 (bmsr & BMSR_LSTATUS))
11955 goto skip_phy_reset;
11956
11957 err = tg3_phy_reset(tp);
11958 if (err)
11959 return err;
11960
11961 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11962 ADVERTISE_100HALF | ADVERTISE_100FULL |
11963 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11964 tg3_ctrl = 0;
11965 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11966 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11967 MII_TG3_CTRL_ADV_1000_FULL);
11968 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11969 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11970 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11971 MII_TG3_CTRL_ENABLE_AS_MASTER);
11972 }
11973
11974 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11975 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11976 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11977 if (!tg3_copper_is_advertising_all(tp, mask)) {
11978 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11979
11980 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11981 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11982
11983 tg3_writephy(tp, MII_BMCR,
11984 BMCR_ANENABLE | BMCR_ANRESTART);
11985 }
11986 tg3_phy_set_wirespeed(tp);
11987
11988 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11989 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11990 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11991 }
11992
11993 skip_phy_reset:
11994 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11995 err = tg3_init_5401phy_dsp(tp);
11996 if (err)
11997 return err;
11998 }
11999
12000 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12001 err = tg3_init_5401phy_dsp(tp);
12002 }
12003
12004 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12005 tp->link_config.advertising =
12006 (ADVERTISED_1000baseT_Half |
12007 ADVERTISED_1000baseT_Full |
12008 ADVERTISED_Autoneg |
12009 ADVERTISED_FIBRE);
12010 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12011 tp->link_config.advertising &=
12012 ~(ADVERTISED_1000baseT_Half |
12013 ADVERTISED_1000baseT_Full);
12014
12015 return err;
12016 }
12017
12018 static void __devinit tg3_read_partno(struct tg3 *tp)
12019 {
12020 unsigned char vpd_data[256]; /* in little-endian format */
12021 unsigned int i;
12022 u32 magic;
12023
12024 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12025 tg3_nvram_read(tp, 0x0, &magic))
12026 goto out_not_found;
12027
12028 if (magic == TG3_EEPROM_MAGIC) {
12029 for (i = 0; i < 256; i += 4) {
12030 u32 tmp;
12031
12032 /* The data is in little-endian format in NVRAM.
12033 * Use the big-endian read routines to preserve
12034 * the byte order as it exists in NVRAM.
12035 */
12036 if (tg3_nvram_read_be32(tp, 0x100 + i, &tmp))
12037 goto out_not_found;
12038
12039 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12040 }
12041 } else {
12042 int vpd_cap;
12043
12044 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
12045 for (i = 0; i < 256; i += 4) {
12046 u32 tmp, j = 0;
12047 __le32 v;
12048 u16 tmp16;
12049
12050 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
12051 i);
12052 while (j++ < 100) {
12053 pci_read_config_word(tp->pdev, vpd_cap +
12054 PCI_VPD_ADDR, &tmp16);
12055 if (tmp16 & 0x8000)
12056 break;
12057 msleep(1);
12058 }
12059 if (!(tmp16 & 0x8000))
12060 goto out_not_found;
12061
12062 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
12063 &tmp);
12064 v = cpu_to_le32(tmp);
12065 memcpy(&vpd_data[i], &v, sizeof(v));
12066 }
12067 }
12068
12069 /* Now parse and find the part number. */
12070 for (i = 0; i < 254; ) {
12071 unsigned char val = vpd_data[i];
12072 unsigned int block_end;
12073
12074 if (val == 0x82 || val == 0x91) {
12075 i = (i + 3 +
12076 (vpd_data[i + 1] +
12077 (vpd_data[i + 2] << 8)));
12078 continue;
12079 }
12080
12081 if (val != 0x90)
12082 goto out_not_found;
12083
12084 block_end = (i + 3 +
12085 (vpd_data[i + 1] +
12086 (vpd_data[i + 2] << 8)));
12087 i += 3;
12088
12089 if (block_end > 256)
12090 goto out_not_found;
12091
12092 while (i < (block_end - 2)) {
12093 if (vpd_data[i + 0] == 'P' &&
12094 vpd_data[i + 1] == 'N') {
12095 int partno_len = vpd_data[i + 2];
12096
12097 i += 3;
12098 if (partno_len > 24 || (partno_len + i) > 256)
12099 goto out_not_found;
12100
12101 memcpy(tp->board_part_number,
12102 &vpd_data[i], partno_len);
12103
12104 /* Success. */
12105 return;
12106 }
12107 i += 3 + vpd_data[i + 2];
12108 }
12109
12110 /* Part number not found. */
12111 goto out_not_found;
12112 }
12113
12114 out_not_found:
12115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12116 strcpy(tp->board_part_number, "BCM95906");
12117 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12118 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12119 strcpy(tp->board_part_number, "BCM57780");
12120 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12121 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12122 strcpy(tp->board_part_number, "BCM57760");
12123 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12124 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12125 strcpy(tp->board_part_number, "BCM57790");
12126 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12127 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12128 strcpy(tp->board_part_number, "BCM57788");
12129 else
12130 strcpy(tp->board_part_number, "none");
12131 }
12132
12133 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12134 {
12135 u32 val;
12136
12137 if (tg3_nvram_read(tp, offset, &val) ||
12138 (val & 0xfc000000) != 0x0c000000 ||
12139 tg3_nvram_read(tp, offset + 4, &val) ||
12140 val != 0)
12141 return 0;
12142
12143 return 1;
12144 }
12145
12146 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12147 {
12148 u32 val, offset, start, ver_offset;
12149 int i;
12150 bool newver = false;
12151
12152 if (tg3_nvram_read(tp, 0xc, &offset) ||
12153 tg3_nvram_read(tp, 0x4, &start))
12154 return;
12155
12156 offset = tg3_nvram_logical_addr(tp, offset);
12157
12158 if (tg3_nvram_read(tp, offset, &val))
12159 return;
12160
12161 if ((val & 0xfc000000) == 0x0c000000) {
12162 if (tg3_nvram_read(tp, offset + 4, &val))
12163 return;
12164
12165 if (val == 0)
12166 newver = true;
12167 }
12168
12169 if (newver) {
12170 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12171 return;
12172
12173 offset = offset + ver_offset - start;
12174 for (i = 0; i < 16; i += 4) {
12175 __be32 v;
12176 if (tg3_nvram_read_be32(tp, offset + i, &v))
12177 return;
12178
12179 memcpy(tp->fw_ver + i, &v, sizeof(v));
12180 }
12181 } else {
12182 u32 major, minor;
12183
12184 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12185 return;
12186
12187 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12188 TG3_NVM_BCVER_MAJSFT;
12189 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12190 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12191 }
12192 }
12193
12194 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12195 {
12196 u32 val, major, minor;
12197
12198 /* Use native endian representation */
12199 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12200 return;
12201
12202 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12203 TG3_NVM_HWSB_CFG1_MAJSFT;
12204 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12205 TG3_NVM_HWSB_CFG1_MINSFT;
12206
12207 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12208 }
12209
12210 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12211 {
12212 u32 offset, major, minor, build;
12213
12214 tp->fw_ver[0] = 's';
12215 tp->fw_ver[1] = 'b';
12216 tp->fw_ver[2] = '\0';
12217
12218 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12219 return;
12220
12221 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12222 case TG3_EEPROM_SB_REVISION_0:
12223 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12224 break;
12225 case TG3_EEPROM_SB_REVISION_2:
12226 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12227 break;
12228 case TG3_EEPROM_SB_REVISION_3:
12229 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12230 break;
12231 default:
12232 return;
12233 }
12234
12235 if (tg3_nvram_read(tp, offset, &val))
12236 return;
12237
12238 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12239 TG3_EEPROM_SB_EDH_BLD_SHFT;
12240 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12241 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12242 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12243
12244 if (minor > 99 || build > 26)
12245 return;
12246
12247 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12248
12249 if (build > 0) {
12250 tp->fw_ver[8] = 'a' + build - 1;
12251 tp->fw_ver[9] = '\0';
12252 }
12253 }
12254
12255 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12256 {
12257 u32 val, offset, start;
12258 int i, vlen;
12259
12260 for (offset = TG3_NVM_DIR_START;
12261 offset < TG3_NVM_DIR_END;
12262 offset += TG3_NVM_DIRENT_SIZE) {
12263 if (tg3_nvram_read(tp, offset, &val))
12264 return;
12265
12266 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12267 break;
12268 }
12269
12270 if (offset == TG3_NVM_DIR_END)
12271 return;
12272
12273 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12274 start = 0x08000000;
12275 else if (tg3_nvram_read(tp, offset - 4, &start))
12276 return;
12277
12278 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12279 !tg3_fw_img_is_valid(tp, offset) ||
12280 tg3_nvram_read(tp, offset + 8, &val))
12281 return;
12282
12283 offset += val - start;
12284
12285 vlen = strlen(tp->fw_ver);
12286
12287 tp->fw_ver[vlen++] = ',';
12288 tp->fw_ver[vlen++] = ' ';
12289
12290 for (i = 0; i < 4; i++) {
12291 __be32 v;
12292 if (tg3_nvram_read_be32(tp, offset, &v))
12293 return;
12294
12295 offset += sizeof(v);
12296
12297 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12298 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12299 break;
12300 }
12301
12302 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12303 vlen += sizeof(v);
12304 }
12305 }
12306
12307 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12308 {
12309 int vlen;
12310 u32 apedata;
12311
12312 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12313 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12314 return;
12315
12316 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12317 if (apedata != APE_SEG_SIG_MAGIC)
12318 return;
12319
12320 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12321 if (!(apedata & APE_FW_STATUS_READY))
12322 return;
12323
12324 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12325
12326 vlen = strlen(tp->fw_ver);
12327
12328 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12329 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12330 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12331 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12332 (apedata & APE_FW_VERSION_BLDMSK));
12333 }
12334
12335 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12336 {
12337 u32 val;
12338
12339 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12340 tp->fw_ver[0] = 's';
12341 tp->fw_ver[1] = 'b';
12342 tp->fw_ver[2] = '\0';
12343
12344 return;
12345 }
12346
12347 if (tg3_nvram_read(tp, 0, &val))
12348 return;
12349
12350 if (val == TG3_EEPROM_MAGIC)
12351 tg3_read_bc_ver(tp);
12352 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12353 tg3_read_sb_ver(tp, val);
12354 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12355 tg3_read_hwsb_ver(tp);
12356 else
12357 return;
12358
12359 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12360 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12361 return;
12362
12363 tg3_read_mgmtfw_ver(tp);
12364
12365 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12366 }
12367
12368 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12369
12370 static int __devinit tg3_get_invariants(struct tg3 *tp)
12371 {
12372 static struct pci_device_id write_reorder_chipsets[] = {
12373 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12374 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12375 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12376 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12377 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12378 PCI_DEVICE_ID_VIA_8385_0) },
12379 { },
12380 };
12381 u32 misc_ctrl_reg;
12382 u32 pci_state_reg, grc_misc_cfg;
12383 u32 val;
12384 u16 pci_cmd;
12385 int err;
12386
12387 /* Force memory write invalidate off. If we leave it on,
12388 * then on 5700_BX chips we have to enable a workaround.
12389 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12390 * to match the cacheline size. The Broadcom driver have this
12391 * workaround but turns MWI off all the times so never uses
12392 * it. This seems to suggest that the workaround is insufficient.
12393 */
12394 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12395 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12396 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12397
12398 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12399 * has the register indirect write enable bit set before
12400 * we try to access any of the MMIO registers. It is also
12401 * critical that the PCI-X hw workaround situation is decided
12402 * before that as well.
12403 */
12404 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12405 &misc_ctrl_reg);
12406
12407 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12408 MISC_HOST_CTRL_CHIPREV_SHIFT);
12409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12410 u32 prod_id_asic_rev;
12411
12412 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
12413 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
12414 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
12415 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
12416 pci_read_config_dword(tp->pdev,
12417 TG3PCI_GEN2_PRODID_ASICREV,
12418 &prod_id_asic_rev);
12419 else
12420 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12421 &prod_id_asic_rev);
12422
12423 tp->pci_chip_rev_id = prod_id_asic_rev;
12424 }
12425
12426 /* Wrong chip ID in 5752 A0. This code can be removed later
12427 * as A0 is not in production.
12428 */
12429 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12430 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12431
12432 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12433 * we need to disable memory and use config. cycles
12434 * only to access all registers. The 5702/03 chips
12435 * can mistakenly decode the special cycles from the
12436 * ICH chipsets as memory write cycles, causing corruption
12437 * of register and memory space. Only certain ICH bridges
12438 * will drive special cycles with non-zero data during the
12439 * address phase which can fall within the 5703's address
12440 * range. This is not an ICH bug as the PCI spec allows
12441 * non-zero address during special cycles. However, only
12442 * these ICH bridges are known to drive non-zero addresses
12443 * during special cycles.
12444 *
12445 * Since special cycles do not cross PCI bridges, we only
12446 * enable this workaround if the 5703 is on the secondary
12447 * bus of these ICH bridges.
12448 */
12449 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12450 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12451 static struct tg3_dev_id {
12452 u32 vendor;
12453 u32 device;
12454 u32 rev;
12455 } ich_chipsets[] = {
12456 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12457 PCI_ANY_ID },
12458 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12459 PCI_ANY_ID },
12460 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12461 0xa },
12462 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12463 PCI_ANY_ID },
12464 { },
12465 };
12466 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12467 struct pci_dev *bridge = NULL;
12468
12469 while (pci_id->vendor != 0) {
12470 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12471 bridge);
12472 if (!bridge) {
12473 pci_id++;
12474 continue;
12475 }
12476 if (pci_id->rev != PCI_ANY_ID) {
12477 if (bridge->revision > pci_id->rev)
12478 continue;
12479 }
12480 if (bridge->subordinate &&
12481 (bridge->subordinate->number ==
12482 tp->pdev->bus->number)) {
12483
12484 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12485 pci_dev_put(bridge);
12486 break;
12487 }
12488 }
12489 }
12490
12491 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12492 static struct tg3_dev_id {
12493 u32 vendor;
12494 u32 device;
12495 } bridge_chipsets[] = {
12496 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12497 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12498 { },
12499 };
12500 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12501 struct pci_dev *bridge = NULL;
12502
12503 while (pci_id->vendor != 0) {
12504 bridge = pci_get_device(pci_id->vendor,
12505 pci_id->device,
12506 bridge);
12507 if (!bridge) {
12508 pci_id++;
12509 continue;
12510 }
12511 if (bridge->subordinate &&
12512 (bridge->subordinate->number <=
12513 tp->pdev->bus->number) &&
12514 (bridge->subordinate->subordinate >=
12515 tp->pdev->bus->number)) {
12516 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12517 pci_dev_put(bridge);
12518 break;
12519 }
12520 }
12521 }
12522
12523 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12524 * DMA addresses > 40-bit. This bridge may have other additional
12525 * 57xx devices behind it in some 4-port NIC designs for example.
12526 * Any tg3 device found behind the bridge will also need the 40-bit
12527 * DMA workaround.
12528 */
12529 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12530 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12531 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12532 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12533 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12534 }
12535 else {
12536 struct pci_dev *bridge = NULL;
12537
12538 do {
12539 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12540 PCI_DEVICE_ID_SERVERWORKS_EPB,
12541 bridge);
12542 if (bridge && bridge->subordinate &&
12543 (bridge->subordinate->number <=
12544 tp->pdev->bus->number) &&
12545 (bridge->subordinate->subordinate >=
12546 tp->pdev->bus->number)) {
12547 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12548 pci_dev_put(bridge);
12549 break;
12550 }
12551 } while (bridge);
12552 }
12553
12554 /* Initialize misc host control in PCI block. */
12555 tp->misc_host_ctrl |= (misc_ctrl_reg &
12556 MISC_HOST_CTRL_CHIPREV);
12557 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12558 tp->misc_host_ctrl);
12559
12560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12561 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12562 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12563 tp->pdev_peer = tg3_find_peer(tp);
12564
12565 /* Intentionally exclude ASIC_REV_5906 */
12566 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12567 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12568 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12569 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12570 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12571 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12573 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12574
12575 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12576 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12577 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12578 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12579 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12580 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12581
12582 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12583 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12584 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12585
12586 /* 5700 B0 chips do not support checksumming correctly due
12587 * to hardware bugs.
12588 */
12589 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12590 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12591 else {
12592 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12593 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12594 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12595 tp->dev->features |= NETIF_F_IPV6_CSUM;
12596 }
12597
12598 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12599 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12600 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12601 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12602 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12603 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12604 tp->pdev_peer == tp->pdev))
12605 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12606
12607 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12608 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12609 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12610 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12611 } else {
12612 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12613 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12614 ASIC_REV_5750 &&
12615 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12616 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12617 }
12618 }
12619
12620 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12621 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
12622
12623 tp->irq_max = 1;
12624
12625 #ifdef TG3_NAPI
12626 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12627 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
12628 tp->irq_max = TG3_IRQ_MAX_VECS;
12629 }
12630 #endif
12631
12632 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12633 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12634 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12635 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
12636
12637 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12638 &pci_state_reg);
12639
12640 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12641 if (tp->pcie_cap != 0) {
12642 u16 lnkctl;
12643
12644 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12645
12646 pcie_set_readrq(tp->pdev, 4096);
12647
12648 pci_read_config_word(tp->pdev,
12649 tp->pcie_cap + PCI_EXP_LNKCTL,
12650 &lnkctl);
12651 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
12652 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12653 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12654 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12655 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12656 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
12657 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
12658 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
12659 }
12660 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12661 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12662 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12663 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12664 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12665 if (!tp->pcix_cap) {
12666 printk(KERN_ERR PFX "Cannot find PCI-X "
12667 "capability, aborting.\n");
12668 return -EIO;
12669 }
12670
12671 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
12672 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12673 }
12674
12675 /* If we have an AMD 762 or VIA K8T800 chipset, write
12676 * reordering to the mailbox registers done by the host
12677 * controller can cause major troubles. We read back from
12678 * every mailbox register write to force the writes to be
12679 * posted to the chip in order.
12680 */
12681 if (pci_dev_present(write_reorder_chipsets) &&
12682 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12683 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12684
12685 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
12686 &tp->pci_cacheline_sz);
12687 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12688 &tp->pci_lat_timer);
12689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12690 tp->pci_lat_timer < 64) {
12691 tp->pci_lat_timer = 64;
12692 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
12693 tp->pci_lat_timer);
12694 }
12695
12696 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12697 /* 5700 BX chips need to have their TX producer index
12698 * mailboxes written twice to workaround a bug.
12699 */
12700 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12701
12702 /* If we are in PCI-X mode, enable register write workaround.
12703 *
12704 * The workaround is to use indirect register accesses
12705 * for all chip writes not to mailbox registers.
12706 */
12707 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12708 u32 pm_reg;
12709
12710 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12711
12712 /* The chip can have it's power management PCI config
12713 * space registers clobbered due to this bug.
12714 * So explicitly force the chip into D0 here.
12715 */
12716 pci_read_config_dword(tp->pdev,
12717 tp->pm_cap + PCI_PM_CTRL,
12718 &pm_reg);
12719 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12720 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12721 pci_write_config_dword(tp->pdev,
12722 tp->pm_cap + PCI_PM_CTRL,
12723 pm_reg);
12724
12725 /* Also, force SERR#/PERR# in PCI command. */
12726 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12727 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12728 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12729 }
12730 }
12731
12732 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12733 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12734 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12735 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12736
12737 /* Chip-specific fixup from Broadcom driver */
12738 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12739 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12740 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12741 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12742 }
12743
12744 /* Default fast path register access methods */
12745 tp->read32 = tg3_read32;
12746 tp->write32 = tg3_write32;
12747 tp->read32_mbox = tg3_read32;
12748 tp->write32_mbox = tg3_write32;
12749 tp->write32_tx_mbox = tg3_write32;
12750 tp->write32_rx_mbox = tg3_write32;
12751
12752 /* Various workaround register access methods */
12753 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12754 tp->write32 = tg3_write_indirect_reg32;
12755 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12756 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12757 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12758 /*
12759 * Back to back register writes can cause problems on these
12760 * chips, the workaround is to read back all reg writes
12761 * except those to mailbox regs.
12762 *
12763 * See tg3_write_indirect_reg32().
12764 */
12765 tp->write32 = tg3_write_flush_reg32;
12766 }
12767
12768 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12769 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12770 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12771 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12772 tp->write32_rx_mbox = tg3_write_flush_reg32;
12773 }
12774
12775 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12776 tp->read32 = tg3_read_indirect_reg32;
12777 tp->write32 = tg3_write_indirect_reg32;
12778 tp->read32_mbox = tg3_read_indirect_mbox;
12779 tp->write32_mbox = tg3_write_indirect_mbox;
12780 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12781 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12782
12783 iounmap(tp->regs);
12784 tp->regs = NULL;
12785
12786 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12787 pci_cmd &= ~PCI_COMMAND_MEMORY;
12788 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12789 }
12790 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12791 tp->read32_mbox = tg3_read32_mbox_5906;
12792 tp->write32_mbox = tg3_write32_mbox_5906;
12793 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12794 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12795 }
12796
12797 if (tp->write32 == tg3_write_indirect_reg32 ||
12798 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12799 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12800 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12801 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12802
12803 /* Get eeprom hw config before calling tg3_set_power_state().
12804 * In particular, the TG3_FLG2_IS_NIC flag must be
12805 * determined before calling tg3_set_power_state() so that
12806 * we know whether or not to switch out of Vaux power.
12807 * When the flag is set, it means that GPIO1 is used for eeprom
12808 * write protect and also implies that it is a LOM where GPIOs
12809 * are not used to switch power.
12810 */
12811 tg3_get_eeprom_hw_cfg(tp);
12812
12813 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12814 /* Allow reads and writes to the
12815 * APE register and memory space.
12816 */
12817 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12818 PCISTATE_ALLOW_APE_SHMEM_WR;
12819 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12820 pci_state_reg);
12821 }
12822
12823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12824 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12825 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12826 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12827 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12828 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12829
12830 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12831 * GPIO1 driven high will bring 5700's external PHY out of reset.
12832 * It is also used as eeprom write protect on LOMs.
12833 */
12834 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12835 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12836 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12837 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12838 GRC_LCLCTRL_GPIO_OUTPUT1);
12839 /* Unused GPIO3 must be driven as output on 5752 because there
12840 * are no pull-up resistors on unused GPIO pins.
12841 */
12842 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12843 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12844
12845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12847 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12848
12849 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
12850 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
12851 /* Turn off the debug UART. */
12852 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12853 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12854 /* Keep VMain power. */
12855 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12856 GRC_LCLCTRL_GPIO_OUTPUT0;
12857 }
12858
12859 /* Force the chip into D0. */
12860 err = tg3_set_power_state(tp, PCI_D0);
12861 if (err) {
12862 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12863 pci_name(tp->pdev));
12864 return err;
12865 }
12866
12867 /* Derive initial jumbo mode from MTU assigned in
12868 * ether_setup() via the alloc_etherdev() call
12869 */
12870 if (tp->dev->mtu > ETH_DATA_LEN &&
12871 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12872 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12873
12874 /* Determine WakeOnLan speed to use. */
12875 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12876 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12877 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12878 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12879 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12880 } else {
12881 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12882 }
12883
12884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12885 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
12886
12887 /* A few boards don't want Ethernet@WireSpeed phy feature */
12888 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12889 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12890 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12891 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12892 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
12893 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12894 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12895
12896 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12897 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12898 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12899 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12900 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12901
12902 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12903 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
12904 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12905 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
12906 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
12907 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12909 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12910 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12911 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12912 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12913 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12914 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12915 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12916 } else
12917 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12918 }
12919
12920 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12921 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12922 tp->phy_otp = tg3_read_otp_phycfg(tp);
12923 if (tp->phy_otp == 0)
12924 tp->phy_otp = TG3_OTP_DEFAULT;
12925 }
12926
12927 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12928 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12929 else
12930 tp->mi_mode = MAC_MI_MODE_BASE;
12931
12932 tp->coalesce_mode = 0;
12933 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12934 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12935 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12936
12937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12939 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12940
12941 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12942 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12943 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12944 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12945
12946 err = tg3_mdio_init(tp);
12947 if (err)
12948 return err;
12949
12950 /* Initialize data/descriptor byte/word swapping. */
12951 val = tr32(GRC_MODE);
12952 val &= GRC_MODE_HOST_STACKUP;
12953 tw32(GRC_MODE, val | tp->grc_mode);
12954
12955 tg3_switch_clocks(tp);
12956
12957 /* Clear this out for sanity. */
12958 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12959
12960 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12961 &pci_state_reg);
12962 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12963 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12964 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12965
12966 if (chiprevid == CHIPREV_ID_5701_A0 ||
12967 chiprevid == CHIPREV_ID_5701_B0 ||
12968 chiprevid == CHIPREV_ID_5701_B2 ||
12969 chiprevid == CHIPREV_ID_5701_B5) {
12970 void __iomem *sram_base;
12971
12972 /* Write some dummy words into the SRAM status block
12973 * area, see if it reads back correctly. If the return
12974 * value is bad, force enable the PCIX workaround.
12975 */
12976 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12977
12978 writel(0x00000000, sram_base);
12979 writel(0x00000000, sram_base + 4);
12980 writel(0xffffffff, sram_base + 4);
12981 if (readl(sram_base) != 0x00000000)
12982 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12983 }
12984 }
12985
12986 udelay(50);
12987 tg3_nvram_init(tp);
12988
12989 grc_misc_cfg = tr32(GRC_MISC_CFG);
12990 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12991
12992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12993 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12994 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12995 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12996
12997 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12998 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12999 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13000 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13001 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13002 HOSTCC_MODE_CLRTICK_TXBD);
13003
13004 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13005 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13006 tp->misc_host_ctrl);
13007 }
13008
13009 /* Preserve the APE MAC_MODE bits */
13010 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13011 tp->mac_mode = tr32(MAC_MODE) |
13012 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13013 else
13014 tp->mac_mode = TG3_DEF_MAC_MODE;
13015
13016 /* these are limited to 10/100 only */
13017 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13018 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13019 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13020 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13021 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13022 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13023 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13024 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13025 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13026 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13027 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13028 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13029 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13030 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13031
13032 err = tg3_phy_probe(tp);
13033 if (err) {
13034 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13035 pci_name(tp->pdev), err);
13036 /* ... but do not return immediately ... */
13037 tg3_mdio_fini(tp);
13038 }
13039
13040 tg3_read_partno(tp);
13041 tg3_read_fw_ver(tp);
13042
13043 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13044 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13045 } else {
13046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13047 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13048 else
13049 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13050 }
13051
13052 /* 5700 {AX,BX} chips have a broken status block link
13053 * change bit implementation, so we must use the
13054 * status register in those cases.
13055 */
13056 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13057 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13058 else
13059 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13060
13061 /* The led_ctrl is set during tg3_phy_probe, here we might
13062 * have to force the link status polling mechanism based
13063 * upon subsystem IDs.
13064 */
13065 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13067 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13068 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13069 TG3_FLAG_USE_LINKCHG_REG);
13070 }
13071
13072 /* For all SERDES we poll the MAC status register. */
13073 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13074 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13075 else
13076 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13077
13078 tp->rx_offset = NET_IP_ALIGN;
13079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13080 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13081 tp->rx_offset = 0;
13082
13083 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13084
13085 /* Increment the rx prod index on the rx std ring by at most
13086 * 8 for these chips to workaround hw errata.
13087 */
13088 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13089 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13090 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13091 tp->rx_std_max_post = 8;
13092
13093 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13094 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13095 PCIE_PWR_MGMT_L1_THRESH_MSK;
13096
13097 return err;
13098 }
13099
13100 #ifdef CONFIG_SPARC
13101 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13102 {
13103 struct net_device *dev = tp->dev;
13104 struct pci_dev *pdev = tp->pdev;
13105 struct device_node *dp = pci_device_to_OF_node(pdev);
13106 const unsigned char *addr;
13107 int len;
13108
13109 addr = of_get_property(dp, "local-mac-address", &len);
13110 if (addr && len == 6) {
13111 memcpy(dev->dev_addr, addr, 6);
13112 memcpy(dev->perm_addr, dev->dev_addr, 6);
13113 return 0;
13114 }
13115 return -ENODEV;
13116 }
13117
13118 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13119 {
13120 struct net_device *dev = tp->dev;
13121
13122 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13123 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13124 return 0;
13125 }
13126 #endif
13127
13128 static int __devinit tg3_get_device_address(struct tg3 *tp)
13129 {
13130 struct net_device *dev = tp->dev;
13131 u32 hi, lo, mac_offset;
13132 int addr_ok = 0;
13133
13134 #ifdef CONFIG_SPARC
13135 if (!tg3_get_macaddr_sparc(tp))
13136 return 0;
13137 #endif
13138
13139 mac_offset = 0x7c;
13140 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13141 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13142 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13143 mac_offset = 0xcc;
13144 if (tg3_nvram_lock(tp))
13145 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13146 else
13147 tg3_nvram_unlock(tp);
13148 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13149 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13150 mac_offset = 0xcc;
13151 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13152 mac_offset = 0x10;
13153
13154 /* First try to get it from MAC address mailbox. */
13155 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13156 if ((hi >> 16) == 0x484b) {
13157 dev->dev_addr[0] = (hi >> 8) & 0xff;
13158 dev->dev_addr[1] = (hi >> 0) & 0xff;
13159
13160 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13161 dev->dev_addr[2] = (lo >> 24) & 0xff;
13162 dev->dev_addr[3] = (lo >> 16) & 0xff;
13163 dev->dev_addr[4] = (lo >> 8) & 0xff;
13164 dev->dev_addr[5] = (lo >> 0) & 0xff;
13165
13166 /* Some old bootcode may report a 0 MAC address in SRAM */
13167 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13168 }
13169 if (!addr_ok) {
13170 /* Next, try NVRAM. */
13171 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13172 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13173 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13174 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13175 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13176 }
13177 /* Finally just fetch it out of the MAC control regs. */
13178 else {
13179 hi = tr32(MAC_ADDR_0_HIGH);
13180 lo = tr32(MAC_ADDR_0_LOW);
13181
13182 dev->dev_addr[5] = lo & 0xff;
13183 dev->dev_addr[4] = (lo >> 8) & 0xff;
13184 dev->dev_addr[3] = (lo >> 16) & 0xff;
13185 dev->dev_addr[2] = (lo >> 24) & 0xff;
13186 dev->dev_addr[1] = hi & 0xff;
13187 dev->dev_addr[0] = (hi >> 8) & 0xff;
13188 }
13189 }
13190
13191 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13192 #ifdef CONFIG_SPARC
13193 if (!tg3_get_default_macaddr_sparc(tp))
13194 return 0;
13195 #endif
13196 return -EINVAL;
13197 }
13198 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13199 return 0;
13200 }
13201
13202 #define BOUNDARY_SINGLE_CACHELINE 1
13203 #define BOUNDARY_MULTI_CACHELINE 2
13204
13205 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13206 {
13207 int cacheline_size;
13208 u8 byte;
13209 int goal;
13210
13211 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13212 if (byte == 0)
13213 cacheline_size = 1024;
13214 else
13215 cacheline_size = (int) byte * 4;
13216
13217 /* On 5703 and later chips, the boundary bits have no
13218 * effect.
13219 */
13220 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13221 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13222 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13223 goto out;
13224
13225 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13226 goal = BOUNDARY_MULTI_CACHELINE;
13227 #else
13228 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13229 goal = BOUNDARY_SINGLE_CACHELINE;
13230 #else
13231 goal = 0;
13232 #endif
13233 #endif
13234
13235 if (!goal)
13236 goto out;
13237
13238 /* PCI controllers on most RISC systems tend to disconnect
13239 * when a device tries to burst across a cache-line boundary.
13240 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13241 *
13242 * Unfortunately, for PCI-E there are only limited
13243 * write-side controls for this, and thus for reads
13244 * we will still get the disconnects. We'll also waste
13245 * these PCI cycles for both read and write for chips
13246 * other than 5700 and 5701 which do not implement the
13247 * boundary bits.
13248 */
13249 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13250 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13251 switch (cacheline_size) {
13252 case 16:
13253 case 32:
13254 case 64:
13255 case 128:
13256 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13257 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13258 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13259 } else {
13260 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13261 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13262 }
13263 break;
13264
13265 case 256:
13266 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13267 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13268 break;
13269
13270 default:
13271 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13272 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13273 break;
13274 }
13275 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13276 switch (cacheline_size) {
13277 case 16:
13278 case 32:
13279 case 64:
13280 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13281 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13282 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13283 break;
13284 }
13285 /* fallthrough */
13286 case 128:
13287 default:
13288 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13289 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13290 break;
13291 }
13292 } else {
13293 switch (cacheline_size) {
13294 case 16:
13295 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13296 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13297 DMA_RWCTRL_WRITE_BNDRY_16);
13298 break;
13299 }
13300 /* fallthrough */
13301 case 32:
13302 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13303 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13304 DMA_RWCTRL_WRITE_BNDRY_32);
13305 break;
13306 }
13307 /* fallthrough */
13308 case 64:
13309 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13310 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13311 DMA_RWCTRL_WRITE_BNDRY_64);
13312 break;
13313 }
13314 /* fallthrough */
13315 case 128:
13316 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13317 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13318 DMA_RWCTRL_WRITE_BNDRY_128);
13319 break;
13320 }
13321 /* fallthrough */
13322 case 256:
13323 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13324 DMA_RWCTRL_WRITE_BNDRY_256);
13325 break;
13326 case 512:
13327 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13328 DMA_RWCTRL_WRITE_BNDRY_512);
13329 break;
13330 case 1024:
13331 default:
13332 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13333 DMA_RWCTRL_WRITE_BNDRY_1024);
13334 break;
13335 }
13336 }
13337
13338 out:
13339 return val;
13340 }
13341
13342 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13343 {
13344 struct tg3_internal_buffer_desc test_desc;
13345 u32 sram_dma_descs;
13346 int i, ret;
13347
13348 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13349
13350 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13351 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13352 tw32(RDMAC_STATUS, 0);
13353 tw32(WDMAC_STATUS, 0);
13354
13355 tw32(BUFMGR_MODE, 0);
13356 tw32(FTQ_RESET, 0);
13357
13358 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13359 test_desc.addr_lo = buf_dma & 0xffffffff;
13360 test_desc.nic_mbuf = 0x00002100;
13361 test_desc.len = size;
13362
13363 /*
13364 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13365 * the *second* time the tg3 driver was getting loaded after an
13366 * initial scan.
13367 *
13368 * Broadcom tells me:
13369 * ...the DMA engine is connected to the GRC block and a DMA
13370 * reset may affect the GRC block in some unpredictable way...
13371 * The behavior of resets to individual blocks has not been tested.
13372 *
13373 * Broadcom noted the GRC reset will also reset all sub-components.
13374 */
13375 if (to_device) {
13376 test_desc.cqid_sqid = (13 << 8) | 2;
13377
13378 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13379 udelay(40);
13380 } else {
13381 test_desc.cqid_sqid = (16 << 8) | 7;
13382
13383 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13384 udelay(40);
13385 }
13386 test_desc.flags = 0x00000005;
13387
13388 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13389 u32 val;
13390
13391 val = *(((u32 *)&test_desc) + i);
13392 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13393 sram_dma_descs + (i * sizeof(u32)));
13394 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13395 }
13396 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13397
13398 if (to_device) {
13399 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13400 } else {
13401 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13402 }
13403
13404 ret = -ENODEV;
13405 for (i = 0; i < 40; i++) {
13406 u32 val;
13407
13408 if (to_device)
13409 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13410 else
13411 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13412 if ((val & 0xffff) == sram_dma_descs) {
13413 ret = 0;
13414 break;
13415 }
13416
13417 udelay(100);
13418 }
13419
13420 return ret;
13421 }
13422
13423 #define TEST_BUFFER_SIZE 0x2000
13424
13425 static int __devinit tg3_test_dma(struct tg3 *tp)
13426 {
13427 dma_addr_t buf_dma;
13428 u32 *buf, saved_dma_rwctrl;
13429 int ret;
13430
13431 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13432 if (!buf) {
13433 ret = -ENOMEM;
13434 goto out_nofree;
13435 }
13436
13437 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13438 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13439
13440 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13441
13442 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13443 /* DMA read watermark not used on PCIE */
13444 tp->dma_rwctrl |= 0x00180000;
13445 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13446 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13447 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13448 tp->dma_rwctrl |= 0x003f0000;
13449 else
13450 tp->dma_rwctrl |= 0x003f000f;
13451 } else {
13452 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13453 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13454 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13455 u32 read_water = 0x7;
13456
13457 /* If the 5704 is behind the EPB bridge, we can
13458 * do the less restrictive ONE_DMA workaround for
13459 * better performance.
13460 */
13461 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13462 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13463 tp->dma_rwctrl |= 0x8000;
13464 else if (ccval == 0x6 || ccval == 0x7)
13465 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13466
13467 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13468 read_water = 4;
13469 /* Set bit 23 to enable PCIX hw bug fix */
13470 tp->dma_rwctrl |=
13471 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13472 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13473 (1 << 23);
13474 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13475 /* 5780 always in PCIX mode */
13476 tp->dma_rwctrl |= 0x00144000;
13477 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13478 /* 5714 always in PCIX mode */
13479 tp->dma_rwctrl |= 0x00148000;
13480 } else {
13481 tp->dma_rwctrl |= 0x001b000f;
13482 }
13483 }
13484
13485 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13486 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13487 tp->dma_rwctrl &= 0xfffffff0;
13488
13489 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13490 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13491 /* Remove this if it causes problems for some boards. */
13492 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13493
13494 /* On 5700/5701 chips, we need to set this bit.
13495 * Otherwise the chip will issue cacheline transactions
13496 * to streamable DMA memory with not all the byte
13497 * enables turned on. This is an error on several
13498 * RISC PCI controllers, in particular sparc64.
13499 *
13500 * On 5703/5704 chips, this bit has been reassigned
13501 * a different meaning. In particular, it is used
13502 * on those chips to enable a PCI-X workaround.
13503 */
13504 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13505 }
13506
13507 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13508
13509 #if 0
13510 /* Unneeded, already done by tg3_get_invariants. */
13511 tg3_switch_clocks(tp);
13512 #endif
13513
13514 ret = 0;
13515 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13516 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13517 goto out;
13518
13519 /* It is best to perform DMA test with maximum write burst size
13520 * to expose the 5700/5701 write DMA bug.
13521 */
13522 saved_dma_rwctrl = tp->dma_rwctrl;
13523 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13524 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13525
13526 while (1) {
13527 u32 *p = buf, i;
13528
13529 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13530 p[i] = i;
13531
13532 /* Send the buffer to the chip. */
13533 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13534 if (ret) {
13535 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
13536 break;
13537 }
13538
13539 #if 0
13540 /* validate data reached card RAM correctly. */
13541 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13542 u32 val;
13543 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13544 if (le32_to_cpu(val) != p[i]) {
13545 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
13546 /* ret = -ENODEV here? */
13547 }
13548 p[i] = 0;
13549 }
13550 #endif
13551 /* Now read it back. */
13552 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13553 if (ret) {
13554 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
13555
13556 break;
13557 }
13558
13559 /* Verify it. */
13560 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13561 if (p[i] == i)
13562 continue;
13563
13564 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13565 DMA_RWCTRL_WRITE_BNDRY_16) {
13566 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13567 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13568 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13569 break;
13570 } else {
13571 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13572 ret = -ENODEV;
13573 goto out;
13574 }
13575 }
13576
13577 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13578 /* Success. */
13579 ret = 0;
13580 break;
13581 }
13582 }
13583 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13584 DMA_RWCTRL_WRITE_BNDRY_16) {
13585 static struct pci_device_id dma_wait_state_chipsets[] = {
13586 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13587 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13588 { },
13589 };
13590
13591 /* DMA test passed without adjusting DMA boundary,
13592 * now look for chipsets that are known to expose the
13593 * DMA bug without failing the test.
13594 */
13595 if (pci_dev_present(dma_wait_state_chipsets)) {
13596 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13597 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13598 }
13599 else
13600 /* Safe to use the calculated DMA boundary. */
13601 tp->dma_rwctrl = saved_dma_rwctrl;
13602
13603 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13604 }
13605
13606 out:
13607 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13608 out_nofree:
13609 return ret;
13610 }
13611
13612 static void __devinit tg3_init_link_config(struct tg3 *tp)
13613 {
13614 tp->link_config.advertising =
13615 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13616 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13617 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13618 ADVERTISED_Autoneg | ADVERTISED_MII);
13619 tp->link_config.speed = SPEED_INVALID;
13620 tp->link_config.duplex = DUPLEX_INVALID;
13621 tp->link_config.autoneg = AUTONEG_ENABLE;
13622 tp->link_config.active_speed = SPEED_INVALID;
13623 tp->link_config.active_duplex = DUPLEX_INVALID;
13624 tp->link_config.phy_is_low_power = 0;
13625 tp->link_config.orig_speed = SPEED_INVALID;
13626 tp->link_config.orig_duplex = DUPLEX_INVALID;
13627 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13628 }
13629
13630 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13631 {
13632 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
13633 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
13634 tp->bufmgr_config.mbuf_read_dma_low_water =
13635 DEFAULT_MB_RDMA_LOW_WATER_5705;
13636 tp->bufmgr_config.mbuf_mac_rx_low_water =
13637 DEFAULT_MB_MACRX_LOW_WATER_5705;
13638 tp->bufmgr_config.mbuf_high_water =
13639 DEFAULT_MB_HIGH_WATER_5705;
13640 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13641 tp->bufmgr_config.mbuf_mac_rx_low_water =
13642 DEFAULT_MB_MACRX_LOW_WATER_5906;
13643 tp->bufmgr_config.mbuf_high_water =
13644 DEFAULT_MB_HIGH_WATER_5906;
13645 }
13646
13647 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13648 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13649 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13650 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13651 tp->bufmgr_config.mbuf_high_water_jumbo =
13652 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13653 } else {
13654 tp->bufmgr_config.mbuf_read_dma_low_water =
13655 DEFAULT_MB_RDMA_LOW_WATER;
13656 tp->bufmgr_config.mbuf_mac_rx_low_water =
13657 DEFAULT_MB_MACRX_LOW_WATER;
13658 tp->bufmgr_config.mbuf_high_water =
13659 DEFAULT_MB_HIGH_WATER;
13660
13661 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13662 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13663 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13664 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13665 tp->bufmgr_config.mbuf_high_water_jumbo =
13666 DEFAULT_MB_HIGH_WATER_JUMBO;
13667 }
13668
13669 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13670 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13671 }
13672
13673 static char * __devinit tg3_phy_string(struct tg3 *tp)
13674 {
13675 switch (tp->phy_id & PHY_ID_MASK) {
13676 case PHY_ID_BCM5400: return "5400";
13677 case PHY_ID_BCM5401: return "5401";
13678 case PHY_ID_BCM5411: return "5411";
13679 case PHY_ID_BCM5701: return "5701";
13680 case PHY_ID_BCM5703: return "5703";
13681 case PHY_ID_BCM5704: return "5704";
13682 case PHY_ID_BCM5705: return "5705";
13683 case PHY_ID_BCM5750: return "5750";
13684 case PHY_ID_BCM5752: return "5752";
13685 case PHY_ID_BCM5714: return "5714";
13686 case PHY_ID_BCM5780: return "5780";
13687 case PHY_ID_BCM5755: return "5755";
13688 case PHY_ID_BCM5787: return "5787";
13689 case PHY_ID_BCM5784: return "5784";
13690 case PHY_ID_BCM5756: return "5722/5756";
13691 case PHY_ID_BCM5906: return "5906";
13692 case PHY_ID_BCM5761: return "5761";
13693 case PHY_ID_BCM8002: return "8002/serdes";
13694 case 0: return "serdes";
13695 default: return "unknown";
13696 }
13697 }
13698
13699 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13700 {
13701 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13702 strcpy(str, "PCI Express");
13703 return str;
13704 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13705 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13706
13707 strcpy(str, "PCIX:");
13708
13709 if ((clock_ctrl == 7) ||
13710 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13711 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13712 strcat(str, "133MHz");
13713 else if (clock_ctrl == 0)
13714 strcat(str, "33MHz");
13715 else if (clock_ctrl == 2)
13716 strcat(str, "50MHz");
13717 else if (clock_ctrl == 4)
13718 strcat(str, "66MHz");
13719 else if (clock_ctrl == 6)
13720 strcat(str, "100MHz");
13721 } else {
13722 strcpy(str, "PCI:");
13723 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13724 strcat(str, "66MHz");
13725 else
13726 strcat(str, "33MHz");
13727 }
13728 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13729 strcat(str, ":32-bit");
13730 else
13731 strcat(str, ":64-bit");
13732 return str;
13733 }
13734
13735 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13736 {
13737 struct pci_dev *peer;
13738 unsigned int func, devnr = tp->pdev->devfn & ~7;
13739
13740 for (func = 0; func < 8; func++) {
13741 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13742 if (peer && peer != tp->pdev)
13743 break;
13744 pci_dev_put(peer);
13745 }
13746 /* 5704 can be configured in single-port mode, set peer to
13747 * tp->pdev in that case.
13748 */
13749 if (!peer) {
13750 peer = tp->pdev;
13751 return peer;
13752 }
13753
13754 /*
13755 * We don't need to keep the refcount elevated; there's no way
13756 * to remove one half of this device without removing the other
13757 */
13758 pci_dev_put(peer);
13759
13760 return peer;
13761 }
13762
13763 static void __devinit tg3_init_coal(struct tg3 *tp)
13764 {
13765 struct ethtool_coalesce *ec = &tp->coal;
13766
13767 memset(ec, 0, sizeof(*ec));
13768 ec->cmd = ETHTOOL_GCOALESCE;
13769 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13770 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13771 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13772 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13773 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13774 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13775 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13776 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13777 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13778
13779 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13780 HOSTCC_MODE_CLRTICK_TXBD)) {
13781 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13782 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13783 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13784 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13785 }
13786
13787 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13788 ec->rx_coalesce_usecs_irq = 0;
13789 ec->tx_coalesce_usecs_irq = 0;
13790 ec->stats_block_coalesce_usecs = 0;
13791 }
13792 }
13793
13794 static const struct net_device_ops tg3_netdev_ops = {
13795 .ndo_open = tg3_open,
13796 .ndo_stop = tg3_close,
13797 .ndo_start_xmit = tg3_start_xmit,
13798 .ndo_get_stats = tg3_get_stats,
13799 .ndo_validate_addr = eth_validate_addr,
13800 .ndo_set_multicast_list = tg3_set_rx_mode,
13801 .ndo_set_mac_address = tg3_set_mac_addr,
13802 .ndo_do_ioctl = tg3_ioctl,
13803 .ndo_tx_timeout = tg3_tx_timeout,
13804 .ndo_change_mtu = tg3_change_mtu,
13805 #if TG3_VLAN_TAG_USED
13806 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13807 #endif
13808 #ifdef CONFIG_NET_POLL_CONTROLLER
13809 .ndo_poll_controller = tg3_poll_controller,
13810 #endif
13811 };
13812
13813 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
13814 .ndo_open = tg3_open,
13815 .ndo_stop = tg3_close,
13816 .ndo_start_xmit = tg3_start_xmit_dma_bug,
13817 .ndo_get_stats = tg3_get_stats,
13818 .ndo_validate_addr = eth_validate_addr,
13819 .ndo_set_multicast_list = tg3_set_rx_mode,
13820 .ndo_set_mac_address = tg3_set_mac_addr,
13821 .ndo_do_ioctl = tg3_ioctl,
13822 .ndo_tx_timeout = tg3_tx_timeout,
13823 .ndo_change_mtu = tg3_change_mtu,
13824 #if TG3_VLAN_TAG_USED
13825 .ndo_vlan_rx_register = tg3_vlan_rx_register,
13826 #endif
13827 #ifdef CONFIG_NET_POLL_CONTROLLER
13828 .ndo_poll_controller = tg3_poll_controller,
13829 #endif
13830 };
13831
13832 static int __devinit tg3_init_one(struct pci_dev *pdev,
13833 const struct pci_device_id *ent)
13834 {
13835 static int tg3_version_printed = 0;
13836 struct net_device *dev;
13837 struct tg3 *tp;
13838 int i, err, pm_cap;
13839 u32 sndmbx, rcvmbx, intmbx;
13840 char str[40];
13841 u64 dma_mask, persist_dma_mask;
13842
13843 if (tg3_version_printed++ == 0)
13844 printk(KERN_INFO "%s", version);
13845
13846 err = pci_enable_device(pdev);
13847 if (err) {
13848 printk(KERN_ERR PFX "Cannot enable PCI device, "
13849 "aborting.\n");
13850 return err;
13851 }
13852
13853 err = pci_request_regions(pdev, DRV_MODULE_NAME);
13854 if (err) {
13855 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13856 "aborting.\n");
13857 goto err_out_disable_pdev;
13858 }
13859
13860 pci_set_master(pdev);
13861
13862 /* Find power-management capability. */
13863 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13864 if (pm_cap == 0) {
13865 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13866 "aborting.\n");
13867 err = -EIO;
13868 goto err_out_free_res;
13869 }
13870
13871 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
13872 if (!dev) {
13873 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13874 err = -ENOMEM;
13875 goto err_out_free_res;
13876 }
13877
13878 SET_NETDEV_DEV(dev, &pdev->dev);
13879
13880 #if TG3_VLAN_TAG_USED
13881 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13882 #endif
13883
13884 tp = netdev_priv(dev);
13885 tp->pdev = pdev;
13886 tp->dev = dev;
13887 tp->pm_cap = pm_cap;
13888 tp->rx_mode = TG3_DEF_RX_MODE;
13889 tp->tx_mode = TG3_DEF_TX_MODE;
13890
13891 if (tg3_debug > 0)
13892 tp->msg_enable = tg3_debug;
13893 else
13894 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13895
13896 /* The word/byte swap controls here control register access byte
13897 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13898 * setting below.
13899 */
13900 tp->misc_host_ctrl =
13901 MISC_HOST_CTRL_MASK_PCI_INT |
13902 MISC_HOST_CTRL_WORD_SWAP |
13903 MISC_HOST_CTRL_INDIR_ACCESS |
13904 MISC_HOST_CTRL_PCISTATE_RW;
13905
13906 /* The NONFRM (non-frame) byte/word swap controls take effect
13907 * on descriptor entries, anything which isn't packet data.
13908 *
13909 * The StrongARM chips on the board (one for tx, one for rx)
13910 * are running in big-endian mode.
13911 */
13912 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13913 GRC_MODE_WSWAP_NONFRM_DATA);
13914 #ifdef __BIG_ENDIAN
13915 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13916 #endif
13917 spin_lock_init(&tp->lock);
13918 spin_lock_init(&tp->indirect_lock);
13919 INIT_WORK(&tp->reset_task, tg3_reset_task);
13920
13921 tp->regs = pci_ioremap_bar(pdev, BAR_0);
13922 if (!tp->regs) {
13923 printk(KERN_ERR PFX "Cannot map device registers, "
13924 "aborting.\n");
13925 err = -ENOMEM;
13926 goto err_out_free_dev;
13927 }
13928
13929 tg3_init_link_config(tp);
13930
13931 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13932 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13933
13934 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13935 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
13936 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
13937 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
13938 struct tg3_napi *tnapi = &tp->napi[i];
13939
13940 tnapi->tp = tp;
13941 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
13942
13943 tnapi->int_mbox = intmbx;
13944 if (i < 4)
13945 intmbx += 0x8;
13946 else
13947 intmbx += 0x4;
13948
13949 tnapi->consmbox = rcvmbx;
13950 tnapi->prodmbox = sndmbx;
13951
13952 if (i)
13953 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
13954 else
13955 tnapi->coal_now = HOSTCC_MODE_NOW;
13956
13957 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
13958 break;
13959
13960 /*
13961 * If we support MSIX, we'll be using RSS. If we're using
13962 * RSS, the first vector only handles link interrupts and the
13963 * remaining vectors handle rx and tx interrupts. Reuse the
13964 * mailbox values for the next iteration. The values we setup
13965 * above are still useful for the single vectored mode.
13966 */
13967 if (!i)
13968 continue;
13969
13970 rcvmbx += 0x8;
13971
13972 if (sndmbx & 0x4)
13973 sndmbx -= 0x4;
13974 else
13975 sndmbx += 0xc;
13976 }
13977
13978 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
13979 dev->ethtool_ops = &tg3_ethtool_ops;
13980 dev->watchdog_timeo = TG3_TX_TIMEOUT;
13981 dev->irq = pdev->irq;
13982
13983 err = tg3_get_invariants(tp);
13984 if (err) {
13985 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13986 "aborting.\n");
13987 goto err_out_iounmap;
13988 }
13989
13990 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13991 dev->netdev_ops = &tg3_netdev_ops;
13992 else
13993 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13994
13995
13996 /* The EPB bridge inside 5714, 5715, and 5780 and any
13997 * device behind the EPB cannot support DMA addresses > 40-bit.
13998 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13999 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14000 * do DMA address check in tg3_start_xmit().
14001 */
14002 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14003 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14004 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14005 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14006 #ifdef CONFIG_HIGHMEM
14007 dma_mask = DMA_BIT_MASK(64);
14008 #endif
14009 } else
14010 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14011
14012 /* Configure DMA attributes. */
14013 if (dma_mask > DMA_BIT_MASK(32)) {
14014 err = pci_set_dma_mask(pdev, dma_mask);
14015 if (!err) {
14016 dev->features |= NETIF_F_HIGHDMA;
14017 err = pci_set_consistent_dma_mask(pdev,
14018 persist_dma_mask);
14019 if (err < 0) {
14020 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14021 "DMA for consistent allocations\n");
14022 goto err_out_iounmap;
14023 }
14024 }
14025 }
14026 if (err || dma_mask == DMA_BIT_MASK(32)) {
14027 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14028 if (err) {
14029 printk(KERN_ERR PFX "No usable DMA configuration, "
14030 "aborting.\n");
14031 goto err_out_iounmap;
14032 }
14033 }
14034
14035 tg3_init_bufmgr_config(tp);
14036
14037 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14038 tp->fw_needed = FIRMWARE_TG3;
14039
14040 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14041 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14042 }
14043 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14044 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14045 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
14046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14047 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
14048 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
14049 } else {
14050 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
14051 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14052 tp->fw_needed = FIRMWARE_TG3TSO5;
14053 else
14054 tp->fw_needed = FIRMWARE_TG3TSO;
14055 }
14056
14057 /* TSO is on by default on chips that support hardware TSO.
14058 * Firmware TSO on older chips gives lower performance, so it
14059 * is off by default, but can be enabled using ethtool.
14060 */
14061 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
14062 if (dev->features & NETIF_F_IP_CSUM)
14063 dev->features |= NETIF_F_TSO;
14064 if ((dev->features & NETIF_F_IPV6_CSUM) &&
14065 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
14066 dev->features |= NETIF_F_TSO6;
14067 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14068 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14069 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14071 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14072 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
14073 dev->features |= NETIF_F_TSO_ECN;
14074 }
14075
14076
14077 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14078 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14079 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14080 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14081 tp->rx_pending = 63;
14082 }
14083
14084 err = tg3_get_device_address(tp);
14085 if (err) {
14086 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14087 "aborting.\n");
14088 goto err_out_fw;
14089 }
14090
14091 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14092 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14093 if (!tp->aperegs) {
14094 printk(KERN_ERR PFX "Cannot map APE registers, "
14095 "aborting.\n");
14096 err = -ENOMEM;
14097 goto err_out_fw;
14098 }
14099
14100 tg3_ape_lock_init(tp);
14101
14102 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14103 tg3_read_dash_ver(tp);
14104 }
14105
14106 /*
14107 * Reset chip in case UNDI or EFI driver did not shutdown
14108 * DMA self test will enable WDMAC and we'll see (spurious)
14109 * pending DMA on the PCI bus at that point.
14110 */
14111 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14112 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14113 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14114 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14115 }
14116
14117 err = tg3_test_dma(tp);
14118 if (err) {
14119 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14120 goto err_out_apeunmap;
14121 }
14122
14123 /* flow control autonegotiation is default behavior */
14124 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14125 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14126
14127 tg3_init_coal(tp);
14128
14129 pci_set_drvdata(pdev, dev);
14130
14131 err = register_netdev(dev);
14132 if (err) {
14133 printk(KERN_ERR PFX "Cannot register net device, "
14134 "aborting.\n");
14135 goto err_out_apeunmap;
14136 }
14137
14138 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14139 dev->name,
14140 tp->board_part_number,
14141 tp->pci_chip_rev_id,
14142 tg3_bus_string(tp, str),
14143 dev->dev_addr);
14144
14145 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
14146 printk(KERN_INFO
14147 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14148 tp->dev->name,
14149 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
14150 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
14151 else
14152 printk(KERN_INFO
14153 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14154 tp->dev->name, tg3_phy_string(tp),
14155 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14156 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14157 "10/100/1000Base-T")),
14158 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14159
14160 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14161 dev->name,
14162 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14163 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14164 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14165 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14166 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14167 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14168 dev->name, tp->dma_rwctrl,
14169 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14170 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14171
14172 return 0;
14173
14174 err_out_apeunmap:
14175 if (tp->aperegs) {
14176 iounmap(tp->aperegs);
14177 tp->aperegs = NULL;
14178 }
14179
14180 err_out_fw:
14181 if (tp->fw)
14182 release_firmware(tp->fw);
14183
14184 err_out_iounmap:
14185 if (tp->regs) {
14186 iounmap(tp->regs);
14187 tp->regs = NULL;
14188 }
14189
14190 err_out_free_dev:
14191 free_netdev(dev);
14192
14193 err_out_free_res:
14194 pci_release_regions(pdev);
14195
14196 err_out_disable_pdev:
14197 pci_disable_device(pdev);
14198 pci_set_drvdata(pdev, NULL);
14199 return err;
14200 }
14201
14202 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14203 {
14204 struct net_device *dev = pci_get_drvdata(pdev);
14205
14206 if (dev) {
14207 struct tg3 *tp = netdev_priv(dev);
14208
14209 if (tp->fw)
14210 release_firmware(tp->fw);
14211
14212 flush_scheduled_work();
14213
14214 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14215 tg3_phy_fini(tp);
14216 tg3_mdio_fini(tp);
14217 }
14218
14219 unregister_netdev(dev);
14220 if (tp->aperegs) {
14221 iounmap(tp->aperegs);
14222 tp->aperegs = NULL;
14223 }
14224 if (tp->regs) {
14225 iounmap(tp->regs);
14226 tp->regs = NULL;
14227 }
14228 free_netdev(dev);
14229 pci_release_regions(pdev);
14230 pci_disable_device(pdev);
14231 pci_set_drvdata(pdev, NULL);
14232 }
14233 }
14234
14235 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14236 {
14237 struct net_device *dev = pci_get_drvdata(pdev);
14238 struct tg3 *tp = netdev_priv(dev);
14239 pci_power_t target_state;
14240 int err;
14241
14242 /* PCI register 4 needs to be saved whether netif_running() or not.
14243 * MSI address and data need to be saved if using MSI and
14244 * netif_running().
14245 */
14246 pci_save_state(pdev);
14247
14248 if (!netif_running(dev))
14249 return 0;
14250
14251 flush_scheduled_work();
14252 tg3_phy_stop(tp);
14253 tg3_netif_stop(tp);
14254
14255 del_timer_sync(&tp->timer);
14256
14257 tg3_full_lock(tp, 1);
14258 tg3_disable_ints(tp);
14259 tg3_full_unlock(tp);
14260
14261 netif_device_detach(dev);
14262
14263 tg3_full_lock(tp, 0);
14264 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14265 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14266 tg3_full_unlock(tp);
14267
14268 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14269
14270 err = tg3_set_power_state(tp, target_state);
14271 if (err) {
14272 int err2;
14273
14274 tg3_full_lock(tp, 0);
14275
14276 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14277 err2 = tg3_restart_hw(tp, 1);
14278 if (err2)
14279 goto out;
14280
14281 tp->timer.expires = jiffies + tp->timer_offset;
14282 add_timer(&tp->timer);
14283
14284 netif_device_attach(dev);
14285 tg3_netif_start(tp);
14286
14287 out:
14288 tg3_full_unlock(tp);
14289
14290 if (!err2)
14291 tg3_phy_start(tp);
14292 }
14293
14294 return err;
14295 }
14296
14297 static int tg3_resume(struct pci_dev *pdev)
14298 {
14299 struct net_device *dev = pci_get_drvdata(pdev);
14300 struct tg3 *tp = netdev_priv(dev);
14301 int err;
14302
14303 pci_restore_state(tp->pdev);
14304
14305 if (!netif_running(dev))
14306 return 0;
14307
14308 err = tg3_set_power_state(tp, PCI_D0);
14309 if (err)
14310 return err;
14311
14312 netif_device_attach(dev);
14313
14314 tg3_full_lock(tp, 0);
14315
14316 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14317 err = tg3_restart_hw(tp, 1);
14318 if (err)
14319 goto out;
14320
14321 tp->timer.expires = jiffies + tp->timer_offset;
14322 add_timer(&tp->timer);
14323
14324 tg3_netif_start(tp);
14325
14326 out:
14327 tg3_full_unlock(tp);
14328
14329 if (!err)
14330 tg3_phy_start(tp);
14331
14332 return err;
14333 }
14334
14335 static struct pci_driver tg3_driver = {
14336 .name = DRV_MODULE_NAME,
14337 .id_table = tg3_pci_tbl,
14338 .probe = tg3_init_one,
14339 .remove = __devexit_p(tg3_remove_one),
14340 .suspend = tg3_suspend,
14341 .resume = tg3_resume
14342 };
14343
14344 static int __init tg3_init(void)
14345 {
14346 return pci_register_driver(&tg3_driver);
14347 }
14348
14349 static void __exit tg3_cleanup(void)
14350 {
14351 pci_unregister_driver(&tg3_driver);
14352 }
14353
14354 module_init(tg3_init);
14355 module_exit(tg3_cleanup);
Support for the Chinese Samsung S3C2440 based development boards