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sparc64: Stop using memory barriers for atomics and locks.
[linux-2.6/mini2440.git] / arch / sparc64 / mm / init.c
blob4bd63968400df7e33d4714190f59dc2c779d635f
1 /*
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27 #include <linux/lmb.h>
28 #include <linux/mmzone.h>
29
30 #include <asm/head.h>
31 #include <asm/system.h>
32 #include <asm/page.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
37 #include <asm/io.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
41 #include <asm/dma.h>
42 #include <asm/starfire.h>
43 #include <asm/tlb.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
46 #include <asm/tsb.h>
47 #include <asm/hypervisor.h>
48 #include <asm/prom.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/irq.h>
52
53 #include "init.h"
54
55 unsigned long kern_linear_pte_xor[2] __read_mostly;
56
57 /* A bitmap, one bit for every 256MB of physical memory. If the bit
58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60 */
61 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62
63 #ifndef CONFIG_DEBUG_PAGEALLOC
64 /* A special kernel TSB for 4MB and 256MB linear mappings.
65 * Space is allocated for this right after the trap table
66 * in arch/sparc64/kernel/head.S
67 */
68 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
69 #endif
70
71 #define MAX_BANKS 32
72
73 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
74 static int pavail_ents __initdata;
75
76 static int cmp_p64(const void *a, const void *b)
77 {
78 const struct linux_prom64_registers *x = a, *y = b;
79
80 if (x->phys_addr > y->phys_addr)
81 return 1;
82 if (x->phys_addr < y->phys_addr)
83 return -1;
84 return 0;
85 }
86
87 static void __init read_obp_memory(const char *property,
88 struct linux_prom64_registers *regs,
89 int *num_ents)
90 {
91 int node = prom_finddevice("/memory");
92 int prop_size = prom_getproplen(node, property);
93 int ents, ret, i;
94
95 ents = prop_size / sizeof(struct linux_prom64_registers);
96 if (ents > MAX_BANKS) {
97 prom_printf("The machine has more %s property entries than "
98 "this kernel can support (%d).\n",
99 property, MAX_BANKS);
100 prom_halt();
101 }
102
103 ret = prom_getproperty(node, property, (char *) regs, prop_size);
104 if (ret == -1) {
105 prom_printf("Couldn't get %s property from /memory.\n");
106 prom_halt();
107 }
108
109 /* Sanitize what we got from the firmware, by page aligning
110 * everything.
111 */
112 for (i = 0; i < ents; i++) {
113 unsigned long base, size;
114
115 base = regs[i].phys_addr;
116 size = regs[i].reg_size;
117
118 size &= PAGE_MASK;
119 if (base & ~PAGE_MASK) {
120 unsigned long new_base = PAGE_ALIGN(base);
121
122 size -= new_base - base;
123 if ((long) size < 0L)
124 size = 0UL;
125 base = new_base;
126 }
127 if (size == 0UL) {
128 /* If it is empty, simply get rid of it.
129 * This simplifies the logic of the other
130 * functions that process these arrays.
131 */
132 memmove(&regs[i], &regs[i + 1],
133 (ents - i - 1) * sizeof(regs[0]));
134 i--;
135 ents--;
136 continue;
137 }
138 regs[i].phys_addr = base;
139 regs[i].reg_size = size;
140 }
141
142 *num_ents = ents;
143
144 sort(regs, ents, sizeof(struct linux_prom64_registers),
145 cmp_p64, NULL);
146 }
147
148 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
149
150 /* Kernel physical address base and size in bytes. */
151 unsigned long kern_base __read_mostly;
152 unsigned long kern_size __read_mostly;
153
154 /* Initial ramdisk setup */
155 extern unsigned long sparc_ramdisk_image64;
156 extern unsigned int sparc_ramdisk_image;
157 extern unsigned int sparc_ramdisk_size;
158
159 struct page *mem_map_zero __read_mostly;
160 EXPORT_SYMBOL(mem_map_zero);
161
162 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
163
164 unsigned long sparc64_kern_pri_context __read_mostly;
165 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
166 unsigned long sparc64_kern_sec_context __read_mostly;
167
168 int num_kernel_image_mappings;
169
170 #ifdef CONFIG_DEBUG_DCFLUSH
171 atomic_t dcpage_flushes = ATOMIC_INIT(0);
172 #ifdef CONFIG_SMP
173 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
174 #endif
175 #endif
176
177 inline void flush_dcache_page_impl(struct page *page)
178 {
179 BUG_ON(tlb_type == hypervisor);
180 #ifdef CONFIG_DEBUG_DCFLUSH
181 atomic_inc(&dcpage_flushes);
182 #endif
183
184 #ifdef DCACHE_ALIASING_POSSIBLE
185 __flush_dcache_page(page_address(page),
186 ((tlb_type == spitfire) &&
187 page_mapping(page) != NULL));
188 #else
189 if (page_mapping(page) != NULL &&
190 tlb_type == spitfire)
191 __flush_icache_page(__pa(page_address(page)));
192 #endif
193 }
194
195 #define PG_dcache_dirty PG_arch_1
196 #define PG_dcache_cpu_shift 32UL
197 #define PG_dcache_cpu_mask \
198 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
199
200 #define dcache_dirty_cpu(page) \
201 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
202
203 static inline void set_dcache_dirty(struct page *page, int this_cpu)
204 {
205 unsigned long mask = this_cpu;
206 unsigned long non_cpu_bits;
207
208 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
209 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
210
211 __asm__ __volatile__("1:\n\t"
212 "ldx [%2], %%g7\n\t"
213 "and %%g7, %1, %%g1\n\t"
214 "or %%g1, %0, %%g1\n\t"
215 "casx [%2], %%g7, %%g1\n\t"
216 "cmp %%g7, %%g1\n\t"
217 "bne,pn %%xcc, 1b\n\t"
218 " nop"
219 : /* no outputs */
220 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
221 : "g1", "g7");
222 }
223
224 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
225 {
226 unsigned long mask = (1UL << PG_dcache_dirty);
227
228 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
229 "1:\n\t"
230 "ldx [%2], %%g7\n\t"
231 "srlx %%g7, %4, %%g1\n\t"
232 "and %%g1, %3, %%g1\n\t"
233 "cmp %%g1, %0\n\t"
234 "bne,pn %%icc, 2f\n\t"
235 " andn %%g7, %1, %%g1\n\t"
236 "casx [%2], %%g7, %%g1\n\t"
237 "cmp %%g7, %%g1\n\t"
238 "bne,pn %%xcc, 1b\n\t"
239 " nop\n"
240 "2:"
241 : /* no outputs */
242 : "r" (cpu), "r" (mask), "r" (&page->flags),
243 "i" (PG_dcache_cpu_mask),
244 "i" (PG_dcache_cpu_shift)
245 : "g1", "g7");
246 }
247
248 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
249 {
250 unsigned long tsb_addr = (unsigned long) ent;
251
252 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
253 tsb_addr = __pa(tsb_addr);
254
255 __tsb_insert(tsb_addr, tag, pte);
256 }
257
258 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
259 unsigned long _PAGE_SZBITS __read_mostly;
260
261 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
262 {
263 struct mm_struct *mm;
264 struct tsb *tsb;
265 unsigned long tag, flags;
266 unsigned long tsb_index, tsb_hash_shift;
267
268 if (tlb_type != hypervisor) {
269 unsigned long pfn = pte_pfn(pte);
270 unsigned long pg_flags;
271 struct page *page;
272
273 if (pfn_valid(pfn) &&
274 (page = pfn_to_page(pfn), page_mapping(page)) &&
275 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
276 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
277 PG_dcache_cpu_mask);
278 int this_cpu = get_cpu();
279
280 /* This is just to optimize away some function calls
281 * in the SMP case.
282 */
283 if (cpu == this_cpu)
284 flush_dcache_page_impl(page);
285 else
286 smp_flush_dcache_page_impl(page, cpu);
287
288 clear_dcache_dirty_cpu(page, cpu);
289
290 put_cpu();
291 }
292 }
293
294 mm = vma->vm_mm;
295
296 tsb_index = MM_TSB_BASE;
297 tsb_hash_shift = PAGE_SHIFT;
298
299 spin_lock_irqsave(&mm->context.lock, flags);
300
301 #ifdef CONFIG_HUGETLB_PAGE
302 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
303 if ((tlb_type == hypervisor &&
304 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
305 (tlb_type != hypervisor &&
306 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
307 tsb_index = MM_TSB_HUGE;
308 tsb_hash_shift = HPAGE_SHIFT;
309 }
310 }
311 #endif
312
313 tsb = mm->context.tsb_block[tsb_index].tsb;
314 tsb += ((address >> tsb_hash_shift) &
315 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
316 tag = (address >> 22UL);
317 tsb_insert(tsb, tag, pte_val(pte));
318
319 spin_unlock_irqrestore(&mm->context.lock, flags);
320 }
321
322 void flush_dcache_page(struct page *page)
323 {
324 struct address_space *mapping;
325 int this_cpu;
326
327 if (tlb_type == hypervisor)
328 return;
329
330 /* Do not bother with the expensive D-cache flush if it
331 * is merely the zero page. The 'bigcore' testcase in GDB
332 * causes this case to run millions of times.
333 */
334 if (page == ZERO_PAGE(0))
335 return;
336
337 this_cpu = get_cpu();
338
339 mapping = page_mapping(page);
340 if (mapping && !mapping_mapped(mapping)) {
341 int dirty = test_bit(PG_dcache_dirty, &page->flags);
342 if (dirty) {
343 int dirty_cpu = dcache_dirty_cpu(page);
344
345 if (dirty_cpu == this_cpu)
346 goto out;
347 smp_flush_dcache_page_impl(page, dirty_cpu);
348 }
349 set_dcache_dirty(page, this_cpu);
350 } else {
351 /* We could delay the flush for the !page_mapping
352 * case too. But that case is for exec env/arg
353 * pages and those are %99 certainly going to get
354 * faulted into the tlb (and thus flushed) anyways.
355 */
356 flush_dcache_page_impl(page);
357 }
358
359 out:
360 put_cpu();
361 }
362
363 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
364 {
365 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
366 if (tlb_type == spitfire) {
367 unsigned long kaddr;
368
369 /* This code only runs on Spitfire cpus so this is
370 * why we can assume _PAGE_PADDR_4U.
371 */
372 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
373 unsigned long paddr, mask = _PAGE_PADDR_4U;
374
375 if (kaddr >= PAGE_OFFSET)
376 paddr = kaddr & mask;
377 else {
378 pgd_t *pgdp = pgd_offset_k(kaddr);
379 pud_t *pudp = pud_offset(pgdp, kaddr);
380 pmd_t *pmdp = pmd_offset(pudp, kaddr);
381 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
382
383 paddr = pte_val(*ptep) & mask;
384 }
385 __flush_icache_page(paddr);
386 }
387 }
388 }
389
390 void mmu_info(struct seq_file *m)
391 {
392 if (tlb_type == cheetah)
393 seq_printf(m, "MMU Type\t: Cheetah\n");
394 else if (tlb_type == cheetah_plus)
395 seq_printf(m, "MMU Type\t: Cheetah+\n");
396 else if (tlb_type == spitfire)
397 seq_printf(m, "MMU Type\t: Spitfire\n");
398 else if (tlb_type == hypervisor)
399 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
400 else
401 seq_printf(m, "MMU Type\t: ???\n");
402
403 #ifdef CONFIG_DEBUG_DCFLUSH
404 seq_printf(m, "DCPageFlushes\t: %d\n",
405 atomic_read(&dcpage_flushes));
406 #ifdef CONFIG_SMP
407 seq_printf(m, "DCPageFlushesXC\t: %d\n",
408 atomic_read(&dcpage_flushes_xcall));
409 #endif /* CONFIG_SMP */
410 #endif /* CONFIG_DEBUG_DCFLUSH */
411 }
412
413 struct linux_prom_translation prom_trans[512] __read_mostly;
414 unsigned int prom_trans_ents __read_mostly;
415
416 unsigned long kern_locked_tte_data;
417
418 /* The obp translations are saved based on 8k pagesize, since obp can
419 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
420 * HI_OBP_ADDRESS range are handled in ktlb.S.
421 */
422 static inline int in_obp_range(unsigned long vaddr)
423 {
424 return (vaddr >= LOW_OBP_ADDRESS &&
425 vaddr < HI_OBP_ADDRESS);
426 }
427
428 static int cmp_ptrans(const void *a, const void *b)
429 {
430 const struct linux_prom_translation *x = a, *y = b;
431
432 if (x->virt > y->virt)
433 return 1;
434 if (x->virt < y->virt)
435 return -1;
436 return 0;
437 }
438
439 /* Read OBP translations property into 'prom_trans[]'. */
440 static void __init read_obp_translations(void)
441 {
442 int n, node, ents, first, last, i;
443
444 node = prom_finddevice("/virtual-memory");
445 n = prom_getproplen(node, "translations");
446 if (unlikely(n == 0 || n == -1)) {
447 prom_printf("prom_mappings: Couldn't get size.\n");
448 prom_halt();
449 }
450 if (unlikely(n > sizeof(prom_trans))) {
451 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
452 prom_halt();
453 }
454
455 if ((n = prom_getproperty(node, "translations",
456 (char *)&prom_trans[0],
457 sizeof(prom_trans))) == -1) {
458 prom_printf("prom_mappings: Couldn't get property.\n");
459 prom_halt();
460 }
461
462 n = n / sizeof(struct linux_prom_translation);
463
464 ents = n;
465
466 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
467 cmp_ptrans, NULL);
468
469 /* Now kick out all the non-OBP entries. */
470 for (i = 0; i < ents; i++) {
471 if (in_obp_range(prom_trans[i].virt))
472 break;
473 }
474 first = i;
475 for (; i < ents; i++) {
476 if (!in_obp_range(prom_trans[i].virt))
477 break;
478 }
479 last = i;
480
481 for (i = 0; i < (last - first); i++) {
482 struct linux_prom_translation *src = &prom_trans[i + first];
483 struct linux_prom_translation *dest = &prom_trans[i];
484
485 *dest = *src;
486 }
487 for (; i < ents; i++) {
488 struct linux_prom_translation *dest = &prom_trans[i];
489 dest->virt = dest->size = dest->data = 0x0UL;
490 }
491
492 prom_trans_ents = last - first;
493
494 if (tlb_type == spitfire) {
495 /* Clear diag TTE bits. */
496 for (i = 0; i < prom_trans_ents; i++)
497 prom_trans[i].data &= ~0x0003fe0000000000UL;
498 }
499 }
500
501 static void __init hypervisor_tlb_lock(unsigned long vaddr,
502 unsigned long pte,
503 unsigned long mmu)
504 {
505 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
506
507 if (ret != 0) {
508 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
509 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
510 prom_halt();
511 }
512 }
513
514 static unsigned long kern_large_tte(unsigned long paddr);
515
516 static void __init remap_kernel(void)
517 {
518 unsigned long phys_page, tte_vaddr, tte_data;
519 int i, tlb_ent = sparc64_highest_locked_tlbent();
520
521 tte_vaddr = (unsigned long) KERNBASE;
522 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
523 tte_data = kern_large_tte(phys_page);
524
525 kern_locked_tte_data = tte_data;
526
527 /* Now lock us into the TLBs via Hypervisor or OBP. */
528 if (tlb_type == hypervisor) {
529 for (i = 0; i < num_kernel_image_mappings; i++) {
530 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
531 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
532 tte_vaddr += 0x400000;
533 tte_data += 0x400000;
534 }
535 } else {
536 for (i = 0; i < num_kernel_image_mappings; i++) {
537 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
538 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
539 tte_vaddr += 0x400000;
540 tte_data += 0x400000;
541 }
542 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
543 }
544 if (tlb_type == cheetah_plus) {
545 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
546 CTX_CHEETAH_PLUS_NUC);
547 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
548 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
549 }
550 }
551
552
553 static void __init inherit_prom_mappings(void)
554 {
555 /* Now fixup OBP's idea about where we really are mapped. */
556 printk("Remapping the kernel... ");
557 remap_kernel();
558 printk("done.\n");
559 }
560
561 void prom_world(int enter)
562 {
563 if (!enter)
564 set_fs((mm_segment_t) { get_thread_current_ds() });
565
566 __asm__ __volatile__("flushw");
567 }
568
569 void __flush_dcache_range(unsigned long start, unsigned long end)
570 {
571 unsigned long va;
572
573 if (tlb_type == spitfire) {
574 int n = 0;
575
576 for (va = start; va < end; va += 32) {
577 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
578 if (++n >= 512)
579 break;
580 }
581 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
582 start = __pa(start);
583 end = __pa(end);
584 for (va = start; va < end; va += 32)
585 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
586 "membar #Sync"
587 : /* no outputs */
588 : "r" (va),
589 "i" (ASI_DCACHE_INVALIDATE));
590 }
591 }
592
593 /* get_new_mmu_context() uses "cache + 1". */
594 DEFINE_SPINLOCK(ctx_alloc_lock);
595 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
596 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
597 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
598 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
599
600 /* Caller does TLB context flushing on local CPU if necessary.
601 * The caller also ensures that CTX_VALID(mm->context) is false.
602 *
603 * We must be careful about boundary cases so that we never
604 * let the user have CTX 0 (nucleus) or we ever use a CTX
605 * version of zero (and thus NO_CONTEXT would not be caught
606 * by version mis-match tests in mmu_context.h).
607 *
608 * Always invoked with interrupts disabled.
609 */
610 void get_new_mmu_context(struct mm_struct *mm)
611 {
612 unsigned long ctx, new_ctx;
613 unsigned long orig_pgsz_bits;
614 unsigned long flags;
615 int new_version;
616
617 spin_lock_irqsave(&ctx_alloc_lock, flags);
618 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
619 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
620 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
621 new_version = 0;
622 if (new_ctx >= (1 << CTX_NR_BITS)) {
623 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
624 if (new_ctx >= ctx) {
625 int i;
626 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
627 CTX_FIRST_VERSION;
628 if (new_ctx == 1)
629 new_ctx = CTX_FIRST_VERSION;
630
631 /* Don't call memset, for 16 entries that's just
632 * plain silly...
633 */
634 mmu_context_bmap[0] = 3;
635 mmu_context_bmap[1] = 0;
636 mmu_context_bmap[2] = 0;
637 mmu_context_bmap[3] = 0;
638 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
639 mmu_context_bmap[i + 0] = 0;
640 mmu_context_bmap[i + 1] = 0;
641 mmu_context_bmap[i + 2] = 0;
642 mmu_context_bmap[i + 3] = 0;
643 }
644 new_version = 1;
645 goto out;
646 }
647 }
648 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
649 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
650 out:
651 tlb_context_cache = new_ctx;
652 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
653 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
654
655 if (unlikely(new_version))
656 smp_new_mmu_context_version();
657 }
658
659 static int numa_enabled = 1;
660 static int numa_debug;
661
662 static int __init early_numa(char *p)
663 {
664 if (!p)
665 return 0;
666
667 if (strstr(p, "off"))
668 numa_enabled = 0;
669
670 if (strstr(p, "debug"))
671 numa_debug = 1;
672
673 return 0;
674 }
675 early_param("numa", early_numa);
676
677 #define numadbg(f, a...) \
678 do { if (numa_debug) \
679 printk(KERN_INFO f, ## a); \
680 } while (0)
681
682 static void __init find_ramdisk(unsigned long phys_base)
683 {
684 #ifdef CONFIG_BLK_DEV_INITRD
685 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
686 unsigned long ramdisk_image;
687
688 /* Older versions of the bootloader only supported a
689 * 32-bit physical address for the ramdisk image
690 * location, stored at sparc_ramdisk_image. Newer
691 * SILO versions set sparc_ramdisk_image to zero and
692 * provide a full 64-bit physical address at
693 * sparc_ramdisk_image64.
694 */
695 ramdisk_image = sparc_ramdisk_image;
696 if (!ramdisk_image)
697 ramdisk_image = sparc_ramdisk_image64;
698
699 /* Another bootloader quirk. The bootloader normalizes
700 * the physical address to KERNBASE, so we have to
701 * factor that back out and add in the lowest valid
702 * physical page address to get the true physical address.
703 */
704 ramdisk_image -= KERNBASE;
705 ramdisk_image += phys_base;
706
707 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
708 ramdisk_image, sparc_ramdisk_size);
709
710 initrd_start = ramdisk_image;
711 initrd_end = ramdisk_image + sparc_ramdisk_size;
712
713 lmb_reserve(initrd_start, sparc_ramdisk_size);
714
715 initrd_start += PAGE_OFFSET;
716 initrd_end += PAGE_OFFSET;
717 }
718 #endif
719 }
720
721 struct node_mem_mask {
722 unsigned long mask;
723 unsigned long val;
724 unsigned long bootmem_paddr;
725 };
726 static struct node_mem_mask node_masks[MAX_NUMNODES];
727 static int num_node_masks;
728
729 int numa_cpu_lookup_table[NR_CPUS];
730 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
731
732 #ifdef CONFIG_NEED_MULTIPLE_NODES
733
734 struct mdesc_mblock {
735 u64 base;
736 u64 size;
737 u64 offset; /* RA-to-PA */
738 };
739 static struct mdesc_mblock *mblocks;
740 static int num_mblocks;
741
742 static unsigned long ra_to_pa(unsigned long addr)
743 {
744 int i;
745
746 for (i = 0; i < num_mblocks; i++) {
747 struct mdesc_mblock *m = &mblocks[i];
748
749 if (addr >= m->base &&
750 addr < (m->base + m->size)) {
751 addr += m->offset;
752 break;
753 }
754 }
755 return addr;
756 }
757
758 static int find_node(unsigned long addr)
759 {
760 int i;
761
762 addr = ra_to_pa(addr);
763 for (i = 0; i < num_node_masks; i++) {
764 struct node_mem_mask *p = &node_masks[i];
765
766 if ((addr & p->mask) == p->val)
767 return i;
768 }
769 return -1;
770 }
771
772 static unsigned long nid_range(unsigned long start, unsigned long end,
773 int *nid)
774 {
775 *nid = find_node(start);
776 start += PAGE_SIZE;
777 while (start < end) {
778 int n = find_node(start);
779
780 if (n != *nid)
781 break;
782 start += PAGE_SIZE;
783 }
784
785 if (start > end)
786 start = end;
787
788 return start;
789 }
790 #else
791 static unsigned long nid_range(unsigned long start, unsigned long end,
792 int *nid)
793 {
794 *nid = 0;
795 return end;
796 }
797 #endif
798
799 /* This must be invoked after performing all of the necessary
800 * add_active_range() calls for 'nid'. We need to be able to get
801 * correct data from get_pfn_range_for_nid().
802 */
803 static void __init allocate_node_data(int nid)
804 {
805 unsigned long paddr, num_pages, start_pfn, end_pfn;
806 struct pglist_data *p;
807
808 #ifdef CONFIG_NEED_MULTIPLE_NODES
809 paddr = lmb_alloc_nid(sizeof(struct pglist_data),
810 SMP_CACHE_BYTES, nid, nid_range);
811 if (!paddr) {
812 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
813 prom_halt();
814 }
815 NODE_DATA(nid) = __va(paddr);
816 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
817
818 NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
819 #endif
820
821 p = NODE_DATA(nid);
822
823 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
824 p->node_start_pfn = start_pfn;
825 p->node_spanned_pages = end_pfn - start_pfn;
826
827 if (p->node_spanned_pages) {
828 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
829
830 paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid,
831 nid_range);
832 if (!paddr) {
833 prom_printf("Cannot allocate bootmap for nid[%d]\n",
834 nid);
835 prom_halt();
836 }
837 node_masks[nid].bootmem_paddr = paddr;
838 }
839 }
840
841 static void init_node_masks_nonnuma(void)
842 {
843 int i;
844
845 numadbg("Initializing tables for non-numa.\n");
846
847 node_masks[0].mask = node_masks[0].val = 0;
848 num_node_masks = 1;
849
850 for (i = 0; i < NR_CPUS; i++)
851 numa_cpu_lookup_table[i] = 0;
852
853 numa_cpumask_lookup_table[0] = CPU_MASK_ALL;
854 }
855
856 #ifdef CONFIG_NEED_MULTIPLE_NODES
857 struct pglist_data *node_data[MAX_NUMNODES];
858
859 EXPORT_SYMBOL(numa_cpu_lookup_table);
860 EXPORT_SYMBOL(numa_cpumask_lookup_table);
861 EXPORT_SYMBOL(node_data);
862
863 struct mdesc_mlgroup {
864 u64 node;
865 u64 latency;
866 u64 match;
867 u64 mask;
868 };
869 static struct mdesc_mlgroup *mlgroups;
870 static int num_mlgroups;
871
872 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
873 u32 cfg_handle)
874 {
875 u64 arc;
876
877 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
878 u64 target = mdesc_arc_target(md, arc);
879 const u64 *val;
880
881 val = mdesc_get_property(md, target,
882 "cfg-handle", NULL);
883 if (val && *val == cfg_handle)
884 return 0;
885 }
886 return -ENODEV;
887 }
888
889 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
890 u32 cfg_handle)
891 {
892 u64 arc, candidate, best_latency = ~(u64)0;
893
894 candidate = MDESC_NODE_NULL;
895 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
896 u64 target = mdesc_arc_target(md, arc);
897 const char *name = mdesc_node_name(md, target);
898 const u64 *val;
899
900 if (strcmp(name, "pio-latency-group"))
901 continue;
902
903 val = mdesc_get_property(md, target, "latency", NULL);
904 if (!val)
905 continue;
906
907 if (*val < best_latency) {
908 candidate = target;
909 best_latency = *val;
910 }
911 }
912
913 if (candidate == MDESC_NODE_NULL)
914 return -ENODEV;
915
916 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
917 }
918
919 int of_node_to_nid(struct device_node *dp)
920 {
921 const struct linux_prom64_registers *regs;
922 struct mdesc_handle *md;
923 u32 cfg_handle;
924 int count, nid;
925 u64 grp;
926
927 /* This is the right thing to do on currently supported
928 * SUN4U NUMA platforms as well, as the PCI controller does
929 * not sit behind any particular memory controller.
930 */
931 if (!mlgroups)
932 return -1;
933
934 regs = of_get_property(dp, "reg", NULL);
935 if (!regs)
936 return -1;
937
938 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
939
940 md = mdesc_grab();
941
942 count = 0;
943 nid = -1;
944 mdesc_for_each_node_by_name(md, grp, "group") {
945 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
946 nid = count;
947 break;
948 }
949 count++;
950 }
951
952 mdesc_release(md);
953
954 return nid;
955 }
956
957 static void __init add_node_ranges(void)
958 {
959 int i;
960
961 for (i = 0; i < lmb.memory.cnt; i++) {
962 unsigned long size = lmb_size_bytes(&lmb.memory, i);
963 unsigned long start, end;
964
965 start = lmb.memory.region[i].base;
966 end = start + size;
967 while (start < end) {
968 unsigned long this_end;
969 int nid;
970
971 this_end = nid_range(start, end, &nid);
972
973 numadbg("Adding active range nid[%d] "
974 "start[%lx] end[%lx]\n",
975 nid, start, this_end);
976
977 add_active_range(nid,
978 start >> PAGE_SHIFT,
979 this_end >> PAGE_SHIFT);
980
981 start = this_end;
982 }
983 }
984 }
985
986 static int __init grab_mlgroups(struct mdesc_handle *md)
987 {
988 unsigned long paddr;
989 int count = 0;
990 u64 node;
991
992 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
993 count++;
994 if (!count)
995 return -ENOENT;
996
997 paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup),
998 SMP_CACHE_BYTES);
999 if (!paddr)
1000 return -ENOMEM;
1001
1002 mlgroups = __va(paddr);
1003 num_mlgroups = count;
1004
1005 count = 0;
1006 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1007 struct mdesc_mlgroup *m = &mlgroups[count++];
1008 const u64 *val;
1009
1010 m->node = node;
1011
1012 val = mdesc_get_property(md, node, "latency", NULL);
1013 m->latency = *val;
1014 val = mdesc_get_property(md, node, "address-match", NULL);
1015 m->match = *val;
1016 val = mdesc_get_property(md, node, "address-mask", NULL);
1017 m->mask = *val;
1018
1019 numadbg("MLGROUP[%d]: node[%lx] latency[%lx] "
1020 "match[%lx] mask[%lx]\n",
1021 count - 1, m->node, m->latency, m->match, m->mask);
1022 }
1023
1024 return 0;
1025 }
1026
1027 static int __init grab_mblocks(struct mdesc_handle *md)
1028 {
1029 unsigned long paddr;
1030 int count = 0;
1031 u64 node;
1032
1033 mdesc_for_each_node_by_name(md, node, "mblock")
1034 count++;
1035 if (!count)
1036 return -ENOENT;
1037
1038 paddr = lmb_alloc(count * sizeof(struct mdesc_mblock),
1039 SMP_CACHE_BYTES);
1040 if (!paddr)
1041 return -ENOMEM;
1042
1043 mblocks = __va(paddr);
1044 num_mblocks = count;
1045
1046 count = 0;
1047 mdesc_for_each_node_by_name(md, node, "mblock") {
1048 struct mdesc_mblock *m = &mblocks[count++];
1049 const u64 *val;
1050
1051 val = mdesc_get_property(md, node, "base", NULL);
1052 m->base = *val;
1053 val = mdesc_get_property(md, node, "size", NULL);
1054 m->size = *val;
1055 val = mdesc_get_property(md, node,
1056 "address-congruence-offset", NULL);
1057 m->offset = *val;
1058
1059 numadbg("MBLOCK[%d]: base[%lx] size[%lx] offset[%lx]\n",
1060 count - 1, m->base, m->size, m->offset);
1061 }
1062
1063 return 0;
1064 }
1065
1066 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1067 u64 grp, cpumask_t *mask)
1068 {
1069 u64 arc;
1070
1071 cpus_clear(*mask);
1072
1073 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1074 u64 target = mdesc_arc_target(md, arc);
1075 const char *name = mdesc_node_name(md, target);
1076 const u64 *id;
1077
1078 if (strcmp(name, "cpu"))
1079 continue;
1080 id = mdesc_get_property(md, target, "id", NULL);
1081 if (*id < NR_CPUS)
1082 cpu_set(*id, *mask);
1083 }
1084 }
1085
1086 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1087 {
1088 int i;
1089
1090 for (i = 0; i < num_mlgroups; i++) {
1091 struct mdesc_mlgroup *m = &mlgroups[i];
1092 if (m->node == node)
1093 return m;
1094 }
1095 return NULL;
1096 }
1097
1098 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1099 int index)
1100 {
1101 struct mdesc_mlgroup *candidate = NULL;
1102 u64 arc, best_latency = ~(u64)0;
1103 struct node_mem_mask *n;
1104
1105 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1106 u64 target = mdesc_arc_target(md, arc);
1107 struct mdesc_mlgroup *m = find_mlgroup(target);
1108 if (!m)
1109 continue;
1110 if (m->latency < best_latency) {
1111 candidate = m;
1112 best_latency = m->latency;
1113 }
1114 }
1115 if (!candidate)
1116 return -ENOENT;
1117
1118 if (num_node_masks != index) {
1119 printk(KERN_ERR "Inconsistent NUMA state, "
1120 "index[%d] != num_node_masks[%d]\n",
1121 index, num_node_masks);
1122 return -EINVAL;
1123 }
1124
1125 n = &node_masks[num_node_masks++];
1126
1127 n->mask = candidate->mask;
1128 n->val = candidate->match;
1129
1130 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%lx])\n",
1131 index, n->mask, n->val, candidate->latency);
1132
1133 return 0;
1134 }
1135
1136 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1137 int index)
1138 {
1139 cpumask_t mask;
1140 int cpu;
1141
1142 numa_parse_mdesc_group_cpus(md, grp, &mask);
1143
1144 for_each_cpu_mask(cpu, mask)
1145 numa_cpu_lookup_table[cpu] = index;
1146 numa_cpumask_lookup_table[index] = mask;
1147
1148 if (numa_debug) {
1149 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1150 for_each_cpu_mask(cpu, mask)
1151 printk("%d ", cpu);
1152 printk("]\n");
1153 }
1154
1155 return numa_attach_mlgroup(md, grp, index);
1156 }
1157
1158 static int __init numa_parse_mdesc(void)
1159 {
1160 struct mdesc_handle *md = mdesc_grab();
1161 int i, err, count;
1162 u64 node;
1163
1164 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1165 if (node == MDESC_NODE_NULL) {
1166 mdesc_release(md);
1167 return -ENOENT;
1168 }
1169
1170 err = grab_mblocks(md);
1171 if (err < 0)
1172 goto out;
1173
1174 err = grab_mlgroups(md);
1175 if (err < 0)
1176 goto out;
1177
1178 count = 0;
1179 mdesc_for_each_node_by_name(md, node, "group") {
1180 err = numa_parse_mdesc_group(md, node, count);
1181 if (err < 0)
1182 break;
1183 count++;
1184 }
1185
1186 add_node_ranges();
1187
1188 for (i = 0; i < num_node_masks; i++) {
1189 allocate_node_data(i);
1190 node_set_online(i);
1191 }
1192
1193 err = 0;
1194 out:
1195 mdesc_release(md);
1196 return err;
1197 }
1198
1199 static int __init numa_parse_jbus(void)
1200 {
1201 unsigned long cpu, index;
1202
1203 /* NUMA node id is encoded in bits 36 and higher, and there is
1204 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1205 */
1206 index = 0;
1207 for_each_present_cpu(cpu) {
1208 numa_cpu_lookup_table[cpu] = index;
1209 numa_cpumask_lookup_table[index] = cpumask_of_cpu(cpu);
1210 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1211 node_masks[index].val = cpu << 36UL;
1212
1213 index++;
1214 }
1215 num_node_masks = index;
1216
1217 add_node_ranges();
1218
1219 for (index = 0; index < num_node_masks; index++) {
1220 allocate_node_data(index);
1221 node_set_online(index);
1222 }
1223
1224 return 0;
1225 }
1226
1227 static int __init numa_parse_sun4u(void)
1228 {
1229 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1230 unsigned long ver;
1231
1232 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1233 if ((ver >> 32UL) == __JALAPENO_ID ||
1234 (ver >> 32UL) == __SERRANO_ID)
1235 return numa_parse_jbus();
1236 }
1237 return -1;
1238 }
1239
1240 static int __init bootmem_init_numa(void)
1241 {
1242 int err = -1;
1243
1244 numadbg("bootmem_init_numa()\n");
1245
1246 if (numa_enabled) {
1247 if (tlb_type == hypervisor)
1248 err = numa_parse_mdesc();
1249 else
1250 err = numa_parse_sun4u();
1251 }
1252 return err;
1253 }
1254
1255 #else
1256
1257 static int bootmem_init_numa(void)
1258 {
1259 return -1;
1260 }
1261
1262 #endif
1263
1264 static void __init bootmem_init_nonnuma(void)
1265 {
1266 unsigned long top_of_ram = lmb_end_of_DRAM();
1267 unsigned long total_ram = lmb_phys_mem_size();
1268 unsigned int i;
1269
1270 numadbg("bootmem_init_nonnuma()\n");
1271
1272 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1273 top_of_ram, total_ram);
1274 printk(KERN_INFO "Memory hole size: %ldMB\n",
1275 (top_of_ram - total_ram) >> 20);
1276
1277 init_node_masks_nonnuma();
1278
1279 for (i = 0; i < lmb.memory.cnt; i++) {
1280 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1281 unsigned long start_pfn, end_pfn;
1282
1283 if (!size)
1284 continue;
1285
1286 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
1287 end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i);
1288 add_active_range(0, start_pfn, end_pfn);
1289 }
1290
1291 allocate_node_data(0);
1292
1293 node_set_online(0);
1294 }
1295
1296 static void __init reserve_range_in_node(int nid, unsigned long start,
1297 unsigned long end)
1298 {
1299 numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1300 nid, start, end);
1301 while (start < end) {
1302 unsigned long this_end;
1303 int n;
1304
1305 this_end = nid_range(start, end, &n);
1306 if (n == nid) {
1307 numadbg(" MATCH reserving range [%lx:%lx]\n",
1308 start, this_end);
1309 reserve_bootmem_node(NODE_DATA(nid), start,
1310 (this_end - start), BOOTMEM_DEFAULT);
1311 } else
1312 numadbg(" NO MATCH, advancing start to %lx\n",
1313 this_end);
1314
1315 start = this_end;
1316 }
1317 }
1318
1319 static void __init trim_reserved_in_node(int nid)
1320 {
1321 int i;
1322
1323 numadbg(" trim_reserved_in_node(%d)\n", nid);
1324
1325 for (i = 0; i < lmb.reserved.cnt; i++) {
1326 unsigned long start = lmb.reserved.region[i].base;
1327 unsigned long size = lmb_size_bytes(&lmb.reserved, i);
1328 unsigned long end = start + size;
1329
1330 reserve_range_in_node(nid, start, end);
1331 }
1332 }
1333
1334 static void __init bootmem_init_one_node(int nid)
1335 {
1336 struct pglist_data *p;
1337
1338 numadbg("bootmem_init_one_node(%d)\n", nid);
1339
1340 p = NODE_DATA(nid);
1341
1342 if (p->node_spanned_pages) {
1343 unsigned long paddr = node_masks[nid].bootmem_paddr;
1344 unsigned long end_pfn;
1345
1346 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1347
1348 numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n",
1349 nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1350
1351 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1352 p->node_start_pfn, end_pfn);
1353
1354 numadbg(" free_bootmem_with_active_regions(%d, %lx)\n",
1355 nid, end_pfn);
1356 free_bootmem_with_active_regions(nid, end_pfn);
1357
1358 trim_reserved_in_node(nid);
1359
1360 numadbg(" sparse_memory_present_with_active_regions(%d)\n",
1361 nid);
1362 sparse_memory_present_with_active_regions(nid);
1363 }
1364 }
1365
1366 static unsigned long __init bootmem_init(unsigned long phys_base)
1367 {
1368 unsigned long end_pfn;
1369 int nid;
1370
1371 end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
1372 max_pfn = max_low_pfn = end_pfn;
1373 min_low_pfn = (phys_base >> PAGE_SHIFT);
1374
1375 if (bootmem_init_numa() < 0)
1376 bootmem_init_nonnuma();
1377
1378 /* XXX cpu notifier XXX */
1379
1380 for_each_online_node(nid)
1381 bootmem_init_one_node(nid);
1382
1383 sparse_init();
1384
1385 return end_pfn;
1386 }
1387
1388 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1389 static int pall_ents __initdata;
1390
1391 #ifdef CONFIG_DEBUG_PAGEALLOC
1392 static unsigned long __ref kernel_map_range(unsigned long pstart,
1393 unsigned long pend, pgprot_t prot)
1394 {
1395 unsigned long vstart = PAGE_OFFSET + pstart;
1396 unsigned long vend = PAGE_OFFSET + pend;
1397 unsigned long alloc_bytes = 0UL;
1398
1399 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1400 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1401 vstart, vend);
1402 prom_halt();
1403 }
1404
1405 while (vstart < vend) {
1406 unsigned long this_end, paddr = __pa(vstart);
1407 pgd_t *pgd = pgd_offset_k(vstart);
1408 pud_t *pud;
1409 pmd_t *pmd;
1410 pte_t *pte;
1411
1412 pud = pud_offset(pgd, vstart);
1413 if (pud_none(*pud)) {
1414 pmd_t *new;
1415
1416 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1417 alloc_bytes += PAGE_SIZE;
1418 pud_populate(&init_mm, pud, new);
1419 }
1420
1421 pmd = pmd_offset(pud, vstart);
1422 if (!pmd_present(*pmd)) {
1423 pte_t *new;
1424
1425 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1426 alloc_bytes += PAGE_SIZE;
1427 pmd_populate_kernel(&init_mm, pmd, new);
1428 }
1429
1430 pte = pte_offset_kernel(pmd, vstart);
1431 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1432 if (this_end > vend)
1433 this_end = vend;
1434
1435 while (vstart < this_end) {
1436 pte_val(*pte) = (paddr | pgprot_val(prot));
1437
1438 vstart += PAGE_SIZE;
1439 paddr += PAGE_SIZE;
1440 pte++;
1441 }
1442 }
1443
1444 return alloc_bytes;
1445 }
1446
1447 extern unsigned int kvmap_linear_patch[1];
1448 #endif /* CONFIG_DEBUG_PAGEALLOC */
1449
1450 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1451 {
1452 const unsigned long shift_256MB = 28;
1453 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1454 const unsigned long size_256MB = (1UL << shift_256MB);
1455
1456 while (start < end) {
1457 long remains;
1458
1459 remains = end - start;
1460 if (remains < size_256MB)
1461 break;
1462
1463 if (start & mask_256MB) {
1464 start = (start + size_256MB) & ~mask_256MB;
1465 continue;
1466 }
1467
1468 while (remains >= size_256MB) {
1469 unsigned long index = start >> shift_256MB;
1470
1471 __set_bit(index, kpte_linear_bitmap);
1472
1473 start += size_256MB;
1474 remains -= size_256MB;
1475 }
1476 }
1477 }
1478
1479 static void __init init_kpte_bitmap(void)
1480 {
1481 unsigned long i;
1482
1483 for (i = 0; i < pall_ents; i++) {
1484 unsigned long phys_start, phys_end;
1485
1486 phys_start = pall[i].phys_addr;
1487 phys_end = phys_start + pall[i].reg_size;
1488
1489 mark_kpte_bitmap(phys_start, phys_end);
1490 }
1491 }
1492
1493 static void __init kernel_physical_mapping_init(void)
1494 {
1495 #ifdef CONFIG_DEBUG_PAGEALLOC
1496 unsigned long i, mem_alloced = 0UL;
1497
1498 for (i = 0; i < pall_ents; i++) {
1499 unsigned long phys_start, phys_end;
1500
1501 phys_start = pall[i].phys_addr;
1502 phys_end = phys_start + pall[i].reg_size;
1503
1504 mem_alloced += kernel_map_range(phys_start, phys_end,
1505 PAGE_KERNEL);
1506 }
1507
1508 printk("Allocated %ld bytes for kernel page tables.\n",
1509 mem_alloced);
1510
1511 kvmap_linear_patch[0] = 0x01000000; /* nop */
1512 flushi(&kvmap_linear_patch[0]);
1513
1514 __flush_tlb_all();
1515 #endif
1516 }
1517
1518 #ifdef CONFIG_DEBUG_PAGEALLOC
1519 void kernel_map_pages(struct page *page, int numpages, int enable)
1520 {
1521 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1522 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1523
1524 kernel_map_range(phys_start, phys_end,
1525 (enable ? PAGE_KERNEL : __pgprot(0)));
1526
1527 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1528 PAGE_OFFSET + phys_end);
1529
1530 /* we should perform an IPI and flush all tlbs,
1531 * but that can deadlock->flush only current cpu.
1532 */
1533 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1534 PAGE_OFFSET + phys_end);
1535 }
1536 #endif
1537
1538 unsigned long __init find_ecache_flush_span(unsigned long size)
1539 {
1540 int i;
1541
1542 for (i = 0; i < pavail_ents; i++) {
1543 if (pavail[i].reg_size >= size)
1544 return pavail[i].phys_addr;
1545 }
1546
1547 return ~0UL;
1548 }
1549
1550 static void __init tsb_phys_patch(void)
1551 {
1552 struct tsb_ldquad_phys_patch_entry *pquad;
1553 struct tsb_phys_patch_entry *p;
1554
1555 pquad = &__tsb_ldquad_phys_patch;
1556 while (pquad < &__tsb_ldquad_phys_patch_end) {
1557 unsigned long addr = pquad->addr;
1558
1559 if (tlb_type == hypervisor)
1560 *(unsigned int *) addr = pquad->sun4v_insn;
1561 else
1562 *(unsigned int *) addr = pquad->sun4u_insn;
1563 wmb();
1564 __asm__ __volatile__("flush %0"
1565 : /* no outputs */
1566 : "r" (addr));
1567
1568 pquad++;
1569 }
1570
1571 p = &__tsb_phys_patch;
1572 while (p < &__tsb_phys_patch_end) {
1573 unsigned long addr = p->addr;
1574
1575 *(unsigned int *) addr = p->insn;
1576 wmb();
1577 __asm__ __volatile__("flush %0"
1578 : /* no outputs */
1579 : "r" (addr));
1580
1581 p++;
1582 }
1583 }
1584
1585 /* Don't mark as init, we give this to the Hypervisor. */
1586 #ifndef CONFIG_DEBUG_PAGEALLOC
1587 #define NUM_KTSB_DESCR 2
1588 #else
1589 #define NUM_KTSB_DESCR 1
1590 #endif
1591 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1592 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1593
1594 static void __init sun4v_ktsb_init(void)
1595 {
1596 unsigned long ktsb_pa;
1597
1598 /* First KTSB for PAGE_SIZE mappings. */
1599 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1600
1601 switch (PAGE_SIZE) {
1602 case 8 * 1024:
1603 default:
1604 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1605 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1606 break;
1607
1608 case 64 * 1024:
1609 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1610 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1611 break;
1612
1613 case 512 * 1024:
1614 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1615 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1616 break;
1617
1618 case 4 * 1024 * 1024:
1619 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1620 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1621 break;
1622 };
1623
1624 ktsb_descr[0].assoc = 1;
1625 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1626 ktsb_descr[0].ctx_idx = 0;
1627 ktsb_descr[0].tsb_base = ktsb_pa;
1628 ktsb_descr[0].resv = 0;
1629
1630 #ifndef CONFIG_DEBUG_PAGEALLOC
1631 /* Second KTSB for 4MB/256MB mappings. */
1632 ktsb_pa = (kern_base +
1633 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1634
1635 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1636 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1637 HV_PGSZ_MASK_256MB);
1638 ktsb_descr[1].assoc = 1;
1639 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1640 ktsb_descr[1].ctx_idx = 0;
1641 ktsb_descr[1].tsb_base = ktsb_pa;
1642 ktsb_descr[1].resv = 0;
1643 #endif
1644 }
1645
1646 void __cpuinit sun4v_ktsb_register(void)
1647 {
1648 unsigned long pa, ret;
1649
1650 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1651
1652 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1653 if (ret != 0) {
1654 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1655 "errors with %lx\n", pa, ret);
1656 prom_halt();
1657 }
1658 }
1659
1660 /* paging_init() sets up the page tables */
1661
1662 static unsigned long last_valid_pfn;
1663 pgd_t swapper_pg_dir[2048];
1664
1665 static void sun4u_pgprot_init(void);
1666 static void sun4v_pgprot_init(void);
1667
1668 /* Dummy function */
1669 void __init setup_per_cpu_areas(void)
1670 {
1671 }
1672
1673 void __init paging_init(void)
1674 {
1675 unsigned long end_pfn, shift, phys_base;
1676 unsigned long real_end, i;
1677
1678 /* These build time checkes make sure that the dcache_dirty_cpu()
1679 * page->flags usage will work.
1680 *
1681 * When a page gets marked as dcache-dirty, we store the
1682 * cpu number starting at bit 32 in the page->flags. Also,
1683 * functions like clear_dcache_dirty_cpu use the cpu mask
1684 * in 13-bit signed-immediate instruction fields.
1685 */
1686
1687 /*
1688 * Page flags must not reach into upper 32 bits that are used
1689 * for the cpu number
1690 */
1691 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1692
1693 /*
1694 * The bit fields placed in the high range must not reach below
1695 * the 32 bit boundary. Otherwise we cannot place the cpu field
1696 * at the 32 bit boundary.
1697 */
1698 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1699 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1700
1701 BUILD_BUG_ON(NR_CPUS > 4096);
1702
1703 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1704 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1705
1706 /* Invalidate both kernel TSBs. */
1707 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1708 #ifndef CONFIG_DEBUG_PAGEALLOC
1709 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1710 #endif
1711
1712 if (tlb_type == hypervisor)
1713 sun4v_pgprot_init();
1714 else
1715 sun4u_pgprot_init();
1716
1717 if (tlb_type == cheetah_plus ||
1718 tlb_type == hypervisor)
1719 tsb_phys_patch();
1720
1721 if (tlb_type == hypervisor) {
1722 sun4v_patch_tlb_handlers();
1723 sun4v_ktsb_init();
1724 }
1725
1726 lmb_init();
1727
1728 /* Find available physical memory...
1729 *
1730 * Read it twice in order to work around a bug in openfirmware.
1731 * The call to grab this table itself can cause openfirmware to
1732 * allocate memory, which in turn can take away some space from
1733 * the list of available memory. Reading it twice makes sure
1734 * we really do get the final value.
1735 */
1736 read_obp_translations();
1737 read_obp_memory("reg", &pall[0], &pall_ents);
1738 read_obp_memory("available", &pavail[0], &pavail_ents);
1739 read_obp_memory("available", &pavail[0], &pavail_ents);
1740
1741 phys_base = 0xffffffffffffffffUL;
1742 for (i = 0; i < pavail_ents; i++) {
1743 phys_base = min(phys_base, pavail[i].phys_addr);
1744 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1745 }
1746
1747 lmb_reserve(kern_base, kern_size);
1748
1749 find_ramdisk(phys_base);
1750
1751 lmb_enforce_memory_limit(cmdline_memory_size);
1752
1753 lmb_analyze();
1754 lmb_dump_all();
1755
1756 set_bit(0, mmu_context_bmap);
1757
1758 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1759
1760 real_end = (unsigned long)_end;
1761 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1762 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1763 num_kernel_image_mappings);
1764
1765 /* Set kernel pgd to upper alias so physical page computations
1766 * work.
1767 */
1768 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1769
1770 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1771
1772 /* Now can init the kernel/bad page tables. */
1773 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1774 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1775
1776 inherit_prom_mappings();
1777
1778 init_kpte_bitmap();
1779
1780 /* Ok, we can use our TLB miss and window trap handlers safely. */
1781 setup_tba();
1782
1783 __flush_tlb_all();
1784
1785 if (tlb_type == hypervisor)
1786 sun4v_ktsb_register();
1787
1788 /* We must setup the per-cpu areas before we pull in the
1789 * PROM and the MDESC. The code there fills in cpu and
1790 * other information into per-cpu data structures.
1791 */
1792 real_setup_per_cpu_areas();
1793
1794 prom_build_devicetree();
1795
1796 if (tlb_type == hypervisor)
1797 sun4v_mdesc_init();
1798
1799 /* Once the OF device tree and MDESC have been setup, we know
1800 * the list of possible cpus. Therefore we can allocate the
1801 * IRQ stacks.
1802 */
1803 for_each_possible_cpu(i) {
1804 /* XXX Use node local allocations... XXX */
1805 softirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1806 hardirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1807 }
1808
1809 /* Setup bootmem... */
1810 last_valid_pfn = end_pfn = bootmem_init(phys_base);
1811
1812 #ifndef CONFIG_NEED_MULTIPLE_NODES
1813 max_mapnr = last_valid_pfn;
1814 #endif
1815 kernel_physical_mapping_init();
1816
1817 {
1818 unsigned long max_zone_pfns[MAX_NR_ZONES];
1819
1820 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1821
1822 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1823
1824 free_area_init_nodes(max_zone_pfns);
1825 }
1826
1827 printk("Booting Linux...\n");
1828 }
1829
1830 int __init page_in_phys_avail(unsigned long paddr)
1831 {
1832 int i;
1833
1834 paddr &= PAGE_MASK;
1835
1836 for (i = 0; i < pavail_ents; i++) {
1837 unsigned long start, end;
1838
1839 start = pavail[i].phys_addr;
1840 end = start + pavail[i].reg_size;
1841
1842 if (paddr >= start && paddr < end)
1843 return 1;
1844 }
1845 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1846 return 1;
1847 #ifdef CONFIG_BLK_DEV_INITRD
1848 if (paddr >= __pa(initrd_start) &&
1849 paddr < __pa(PAGE_ALIGN(initrd_end)))
1850 return 1;
1851 #endif
1852
1853 return 0;
1854 }
1855
1856 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1857 static int pavail_rescan_ents __initdata;
1858
1859 /* Certain OBP calls, such as fetching "available" properties, can
1860 * claim physical memory. So, along with initializing the valid
1861 * address bitmap, what we do here is refetch the physical available
1862 * memory list again, and make sure it provides at least as much
1863 * memory as 'pavail' does.
1864 */
1865 static void __init setup_valid_addr_bitmap_from_pavail(void)
1866 {
1867 int i;
1868
1869 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1870
1871 for (i = 0; i < pavail_ents; i++) {
1872 unsigned long old_start, old_end;
1873
1874 old_start = pavail[i].phys_addr;
1875 old_end = old_start + pavail[i].reg_size;
1876 while (old_start < old_end) {
1877 int n;
1878
1879 for (n = 0; n < pavail_rescan_ents; n++) {
1880 unsigned long new_start, new_end;
1881
1882 new_start = pavail_rescan[n].phys_addr;
1883 new_end = new_start +
1884 pavail_rescan[n].reg_size;
1885
1886 if (new_start <= old_start &&
1887 new_end >= (old_start + PAGE_SIZE)) {
1888 set_bit(old_start >> 22,
1889 sparc64_valid_addr_bitmap);
1890 goto do_next_page;
1891 }
1892 }
1893
1894 prom_printf("mem_init: Lost memory in pavail\n");
1895 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1896 pavail[i].phys_addr,
1897 pavail[i].reg_size);
1898 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1899 pavail_rescan[i].phys_addr,
1900 pavail_rescan[i].reg_size);
1901 prom_printf("mem_init: Cannot continue, aborting.\n");
1902 prom_halt();
1903
1904 do_next_page:
1905 old_start += PAGE_SIZE;
1906 }
1907 }
1908 }
1909
1910 void __init mem_init(void)
1911 {
1912 unsigned long codepages, datapages, initpages;
1913 unsigned long addr, last;
1914 int i;
1915
1916 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1917 i += 1;
1918 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1919 if (sparc64_valid_addr_bitmap == NULL) {
1920 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1921 prom_halt();
1922 }
1923 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1924
1925 addr = PAGE_OFFSET + kern_base;
1926 last = PAGE_ALIGN(kern_size) + addr;
1927 while (addr < last) {
1928 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1929 addr += PAGE_SIZE;
1930 }
1931
1932 setup_valid_addr_bitmap_from_pavail();
1933
1934 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1935
1936 #ifdef CONFIG_NEED_MULTIPLE_NODES
1937 for_each_online_node(i) {
1938 if (NODE_DATA(i)->node_spanned_pages != 0) {
1939 totalram_pages +=
1940 free_all_bootmem_node(NODE_DATA(i));
1941 }
1942 }
1943 #else
1944 totalram_pages = free_all_bootmem();
1945 #endif
1946
1947 /* We subtract one to account for the mem_map_zero page
1948 * allocated below.
1949 */
1950 totalram_pages -= 1;
1951 num_physpages = totalram_pages;
1952
1953 /*
1954 * Set up the zero page, mark it reserved, so that page count
1955 * is not manipulated when freeing the page from user ptes.
1956 */
1957 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1958 if (mem_map_zero == NULL) {
1959 prom_printf("paging_init: Cannot alloc zero page.\n");
1960 prom_halt();
1961 }
1962 SetPageReserved(mem_map_zero);
1963
1964 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1965 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1966 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1967 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1968 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1969 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1970
1971 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1972 nr_free_pages() << (PAGE_SHIFT-10),
1973 codepages << (PAGE_SHIFT-10),
1974 datapages << (PAGE_SHIFT-10),
1975 initpages << (PAGE_SHIFT-10),
1976 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1977
1978 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1979 cheetah_ecache_flush_init();
1980 }
1981
1982 void free_initmem(void)
1983 {
1984 unsigned long addr, initend;
1985 int do_free = 1;
1986
1987 /* If the physical memory maps were trimmed by kernel command
1988 * line options, don't even try freeing this initmem stuff up.
1989 * The kernel image could have been in the trimmed out region
1990 * and if so the freeing below will free invalid page structs.
1991 */
1992 if (cmdline_memory_size)
1993 do_free = 0;
1994
1995 /*
1996 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1997 */
1998 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1999 initend = (unsigned long)(__init_end) & PAGE_MASK;
2000 for (; addr < initend; addr += PAGE_SIZE) {
2001 unsigned long page;
2002 struct page *p;
2003
2004 page = (addr +
2005 ((unsigned long) __va(kern_base)) -
2006 ((unsigned long) KERNBASE));
2007 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2008
2009 if (do_free) {
2010 p = virt_to_page(page);
2011
2012 ClearPageReserved(p);
2013 init_page_count(p);
2014 __free_page(p);
2015 num_physpages++;
2016 totalram_pages++;
2017 }
2018 }
2019 }
2020
2021 #ifdef CONFIG_BLK_DEV_INITRD
2022 void free_initrd_mem(unsigned long start, unsigned long end)
2023 {
2024 if (start < end)
2025 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2026 for (; start < end; start += PAGE_SIZE) {
2027 struct page *p = virt_to_page(start);
2028
2029 ClearPageReserved(p);
2030 init_page_count(p);
2031 __free_page(p);
2032 num_physpages++;
2033 totalram_pages++;
2034 }
2035 }
2036 #endif
2037
2038 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2039 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2040 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2041 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2042 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2043 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2044
2045 pgprot_t PAGE_KERNEL __read_mostly;
2046 EXPORT_SYMBOL(PAGE_KERNEL);
2047
2048 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2049 pgprot_t PAGE_COPY __read_mostly;
2050
2051 pgprot_t PAGE_SHARED __read_mostly;
2052 EXPORT_SYMBOL(PAGE_SHARED);
2053
2054 unsigned long pg_iobits __read_mostly;
2055
2056 unsigned long _PAGE_IE __read_mostly;
2057 EXPORT_SYMBOL(_PAGE_IE);
2058
2059 unsigned long _PAGE_E __read_mostly;
2060 EXPORT_SYMBOL(_PAGE_E);
2061
2062 unsigned long _PAGE_CACHE __read_mostly;
2063 EXPORT_SYMBOL(_PAGE_CACHE);
2064
2065 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2066 unsigned long vmemmap_table[VMEMMAP_SIZE];
2067
2068 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2069 {
2070 unsigned long vstart = (unsigned long) start;
2071 unsigned long vend = (unsigned long) (start + nr);
2072 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2073 unsigned long phys_end = (vend - VMEMMAP_BASE);
2074 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2075 unsigned long end = VMEMMAP_ALIGN(phys_end);
2076 unsigned long pte_base;
2077
2078 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2079 _PAGE_CP_4U | _PAGE_CV_4U |
2080 _PAGE_P_4U | _PAGE_W_4U);
2081 if (tlb_type == hypervisor)
2082 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2083 _PAGE_CP_4V | _PAGE_CV_4V |
2084 _PAGE_P_4V | _PAGE_W_4V);
2085
2086 for (; addr < end; addr += VMEMMAP_CHUNK) {
2087 unsigned long *vmem_pp =
2088 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2089 void *block;
2090
2091 if (!(*vmem_pp & _PAGE_VALID)) {
2092 block = vmemmap_alloc_block(1UL << 22, node);
2093 if (!block)
2094 return -ENOMEM;
2095
2096 *vmem_pp = pte_base | __pa(block);
2097
2098 printk(KERN_INFO "[%p-%p] page_structs=%lu "
2099 "node=%d entry=%lu/%lu\n", start, block, nr,
2100 node,
2101 addr >> VMEMMAP_CHUNK_SHIFT,
2102 VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
2103 }
2104 }
2105 return 0;
2106 }
2107 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2108
2109 static void prot_init_common(unsigned long page_none,
2110 unsigned long page_shared,
2111 unsigned long page_copy,
2112 unsigned long page_readonly,
2113 unsigned long page_exec_bit)
2114 {
2115 PAGE_COPY = __pgprot(page_copy);
2116 PAGE_SHARED = __pgprot(page_shared);
2117
2118 protection_map[0x0] = __pgprot(page_none);
2119 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2120 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2121 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2122 protection_map[0x4] = __pgprot(page_readonly);
2123 protection_map[0x5] = __pgprot(page_readonly);
2124 protection_map[0x6] = __pgprot(page_copy);
2125 protection_map[0x7] = __pgprot(page_copy);
2126 protection_map[0x8] = __pgprot(page_none);
2127 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2128 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2129 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2130 protection_map[0xc] = __pgprot(page_readonly);
2131 protection_map[0xd] = __pgprot(page_readonly);
2132 protection_map[0xe] = __pgprot(page_shared);
2133 protection_map[0xf] = __pgprot(page_shared);
2134 }
2135
2136 static void __init sun4u_pgprot_init(void)
2137 {
2138 unsigned long page_none, page_shared, page_copy, page_readonly;
2139 unsigned long page_exec_bit;
2140
2141 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2142 _PAGE_CACHE_4U | _PAGE_P_4U |
2143 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2144 _PAGE_EXEC_4U);
2145 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2146 _PAGE_CACHE_4U | _PAGE_P_4U |
2147 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2148 _PAGE_EXEC_4U | _PAGE_L_4U);
2149
2150 _PAGE_IE = _PAGE_IE_4U;
2151 _PAGE_E = _PAGE_E_4U;
2152 _PAGE_CACHE = _PAGE_CACHE_4U;
2153
2154 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2155 __ACCESS_BITS_4U | _PAGE_E_4U);
2156
2157 #ifdef CONFIG_DEBUG_PAGEALLOC
2158 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2159 0xfffff80000000000UL;
2160 #else
2161 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2162 0xfffff80000000000UL;
2163 #endif
2164 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2165 _PAGE_P_4U | _PAGE_W_4U);
2166
2167 /* XXX Should use 256MB on Panther. XXX */
2168 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2169
2170 _PAGE_SZBITS = _PAGE_SZBITS_4U;
2171 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2172 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2173 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2174
2175
2176 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2177 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2178 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2179 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2180 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2181 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2182 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2183
2184 page_exec_bit = _PAGE_EXEC_4U;
2185
2186 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2187 page_exec_bit);
2188 }
2189
2190 static void __init sun4v_pgprot_init(void)
2191 {
2192 unsigned long page_none, page_shared, page_copy, page_readonly;
2193 unsigned long page_exec_bit;
2194
2195 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2196 _PAGE_CACHE_4V | _PAGE_P_4V |
2197 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2198 _PAGE_EXEC_4V);
2199 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2200
2201 _PAGE_IE = _PAGE_IE_4V;
2202 _PAGE_E = _PAGE_E_4V;
2203 _PAGE_CACHE = _PAGE_CACHE_4V;
2204
2205 #ifdef CONFIG_DEBUG_PAGEALLOC
2206 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2207 0xfffff80000000000UL;
2208 #else
2209 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2210 0xfffff80000000000UL;
2211 #endif
2212 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2213 _PAGE_P_4V | _PAGE_W_4V);
2214
2215 #ifdef CONFIG_DEBUG_PAGEALLOC
2216 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2217 0xfffff80000000000UL;
2218 #else
2219 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2220 0xfffff80000000000UL;
2221 #endif
2222 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2223 _PAGE_P_4V | _PAGE_W_4V);
2224
2225 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2226 __ACCESS_BITS_4V | _PAGE_E_4V);
2227
2228 _PAGE_SZBITS = _PAGE_SZBITS_4V;
2229 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2230 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2231 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2232 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2233
2234 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2235 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2236 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2237 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2238 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2239 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2240 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2241
2242 page_exec_bit = _PAGE_EXEC_4V;
2243
2244 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2245 page_exec_bit);
2246 }
2247
2248 unsigned long pte_sz_bits(unsigned long sz)
2249 {
2250 if (tlb_type == hypervisor) {
2251 switch (sz) {
2252 case 8 * 1024:
2253 default:
2254 return _PAGE_SZ8K_4V;
2255 case 64 * 1024:
2256 return _PAGE_SZ64K_4V;
2257 case 512 * 1024:
2258 return _PAGE_SZ512K_4V;
2259 case 4 * 1024 * 1024:
2260 return _PAGE_SZ4MB_4V;
2261 };
2262 } else {
2263 switch (sz) {
2264 case 8 * 1024:
2265 default:
2266 return _PAGE_SZ8K_4U;
2267 case 64 * 1024:
2268 return _PAGE_SZ64K_4U;
2269 case 512 * 1024:
2270 return _PAGE_SZ512K_4U;
2271 case 4 * 1024 * 1024:
2272 return _PAGE_SZ4MB_4U;
2273 };
2274 }
2275 }
2276
2277 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2278 {
2279 pte_t pte;
2280
2281 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2282 pte_val(pte) |= (((unsigned long)space) << 32);
2283 pte_val(pte) |= pte_sz_bits(page_size);
2284
2285 return pte;
2286 }
2287
2288 static unsigned long kern_large_tte(unsigned long paddr)
2289 {
2290 unsigned long val;
2291
2292 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2293 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2294 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2295 if (tlb_type == hypervisor)
2296 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2297 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2298 _PAGE_EXEC_4V | _PAGE_W_4V);
2299
2300 return val | paddr;
2301 }
2302
2303 /* If not locked, zap it. */
2304 void __flush_tlb_all(void)
2305 {
2306 unsigned long pstate;
2307 int i;
2308
2309 __asm__ __volatile__("flushw\n\t"
2310 "rdpr %%pstate, %0\n\t"
2311 "wrpr %0, %1, %%pstate"
2312 : "=r" (pstate)
2313 : "i" (PSTATE_IE));
2314 if (tlb_type == hypervisor) {
2315 sun4v_mmu_demap_all();
2316 } else if (tlb_type == spitfire) {
2317 for (i = 0; i < 64; i++) {
2318 /* Spitfire Errata #32 workaround */
2319 /* NOTE: Always runs on spitfire, so no
2320 * cheetah+ page size encodings.
2321 */
2322 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2323 "flush %%g6"
2324 : /* No outputs */
2325 : "r" (0),
2326 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2327
2328 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2329 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2330 "membar #Sync"
2331 : /* no outputs */
2332 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2333 spitfire_put_dtlb_data(i, 0x0UL);
2334 }
2335
2336 /* Spitfire Errata #32 workaround */
2337 /* NOTE: Always runs on spitfire, so no
2338 * cheetah+ page size encodings.
2339 */
2340 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2341 "flush %%g6"
2342 : /* No outputs */
2343 : "r" (0),
2344 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2345
2346 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2347 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2348 "membar #Sync"
2349 : /* no outputs */
2350 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2351 spitfire_put_itlb_data(i, 0x0UL);
2352 }
2353 }
2354 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2355 cheetah_flush_dtlb_all();
2356 cheetah_flush_itlb_all();
2357 }
2358 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2359 : : "r" (pstate));
2360 }
Support for the Chinese Samsung S3C2440 based development boards