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[PATCH] update max_sectors documentation
[linux-2.6/mini2440.git] / drivers / scsi / sata_qstor.c
blob9ffe1ef0d20511eb158fa34a17d05bb672a96877
1 /*
2 * sata_qstor.c - Pacific Digital Corporation QStor SATA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Pacific Digital Corporation.
7 * (OSL/GPL code release authorized by Jalil Fadavi).
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; see the file COPYING. If not, write to
22 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 *
25 * libata documentation is available via 'make {ps|pdf}docs',
26 * as Documentation/DocBook/libata.*
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/sched.h>
38 #include <linux/device.h>
39 #include <scsi/scsi_host.h>
40 #include <asm/io.h>
41 #include <linux/libata.h>
42
43 #define DRV_NAME "sata_qstor"
44 #define DRV_VERSION "0.05"
45
46 enum {
47 QS_PORTS = 4,
48 QS_MAX_PRD = LIBATA_MAX_PRD,
49 QS_CPB_ORDER = 6,
50 QS_CPB_BYTES = (1 << QS_CPB_ORDER),
51 QS_PRD_BYTES = QS_MAX_PRD * 16,
52 QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES,
53
54 /* global register offsets */
55 QS_HCF_CNFG3 = 0x0003, /* host configuration offset */
56 QS_HID_HPHY = 0x0004, /* host physical interface info */
57 QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */
58 QS_HST_SFF = 0x0100, /* host status fifo offset */
59 QS_HVS_SERD3 = 0x0393, /* PHY enable offset */
60
61 /* global control bits */
62 QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */
63 QS_CNFG3_GSRST = 0x01, /* global chip reset */
64 QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/
65
66 /* per-channel register offsets */
67 QS_CCF_CPBA = 0x0710, /* chan CPB base address */
68 QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */
69 QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */
70 QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */
71 QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */
72 QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */
73 QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */
74 QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */
75 QS_CCT_CFF = 0x0a00, /* chan command fifo offset */
76
77 /* channel control bits */
78 QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */
79 QS_CTR0_CLER = (1 << 2), /* clear channel errors */
80 QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */
81 QS_CTR1_RCHN = (1 << 4), /* reset channel logic */
82 QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */
83
84 /* pkt sub-field headers */
85 QS_HCB_HDR = 0x01, /* Host Control Block header */
86 QS_DCB_HDR = 0x02, /* Device Control Block header */
87
88 /* pkt HCB flag bits */
89 QS_HF_DIRO = (1 << 0), /* data DIRection Out */
90 QS_HF_DAT = (1 << 3), /* DATa pkt */
91 QS_HF_IEN = (1 << 4), /* Interrupt ENable */
92 QS_HF_VLD = (1 << 5), /* VaLiD pkt */
93
94 /* pkt DCB flag bits */
95 QS_DF_PORD = (1 << 2), /* Pio OR Dma */
96 QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */
97
98 /* PCI device IDs */
99 board_2068_idx = 0, /* QStor 4-port SATA/RAID */
100 };
101
102 enum {
103 QS_DMA_BOUNDARY = ~0UL
104 };
105
106 typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t;
107
108 struct qs_port_priv {
109 u8 *pkt;
110 dma_addr_t pkt_dma;
111 qs_state_t state;
112 };
113
114 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg);
115 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
116 static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
117 static irqreturn_t qs_intr (int irq, void *dev_instance, struct pt_regs *regs);
118 static int qs_port_start(struct ata_port *ap);
119 static void qs_host_stop(struct ata_host_set *host_set);
120 static void qs_port_stop(struct ata_port *ap);
121 static void qs_phy_reset(struct ata_port *ap);
122 static void qs_qc_prep(struct ata_queued_cmd *qc);
123 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc);
124 static int qs_check_atapi_dma(struct ata_queued_cmd *qc);
125 static void qs_bmdma_stop(struct ata_queued_cmd *qc);
126 static u8 qs_bmdma_status(struct ata_port *ap);
127 static void qs_irq_clear(struct ata_port *ap);
128 static void qs_eng_timeout(struct ata_port *ap);
129
130 static struct scsi_host_template qs_ata_sht = {
131 .module = THIS_MODULE,
132 .name = DRV_NAME,
133 .ioctl = ata_scsi_ioctl,
134 .queuecommand = ata_scsi_queuecmd,
135 .eh_strategy_handler = ata_scsi_error,
136 .can_queue = ATA_DEF_QUEUE,
137 .this_id = ATA_SHT_THIS_ID,
138 .sg_tablesize = QS_MAX_PRD,
139 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
140 .emulated = ATA_SHT_EMULATED,
141 //FIXME .use_clustering = ATA_SHT_USE_CLUSTERING,
142 .use_clustering = ENABLE_CLUSTERING,
143 .proc_name = DRV_NAME,
144 .dma_boundary = QS_DMA_BOUNDARY,
145 .slave_configure = ata_scsi_slave_config,
146 .bios_param = ata_std_bios_param,
147 };
148
149 static const struct ata_port_operations qs_ata_ops = {
150 .port_disable = ata_port_disable,
151 .tf_load = ata_tf_load,
152 .tf_read = ata_tf_read,
153 .check_status = ata_check_status,
154 .check_atapi_dma = qs_check_atapi_dma,
155 .exec_command = ata_exec_command,
156 .dev_select = ata_std_dev_select,
157 .phy_reset = qs_phy_reset,
158 .qc_prep = qs_qc_prep,
159 .qc_issue = qs_qc_issue,
160 .eng_timeout = qs_eng_timeout,
161 .irq_handler = qs_intr,
162 .irq_clear = qs_irq_clear,
163 .scr_read = qs_scr_read,
164 .scr_write = qs_scr_write,
165 .port_start = qs_port_start,
166 .port_stop = qs_port_stop,
167 .host_stop = qs_host_stop,
168 .bmdma_stop = qs_bmdma_stop,
169 .bmdma_status = qs_bmdma_status,
170 };
171
172 static const struct ata_port_info qs_port_info[] = {
173 /* board_2068_idx */
174 {
175 .sht = &qs_ata_sht,
176 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
177 ATA_FLAG_SATA_RESET |
178 //FIXME ATA_FLAG_SRST |
179 ATA_FLAG_MMIO,
180 .pio_mask = 0x10, /* pio4 */
181 .udma_mask = 0x7f, /* udma0-6 */
182 .port_ops = &qs_ata_ops,
183 },
184 };
185
186 static const struct pci_device_id qs_ata_pci_tbl[] = {
187 { PCI_VENDOR_ID_PDC, 0x2068, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
188 board_2068_idx },
189
190 { } /* terminate list */
191 };
192
193 static struct pci_driver qs_ata_pci_driver = {
194 .name = DRV_NAME,
195 .id_table = qs_ata_pci_tbl,
196 .probe = qs_ata_init_one,
197 .remove = ata_pci_remove_one,
198 };
199
200 static int qs_check_atapi_dma(struct ata_queued_cmd *qc)
201 {
202 return 1; /* ATAPI DMA not supported */
203 }
204
205 static void qs_bmdma_stop(struct ata_queued_cmd *qc)
206 {
207 /* nothing */
208 }
209
210 static u8 qs_bmdma_status(struct ata_port *ap)
211 {
212 return 0;
213 }
214
215 static void qs_irq_clear(struct ata_port *ap)
216 {
217 /* nothing */
218 }
219
220 static inline void qs_enter_reg_mode(struct ata_port *ap)
221 {
222 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
223
224 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
225 readb(chan + QS_CCT_CTR0); /* flush */
226 }
227
228 static inline void qs_reset_channel_logic(struct ata_port *ap)
229 {
230 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
231
232 writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1);
233 readb(chan + QS_CCT_CTR0); /* flush */
234 qs_enter_reg_mode(ap);
235 }
236
237 static void qs_phy_reset(struct ata_port *ap)
238 {
239 struct qs_port_priv *pp = ap->private_data;
240
241 pp->state = qs_state_idle;
242 qs_reset_channel_logic(ap);
243 sata_phy_reset(ap);
244 }
245
246 static void qs_eng_timeout(struct ata_port *ap)
247 {
248 struct qs_port_priv *pp = ap->private_data;
249
250 if (pp->state != qs_state_idle) /* healthy paranoia */
251 pp->state = qs_state_mmio;
252 qs_reset_channel_logic(ap);
253 ata_eng_timeout(ap);
254 }
255
256 static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg)
257 {
258 if (sc_reg > SCR_CONTROL)
259 return ~0U;
260 return readl((void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
261 }
262
263 static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
264 {
265 if (sc_reg > SCR_CONTROL)
266 return;
267 writel(val, (void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8)));
268 }
269
270 static unsigned int qs_fill_sg(struct ata_queued_cmd *qc)
271 {
272 struct scatterlist *sg;
273 struct ata_port *ap = qc->ap;
274 struct qs_port_priv *pp = ap->private_data;
275 unsigned int nelem;
276 u8 *prd = pp->pkt + QS_CPB_BYTES;
277
278 WARN_ON(qc->__sg == NULL);
279 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
280
281 nelem = 0;
282 ata_for_each_sg(sg, qc) {
283 u64 addr;
284 u32 len;
285
286 addr = sg_dma_address(sg);
287 *(__le64 *)prd = cpu_to_le64(addr);
288 prd += sizeof(u64);
289
290 len = sg_dma_len(sg);
291 *(__le32 *)prd = cpu_to_le32(len);
292 prd += sizeof(u64);
293
294 VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem,
295 (unsigned long long)addr, len);
296 nelem++;
297 }
298
299 return nelem;
300 }
301
302 static void qs_qc_prep(struct ata_queued_cmd *qc)
303 {
304 struct qs_port_priv *pp = qc->ap->private_data;
305 u8 dflags = QS_DF_PORD, *buf = pp->pkt;
306 u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD;
307 u64 addr;
308 unsigned int nelem;
309
310 VPRINTK("ENTER\n");
311
312 qs_enter_reg_mode(qc->ap);
313 if (qc->tf.protocol != ATA_PROT_DMA) {
314 ata_qc_prep(qc);
315 return;
316 }
317
318 nelem = qs_fill_sg(qc);
319
320 if ((qc->tf.flags & ATA_TFLAG_WRITE))
321 hflags |= QS_HF_DIRO;
322 if ((qc->tf.flags & ATA_TFLAG_LBA48))
323 dflags |= QS_DF_ELBA;
324
325 /* host control block (HCB) */
326 buf[ 0] = QS_HCB_HDR;
327 buf[ 1] = hflags;
328 *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nsect * ATA_SECT_SIZE);
329 *(__le32 *)(&buf[ 8]) = cpu_to_le32(nelem);
330 addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES;
331 *(__le64 *)(&buf[16]) = cpu_to_le64(addr);
332
333 /* device control block (DCB) */
334 buf[24] = QS_DCB_HDR;
335 buf[28] = dflags;
336
337 /* frame information structure (FIS) */
338 ata_tf_to_fis(&qc->tf, &buf[32], 0);
339 }
340
341 static inline void qs_packet_start(struct ata_queued_cmd *qc)
342 {
343 struct ata_port *ap = qc->ap;
344 u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000);
345
346 VPRINTK("ENTER, ap %p\n", ap);
347
348 writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0);
349 wmb(); /* flush PRDs and pkt to memory */
350 writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF);
351 readl(chan + QS_CCT_CFF); /* flush */
352 }
353
354 static unsigned int qs_qc_issue(struct ata_queued_cmd *qc)
355 {
356 struct qs_port_priv *pp = qc->ap->private_data;
357
358 switch (qc->tf.protocol) {
359 case ATA_PROT_DMA:
360
361 pp->state = qs_state_pkt;
362 qs_packet_start(qc);
363 return 0;
364
365 case ATA_PROT_ATAPI_DMA:
366 BUG();
367 break;
368
369 default:
370 break;
371 }
372
373 pp->state = qs_state_mmio;
374 return ata_qc_issue_prot(qc);
375 }
376
377 static inline unsigned int qs_intr_pkt(struct ata_host_set *host_set)
378 {
379 unsigned int handled = 0;
380 u8 sFFE;
381 u8 __iomem *mmio_base = host_set->mmio_base;
382
383 do {
384 u32 sff0 = readl(mmio_base + QS_HST_SFF);
385 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
386 u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */
387 sFFE = sff1 >> 31; /* empty flag */
388
389 if (sEVLD) {
390 u8 sDST = sff0 >> 16; /* dev status */
391 u8 sHST = sff1 & 0x3f; /* host status */
392 unsigned int port_no = (sff1 >> 8) & 0x03;
393 struct ata_port *ap = host_set->ports[port_no];
394
395 DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n",
396 sff1, sff0, port_no, sHST, sDST);
397 handled = 1;
398 if (ap && !(ap->flags &
399 (ATA_FLAG_PORT_DISABLED|ATA_FLAG_NOINTR))) {
400 struct ata_queued_cmd *qc;
401 struct qs_port_priv *pp = ap->private_data;
402 if (!pp || pp->state != qs_state_pkt)
403 continue;
404 qc = ata_qc_from_tag(ap, ap->active_tag);
405 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
406 switch (sHST) {
407 case 0: /* successful CPB */
408 case 3: /* device error */
409 pp->state = qs_state_idle;
410 qs_enter_reg_mode(qc->ap);
411 qc->err_mask |= ac_err_mask(sDST);
412 ata_qc_complete(qc);
413 break;
414 default:
415 break;
416 }
417 }
418 }
419 }
420 } while (!sFFE);
421 return handled;
422 }
423
424 static inline unsigned int qs_intr_mmio(struct ata_host_set *host_set)
425 {
426 unsigned int handled = 0, port_no;
427
428 for (port_no = 0; port_no < host_set->n_ports; ++port_no) {
429 struct ata_port *ap;
430 ap = host_set->ports[port_no];
431 if (ap &&
432 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
433 struct ata_queued_cmd *qc;
434 struct qs_port_priv *pp = ap->private_data;
435 if (!pp || pp->state != qs_state_mmio)
436 continue;
437 qc = ata_qc_from_tag(ap, ap->active_tag);
438 if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
439
440 /* check main status, clearing INTRQ */
441 u8 status = ata_check_status(ap);
442 if ((status & ATA_BUSY))
443 continue;
444 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
445 ap->id, qc->tf.protocol, status);
446
447 /* complete taskfile transaction */
448 pp->state = qs_state_idle;
449 qc->err_mask |= ac_err_mask(status);
450 ata_qc_complete(qc);
451 handled = 1;
452 }
453 }
454 }
455 return handled;
456 }
457
458 static irqreturn_t qs_intr(int irq, void *dev_instance, struct pt_regs *regs)
459 {
460 struct ata_host_set *host_set = dev_instance;
461 unsigned int handled = 0;
462
463 VPRINTK("ENTER\n");
464
465 spin_lock(&host_set->lock);
466 handled = qs_intr_pkt(host_set) | qs_intr_mmio(host_set);
467 spin_unlock(&host_set->lock);
468
469 VPRINTK("EXIT\n");
470
471 return IRQ_RETVAL(handled);
472 }
473
474 static void qs_ata_setup_port(struct ata_ioports *port, unsigned long base)
475 {
476 port->cmd_addr =
477 port->data_addr = base + 0x400;
478 port->error_addr =
479 port->feature_addr = base + 0x408; /* hob_feature = 0x409 */
480 port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */
481 port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */
482 port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */
483 port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */
484 port->device_addr = base + 0x430;
485 port->status_addr =
486 port->command_addr = base + 0x438;
487 port->altstatus_addr =
488 port->ctl_addr = base + 0x440;
489 port->scr_addr = base + 0xc00;
490 }
491
492 static int qs_port_start(struct ata_port *ap)
493 {
494 struct device *dev = ap->host_set->dev;
495 struct qs_port_priv *pp;
496 void __iomem *mmio_base = ap->host_set->mmio_base;
497 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
498 u64 addr;
499 int rc;
500
501 rc = ata_port_start(ap);
502 if (rc)
503 return rc;
504 qs_enter_reg_mode(ap);
505 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
506 if (!pp) {
507 rc = -ENOMEM;
508 goto err_out;
509 }
510 pp->pkt = dma_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma,
511 GFP_KERNEL);
512 if (!pp->pkt) {
513 rc = -ENOMEM;
514 goto err_out_kfree;
515 }
516 memset(pp->pkt, 0, QS_PKT_BYTES);
517 ap->private_data = pp;
518
519 addr = (u64)pp->pkt_dma;
520 writel((u32) addr, chan + QS_CCF_CPBA);
521 writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4);
522 return 0;
523
524 err_out_kfree:
525 kfree(pp);
526 err_out:
527 ata_port_stop(ap);
528 return rc;
529 }
530
531 static void qs_port_stop(struct ata_port *ap)
532 {
533 struct device *dev = ap->host_set->dev;
534 struct qs_port_priv *pp = ap->private_data;
535
536 if (pp != NULL) {
537 ap->private_data = NULL;
538 if (pp->pkt != NULL)
539 dma_free_coherent(dev, QS_PKT_BYTES, pp->pkt,
540 pp->pkt_dma);
541 kfree(pp);
542 }
543 ata_port_stop(ap);
544 }
545
546 static void qs_host_stop(struct ata_host_set *host_set)
547 {
548 void __iomem *mmio_base = host_set->mmio_base;
549 struct pci_dev *pdev = to_pci_dev(host_set->dev);
550
551 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
552 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
553
554 pci_iounmap(pdev, mmio_base);
555 }
556
557 static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
558 {
559 void __iomem *mmio_base = pe->mmio_base;
560 unsigned int port_no;
561
562 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
563 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
564
565 /* reset each channel in turn */
566 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
567 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
568 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
569 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
570 readb(chan + QS_CCT_CTR0); /* flush */
571 }
572 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
573
574 for (port_no = 0; port_no < pe->n_ports; ++port_no) {
575 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
576 /* set FIFO depths to same settings as Windows driver */
577 writew(32, chan + QS_CFC_HUFT);
578 writew(32, chan + QS_CFC_HDFT);
579 writew(10, chan + QS_CFC_DUFT);
580 writew( 8, chan + QS_CFC_DDFT);
581 /* set CPB size in bytes, as a power of two */
582 writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP);
583 }
584 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
585 }
586
587 /*
588 * The QStor understands 64-bit buses, and uses 64-bit fields
589 * for DMA pointers regardless of bus width. We just have to
590 * make sure our DMA masks are set appropriately for whatever
591 * bridge lies between us and the QStor, and then the DMA mapping
592 * code will ensure we only ever "see" appropriate buffer addresses.
593 * If we're 32-bit limited somewhere, then our 64-bit fields will
594 * just end up with zeros in the upper 32-bits, without any special
595 * logic required outside of this routine (below).
596 */
597 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
598 {
599 u32 bus_info = readl(mmio_base + QS_HID_HPHY);
600 int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT);
601
602 if (have_64bit_bus &&
603 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
604 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
605 if (rc) {
606 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
607 if (rc) {
608 dev_printk(KERN_ERR, &pdev->dev,
609 "64-bit DMA enable failed\n");
610 return rc;
611 }
612 }
613 } else {
614 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
615 if (rc) {
616 dev_printk(KERN_ERR, &pdev->dev,
617 "32-bit DMA enable failed\n");
618 return rc;
619 }
620 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
621 if (rc) {
622 dev_printk(KERN_ERR, &pdev->dev,
623 "32-bit consistent DMA enable failed\n");
624 return rc;
625 }
626 }
627 return 0;
628 }
629
630 static int qs_ata_init_one(struct pci_dev *pdev,
631 const struct pci_device_id *ent)
632 {
633 static int printed_version;
634 struct ata_probe_ent *probe_ent = NULL;
635 void __iomem *mmio_base;
636 unsigned int board_idx = (unsigned int) ent->driver_data;
637 int rc, port_no;
638
639 if (!printed_version++)
640 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
641
642 rc = pci_enable_device(pdev);
643 if (rc)
644 return rc;
645
646 rc = pci_request_regions(pdev, DRV_NAME);
647 if (rc)
648 goto err_out;
649
650 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) {
651 rc = -ENODEV;
652 goto err_out_regions;
653 }
654
655 mmio_base = pci_iomap(pdev, 4, 0);
656 if (mmio_base == NULL) {
657 rc = -ENOMEM;
658 goto err_out_regions;
659 }
660
661 rc = qs_set_dma_masks(pdev, mmio_base);
662 if (rc)
663 goto err_out_iounmap;
664
665 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
666 if (probe_ent == NULL) {
667 rc = -ENOMEM;
668 goto err_out_iounmap;
669 }
670
671 memset(probe_ent, 0, sizeof(*probe_ent));
672 probe_ent->dev = pci_dev_to_dev(pdev);
673 INIT_LIST_HEAD(&probe_ent->node);
674
675 probe_ent->sht = qs_port_info[board_idx].sht;
676 probe_ent->host_flags = qs_port_info[board_idx].host_flags;
677 probe_ent->pio_mask = qs_port_info[board_idx].pio_mask;
678 probe_ent->mwdma_mask = qs_port_info[board_idx].mwdma_mask;
679 probe_ent->udma_mask = qs_port_info[board_idx].udma_mask;
680 probe_ent->port_ops = qs_port_info[board_idx].port_ops;
681
682 probe_ent->irq = pdev->irq;
683 probe_ent->irq_flags = SA_SHIRQ;
684 probe_ent->mmio_base = mmio_base;
685 probe_ent->n_ports = QS_PORTS;
686
687 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
688 unsigned long chan = (unsigned long)mmio_base +
689 (port_no * 0x4000);
690 qs_ata_setup_port(&probe_ent->port[port_no], chan);
691 }
692
693 pci_set_master(pdev);
694
695 /* initialize adapter */
696 qs_host_init(board_idx, probe_ent);
697
698 rc = ata_device_add(probe_ent);
699 kfree(probe_ent);
700 if (rc != QS_PORTS)
701 goto err_out_iounmap;
702 return 0;
703
704 err_out_iounmap:
705 pci_iounmap(pdev, mmio_base);
706 err_out_regions:
707 pci_release_regions(pdev);
708 err_out:
709 pci_disable_device(pdev);
710 return rc;
711 }
712
713 static int __init qs_ata_init(void)
714 {
715 return pci_module_init(&qs_ata_pci_driver);
716 }
717
718 static void __exit qs_ata_exit(void)
719 {
720 pci_unregister_driver(&qs_ata_pci_driver);
721 }
722
723 MODULE_AUTHOR("Mark Lord");
724 MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver");
725 MODULE_LICENSE("GPL");
726 MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl);
727 MODULE_VERSION(DRV_VERSION);
728
729 module_init(qs_ata_init);
730 module_exit(qs_ata_exit);
Support for the Chinese Samsung S3C2440 based development boards