3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
20 #include <linux/kvm_host.h>
21 #include <linux/kvm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
27 #include <linux/module.h>
28 #include <linux/math64.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/atomic.h>
35 #include "kvm_cache_regs.h"
43 #define APIC_BUS_CYCLE_NS 1
45 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
46 #define apic_debug(fmt, arg...)
48 #define APIC_LVT_NUM 6
49 /* 14 is the version for Xeon and Pentium 8.4.8*/
50 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
51 #define LAPIC_MMIO_LENGTH (1 << 12)
52 /* followed define is not in apicdef.h */
53 #define APIC_SHORT_MASK 0xc0000
54 #define APIC_DEST_NOSHORT 0x0
55 #define APIC_DEST_MASK 0x800
56 #define MAX_APIC_VECTOR 256
58 #define VEC_POS(v) ((v) & (32 - 1))
59 #define REG_POS(v) (((v) >> 5) << 4)
61 static inline u32
apic_get_reg(struct kvm_lapic
*apic
, int reg_off
)
63 return *((u32
*) (apic
->regs
+ reg_off
));
66 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
68 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
71 static inline int apic_test_and_set_vector(int vec
, void *bitmap
)
73 return test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
76 static inline int apic_test_and_clear_vector(int vec
, void *bitmap
)
78 return test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
81 static inline void apic_set_vector(int vec
, void *bitmap
)
83 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
86 static inline void apic_clear_vector(int vec
, void *bitmap
)
88 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
91 static inline int apic_hw_enabled(struct kvm_lapic
*apic
)
93 return (apic
)->vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
;
96 static inline int apic_sw_enabled(struct kvm_lapic
*apic
)
98 return apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_APIC_ENABLED
;
101 static inline int apic_enabled(struct kvm_lapic
*apic
)
103 return apic_sw_enabled(apic
) && apic_hw_enabled(apic
);
107 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
110 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
111 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
113 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
115 return (apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
118 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
120 return !(apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
123 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
125 return apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
128 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
130 return apic_get_reg(apic
, APIC_LVTT
) & APIC_LVT_TIMER_PERIODIC
;
133 static unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
134 LVT_MASK
| APIC_LVT_TIMER_PERIODIC
, /* LVTT */
135 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
136 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
137 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
138 LVT_MASK
/* LVTERR */
141 static int find_highest_vector(void *bitmap
)
144 int word_offset
= MAX_APIC_VECTOR
>> 5;
146 while ((word_offset
!= 0) && (word
[(--word_offset
) << 2] == 0))
149 if (likely(!word_offset
&& !word
[0]))
152 return fls(word
[word_offset
<< 2]) - 1 + (word_offset
<< 5);
155 static inline int apic_test_and_set_irr(int vec
, struct kvm_lapic
*apic
)
157 return apic_test_and_set_vector(vec
, apic
->regs
+ APIC_IRR
);
160 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
162 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
165 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
169 result
= find_highest_vector(apic
->regs
+ APIC_IRR
);
170 ASSERT(result
== -1 || result
>= 16);
175 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
177 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
182 highest_irr
= apic_find_highest_irr(apic
);
186 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr
);
188 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, u8 vec
, u8 trig
)
190 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
192 if (!apic_test_and_set_irr(vec
, apic
)) {
193 /* a new pending irq is set in IRR */
195 apic_set_vector(vec
, apic
->regs
+ APIC_TMR
);
197 apic_clear_vector(vec
, apic
->regs
+ APIC_TMR
);
198 kvm_vcpu_kick(apic
->vcpu
);
204 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
208 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
209 ASSERT(result
== -1 || result
>= 16);
214 static void apic_update_ppr(struct kvm_lapic
*apic
)
219 tpr
= apic_get_reg(apic
, APIC_TASKPRI
);
220 isr
= apic_find_highest_isr(apic
);
221 isrv
= (isr
!= -1) ? isr
: 0;
223 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
228 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
229 apic
, ppr
, isr
, isrv
);
231 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
234 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
236 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
237 apic_update_ppr(apic
);
240 int kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u16 dest
)
242 return kvm_apic_id(apic
) == dest
;
245 int kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u8 mda
)
250 logical_id
= GET_APIC_LOGICAL_ID(apic_get_reg(apic
, APIC_LDR
));
252 switch (apic_get_reg(apic
, APIC_DFR
)) {
254 if (logical_id
& mda
)
257 case APIC_DFR_CLUSTER
:
258 if (((logical_id
>> 4) == (mda
>> 0x4))
259 && (logical_id
& mda
& 0xf))
263 printk(KERN_WARNING
"Bad DFR vcpu %d: %08x\n",
264 apic
->vcpu
->vcpu_id
, apic_get_reg(apic
, APIC_DFR
));
271 static int apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
272 int short_hand
, int dest
, int dest_mode
)
275 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
277 apic_debug("target %p, source %p, dest 0x%x, "
278 "dest_mode 0x%x, short_hand 0x%x",
279 target
, source
, dest
, dest_mode
, short_hand
);
282 switch (short_hand
) {
283 case APIC_DEST_NOSHORT
:
284 if (dest_mode
== 0) {
286 if ((dest
== 0xFF) || (dest
== kvm_apic_id(target
)))
290 result
= kvm_apic_match_logical_addr(target
, dest
);
293 if (target
== source
)
296 case APIC_DEST_ALLINC
:
299 case APIC_DEST_ALLBUT
:
300 if (target
!= source
)
304 printk(KERN_WARNING
"Bad dest shorthand value %x\n",
313 * Add a pending IRQ into lapic.
314 * Return 1 if successfully added and 0 if discarded.
316 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
317 int vector
, int level
, int trig_mode
)
319 int orig_irr
, result
= 0;
320 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
322 switch (delivery_mode
) {
325 /* FIXME add logic for vcpu on reset */
326 if (unlikely(!apic_enabled(apic
)))
329 orig_irr
= apic_test_and_set_irr(vector
, apic
);
330 if (orig_irr
&& trig_mode
) {
331 apic_debug("level trig mode repeatedly for vector %d",
337 apic_debug("level trig mode for vector %d", vector
);
338 apic_set_vector(vector
, apic
->regs
+ APIC_TMR
);
340 apic_clear_vector(vector
, apic
->regs
+ APIC_TMR
);
344 result
= (orig_irr
== 0);
348 printk(KERN_DEBUG
"Ignoring delivery mode 3\n");
352 printk(KERN_DEBUG
"Ignoring guest SMI\n");
356 kvm_inject_nmi(vcpu
);
362 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_RUNNABLE
)
364 "INIT on a runnable vcpu %d\n",
366 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
369 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
374 case APIC_DM_STARTUP
:
375 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
376 vcpu
->vcpu_id
, vector
);
377 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
378 vcpu
->arch
.sipi_vector
= vector
;
379 vcpu
->arch
.mp_state
= KVM_MP_STATE_SIPI_RECEIVED
;
386 * Should only be called by kvm_apic_local_deliver() with LVT0,
387 * before NMI watchdog was enabled. Already handled by
388 * kvm_apic_accept_pic_intr().
393 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
400 static struct kvm_lapic
*kvm_apic_round_robin(struct kvm
*kvm
, u8 vector
,
401 unsigned long bitmap
)
405 struct kvm_lapic
*apic
= NULL
;
407 last
= kvm
->arch
.round_robin_prev_vcpu
;
411 if (++next
== KVM_MAX_VCPUS
)
413 if (kvm
->vcpus
[next
] == NULL
|| !test_bit(next
, &bitmap
))
415 apic
= kvm
->vcpus
[next
]->arch
.apic
;
416 if (apic
&& apic_enabled(apic
))
419 } while (next
!= last
);
420 kvm
->arch
.round_robin_prev_vcpu
= next
;
423 printk(KERN_DEBUG
"vcpu not ready for apic_round_robin\n");
428 struct kvm_vcpu
*kvm_get_lowest_prio_vcpu(struct kvm
*kvm
, u8 vector
,
429 unsigned long bitmap
)
431 struct kvm_lapic
*apic
;
433 apic
= kvm_apic_round_robin(kvm
, vector
, bitmap
);
439 static void apic_set_eoi(struct kvm_lapic
*apic
)
441 int vector
= apic_find_highest_isr(apic
);
444 * Not every write EOI will has corresponding ISR,
445 * one example is when Kernel check timer on setup_IO_APIC
450 apic_clear_vector(vector
, apic
->regs
+ APIC_ISR
);
451 apic_update_ppr(apic
);
453 if (apic_test_and_clear_vector(vector
, apic
->regs
+ APIC_TMR
))
454 trigger_mode
= IOAPIC_LEVEL_TRIG
;
456 trigger_mode
= IOAPIC_EDGE_TRIG
;
457 kvm_ioapic_update_eoi(apic
->vcpu
->kvm
, vector
, trigger_mode
);
460 static void apic_send_ipi(struct kvm_lapic
*apic
)
462 u32 icr_low
= apic_get_reg(apic
, APIC_ICR
);
463 u32 icr_high
= apic_get_reg(apic
, APIC_ICR2
);
465 unsigned int dest
= GET_APIC_DEST_FIELD(icr_high
);
466 unsigned int short_hand
= icr_low
& APIC_SHORT_MASK
;
467 unsigned int trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
468 unsigned int level
= icr_low
& APIC_INT_ASSERT
;
469 unsigned int dest_mode
= icr_low
& APIC_DEST_MASK
;
470 unsigned int delivery_mode
= icr_low
& APIC_MODE_MASK
;
471 unsigned int vector
= icr_low
& APIC_VECTOR_MASK
;
473 struct kvm_vcpu
*target
;
474 struct kvm_vcpu
*vcpu
;
475 unsigned long lpr_map
= 0;
478 apic_debug("icr_high 0x%x, icr_low 0x%x, "
479 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
480 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
481 icr_high
, icr_low
, short_hand
, dest
,
482 trig_mode
, level
, dest_mode
, delivery_mode
, vector
);
484 for (i
= 0; i
< KVM_MAX_VCPUS
; i
++) {
485 vcpu
= apic
->vcpu
->kvm
->vcpus
[i
];
489 if (vcpu
->arch
.apic
&&
490 apic_match_dest(vcpu
, apic
, short_hand
, dest
, dest_mode
)) {
491 if (delivery_mode
== APIC_DM_LOWEST
)
492 set_bit(vcpu
->vcpu_id
, &lpr_map
);
494 __apic_accept_irq(vcpu
->arch
.apic
, delivery_mode
,
495 vector
, level
, trig_mode
);
499 if (delivery_mode
== APIC_DM_LOWEST
) {
500 target
= kvm_get_lowest_prio_vcpu(vcpu
->kvm
, vector
, lpr_map
);
502 __apic_accept_irq(target
->arch
.apic
, delivery_mode
,
503 vector
, level
, trig_mode
);
507 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
513 ASSERT(apic
!= NULL
);
515 now
= apic
->timer
.dev
.base
->get_time();
516 tmcct
= apic_get_reg(apic
, APIC_TMICT
);
518 /* if initial count is 0, current count should also be 0 */
522 if (unlikely(ktime_to_ns(now
) <=
523 ktime_to_ns(apic
->timer
.last_update
))) {
525 passed
= ktime_add(( {
528 (apic
->timer
.last_update
).tv64
}; }
530 apic_debug("time elapsed\n");
532 passed
= ktime_sub(now
, apic
->timer
.last_update
);
534 counter_passed
= div64_u64(ktime_to_ns(passed
),
535 (APIC_BUS_CYCLE_NS
* apic
->timer
.divide_count
));
537 if (counter_passed
> tmcct
) {
538 if (unlikely(!apic_lvtt_period(apic
))) {
539 /* one-shot timers stick at 0 until reset */
543 * periodic timers reset to APIC_TMICT when they
544 * hit 0. The while loop simulates this happening N
545 * times. (counter_passed %= tmcct) would also work,
546 * but might be slower or not work on 32-bit??
548 while (counter_passed
> tmcct
)
549 counter_passed
-= tmcct
;
550 tmcct
-= counter_passed
;
553 tmcct
-= counter_passed
;
559 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
561 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
562 struct kvm_run
*run
= vcpu
->run
;
564 set_bit(KVM_REQ_REPORT_TPR_ACCESS
, &vcpu
->requests
);
565 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
566 run
->tpr_access
.is_write
= write
;
569 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
571 if (apic
->vcpu
->arch
.tpr_access_reporting
)
572 __report_tpr_access(apic
, write
);
575 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
579 KVMTRACE_1D(APIC_ACCESS
, apic
->vcpu
, (u32
)offset
, handler
);
581 if (offset
>= LAPIC_MMIO_LENGTH
)
586 printk(KERN_WARNING
"Access APIC ARBPRI register "
587 "which is for P6\n");
590 case APIC_TMCCT
: /* Timer CCR */
591 val
= apic_get_tmcct(apic
);
595 report_tpr_access(apic
, false);
598 apic_update_ppr(apic
);
599 val
= apic_get_reg(apic
, offset
);
606 static void apic_mmio_read(struct kvm_io_device
*this,
607 gpa_t address
, int len
, void *data
)
609 struct kvm_lapic
*apic
= (struct kvm_lapic
*)this->private;
610 unsigned int offset
= address
- apic
->base_address
;
611 unsigned char alignment
= offset
& 0xf;
614 if ((alignment
+ len
) > 4) {
615 printk(KERN_ERR
"KVM_APIC_READ: alignment error %lx %d",
616 (unsigned long)address
, len
);
619 result
= __apic_read(apic
, offset
& ~0xf);
625 memcpy(data
, (char *)&result
+ alignment
, len
);
628 printk(KERN_ERR
"Local APIC read with len = %x, "
629 "should be 1,2, or 4 instead\n", len
);
634 static void update_divide_count(struct kvm_lapic
*apic
)
636 u32 tmp1
, tmp2
, tdcr
;
638 tdcr
= apic_get_reg(apic
, APIC_TDCR
);
640 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
641 apic
->timer
.divide_count
= 0x1 << (tmp2
& 0x7);
643 apic_debug("timer divide count is 0x%x\n",
644 apic
->timer
.divide_count
);
647 static void start_apic_timer(struct kvm_lapic
*apic
)
649 ktime_t now
= apic
->timer
.dev
.base
->get_time();
651 apic
->timer
.last_update
= now
;
653 apic
->timer
.period
= apic_get_reg(apic
, APIC_TMICT
) *
654 APIC_BUS_CYCLE_NS
* apic
->timer
.divide_count
;
655 atomic_set(&apic
->timer
.pending
, 0);
657 if (!apic
->timer
.period
)
660 hrtimer_start(&apic
->timer
.dev
,
661 ktime_add_ns(now
, apic
->timer
.period
),
664 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
666 "timer initial count 0x%x, period %lldns, "
667 "expire @ 0x%016" PRIx64
".\n", __func__
,
668 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
669 apic_get_reg(apic
, APIC_TMICT
),
671 ktime_to_ns(ktime_add_ns(now
,
672 apic
->timer
.period
)));
675 static void apic_mmio_write(struct kvm_io_device
*this,
676 gpa_t address
, int len
, const void *data
)
678 struct kvm_lapic
*apic
= (struct kvm_lapic
*)this->private;
679 unsigned int offset
= address
- apic
->base_address
;
680 unsigned char alignment
= offset
& 0xf;
684 * APIC register must be aligned on 128-bits boundary.
685 * 32/64/128 bits registers must be accessed thru 32 bits.
688 if (len
!= 4 || alignment
) {
689 /* Don't shout loud, $infamous_os would cause only noise. */
690 apic_debug("apic write: bad size=%d %lx\n",
697 /* too common printing */
698 if (offset
!= APIC_EOI
)
699 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
700 "0x%x\n", __func__
, offset
, len
, val
);
704 KVMTRACE_1D(APIC_ACCESS
, apic
->vcpu
, (u32
)offset
, handler
);
707 case APIC_ID
: /* Local APIC ID */
708 apic_set_reg(apic
, APIC_ID
, val
);
712 report_tpr_access(apic
, true);
713 apic_set_tpr(apic
, val
& 0xff);
721 apic_set_reg(apic
, APIC_LDR
, val
& APIC_LDR_MASK
);
725 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
729 apic_set_reg(apic
, APIC_SPIV
, val
& 0x3ff);
730 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
734 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
735 lvt_val
= apic_get_reg(apic
,
736 APIC_LVTT
+ 0x10 * i
);
737 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
738 lvt_val
| APIC_LVT_MASKED
);
740 atomic_set(&apic
->timer
.pending
, 0);
746 /* No delay here, so we always clear the pending bit */
747 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
752 apic_set_reg(apic
, APIC_ICR2
, val
& 0xff000000);
756 if (val
== APIC_DM_NMI
)
757 apic_debug("Receive NMI setting on APIC_LVT0 "
758 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
764 /* TODO: Check vector */
765 if (!apic_sw_enabled(apic
))
766 val
|= APIC_LVT_MASKED
;
768 val
&= apic_lvt_mask
[(offset
- APIC_LVTT
) >> 4];
769 apic_set_reg(apic
, offset
, val
);
774 hrtimer_cancel(&apic
->timer
.dev
);
775 apic_set_reg(apic
, APIC_TMICT
, val
);
776 start_apic_timer(apic
);
781 printk(KERN_ERR
"KVM_WRITE:TDCR %x\n", val
);
782 apic_set_reg(apic
, APIC_TDCR
, val
);
783 update_divide_count(apic
);
787 apic_debug("Local APIC Write to read-only register %x\n",
794 static int apic_mmio_range(struct kvm_io_device
*this, gpa_t addr
,
797 struct kvm_lapic
*apic
= (struct kvm_lapic
*)this->private;
801 if (apic_hw_enabled(apic
) &&
802 (addr
>= apic
->base_address
) &&
803 (addr
< (apic
->base_address
+ LAPIC_MMIO_LENGTH
)))
809 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
811 if (!vcpu
->arch
.apic
)
814 hrtimer_cancel(&vcpu
->arch
.apic
->timer
.dev
);
816 if (vcpu
->arch
.apic
->regs_page
)
817 __free_page(vcpu
->arch
.apic
->regs_page
);
819 kfree(vcpu
->arch
.apic
);
823 *----------------------------------------------------------------------
825 *----------------------------------------------------------------------
828 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
830 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
834 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
835 | (apic_get_reg(apic
, APIC_TASKPRI
) & 4));
837 EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr
);
839 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
841 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
846 tpr
= (u64
) apic_get_reg(apic
, APIC_TASKPRI
);
848 return (tpr
& 0xf0) >> 4;
850 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8
);
852 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
854 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
857 value
|= MSR_IA32_APICBASE_BSP
;
858 vcpu
->arch
.apic_base
= value
;
861 if (apic
->vcpu
->vcpu_id
)
862 value
&= ~MSR_IA32_APICBASE_BSP
;
864 vcpu
->arch
.apic_base
= value
;
865 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
866 MSR_IA32_APICBASE_BASE
;
868 /* with FSB delivery interrupt, we can restart APIC functionality */
869 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
870 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
874 u64
kvm_lapic_get_base(struct kvm_vcpu
*vcpu
)
876 return vcpu
->arch
.apic_base
;
878 EXPORT_SYMBOL_GPL(kvm_lapic_get_base
);
880 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
)
882 struct kvm_lapic
*apic
;
885 apic_debug("%s\n", __func__
);
888 apic
= vcpu
->arch
.apic
;
889 ASSERT(apic
!= NULL
);
891 /* Stop the timer in case it's a reset to an active apic */
892 hrtimer_cancel(&apic
->timer
.dev
);
894 apic_set_reg(apic
, APIC_ID
, vcpu
->vcpu_id
<< 24);
895 apic_set_reg(apic
, APIC_LVR
, APIC_VERSION
);
897 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
898 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
899 apic_set_reg(apic
, APIC_LVT0
,
900 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
902 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
903 apic_set_reg(apic
, APIC_SPIV
, 0xff);
904 apic_set_reg(apic
, APIC_TASKPRI
, 0);
905 apic_set_reg(apic
, APIC_LDR
, 0);
906 apic_set_reg(apic
, APIC_ESR
, 0);
907 apic_set_reg(apic
, APIC_ICR
, 0);
908 apic_set_reg(apic
, APIC_ICR2
, 0);
909 apic_set_reg(apic
, APIC_TDCR
, 0);
910 apic_set_reg(apic
, APIC_TMICT
, 0);
911 for (i
= 0; i
< 8; i
++) {
912 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
913 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
914 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
916 update_divide_count(apic
);
917 atomic_set(&apic
->timer
.pending
, 0);
918 if (vcpu
->vcpu_id
== 0)
919 vcpu
->arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
920 apic_update_ppr(apic
);
922 apic_debug(KERN_INFO
"%s: vcpu=%p, id=%d, base_msr="
923 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
924 vcpu
, kvm_apic_id(apic
),
925 vcpu
->arch
.apic_base
, apic
->base_address
);
927 EXPORT_SYMBOL_GPL(kvm_lapic_reset
);
929 int kvm_lapic_enabled(struct kvm_vcpu
*vcpu
)
931 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
936 ret
= apic_enabled(apic
);
940 EXPORT_SYMBOL_GPL(kvm_lapic_enabled
);
943 *----------------------------------------------------------------------
945 *----------------------------------------------------------------------
948 /* TODO: make sure __apic_timer_fn runs in current pCPU */
949 static int __apic_timer_fn(struct kvm_lapic
*apic
)
952 wait_queue_head_t
*q
= &apic
->vcpu
->wq
;
954 if(!atomic_inc_and_test(&apic
->timer
.pending
))
955 set_bit(KVM_REQ_PENDING_TIMER
, &apic
->vcpu
->requests
);
956 if (waitqueue_active(q
))
957 wake_up_interruptible(q
);
959 if (apic_lvtt_period(apic
)) {
961 hrtimer_add_expires_ns(&apic
->timer
.dev
, apic
->timer
.period
);
966 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
968 struct kvm_lapic
*lapic
= vcpu
->arch
.apic
;
970 if (lapic
&& apic_enabled(lapic
) && apic_lvt_enabled(lapic
, APIC_LVTT
))
971 return atomic_read(&lapic
->timer
.pending
);
976 int kvm_apic_local_deliver(struct kvm_vcpu
*vcpu
, int lvt_type
)
978 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
979 int vector
, mode
, trig_mode
;
982 if (apic
&& apic_enabled(apic
)) {
983 reg
= apic_get_reg(apic
, lvt_type
);
984 vector
= reg
& APIC_VECTOR_MASK
;
985 mode
= reg
& APIC_MODE_MASK
;
986 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
987 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
);
992 static inline int __inject_apic_timer_irq(struct kvm_lapic
*apic
)
994 return kvm_apic_local_deliver(apic
->vcpu
, APIC_LVTT
);
997 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
999 struct kvm_lapic
*apic
;
1000 int restart_timer
= 0;
1002 apic
= container_of(data
, struct kvm_lapic
, timer
.dev
);
1004 restart_timer
= __apic_timer_fn(apic
);
1007 return HRTIMER_RESTART
;
1009 return HRTIMER_NORESTART
;
1012 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1014 struct kvm_lapic
*apic
;
1016 ASSERT(vcpu
!= NULL
);
1017 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1019 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1023 vcpu
->arch
.apic
= apic
;
1025 apic
->regs_page
= alloc_page(GFP_KERNEL
);
1026 if (apic
->regs_page
== NULL
) {
1027 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1029 goto nomem_free_apic
;
1031 apic
->regs
= page_address(apic
->regs_page
);
1032 memset(apic
->regs
, 0, PAGE_SIZE
);
1035 hrtimer_init(&apic
->timer
.dev
, CLOCK_MONOTONIC
, HRTIMER_MODE_ABS
);
1036 apic
->timer
.dev
.function
= apic_timer_fn
;
1037 apic
->base_address
= APIC_DEFAULT_PHYS_BASE
;
1038 vcpu
->arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
;
1040 kvm_lapic_reset(vcpu
);
1041 apic
->dev
.read
= apic_mmio_read
;
1042 apic
->dev
.write
= apic_mmio_write
;
1043 apic
->dev
.in_range
= apic_mmio_range
;
1044 apic
->dev
.private = apic
;
1052 EXPORT_SYMBOL_GPL(kvm_create_lapic
);
1054 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1056 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1059 if (!apic
|| !apic_enabled(apic
))
1062 apic_update_ppr(apic
);
1063 highest_irr
= apic_find_highest_irr(apic
);
1064 if ((highest_irr
== -1) ||
1065 ((highest_irr
& 0xF0) <= apic_get_reg(apic
, APIC_PROCPRI
)))
1070 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1072 u32 lvt0
= apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1075 if (vcpu
->vcpu_id
== 0) {
1076 if (!apic_hw_enabled(vcpu
->arch
.apic
))
1078 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1079 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1085 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1087 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1089 if (apic
&& apic_lvt_enabled(apic
, APIC_LVTT
) &&
1090 atomic_read(&apic
->timer
.pending
) > 0) {
1091 if (__inject_apic_timer_irq(apic
))
1092 atomic_dec(&apic
->timer
.pending
);
1096 void kvm_apic_timer_intr_post(struct kvm_vcpu
*vcpu
, int vec
)
1098 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1100 if (apic
&& apic_lvt_vector(apic
, APIC_LVTT
) == vec
)
1101 apic
->timer
.last_update
= ktime_add_ns(
1102 apic
->timer
.last_update
,
1103 apic
->timer
.period
);
1106 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1108 int vector
= kvm_apic_has_interrupt(vcpu
);
1109 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1114 apic_set_vector(vector
, apic
->regs
+ APIC_ISR
);
1115 apic_update_ppr(apic
);
1116 apic_clear_irr(vector
, apic
);
1120 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
)
1122 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1124 apic
->base_address
= vcpu
->arch
.apic_base
&
1125 MSR_IA32_APICBASE_BASE
;
1126 apic_set_reg(apic
, APIC_LVR
, APIC_VERSION
);
1127 apic_update_ppr(apic
);
1128 hrtimer_cancel(&apic
->timer
.dev
);
1129 update_divide_count(apic
);
1130 start_apic_timer(apic
);
1133 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1135 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1136 struct hrtimer
*timer
;
1141 timer
= &apic
->timer
.dev
;
1142 if (hrtimer_cancel(timer
))
1143 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1146 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1151 if (!irqchip_in_kernel(vcpu
->kvm
) || !vcpu
->arch
.apic
->vapic_addr
)
1154 vapic
= kmap_atomic(vcpu
->arch
.apic
->vapic_page
, KM_USER0
);
1155 data
= *(u32
*)(vapic
+ offset_in_page(vcpu
->arch
.apic
->vapic_addr
));
1156 kunmap_atomic(vapic
, KM_USER0
);
1158 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1161 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
1164 int max_irr
, max_isr
;
1165 struct kvm_lapic
*apic
;
1168 if (!irqchip_in_kernel(vcpu
->kvm
) || !vcpu
->arch
.apic
->vapic_addr
)
1171 apic
= vcpu
->arch
.apic
;
1172 tpr
= apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
1173 max_irr
= apic_find_highest_irr(apic
);
1176 max_isr
= apic_find_highest_isr(apic
);
1179 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
1181 vapic
= kmap_atomic(vcpu
->arch
.apic
->vapic_page
, KM_USER0
);
1182 *(u32
*)(vapic
+ offset_in_page(vcpu
->arch
.apic
->vapic_addr
)) = data
;
1183 kunmap_atomic(vapic
, KM_USER0
);
1186 void kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
1188 if (!irqchip_in_kernel(vcpu
->kvm
))
1191 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;