[POWERPC] Handle alignment faults on SPE load/store instructions
[linux-2.6/mini2440.git] / include / asm-v850 / irq.h
blob7d0d4cd1ce548d611f2ea4a34ec40c222e1a384d
1 /*
2 * include/asm-v850/irq.h -- Machine interrupt handling
4 * Copyright (C) 2001,02,04 NEC Electronics Corporation
5 * Copyright (C) 2001,02,04 Miles Bader <miles@gnu.org>
7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this
9 * archive for more details.
11 * Written by Miles Bader <miles@gnu.org>
14 #ifndef __V850_IRQ_H__
15 #define __V850_IRQ_H__
17 #include <asm/machdep.h>
19 /* Default NUM_MACH_IRQS. */
20 #ifndef NUM_MACH_IRQS
21 #define NUM_MACH_IRQS NUM_CPU_IRQS
22 #endif
24 /* NMIs have IRQ numbers from FIRST_NMI to FIRST_NMI+NUM_NMIS-1. */
25 #define FIRST_NMI NUM_MACH_IRQS
26 #define IRQ_NMI(n) (FIRST_NMI + (n))
27 /* v850 processors have 3 non-maskable interrupts. */
28 #define NUM_NMIS 3
30 /* Includes both maskable and non-maskable irqs. */
31 #define NR_IRQS (NUM_MACH_IRQS + NUM_NMIS)
34 #ifndef __ASSEMBLY__
36 struct pt_regs;
37 struct hw_interrupt_type;
38 struct irqaction;
40 #define irq_canonicalize(irq) (irq)
42 /* Initialize irq handling for IRQs.
43 BASE_IRQ, BASE_IRQ+INTERVAL, ..., BASE_IRQ+NUM*INTERVAL
44 to IRQ_TYPE. An IRQ_TYPE of 0 means to use a generic interrupt type. */
45 extern void
46 init_irq_handlers (int base_irq, int num, int interval,
47 struct hw_interrupt_type *irq_type);
49 /* Handle interrupt IRQ. REGS are the registers at the time of ther
50 interrupt. */
51 extern unsigned int handle_irq (int irq, struct pt_regs *regs);
53 #endif /* !__ASSEMBLY__ */
55 #endif /* __V850_IRQ_H__ */