[POWERPC] Handle alignment faults on SPE load/store instructions
[linux-2.6/mini2440.git] / include / asm-arm / dma.h
blob9f2c5305c26014a9aea95faaf73a9c82c1260201
1 #ifndef __ASM_ARM_DMA_H
2 #define __ASM_ARM_DMA_H
4 typedef unsigned int dmach_t;
6 #include <linux/spinlock.h>
7 #include <asm/system.h>
8 #include <asm/scatterlist.h>
9 #include <asm/arch/dma.h>
12 * This is the maximum virtual address which can be DMA'd from.
14 #ifndef MAX_DMA_ADDRESS
15 #define MAX_DMA_ADDRESS 0xffffffff
16 #endif
19 * DMA modes
21 typedef unsigned int dmamode_t;
23 #define DMA_MODE_MASK 3
25 #define DMA_MODE_READ 0
26 #define DMA_MODE_WRITE 1
27 #define DMA_MODE_CASCADE 2
28 #define DMA_AUTOINIT 4
30 extern spinlock_t dma_spin_lock;
32 static inline unsigned long claim_dma_lock(void)
34 unsigned long flags;
35 spin_lock_irqsave(&dma_spin_lock, flags);
36 return flags;
39 static inline void release_dma_lock(unsigned long flags)
41 spin_unlock_irqrestore(&dma_spin_lock, flags);
44 /* Clear the 'DMA Pointer Flip Flop'.
45 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
47 #define clear_dma_ff(channel)
49 /* Set only the page register bits of the transfer address.
51 * NOTE: This is an architecture specific function, and should
52 * be hidden from the drivers
54 extern void set_dma_page(dmach_t channel, char pagenr);
56 /* Request a DMA channel
58 * Some architectures may need to do allocate an interrupt
60 extern int request_dma(dmach_t channel, const char * device_id);
62 /* Free a DMA channel
64 * Some architectures may need to do free an interrupt
66 extern void free_dma(dmach_t channel);
68 /* Enable DMA for this channel
70 * On some architectures, this may have other side effects like
71 * enabling an interrupt and setting the DMA registers.
73 extern void enable_dma(dmach_t channel);
75 /* Disable DMA for this channel
77 * On some architectures, this may have other side effects like
78 * disabling an interrupt or whatever.
80 extern void disable_dma(dmach_t channel);
82 /* Test whether the specified channel has an active DMA transfer
84 extern int dma_channel_active(dmach_t channel);
86 /* Set the DMA scatter gather list for this channel
88 * This should not be called if a DMA channel is enabled,
89 * especially since some DMA architectures don't update the
90 * DMA address immediately, but defer it to the enable_dma().
92 extern void set_dma_sg(dmach_t channel, struct scatterlist *sg, int nr_sg);
94 /* Set the DMA address for this channel
96 * This should not be called if a DMA channel is enabled,
97 * especially since some DMA architectures don't update the
98 * DMA address immediately, but defer it to the enable_dma().
100 extern void __set_dma_addr(dmach_t channel, void *addr);
101 #define set_dma_addr(channel, addr) \
102 __set_dma_addr(channel, bus_to_virt(addr))
104 /* Set the DMA byte count for this channel
106 * This should not be called if a DMA channel is enabled,
107 * especially since some DMA architectures don't update the
108 * DMA count immediately, but defer it to the enable_dma().
110 extern void set_dma_count(dmach_t channel, unsigned long count);
112 /* Set the transfer direction for this channel
114 * This should not be called if a DMA channel is enabled,
115 * especially since some DMA architectures don't update the
116 * DMA transfer direction immediately, but defer it to the
117 * enable_dma().
119 extern void set_dma_mode(dmach_t channel, dmamode_t mode);
121 /* Set the transfer speed for this channel
123 extern void set_dma_speed(dmach_t channel, int cycle_ns);
125 /* Get DMA residue count. After a DMA transfer, this
126 * should return zero. Reading this while a DMA transfer is
127 * still in progress will return unpredictable results.
128 * If called before the channel has been used, it may return 1.
129 * Otherwise, it returns the number of _bytes_ left to transfer.
131 extern int get_dma_residue(dmach_t channel);
133 #ifndef NO_DMA
134 #define NO_DMA 255
135 #endif
137 #ifdef CONFIG_PCI
138 extern int isa_dma_bridge_buggy;
139 #else
140 #define isa_dma_bridge_buggy (0)
141 #endif
143 #endif /* _ARM_DMA_H */