1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/slab.h>
34 #include <linux/if_ether.h>
36 #include "e1000_mac.h"
37 #include "e1000_82575.h"
39 static s32
igb_get_invariants_82575(struct e1000_hw
*);
40 static s32
igb_acquire_phy_82575(struct e1000_hw
*);
41 static void igb_release_phy_82575(struct e1000_hw
*);
42 static s32
igb_acquire_nvm_82575(struct e1000_hw
*);
43 static void igb_release_nvm_82575(struct e1000_hw
*);
44 static s32
igb_check_for_link_82575(struct e1000_hw
*);
45 static s32
igb_get_cfg_done_82575(struct e1000_hw
*);
46 static s32
igb_init_hw_82575(struct e1000_hw
*);
47 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*);
48 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
*);
49 static s32
igb_reset_hw_82575(struct e1000_hw
*);
50 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*, bool);
51 static s32
igb_setup_copper_link_82575(struct e1000_hw
*);
52 static s32
igb_setup_fiber_serdes_link_82575(struct e1000_hw
*);
53 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
);
54 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*);
55 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*, u16
);
56 static s32
igb_configure_pcs_link_82575(struct e1000_hw
*);
57 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*, u16
*,
59 static s32
igb_get_phy_id_82575(struct e1000_hw
*);
60 static void igb_release_swfw_sync_82575(struct e1000_hw
*, u16
);
61 static bool igb_sgmii_active_82575(struct e1000_hw
*);
62 static s32
igb_reset_init_script_82575(struct e1000_hw
*);
63 static s32
igb_read_mac_addr_82575(struct e1000_hw
*);
66 struct e1000_dev_spec_82575
{
70 static s32
igb_get_invariants_82575(struct e1000_hw
*hw
)
72 struct e1000_phy_info
*phy
= &hw
->phy
;
73 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
74 struct e1000_mac_info
*mac
= &hw
->mac
;
75 struct e1000_dev_spec_82575
*dev_spec
;
81 switch (hw
->device_id
) {
82 case E1000_DEV_ID_82575EB_COPPER
:
83 case E1000_DEV_ID_82575EB_FIBER_SERDES
:
84 case E1000_DEV_ID_82575GB_QUAD_COPPER
:
85 mac
->type
= e1000_82575
;
87 case E1000_DEV_ID_82576
:
88 case E1000_DEV_ID_82576_FIBER
:
89 case E1000_DEV_ID_82576_SERDES
:
90 mac
->type
= e1000_82576
;
93 return -E1000_ERR_MAC_INIT
;
97 /* MAC initialization */
98 hw
->dev_spec_size
= sizeof(struct e1000_dev_spec_82575
);
100 /* Device-specific structure allocation */
101 hw
->dev_spec
= kzalloc(hw
->dev_spec_size
, GFP_KERNEL
);
106 dev_spec
= (struct e1000_dev_spec_82575
*)hw
->dev_spec
;
110 * The 82575 uses bits 22:23 for link mode. The mode can be changed
111 * based on the EEPROM. We cannot rely upon device ID. There
112 * is no distinguishable difference between fiber and internal
113 * SerDes mode on the 82575. There can be an external PHY attached
114 * on the SGMII interface. For this, we'll set sgmii_active to true.
116 phy
->media_type
= e1000_media_type_copper
;
117 dev_spec
->sgmii_active
= false;
119 ctrl_ext
= rd32(E1000_CTRL_EXT
);
120 if ((ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) ==
121 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
) {
122 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
123 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
124 } else if (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_SGMII
) {
125 dev_spec
->sgmii_active
= true;
126 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
128 ctrl_ext
&= ~E1000_CTRL_I2C_ENA
;
130 wr32(E1000_CTRL_EXT
, ctrl_ext
);
132 /* Set mta register count */
133 mac
->mta_reg_count
= 128;
134 /* Set rar entry count */
135 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82575
;
136 if (mac
->type
== e1000_82576
)
137 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82576
;
138 /* Set if part includes ASF firmware */
139 mac
->asf_firmware_present
= true;
140 /* Set if manageability features are enabled. */
141 mac
->arc_subsystem_valid
=
142 (rd32(E1000_FWSM
) & E1000_FWSM_MODE_MASK
)
145 /* physical interface link setup */
146 mac
->ops
.setup_physical_interface
=
147 (hw
->phy
.media_type
== e1000_media_type_copper
)
148 ? igb_setup_copper_link_82575
149 : igb_setup_fiber_serdes_link_82575
;
151 /* NVM initialization */
152 eecd
= rd32(E1000_EECD
);
154 nvm
->opcode_bits
= 8;
156 switch (nvm
->override
) {
157 case e1000_nvm_override_spi_large
:
159 nvm
->address_bits
= 16;
161 case e1000_nvm_override_spi_small
:
163 nvm
->address_bits
= 8;
166 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
167 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
? 16 : 8;
171 nvm
->type
= e1000_nvm_eeprom_spi
;
173 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
174 E1000_EECD_SIZE_EX_SHIFT
);
177 * Added to a constant, "size" becomes the left-shift value
178 * for setting word_size.
180 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
182 /* EEPROM access above 16k is unsupported */
185 nvm
->word_size
= 1 << size
;
187 /* setup PHY parameters */
188 if (phy
->media_type
!= e1000_media_type_copper
) {
189 phy
->type
= e1000_phy_none
;
193 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
194 phy
->reset_delay_us
= 100;
196 /* PHY function pointers */
197 if (igb_sgmii_active_82575(hw
)) {
198 phy
->ops
.reset_phy
= igb_phy_hw_reset_sgmii_82575
;
199 phy
->ops
.read_phy_reg
= igb_read_phy_reg_sgmii_82575
;
200 phy
->ops
.write_phy_reg
= igb_write_phy_reg_sgmii_82575
;
202 phy
->ops
.reset_phy
= igb_phy_hw_reset
;
203 phy
->ops
.read_phy_reg
= igb_read_phy_reg_igp
;
204 phy
->ops
.write_phy_reg
= igb_write_phy_reg_igp
;
207 /* Set phy->phy_addr and phy->id. */
208 ret_val
= igb_get_phy_id_82575(hw
);
212 /* Verify phy id and set remaining function pointers */
214 case M88E1111_I_PHY_ID
:
215 phy
->type
= e1000_phy_m88
;
216 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
217 phy
->ops
.get_cable_length
= igb_get_cable_length_m88
;
218 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
220 case IGP03E1000_E_PHY_ID
:
221 phy
->type
= e1000_phy_igp_3
;
222 phy
->ops
.get_phy_info
= igb_get_phy_info_igp
;
223 phy
->ops
.get_cable_length
= igb_get_cable_length_igp_2
;
224 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_igp
;
225 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82575
;
226 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state
;
229 return -E1000_ERR_PHY
;
236 * igb_acquire_phy_82575 - Acquire rights to access PHY
237 * @hw: pointer to the HW structure
239 * Acquire access rights to the correct PHY. This is a
240 * function pointer entry point called by the api module.
242 static s32
igb_acquire_phy_82575(struct e1000_hw
*hw
)
246 mask
= hw
->bus
.func
? E1000_SWFW_PHY1_SM
: E1000_SWFW_PHY0_SM
;
248 return igb_acquire_swfw_sync_82575(hw
, mask
);
252 * igb_release_phy_82575 - Release rights to access PHY
253 * @hw: pointer to the HW structure
255 * A wrapper to release access rights to the correct PHY. This is a
256 * function pointer entry point called by the api module.
258 static void igb_release_phy_82575(struct e1000_hw
*hw
)
262 mask
= hw
->bus
.func
? E1000_SWFW_PHY1_SM
: E1000_SWFW_PHY0_SM
;
263 igb_release_swfw_sync_82575(hw
, mask
);
267 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
268 * @hw: pointer to the HW structure
269 * @offset: register offset to be read
270 * @data: pointer to the read data
272 * Reads the PHY register at offset using the serial gigabit media independent
273 * interface and stores the retrieved information in data.
275 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
278 struct e1000_phy_info
*phy
= &hw
->phy
;
281 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
282 hw_dbg("PHY Address %u is out of range\n", offset
);
283 return -E1000_ERR_PARAM
;
287 * Set up Op-code, Phy Address, and register address in the I2CCMD
288 * register. The MAC will take care of interfacing with the
289 * PHY to retrieve the desired data.
291 i2ccmd
= ((offset
<< E1000_I2CCMD_REG_ADDR_SHIFT
) |
292 (phy
->addr
<< E1000_I2CCMD_PHY_ADDR_SHIFT
) |
293 (E1000_I2CCMD_OPCODE_READ
));
295 wr32(E1000_I2CCMD
, i2ccmd
);
297 /* Poll the ready bit to see if the I2C read completed */
298 for (i
= 0; i
< E1000_I2CCMD_PHY_TIMEOUT
; i
++) {
300 i2ccmd
= rd32(E1000_I2CCMD
);
301 if (i2ccmd
& E1000_I2CCMD_READY
)
304 if (!(i2ccmd
& E1000_I2CCMD_READY
)) {
305 hw_dbg("I2CCMD Read did not complete\n");
306 return -E1000_ERR_PHY
;
308 if (i2ccmd
& E1000_I2CCMD_ERROR
) {
309 hw_dbg("I2CCMD Error bit set\n");
310 return -E1000_ERR_PHY
;
313 /* Need to byte-swap the 16-bit value. */
314 *data
= ((i2ccmd
>> 8) & 0x00FF) | ((i2ccmd
<< 8) & 0xFF00);
320 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
321 * @hw: pointer to the HW structure
322 * @offset: register offset to write to
323 * @data: data to write at register offset
325 * Writes the data to PHY register at the offset using the serial gigabit
326 * media independent interface.
328 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
331 struct e1000_phy_info
*phy
= &hw
->phy
;
333 u16 phy_data_swapped
;
335 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
336 hw_dbg("PHY Address %d is out of range\n", offset
);
337 return -E1000_ERR_PARAM
;
340 /* Swap the data bytes for the I2C interface */
341 phy_data_swapped
= ((data
>> 8) & 0x00FF) | ((data
<< 8) & 0xFF00);
344 * Set up Op-code, Phy Address, and register address in the I2CCMD
345 * register. The MAC will take care of interfacing with the
346 * PHY to retrieve the desired data.
348 i2ccmd
= ((offset
<< E1000_I2CCMD_REG_ADDR_SHIFT
) |
349 (phy
->addr
<< E1000_I2CCMD_PHY_ADDR_SHIFT
) |
350 E1000_I2CCMD_OPCODE_WRITE
|
353 wr32(E1000_I2CCMD
, i2ccmd
);
355 /* Poll the ready bit to see if the I2C read completed */
356 for (i
= 0; i
< E1000_I2CCMD_PHY_TIMEOUT
; i
++) {
358 i2ccmd
= rd32(E1000_I2CCMD
);
359 if (i2ccmd
& E1000_I2CCMD_READY
)
362 if (!(i2ccmd
& E1000_I2CCMD_READY
)) {
363 hw_dbg("I2CCMD Write did not complete\n");
364 return -E1000_ERR_PHY
;
366 if (i2ccmd
& E1000_I2CCMD_ERROR
) {
367 hw_dbg("I2CCMD Error bit set\n");
368 return -E1000_ERR_PHY
;
375 * igb_get_phy_id_82575 - Retrieve PHY addr and id
376 * @hw: pointer to the HW structure
378 * Retrieves the PHY address and ID for both PHY's which do and do not use
381 static s32
igb_get_phy_id_82575(struct e1000_hw
*hw
)
383 struct e1000_phy_info
*phy
= &hw
->phy
;
388 * For SGMII PHYs, we try the list of possible addresses until
389 * we find one that works. For non-SGMII PHYs
390 * (e.g. integrated copper PHYs), an address of 1 should
391 * work. The result of this function should mean phy->phy_addr
392 * and phy->id are set correctly.
394 if (!(igb_sgmii_active_82575(hw
))) {
396 ret_val
= igb_get_phy_id(hw
);
401 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
402 * Therefore, we need to test 1-7
404 for (phy
->addr
= 1; phy
->addr
< 8; phy
->addr
++) {
405 ret_val
= igb_read_phy_reg_sgmii_82575(hw
, PHY_ID1
, &phy_id
);
407 hw_dbg("Vendor ID 0x%08X read at address %u\n",
410 * At the time of this writing, The M88 part is
411 * the only supported SGMII PHY product.
413 if (phy_id
== M88_VENDOR
)
416 hw_dbg("PHY address %u was unreadable\n", phy
->addr
);
420 /* A valid PHY type couldn't be found. */
421 if (phy
->addr
== 8) {
423 ret_val
= -E1000_ERR_PHY
;
427 ret_val
= igb_get_phy_id(hw
);
434 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
435 * @hw: pointer to the HW structure
437 * Resets the PHY using the serial gigabit media independent interface.
439 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*hw
)
444 * This isn't a true "hard" reset, but is the only reset
445 * available to us at this time.
448 hw_dbg("Soft resetting SGMII attached PHY...\n");
451 * SFP documentation requires the following to configure the SPF module
452 * to work on SGMII. No further documentation is given.
454 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, 0x1B, 0x8084);
458 ret_val
= igb_phy_sw_reset(hw
);
465 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
466 * @hw: pointer to the HW structure
467 * @active: true to enable LPLU, false to disable
469 * Sets the LPLU D0 state according to the active flag. When
470 * activating LPLU this function also disables smart speed
471 * and vice versa. LPLU will not be activated unless the
472 * device autonegotiation advertisement meets standards of
473 * either 10 or 10/100 or 10/100/1000 at all duplexes.
474 * This is a function pointer entry point only called by
475 * PHY setup routines.
477 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*hw
, bool active
)
479 struct e1000_phy_info
*phy
= &hw
->phy
;
483 ret_val
= phy
->ops
.read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
488 data
|= IGP02E1000_PM_D0_LPLU
;
489 ret_val
= phy
->ops
.write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
494 /* When LPLU is enabled, we should disable SmartSpeed */
495 ret_val
= phy
->ops
.read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
497 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
498 ret_val
= phy
->ops
.write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
503 data
&= ~IGP02E1000_PM_D0_LPLU
;
504 ret_val
= phy
->ops
.write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
507 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
508 * during Dx states where the power conservation is most
509 * important. During driver activity we should enable
510 * SmartSpeed, so performance is maintained.
512 if (phy
->smart_speed
== e1000_smart_speed_on
) {
513 ret_val
= phy
->ops
.read_phy_reg(hw
,
514 IGP01E1000_PHY_PORT_CONFIG
, &data
);
518 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
519 ret_val
= phy
->ops
.write_phy_reg(hw
,
520 IGP01E1000_PHY_PORT_CONFIG
, data
);
523 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
524 ret_val
= phy
->ops
.read_phy_reg(hw
,
525 IGP01E1000_PHY_PORT_CONFIG
, &data
);
529 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
530 ret_val
= phy
->ops
.write_phy_reg(hw
,
531 IGP01E1000_PHY_PORT_CONFIG
, data
);
542 * igb_acquire_nvm_82575 - Request for access to EEPROM
543 * @hw: pointer to the HW structure
545 * Acquire the necessary semaphores for exclusive access to the EEPROM.
546 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
547 * Return successful if access grant bit set, else clear the request for
548 * EEPROM access and return -E1000_ERR_NVM (-1).
550 static s32
igb_acquire_nvm_82575(struct e1000_hw
*hw
)
554 ret_val
= igb_acquire_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
558 ret_val
= igb_acquire_nvm(hw
);
561 igb_release_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
568 * igb_release_nvm_82575 - Release exclusive access to EEPROM
569 * @hw: pointer to the HW structure
571 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
572 * then release the semaphores acquired.
574 static void igb_release_nvm_82575(struct e1000_hw
*hw
)
577 igb_release_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
581 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
582 * @hw: pointer to the HW structure
583 * @mask: specifies which semaphore to acquire
585 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
586 * will also specify which port we're acquiring the lock for.
588 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
592 u32 fwmask
= mask
<< 16;
594 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
596 while (i
< timeout
) {
597 if (igb_get_hw_semaphore(hw
)) {
598 ret_val
= -E1000_ERR_SWFW_SYNC
;
602 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
603 if (!(swfw_sync
& (fwmask
| swmask
)))
607 * Firmware currently using resource (fwmask)
608 * or other software thread using resource (swmask)
610 igb_put_hw_semaphore(hw
);
616 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
617 ret_val
= -E1000_ERR_SWFW_SYNC
;
622 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
624 igb_put_hw_semaphore(hw
);
631 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
632 * @hw: pointer to the HW structure
633 * @mask: specifies which semaphore to acquire
635 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
636 * will also specify which port we're releasing the lock for.
638 static void igb_release_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
642 while (igb_get_hw_semaphore(hw
) != 0);
645 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
647 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
649 igb_put_hw_semaphore(hw
);
653 * igb_get_cfg_done_82575 - Read config done bit
654 * @hw: pointer to the HW structure
656 * Read the management control register for the config done bit for
657 * completion status. NOTE: silicon which is EEPROM-less will fail trying
658 * to read the config done bit, so an error is *ONLY* logged and returns
659 * 0. If we were to return with error, EEPROM-less silicon
660 * would not be able to be reset or change link.
662 static s32
igb_get_cfg_done_82575(struct e1000_hw
*hw
)
664 s32 timeout
= PHY_CFG_TIMEOUT
;
666 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
668 if (hw
->bus
.func
== 1)
669 mask
= E1000_NVM_CFG_DONE_PORT_1
;
672 if (rd32(E1000_EEMNGCTL
) & mask
)
678 hw_dbg("MNG configuration cycle has not completed.\n");
680 /* If EEPROM is not marked present, init the PHY manually */
681 if (((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0) &&
682 (hw
->phy
.type
== e1000_phy_igp_3
))
683 igb_phy_init_script_igp3(hw
);
689 * igb_check_for_link_82575 - Check for link
690 * @hw: pointer to the HW structure
692 * If sgmii is enabled, then use the pcs register to determine link, otherwise
693 * use the generic interface for determining link.
695 static s32
igb_check_for_link_82575(struct e1000_hw
*hw
)
700 /* SGMII link check is done through the PCS register. */
701 if ((hw
->phy
.media_type
!= e1000_media_type_copper
) ||
702 (igb_sgmii_active_82575(hw
)))
703 ret_val
= igb_get_pcs_speed_and_duplex_82575(hw
, &speed
,
706 ret_val
= igb_check_for_copper_link(hw
);
711 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
712 * @hw: pointer to the HW structure
713 * @speed: stores the current speed
714 * @duplex: stores the current duplex
716 * Using the physical coding sub-layer (PCS), retrieve the current speed and
717 * duplex, then store the values in the pointers provided.
719 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*hw
, u16
*speed
,
722 struct e1000_mac_info
*mac
= &hw
->mac
;
725 /* Set up defaults for the return values of this function */
726 mac
->serdes_has_link
= false;
731 * Read the PCS Status register for link state. For non-copper mode,
732 * the status register is not accurate. The PCS status register is
735 pcs
= rd32(E1000_PCS_LSTAT
);
738 * The link up bit determines when link is up on autoneg. The sync ok
739 * gets set once both sides sync up and agree upon link. Stable link
740 * can be determined by checking for both link up and link sync ok
742 if ((pcs
& E1000_PCS_LSTS_LINK_OK
) && (pcs
& E1000_PCS_LSTS_SYNK_OK
)) {
743 mac
->serdes_has_link
= true;
745 /* Detect and store PCS speed */
746 if (pcs
& E1000_PCS_LSTS_SPEED_1000
) {
748 } else if (pcs
& E1000_PCS_LSTS_SPEED_100
) {
754 /* Detect and store PCS duplex */
755 if (pcs
& E1000_PCS_LSTS_DUPLEX_FULL
) {
756 *duplex
= FULL_DUPLEX
;
758 *duplex
= HALF_DUPLEX
;
766 * igb_init_rx_addrs_82575 - Initialize receive address's
767 * @hw: pointer to the HW structure
768 * @rar_count: receive address registers
770 * Setups the receive address registers by setting the base receive address
771 * register to the devices MAC address and clearing all the other receive
772 * address registers to 0.
774 static void igb_init_rx_addrs_82575(struct e1000_hw
*hw
, u16 rar_count
)
777 u8 addr
[6] = {0,0,0,0,0,0};
779 * This function is essentially the same as that of
780 * e1000_init_rx_addrs_generic. However it also takes care
781 * of the special case where the register offset of the
782 * second set of RARs begins elsewhere. This is implicitly taken care by
783 * function e1000_rar_set_generic.
786 hw_dbg("e1000_init_rx_addrs_82575");
788 /* Setup the receive address */
789 hw_dbg("Programming MAC Address into RAR[0]\n");
790 hw
->mac
.ops
.rar_set(hw
, hw
->mac
.addr
, 0);
792 /* Zero out the other (rar_entry_count - 1) receive addresses */
793 hw_dbg("Clearing RAR[1-%u]\n", rar_count
-1);
794 for (i
= 1; i
< rar_count
; i
++)
795 hw
->mac
.ops
.rar_set(hw
, addr
, i
);
799 * igb_update_mc_addr_list_82575 - Update Multicast addresses
800 * @hw: pointer to the HW structure
801 * @mc_addr_list: array of multicast addresses to program
802 * @mc_addr_count: number of multicast addresses to program
803 * @rar_used_count: the first RAR register free to program
804 * @rar_count: total number of supported Receive Address Registers
806 * Updates the Receive Address Registers and Multicast Table Array.
807 * The caller must have a packed mc_addr_list of multicast addresses.
808 * The parameter rar_count will usually be hw->mac.rar_entry_count
809 * unless there are workarounds that change this.
811 void igb_update_mc_addr_list_82575(struct e1000_hw
*hw
,
812 u8
*mc_addr_list
, u32 mc_addr_count
,
813 u32 rar_used_count
, u32 rar_count
)
817 u8 addr
[6] = {0,0,0,0,0,0};
819 * This function is essentially the same as that of
820 * igb_update_mc_addr_list_generic. However it also takes care
821 * of the special case where the register offset of the
822 * second set of RARs begins elsewhere. This is implicitly taken care by
823 * function e1000_rar_set_generic.
827 * Load the first set of multicast addresses into the exact
828 * filters (RAR). If there are not enough to fill the RAR
829 * array, clear the filters.
831 for (i
= rar_used_count
; i
< rar_count
; i
++) {
833 igb_rar_set(hw
, mc_addr_list
, i
);
835 mc_addr_list
+= ETH_ALEN
;
837 igb_rar_set(hw
, addr
, i
);
841 /* Clear the old settings from the MTA */
842 hw_dbg("Clearing MTA\n");
843 for (i
= 0; i
< hw
->mac
.mta_reg_count
; i
++) {
844 array_wr32(E1000_MTA
, i
, 0);
848 /* Load any remaining multicast addresses into the hash table. */
849 for (; mc_addr_count
> 0; mc_addr_count
--) {
850 hash_value
= igb_hash_mc_addr(hw
, mc_addr_list
);
851 hw_dbg("Hash value = 0x%03X\n", hash_value
);
852 igb_mta_set(hw
, hash_value
);
853 mc_addr_list
+= ETH_ALEN
;
858 * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down
859 * @hw: pointer to the HW structure
861 * In the case of fiber serdes, shut down optics and PCS on driver unload
862 * when management pass thru is not enabled.
864 void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw
*hw
)
868 if (hw
->mac
.type
!= e1000_82576
||
869 (hw
->phy
.media_type
!= e1000_media_type_fiber
&&
870 hw
->phy
.media_type
!= e1000_media_type_internal_serdes
))
873 /* if the management interface is not enabled, then power down */
874 if (!igb_enable_mng_pass_thru(hw
)) {
875 /* Disable PCS to turn off link */
876 reg
= rd32(E1000_PCS_CFG0
);
877 reg
&= ~E1000_PCS_CFG_PCS_EN
;
878 wr32(E1000_PCS_CFG0
, reg
);
880 /* shutdown the laser */
881 reg
= rd32(E1000_CTRL_EXT
);
882 reg
|= E1000_CTRL_EXT_SDP7_DATA
;
883 wr32(E1000_CTRL_EXT
, reg
);
885 /* flush the write to verify completion */
894 * igb_reset_hw_82575 - Reset hardware
895 * @hw: pointer to the HW structure
897 * This resets the hardware into a known state. This is a
898 * function pointer entry point called by the api module.
900 static s32
igb_reset_hw_82575(struct e1000_hw
*hw
)
906 * Prevent the PCI-E bus from sticking if there is no TLP connection
907 * on the last TLP read/write transaction when MAC is reset.
909 ret_val
= igb_disable_pcie_master(hw
);
911 hw_dbg("PCI-E Master disable polling has failed.\n");
913 hw_dbg("Masking off all interrupts\n");
914 wr32(E1000_IMC
, 0xffffffff);
917 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
922 ctrl
= rd32(E1000_CTRL
);
924 hw_dbg("Issuing a global reset to MAC\n");
925 wr32(E1000_CTRL
, ctrl
| E1000_CTRL_RST
);
927 ret_val
= igb_get_auto_rd_done(hw
);
930 * When auto config read does not complete, do not
931 * return with an error. This can happen in situations
932 * where there is no eeprom and prevents getting link.
934 hw_dbg("Auto Read Done did not complete\n");
937 /* If EEPROM is not present, run manual init scripts */
938 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
939 igb_reset_init_script_82575(hw
);
941 /* Clear any pending interrupt events. */
942 wr32(E1000_IMC
, 0xffffffff);
943 icr
= rd32(E1000_ICR
);
945 igb_check_alt_mac_addr(hw
);
951 * igb_init_hw_82575 - Initialize hardware
952 * @hw: pointer to the HW structure
954 * This inits the hardware readying it for operation.
956 static s32
igb_init_hw_82575(struct e1000_hw
*hw
)
958 struct e1000_mac_info
*mac
= &hw
->mac
;
960 u16 i
, rar_count
= mac
->rar_entry_count
;
962 /* Initialize identification LED */
963 ret_val
= igb_id_led_init(hw
);
965 hw_dbg("Error initializing identification LED\n");
966 /* This is not fatal and we should not stop init due to this */
969 /* Disabling VLAN filtering */
970 hw_dbg("Initializing the IEEE VLAN\n");
973 /* Setup the receive address */
974 igb_init_rx_addrs_82575(hw
, rar_count
);
975 /* Zero out the Multicast HASH table */
976 hw_dbg("Zeroing the MTA\n");
977 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
978 array_wr32(E1000_MTA
, i
, 0);
980 /* Setup link and flow control */
981 ret_val
= igb_setup_link(hw
);
984 * Clear all of the statistics registers (clear on read). It is
985 * important that we do this after we have tried to establish link
986 * because the symbol error count will increment wildly if there
989 igb_clear_hw_cntrs_82575(hw
);
995 * igb_setup_copper_link_82575 - Configure copper link settings
996 * @hw: pointer to the HW structure
998 * Configures the link for auto-neg or forced speed and duplex. Then we check
999 * for link, once link is established calls to configure collision distance
1000 * and flow control are called.
1002 static s32
igb_setup_copper_link_82575(struct e1000_hw
*hw
)
1008 ctrl
= rd32(E1000_CTRL
);
1009 ctrl
|= E1000_CTRL_SLU
;
1010 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1011 wr32(E1000_CTRL
, ctrl
);
1013 switch (hw
->phy
.type
) {
1015 ret_val
= igb_copper_link_setup_m88(hw
);
1017 case e1000_phy_igp_3
:
1018 ret_val
= igb_copper_link_setup_igp(hw
);
1019 /* Setup activity LED */
1020 led_ctrl
= rd32(E1000_LEDCTL
);
1021 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
1022 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
1023 wr32(E1000_LEDCTL
, led_ctrl
);
1026 ret_val
= -E1000_ERR_PHY
;
1033 if (hw
->mac
.autoneg
) {
1035 * Setup autoneg and flow control advertisement
1036 * and perform autonegotiation.
1038 ret_val
= igb_copper_link_autoneg(hw
);
1043 * PHY will be set to 10H, 10F, 100H or 100F
1044 * depending on user settings.
1046 hw_dbg("Forcing Speed and Duplex\n");
1047 ret_val
= igb_phy_force_speed_duplex(hw
);
1049 hw_dbg("Error Forcing Speed and Duplex\n");
1054 ret_val
= igb_configure_pcs_link_82575(hw
);
1059 * Check link status. Wait up to 100 microseconds for link to become
1062 ret_val
= igb_phy_has_link(hw
, COPPER_LINK_UP_LIMIT
, 10, &link
);
1067 hw_dbg("Valid link established!!!\n");
1068 /* Config the MAC and PHY after link is up */
1069 igb_config_collision_dist(hw
);
1070 ret_val
= igb_config_fc_after_link_up(hw
);
1072 hw_dbg("Unable to establish link!!!\n");
1080 * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
1081 * @hw: pointer to the HW structure
1083 * Configures speed and duplex for fiber and serdes links.
1085 static s32
igb_setup_fiber_serdes_link_82575(struct e1000_hw
*hw
)
1090 * On the 82575, SerDes loopback mode persists until it is
1091 * explicitly turned off or a power cycle is performed. A read to
1092 * the register does not indicate its status. Therefore, we ensure
1093 * loopback mode is disabled during initialization.
1095 wr32(E1000_SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1097 /* Force link up, set 1gb, set both sw defined pins */
1098 reg
= rd32(E1000_CTRL
);
1099 reg
|= E1000_CTRL_SLU
|
1100 E1000_CTRL_SPD_1000
|
1102 E1000_CTRL_SWDPIN0
|
1104 wr32(E1000_CTRL
, reg
);
1106 /* Set switch control to serdes energy detect */
1107 reg
= rd32(E1000_CONNSW
);
1108 reg
|= E1000_CONNSW_ENRGSRC
;
1109 wr32(E1000_CONNSW
, reg
);
1112 * New SerDes mode allows for forcing speed or autonegotiating speed
1113 * at 1gb. Autoneg should be default set by most drivers. This is the
1114 * mode that will be compatible with older link partners and switches.
1115 * However, both are supported by the hardware and some drivers/tools.
1117 reg
= rd32(E1000_PCS_LCTL
);
1119 reg
&= ~(E1000_PCS_LCTL_AN_ENABLE
| E1000_PCS_LCTL_FLV_LINK_UP
|
1120 E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1122 if (hw
->mac
.autoneg
) {
1123 /* Set PCS register for autoneg */
1124 reg
|= E1000_PCS_LCTL_FSV_1000
| /* Force 1000 */
1125 E1000_PCS_LCTL_FDV_FULL
| /* SerDes Full duplex */
1126 E1000_PCS_LCTL_AN_ENABLE
| /* Enable Autoneg */
1127 E1000_PCS_LCTL_AN_RESTART
; /* Restart autoneg */
1128 hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg
);
1130 /* Set PCS register for forced speed */
1131 reg
|= E1000_PCS_LCTL_FLV_LINK_UP
| /* Force link up */
1132 E1000_PCS_LCTL_FSV_1000
| /* Force 1000 */
1133 E1000_PCS_LCTL_FDV_FULL
| /* SerDes Full duplex */
1134 E1000_PCS_LCTL_FSD
| /* Force Speed */
1135 E1000_PCS_LCTL_FORCE_LINK
; /* Force Link */
1136 hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg
);
1139 if (hw
->mac
.type
== e1000_82576
) {
1140 reg
|= E1000_PCS_LCTL_FORCE_FCTRL
;
1141 igb_force_mac_fc(hw
);
1144 wr32(E1000_PCS_LCTL
, reg
);
1150 * igb_configure_pcs_link_82575 - Configure PCS link
1151 * @hw: pointer to the HW structure
1153 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1154 * only used on copper connections where the serialized gigabit media
1155 * independent interface (sgmii) is being used. Configures the link
1156 * for auto-negotiation or forces speed/duplex.
1158 static s32
igb_configure_pcs_link_82575(struct e1000_hw
*hw
)
1160 struct e1000_mac_info
*mac
= &hw
->mac
;
1163 if (hw
->phy
.media_type
!= e1000_media_type_copper
||
1164 !(igb_sgmii_active_82575(hw
)))
1167 /* For SGMII, we need to issue a PCS autoneg restart */
1168 reg
= rd32(E1000_PCS_LCTL
);
1170 /* AN time out should be disabled for SGMII mode */
1171 reg
&= ~(E1000_PCS_LCTL_AN_TIMEOUT
);
1174 /* Make sure forced speed and force link are not set */
1175 reg
&= ~(E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1178 * The PHY should be setup prior to calling this function.
1179 * All we need to do is restart autoneg and enable autoneg.
1181 reg
|= E1000_PCS_LCTL_AN_RESTART
| E1000_PCS_LCTL_AN_ENABLE
;
1183 /* Set PCS register for forced speed */
1185 /* Turn off bits for full duplex, speed, and autoneg */
1186 reg
&= ~(E1000_PCS_LCTL_FSV_1000
|
1187 E1000_PCS_LCTL_FSV_100
|
1188 E1000_PCS_LCTL_FDV_FULL
|
1189 E1000_PCS_LCTL_AN_ENABLE
);
1191 /* Check for duplex first */
1192 if (mac
->forced_speed_duplex
& E1000_ALL_FULL_DUPLEX
)
1193 reg
|= E1000_PCS_LCTL_FDV_FULL
;
1196 if (mac
->forced_speed_duplex
& E1000_ALL_100_SPEED
)
1197 reg
|= E1000_PCS_LCTL_FSV_100
;
1199 /* Force speed and force link */
1200 reg
|= E1000_PCS_LCTL_FSD
|
1201 E1000_PCS_LCTL_FORCE_LINK
|
1202 E1000_PCS_LCTL_FLV_LINK_UP
;
1204 hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1207 wr32(E1000_PCS_LCTL
, reg
);
1214 * igb_sgmii_active_82575 - Return sgmii state
1215 * @hw: pointer to the HW structure
1217 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1218 * which can be enabled for use in the embedded applications. Simply
1219 * return the current state of the sgmii interface.
1221 static bool igb_sgmii_active_82575(struct e1000_hw
*hw
)
1223 struct e1000_dev_spec_82575
*dev_spec
;
1226 if (hw
->mac
.type
!= e1000_82575
) {
1231 dev_spec
= (struct e1000_dev_spec_82575
*)hw
->dev_spec
;
1233 ret_val
= dev_spec
->sgmii_active
;
1240 * igb_reset_init_script_82575 - Inits HW defaults after reset
1241 * @hw: pointer to the HW structure
1243 * Inits recommended HW defaults after a reset when there is no EEPROM
1244 * detected. This is only for the 82575.
1246 static s32
igb_reset_init_script_82575(struct e1000_hw
*hw
)
1248 if (hw
->mac
.type
== e1000_82575
) {
1249 hw_dbg("Running reset init script for 82575\n");
1250 /* SerDes configuration via SERDESCTRL */
1251 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x00, 0x0C);
1252 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x01, 0x78);
1253 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x1B, 0x23);
1254 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x23, 0x15);
1256 /* CCM configuration via CCMCTL register */
1257 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x14, 0x00);
1258 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x10, 0x00);
1260 /* PCIe lanes configuration */
1261 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x00, 0xEC);
1262 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x61, 0xDF);
1263 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x34, 0x05);
1264 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x2F, 0x81);
1266 /* PCIe PLL Configuration */
1267 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x02, 0x47);
1268 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x14, 0x00);
1269 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x10, 0x00);
1276 * igb_read_mac_addr_82575 - Read device MAC address
1277 * @hw: pointer to the HW structure
1279 static s32
igb_read_mac_addr_82575(struct e1000_hw
*hw
)
1283 if (igb_check_alt_mac_addr(hw
))
1284 ret_val
= igb_read_mac_addr(hw
);
1290 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1291 * @hw: pointer to the HW structure
1293 * Clears the hardware counters by reading the counter registers.
1295 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*hw
)
1299 igb_clear_hw_cntrs_base(hw
);
1301 temp
= rd32(E1000_PRC64
);
1302 temp
= rd32(E1000_PRC127
);
1303 temp
= rd32(E1000_PRC255
);
1304 temp
= rd32(E1000_PRC511
);
1305 temp
= rd32(E1000_PRC1023
);
1306 temp
= rd32(E1000_PRC1522
);
1307 temp
= rd32(E1000_PTC64
);
1308 temp
= rd32(E1000_PTC127
);
1309 temp
= rd32(E1000_PTC255
);
1310 temp
= rd32(E1000_PTC511
);
1311 temp
= rd32(E1000_PTC1023
);
1312 temp
= rd32(E1000_PTC1522
);
1314 temp
= rd32(E1000_ALGNERRC
);
1315 temp
= rd32(E1000_RXERRC
);
1316 temp
= rd32(E1000_TNCRS
);
1317 temp
= rd32(E1000_CEXTERR
);
1318 temp
= rd32(E1000_TSCTC
);
1319 temp
= rd32(E1000_TSCTFC
);
1321 temp
= rd32(E1000_MGTPRC
);
1322 temp
= rd32(E1000_MGTPDC
);
1323 temp
= rd32(E1000_MGTPTC
);
1325 temp
= rd32(E1000_IAC
);
1326 temp
= rd32(E1000_ICRXOC
);
1328 temp
= rd32(E1000_ICRXPTC
);
1329 temp
= rd32(E1000_ICRXATC
);
1330 temp
= rd32(E1000_ICTXPTC
);
1331 temp
= rd32(E1000_ICTXATC
);
1332 temp
= rd32(E1000_ICTXQEC
);
1333 temp
= rd32(E1000_ICTXQMTC
);
1334 temp
= rd32(E1000_ICRXDMTC
);
1336 temp
= rd32(E1000_CBTMPC
);
1337 temp
= rd32(E1000_HTDPMC
);
1338 temp
= rd32(E1000_CBRMPC
);
1339 temp
= rd32(E1000_RPTHC
);
1340 temp
= rd32(E1000_HGPTC
);
1341 temp
= rd32(E1000_HTCBDPC
);
1342 temp
= rd32(E1000_HGORCL
);
1343 temp
= rd32(E1000_HGORCH
);
1344 temp
= rd32(E1000_HGOTCL
);
1345 temp
= rd32(E1000_HGOTCH
);
1346 temp
= rd32(E1000_LENERRS
);
1348 /* This register should not be read in copper configurations */
1349 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
1350 temp
= rd32(E1000_SCVPC
);
1354 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1355 * @hw: pointer to the HW structure
1357 * After rx enable if managability is enabled then there is likely some
1358 * bad data at the start of the fifo and possibly in the DMA fifo. This
1359 * function clears the fifos and flushes any packets that came in as rx was
1362 void igb_rx_fifo_flush_82575(struct e1000_hw
*hw
)
1364 u32 rctl
, rlpml
, rxdctl
[4], rfctl
, temp_rctl
, rx_enabled
;
1367 if (hw
->mac
.type
!= e1000_82575
||
1368 !(rd32(E1000_MANC
) & E1000_MANC_RCV_TCO_EN
))
1371 /* Disable all RX queues */
1372 for (i
= 0; i
< 4; i
++) {
1373 rxdctl
[i
] = rd32(E1000_RXDCTL(i
));
1374 wr32(E1000_RXDCTL(i
),
1375 rxdctl
[i
] & ~E1000_RXDCTL_QUEUE_ENABLE
);
1377 /* Poll all queues to verify they have shut down */
1378 for (ms_wait
= 0; ms_wait
< 10; ms_wait
++) {
1381 for (i
= 0; i
< 4; i
++)
1382 rx_enabled
|= rd32(E1000_RXDCTL(i
));
1383 if (!(rx_enabled
& E1000_RXDCTL_QUEUE_ENABLE
))
1388 hw_dbg("Queue disable timed out after 10ms\n");
1390 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1391 * incoming packets are rejected. Set enable and wait 2ms so that
1392 * any packet that was coming in as RCTL.EN was set is flushed
1394 rfctl
= rd32(E1000_RFCTL
);
1395 wr32(E1000_RFCTL
, rfctl
& ~E1000_RFCTL_LEF
);
1397 rlpml
= rd32(E1000_RLPML
);
1398 wr32(E1000_RLPML
, 0);
1400 rctl
= rd32(E1000_RCTL
);
1401 temp_rctl
= rctl
& ~(E1000_RCTL_EN
| E1000_RCTL_SBP
);
1402 temp_rctl
|= E1000_RCTL_LPE
;
1404 wr32(E1000_RCTL
, temp_rctl
);
1405 wr32(E1000_RCTL
, temp_rctl
| E1000_RCTL_EN
);
1409 /* Enable RX queues that were previously enabled and restore our
1412 for (i
= 0; i
< 4; i
++)
1413 wr32(E1000_RXDCTL(i
), rxdctl
[i
]);
1414 wr32(E1000_RCTL
, rctl
);
1417 wr32(E1000_RLPML
, rlpml
);
1418 wr32(E1000_RFCTL
, rfctl
);
1420 /* Flush receive errors generated by workaround */
1426 static struct e1000_mac_operations e1000_mac_ops_82575
= {
1427 .reset_hw
= igb_reset_hw_82575
,
1428 .init_hw
= igb_init_hw_82575
,
1429 .check_for_link
= igb_check_for_link_82575
,
1430 .rar_set
= igb_rar_set
,
1431 .read_mac_addr
= igb_read_mac_addr_82575
,
1432 .get_speed_and_duplex
= igb_get_speed_and_duplex_copper
,
1435 static struct e1000_phy_operations e1000_phy_ops_82575
= {
1436 .acquire_phy
= igb_acquire_phy_82575
,
1437 .get_cfg_done
= igb_get_cfg_done_82575
,
1438 .release_phy
= igb_release_phy_82575
,
1441 static struct e1000_nvm_operations e1000_nvm_ops_82575
= {
1442 .acquire_nvm
= igb_acquire_nvm_82575
,
1443 .read_nvm
= igb_read_nvm_eerd
,
1444 .release_nvm
= igb_release_nvm_82575
,
1445 .write_nvm
= igb_write_nvm_spi
,
1448 const struct e1000_info e1000_82575_info
= {
1449 .get_invariants
= igb_get_invariants_82575
,
1450 .mac_ops
= &e1000_mac_ops_82575
,
1451 .phy_ops
= &e1000_phy_ops_82575
,
1452 .nvm_ops
= &e1000_nvm_ops_82575
,