arch/sh/kernel/cpu/clock-cpg.c

   1 #include <linux/clk.h>
   2 #include <linux/compiler.h>
   3 #include <linux/bootmem.h>
   4 #include <linux/io.h>
   5 #include <asm/clock.h>
   6
   7 static int sh_clk_mstp32_enable(struct clk *clk)
   8 {
   9         __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
  10                      clk->enable_reg);
  11         return 0;
  12 }
  13
  14 static void sh_clk_mstp32_disable(struct clk *clk)
  15 {
  16         __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
  17                      clk->enable_reg);
  18 }
  19
  20 static struct clk_ops sh_clk_mstp32_clk_ops = {
  21         .enable         = sh_clk_mstp32_enable,
  22         .disable        = sh_clk_mstp32_disable,
  23         .recalc         = followparent_recalc,
  24 };
  25
  26 int __init sh_clk_mstp32_register(struct clk *clks, int nr)
  27 {
  28         struct clk *clkp;
  29         int ret = 0;
  30         int k;
  31
  32         for (k = 0; !ret && (k < nr); k++) {
  33                 clkp = clks + k;
  34                 clkp->ops = &sh_clk_mstp32_clk_ops;
  35                 ret |= clk_register(clkp);
  36         }
  37
  38         return ret;
  39 }
  40
  41 static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
  42 {
  43         return clk_rate_table_round(clk, clk->freq_table, rate);
  44 }
  45
  46 static int sh_clk_div6_divisors[64] = {
  47         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
  48         17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
  49         33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
  50         49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
  51 };
  52
  53 static struct clk_div_mult_table sh_clk_div6_table = {
  54         .divisors = sh_clk_div6_divisors,
  55         .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
  56 };
  57
  58 static unsigned long sh_clk_div6_recalc(struct clk *clk)
  59 {
  60         struct clk_div_mult_table *table = &sh_clk_div6_table;
  61         unsigned int idx;
  62
  63         clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
  64                              table, NULL);
  65
  66         idx = __raw_readl(clk->enable_reg) & 0x003f;
  67
  68         return clk->freq_table[idx].frequency;
  69 }
  70
  71 static struct clk_ops sh_clk_div6_clk_ops = {
  72         .recalc         = sh_clk_div6_recalc,
  73         .round_rate     = sh_clk_div_round_rate,
  74 };
  75
  76 int __init sh_clk_div6_register(struct clk *clks, int nr)
  77 {
  78         struct clk *clkp;
  79         void *freq_table;
  80         int nr_divs = sh_clk_div6_table.nr_divisors;
  81         int freq_table_size = sizeof(struct cpufreq_frequency_table);
  82         int ret = 0;
  83         int k;
  84
  85         freq_table_size *= (nr_divs + 1);
  86
  87         freq_table = alloc_bootmem(freq_table_size * nr);
  88         if (!freq_table)
  89                 return -ENOMEM;
  90
  91         for (k = 0; !ret && (k < nr); k++) {
  92                 clkp = clks + k;
  93
  94                 clkp->ops = &sh_clk_div6_clk_ops;
  95                 clkp->id = -1;
  96                 clkp->freq_table = freq_table + (k * freq_table_size);
  97                 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
  98
  99                 ret = clk_register(clkp);
 100         }
 101
 102         return ret;
 103 }
 104
 105 static unsigned long sh_clk_div4_recalc(struct clk *clk)
 106 {
 107         struct clk_div_mult_table *table = clk->priv;
 108         unsigned int idx;
 109
 110         clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
 111                              table, &clk->arch_flags);
 112
 113         idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
 114
 115         return clk->freq_table[idx].frequency;
 116 }
 117
 118 static struct clk_ops sh_clk_div4_clk_ops = {
 119         .recalc         = sh_clk_div4_recalc,
 120         .round_rate     = sh_clk_div_round_rate,
 121 };
 122
 123 int __init sh_clk_div4_register(struct clk *clks, int nr,
 124                                 struct clk_div_mult_table *table)
 125 {
 126         struct clk *clkp;
 127         void *freq_table;
 128         int nr_divs = table->nr_divisors;
 129         int freq_table_size = sizeof(struct cpufreq_frequency_table);
 130         int ret = 0;
 131         int k;
 132
 133         freq_table_size *= (nr_divs + 1);
 134
 135         freq_table = alloc_bootmem(freq_table_size * nr);
 136         if (!freq_table)
 137                 return -ENOMEM;
 138
 139         for (k = 0; !ret && (k < nr); k++) {
 140                 clkp = clks + k;
 141
 142                 clkp->ops = &sh_clk_div4_clk_ops;
 143                 clkp->id = -1;
 144                 clkp->priv = table;
 145
 146                 clkp->freq_table = freq_table + (k * freq_table_size);
 147                 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
 148
 149                 ret = clk_register(clkp);
 150         }
 151
 152         return ret;
 153 }
 154
 155 #ifdef CONFIG_SH_CLK_CPG_LEGACY
 156 static struct clk master_clk = {
 157         .name           = "master_clk",
 158         .flags          = CLK_ENABLE_ON_INIT,
 159         .rate           = CONFIG_SH_PCLK_FREQ,
 160 };
 161
 162 static struct clk peripheral_clk = {
 163         .name           = "peripheral_clk",
 164         .parent         = &master_clk,
 165         .flags          = CLK_ENABLE_ON_INIT,
 166 };
 167
 168 static struct clk bus_clk = {
 169         .name           = "bus_clk",
 170         .parent         = &master_clk,
 171         .flags          = CLK_ENABLE_ON_INIT,
 172 };
 173
 174 static struct clk cpu_clk = {
 175         .name           = "cpu_clk",
 176         .parent         = &master_clk,
 177         .flags          = CLK_ENABLE_ON_INIT,
 178 };
 179
 180 /*
 181  * The ordering of these clocks matters, do not change it.
 182  */
 183 static struct clk *onchip_clocks[] = {
 184         &master_clk,
 185         &peripheral_clk,
 186         &bus_clk,
 187         &cpu_clk,
 188 };
 189
 190 int __init __deprecated cpg_clk_init(void)
 191 {
 192         int i, ret = 0;
 193
 194         for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
 195                 struct clk *clk = onchip_clocks[i];
 196                 arch_init_clk_ops(&clk->ops, i);
 197                 if (clk->ops)
 198                         ret |= clk_register(clk);
 199         }
 200
 201         return ret;
 202 }
 203
 204 /*
 205  * Placeholder for compatability, until the lazy CPUs do this
 206  * on their own.
 207  */
 208 int __init __weak arch_clk_init(void)
 209 {
 210         return cpg_clk_init();
 211 }
 212 #endif /* CONFIG_SH_CPG_CLK_LEGACY */