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IPoIB: fix error handling in ipoib_open
[linux-2.6/mini2440.git] / drivers / serial / sunsab.c
blobba9381fd3f2da3916e309cc41ad535a448d566ac
1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
5 *
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
8 *
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@redhat.com>
16 */
17
18 #include <linux/config.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/errno.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/major.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/ioport.h>
29 #include <linux/circ_buf.h>
30 #include <linux/serial.h>
31 #include <linux/sysrq.h>
32 #include <linux/console.h>
33 #include <linux/spinlock.h>
34 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 #include <asm/oplib.h>
41 #include <asm/ebus.h>
42
43 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
44 #define SUPPORT_SYSRQ
45 #endif
46
47 #include <linux/serial_core.h>
48
49 #include "suncore.h"
50 #include "sunsab.h"
51
52 struct uart_sunsab_port {
53 struct uart_port port; /* Generic UART port */
54 union sab82532_async_regs __iomem *regs; /* Chip registers */
55 unsigned long irqflags; /* IRQ state flags */
56 int dsr; /* Current DSR state */
57 unsigned int cec_timeout; /* Chip poll timeout... */
58 unsigned int tec_timeout; /* likewise */
59 unsigned char interrupt_mask0;/* ISR0 masking */
60 unsigned char interrupt_mask1;/* ISR1 masking */
61 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
62 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
63 int type; /* SAB82532 version */
64
65 /* Setting configuration bits while the transmitter is active
66 * can cause garbage characters to get emitted by the chip.
67 * Therefore, we cache such writes here and do the real register
68 * write the next time the transmitter becomes idle.
69 */
70 unsigned int cached_ebrg;
71 unsigned char cached_mode;
72 unsigned char cached_pvr;
73 unsigned char cached_dafo;
74 };
75
76 /*
77 * This assumes you have a 29.4912 MHz clock for your UART.
78 */
79 #define SAB_BASE_BAUD ( 29491200 / 16 )
80
81 static char *sab82532_version[16] = {
82 "V1.0", "V2.0", "V3.2", "V(0x03)",
83 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
84 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
85 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
86 };
87
88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
89 #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
90
91 #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
92 #define SAB82532_XMIT_FIFO_SIZE 32
93
94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
95 {
96 int timeout = up->tec_timeout;
97
98 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
99 udelay(1);
100 }
101
102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
103 {
104 int timeout = up->cec_timeout;
105
106 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
107 udelay(1);
108 }
109
110 static struct tty_struct *
111 receive_chars(struct uart_sunsab_port *up,
112 union sab82532_irq_status *stat,
113 struct pt_regs *regs)
114 {
115 struct tty_struct *tty = NULL;
116 unsigned char buf[32];
117 int saw_console_brk = 0;
118 int free_fifo = 0;
119 int count = 0;
120 int i;
121
122 if (up->port.info != NULL) /* Unopened serial console */
123 tty = up->port.info->tty;
124
125 /* Read number of BYTES (Character + Status) available. */
126 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
127 count = SAB82532_RECV_FIFO_SIZE;
128 free_fifo++;
129 }
130
131 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
132 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
133 free_fifo++;
134 }
135
136 /* Issue a FIFO read command in case we where idle. */
137 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
138 sunsab_cec_wait(up);
139 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
140 return tty;
141 }
142
143 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
144 free_fifo++;
145
146 /* Read the FIFO. */
147 for (i = 0; i < count; i++)
148 buf[i] = readb(&up->regs->r.rfifo[i]);
149
150 /* Issue Receive Message Complete command. */
151 if (free_fifo) {
152 sunsab_cec_wait(up);
153 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
154 }
155
156 /* Count may be zero for BRK, so we check for it here */
157 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
158 (up->port.line == up->port.cons->index))
159 saw_console_brk = 1;
160
161 for (i = 0; i < count; i++) {
162 unsigned char ch = buf[i];
163
164 if (tty == NULL) {
165 uart_handle_sysrq_char(&up->port, ch, regs);
166 continue;
167 }
168
169 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
170 tty->flip.work.func((void *)tty);
171 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
172 return tty; // if TTY_DONT_FLIP is set
173 }
174
175 *tty->flip.char_buf_ptr = ch;
176 *tty->flip.flag_buf_ptr = TTY_NORMAL;
177 up->port.icount.rx++;
178
179 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
180 SAB82532_ISR0_FERR |
181 SAB82532_ISR0_RFO)) ||
182 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
183 /*
184 * For statistics only
185 */
186 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
187 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
188 SAB82532_ISR0_FERR);
189 up->port.icount.brk++;
190 /*
191 * We do the SysRQ and SAK checking
192 * here because otherwise the break
193 * may get masked by ignore_status_mask
194 * or read_status_mask.
195 */
196 if (uart_handle_break(&up->port))
197 continue;
198 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
199 up->port.icount.parity++;
200 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
201 up->port.icount.frame++;
202 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
203 up->port.icount.overrun++;
204
205 /*
206 * Mask off conditions which should be ingored.
207 */
208 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
209 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
210
211 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
212 *tty->flip.flag_buf_ptr = TTY_BREAK;
213 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
214 *tty->flip.flag_buf_ptr = TTY_PARITY;
215 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
216 *tty->flip.flag_buf_ptr = TTY_FRAME;
217 }
218
219 if (uart_handle_sysrq_char(&up->port, ch, regs))
220 continue;
221
222 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
223 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0){
224 tty->flip.flag_buf_ptr++;
225 tty->flip.char_buf_ptr++;
226 tty->flip.count++;
227 }
228 if ((stat->sreg.isr0 & SAB82532_ISR0_RFO) &&
229 tty->flip.count < TTY_FLIPBUF_SIZE) {
230 /*
231 * Overrun is special, since it's reported
232 * immediately, and doesn't affect the current
233 * character.
234 */
235 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
236 tty->flip.flag_buf_ptr++;
237 tty->flip.char_buf_ptr++;
238 tty->flip.count++;
239 }
240 }
241
242 if (saw_console_brk)
243 sun_do_break();
244
245 return tty;
246 }
247
248 static void sunsab_stop_tx(struct uart_port *);
249 static void sunsab_tx_idle(struct uart_sunsab_port *);
250
251 static void transmit_chars(struct uart_sunsab_port *up,
252 union sab82532_irq_status *stat)
253 {
254 struct circ_buf *xmit = &up->port.info->xmit;
255 int i;
256
257 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
258 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
259 writeb(up->interrupt_mask1, &up->regs->w.imr1);
260 set_bit(SAB82532_ALLS, &up->irqflags);
261 }
262
263 #if 0 /* bde@nwlink.com says this check causes problems */
264 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
265 return;
266 #endif
267
268 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
269 return;
270
271 set_bit(SAB82532_XPR, &up->irqflags);
272 sunsab_tx_idle(up);
273
274 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
275 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
276 writeb(up->interrupt_mask1, &up->regs->w.imr1);
277 return;
278 }
279
280 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
281 writeb(up->interrupt_mask1, &up->regs->w.imr1);
282 clear_bit(SAB82532_ALLS, &up->irqflags);
283
284 /* Stuff 32 bytes into Transmit FIFO. */
285 clear_bit(SAB82532_XPR, &up->irqflags);
286 for (i = 0; i < up->port.fifosize; i++) {
287 writeb(xmit->buf[xmit->tail],
288 &up->regs->w.xfifo[i]);
289 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
290 up->port.icount.tx++;
291 if (uart_circ_empty(xmit))
292 break;
293 }
294
295 /* Issue a Transmit Frame command. */
296 sunsab_cec_wait(up);
297 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
298
299 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
300 uart_write_wakeup(&up->port);
301
302 if (uart_circ_empty(xmit))
303 sunsab_stop_tx(&up->port);
304 }
305
306 static void check_status(struct uart_sunsab_port *up,
307 union sab82532_irq_status *stat)
308 {
309 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
310 uart_handle_dcd_change(&up->port,
311 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
312
313 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
314 uart_handle_cts_change(&up->port,
315 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
316
317 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
318 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
319 up->port.icount.dsr++;
320 }
321
322 wake_up_interruptible(&up->port.info->delta_msr_wait);
323 }
324
325 static irqreturn_t sunsab_interrupt(int irq, void *dev_id, struct pt_regs *regs)
326 {
327 struct uart_sunsab_port *up = dev_id;
328 struct tty_struct *tty;
329 union sab82532_irq_status status;
330 unsigned long flags;
331
332 spin_lock_irqsave(&up->port.lock, flags);
333
334 status.stat = 0;
335 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA0)
336 status.sreg.isr0 = readb(&up->regs->r.isr0);
337 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA1)
338 status.sreg.isr1 = readb(&up->regs->r.isr1);
339
340 tty = NULL;
341 if (status.stat) {
342 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
343 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
344 (status.sreg.isr1 & SAB82532_ISR1_BRK))
345 tty = receive_chars(up, &status, regs);
346 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
347 (status.sreg.isr1 & SAB82532_ISR1_CSC))
348 check_status(up, &status);
349 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
350 transmit_chars(up, &status);
351 }
352
353 spin_unlock(&up->port.lock);
354
355 if (tty)
356 tty_flip_buffer_push(tty);
357
358 up++;
359
360 spin_lock(&up->port.lock);
361
362 status.stat = 0;
363 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB0)
364 status.sreg.isr0 = readb(&up->regs->r.isr0);
365 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB1)
366 status.sreg.isr1 = readb(&up->regs->r.isr1);
367
368 tty = NULL;
369 if (status.stat) {
370 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
371 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
372 (status.sreg.isr1 & SAB82532_ISR1_BRK))
373
374 tty = receive_chars(up, &status, regs);
375 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
376 (status.sreg.isr1 & (SAB82532_ISR1_BRK | SAB82532_ISR1_CSC)))
377 check_status(up, &status);
378 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
379 transmit_chars(up, &status);
380 }
381
382 spin_unlock_irqrestore(&up->port.lock, flags);
383
384 if (tty)
385 tty_flip_buffer_push(tty);
386
387 return IRQ_HANDLED;
388 }
389
390 /* port->lock is not held. */
391 static unsigned int sunsab_tx_empty(struct uart_port *port)
392 {
393 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
394 int ret;
395
396 /* Do not need a lock for a state test like this. */
397 if (test_bit(SAB82532_ALLS, &up->irqflags))
398 ret = TIOCSER_TEMT;
399 else
400 ret = 0;
401
402 return ret;
403 }
404
405 /* port->lock held by caller. */
406 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
407 {
408 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
409
410 if (mctrl & TIOCM_RTS) {
411 up->cached_mode &= ~SAB82532_MODE_FRTS;
412 up->cached_mode |= SAB82532_MODE_RTS;
413 } else {
414 up->cached_mode |= (SAB82532_MODE_FRTS |
415 SAB82532_MODE_RTS);
416 }
417 if (mctrl & TIOCM_DTR) {
418 up->cached_pvr &= ~(up->pvr_dtr_bit);
419 } else {
420 up->cached_pvr |= up->pvr_dtr_bit;
421 }
422
423 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
424 if (test_bit(SAB82532_XPR, &up->irqflags))
425 sunsab_tx_idle(up);
426 }
427
428 /* port->lock is held by caller and interrupts are disabled. */
429 static unsigned int sunsab_get_mctrl(struct uart_port *port)
430 {
431 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
432 unsigned char val;
433 unsigned int result;
434
435 result = 0;
436
437 val = readb(&up->regs->r.pvr);
438 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
439
440 val = readb(&up->regs->r.vstr);
441 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
442
443 val = readb(&up->regs->r.star);
444 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
445
446 return result;
447 }
448
449 /* port->lock held by caller. */
450 static void sunsab_stop_tx(struct uart_port *port)
451 {
452 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
453
454 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
455 writeb(up->interrupt_mask1, &up->regs->w.imr1);
456 }
457
458 /* port->lock held by caller. */
459 static void sunsab_tx_idle(struct uart_sunsab_port *up)
460 {
461 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
462 u8 tmp;
463
464 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
465 writeb(up->cached_mode, &up->regs->rw.mode);
466 writeb(up->cached_pvr, &up->regs->rw.pvr);
467 writeb(up->cached_dafo, &up->regs->w.dafo);
468
469 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
470 tmp = readb(&up->regs->rw.ccr2);
471 tmp &= ~0xc0;
472 tmp |= (up->cached_ebrg >> 2) & 0xc0;
473 writeb(tmp, &up->regs->rw.ccr2);
474 }
475 }
476
477 /* port->lock held by caller. */
478 static void sunsab_start_tx(struct uart_port *port)
479 {
480 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
481 struct circ_buf *xmit = &up->port.info->xmit;
482 int i;
483
484 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
485 writeb(up->interrupt_mask1, &up->regs->w.imr1);
486
487 if (!test_bit(SAB82532_XPR, &up->irqflags))
488 return;
489
490 clear_bit(SAB82532_ALLS, &up->irqflags);
491 clear_bit(SAB82532_XPR, &up->irqflags);
492
493 for (i = 0; i < up->port.fifosize; i++) {
494 writeb(xmit->buf[xmit->tail],
495 &up->regs->w.xfifo[i]);
496 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
497 up->port.icount.tx++;
498 if (uart_circ_empty(xmit))
499 break;
500 }
501
502 /* Issue a Transmit Frame command. */
503 sunsab_cec_wait(up);
504 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
505 }
506
507 /* port->lock is not held. */
508 static void sunsab_send_xchar(struct uart_port *port, char ch)
509 {
510 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
511 unsigned long flags;
512
513 spin_lock_irqsave(&up->port.lock, flags);
514
515 sunsab_tec_wait(up);
516 writeb(ch, &up->regs->w.tic);
517
518 spin_unlock_irqrestore(&up->port.lock, flags);
519 }
520
521 /* port->lock held by caller. */
522 static void sunsab_stop_rx(struct uart_port *port)
523 {
524 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
525
526 up->interrupt_mask0 |= SAB82532_ISR0_TCD;
527 writeb(up->interrupt_mask1, &up->regs->w.imr0);
528 }
529
530 /* port->lock held by caller. */
531 static void sunsab_enable_ms(struct uart_port *port)
532 {
533 /* For now we always receive these interrupts. */
534 }
535
536 /* port->lock is not held. */
537 static void sunsab_break_ctl(struct uart_port *port, int break_state)
538 {
539 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
540 unsigned long flags;
541 unsigned char val;
542
543 spin_lock_irqsave(&up->port.lock, flags);
544
545 val = up->cached_dafo;
546 if (break_state)
547 val |= SAB82532_DAFO_XBRK;
548 else
549 val &= ~SAB82532_DAFO_XBRK;
550 up->cached_dafo = val;
551
552 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
553 if (test_bit(SAB82532_XPR, &up->irqflags))
554 sunsab_tx_idle(up);
555
556 spin_unlock_irqrestore(&up->port.lock, flags);
557 }
558
559 /* port->lock is not held. */
560 static int sunsab_startup(struct uart_port *port)
561 {
562 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
563 unsigned long flags;
564 unsigned char tmp;
565
566 spin_lock_irqsave(&up->port.lock, flags);
567
568 /*
569 * Wait for any commands or immediate characters
570 */
571 sunsab_cec_wait(up);
572 sunsab_tec_wait(up);
573
574 /*
575 * Clear the FIFO buffers.
576 */
577 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
578 sunsab_cec_wait(up);
579 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
580
581 /*
582 * Clear the interrupt registers.
583 */
584 (void) readb(&up->regs->r.isr0);
585 (void) readb(&up->regs->r.isr1);
586
587 /*
588 * Now, initialize the UART
589 */
590 writeb(0, &up->regs->w.ccr0); /* power-down */
591 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
592 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
593 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
594 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
595 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
596 writeb(0, &up->regs->w.ccr3);
597 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
598 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
599 SAB82532_MODE_RAC);
600 writeb(up->cached_mode, &up->regs->w.mode);
601 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
602
603 tmp = readb(&up->regs->rw.ccr0);
604 tmp |= SAB82532_CCR0_PU; /* power-up */
605 writeb(tmp, &up->regs->rw.ccr0);
606
607 /*
608 * Finally, enable interrupts
609 */
610 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
611 SAB82532_IMR0_PLLA);
612 writeb(up->interrupt_mask0, &up->regs->w.imr0);
613 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
614 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
615 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
616 SAB82532_IMR1_XPR);
617 writeb(up->interrupt_mask1, &up->regs->w.imr1);
618 set_bit(SAB82532_ALLS, &up->irqflags);
619 set_bit(SAB82532_XPR, &up->irqflags);
620
621 spin_unlock_irqrestore(&up->port.lock, flags);
622
623 return 0;
624 }
625
626 /* port->lock is not held. */
627 static void sunsab_shutdown(struct uart_port *port)
628 {
629 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
630 unsigned long flags;
631
632 spin_lock_irqsave(&up->port.lock, flags);
633
634 /* Disable Interrupts */
635 up->interrupt_mask0 = 0xff;
636 writeb(up->interrupt_mask0, &up->regs->w.imr0);
637 up->interrupt_mask1 = 0xff;
638 writeb(up->interrupt_mask1, &up->regs->w.imr1);
639
640 /* Disable break condition */
641 up->cached_dafo = readb(&up->regs->rw.dafo);
642 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
643 writeb(up->cached_dafo, &up->regs->rw.dafo);
644
645 /* Disable Receiver */
646 up->cached_mode &= ~SAB82532_MODE_RAC;
647 writeb(up->cached_mode, &up->regs->rw.mode);
648
649 /*
650 * XXX FIXME
651 *
652 * If the chip is powered down here the system hangs/crashes during
653 * reboot or shutdown. This needs to be investigated further,
654 * similar behaviour occurs in 2.4 when the driver is configured
655 * as a module only. One hint may be that data is sometimes
656 * transmitted at 9600 baud during shutdown (regardless of the
657 * speed the chip was configured for when the port was open).
658 */
659 #if 0
660 /* Power Down */
661 tmp = readb(&up->regs->rw.ccr0);
662 tmp &= ~SAB82532_CCR0_PU;
663 writeb(tmp, &up->regs->rw.ccr0);
664 #endif
665
666 spin_unlock_irqrestore(&up->port.lock, flags);
667 }
668
669 /*
670 * This is used to figure out the divisor speeds.
671 *
672 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
673 *
674 * with 0 <= N < 64 and 0 <= M < 16
675 */
676
677 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
678 {
679 int n, m;
680
681 if (baud == 0) {
682 *n_ret = 0;
683 *m_ret = 0;
684 return;
685 }
686
687 /*
688 * We scale numbers by 10 so that we get better accuracy
689 * without having to use floating point. Here we increment m
690 * until n is within the valid range.
691 */
692 n = (SAB_BASE_BAUD * 10) / baud;
693 m = 0;
694 while (n >= 640) {
695 n = n / 2;
696 m++;
697 }
698 n = (n+5) / 10;
699 /*
700 * We try very hard to avoid speeds with M == 0 since they may
701 * not work correctly for XTAL frequences above 10 MHz.
702 */
703 if ((m == 0) && ((n & 1) == 0)) {
704 n = n / 2;
705 m++;
706 }
707 *n_ret = n - 1;
708 *m_ret = m;
709 }
710
711 /* Internal routine, port->lock is held and local interrupts are disabled. */
712 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
713 unsigned int iflag, unsigned int baud,
714 unsigned int quot)
715 {
716 unsigned char dafo;
717 int bits, n, m;
718
719 /* Byte size and parity */
720 switch (cflag & CSIZE) {
721 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
722 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
723 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
724 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
725 /* Never happens, but GCC is too dumb to figure it out */
726 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
727 }
728
729 if (cflag & CSTOPB) {
730 dafo |= SAB82532_DAFO_STOP;
731 bits++;
732 }
733
734 if (cflag & PARENB) {
735 dafo |= SAB82532_DAFO_PARE;
736 bits++;
737 }
738
739 if (cflag & PARODD) {
740 dafo |= SAB82532_DAFO_PAR_ODD;
741 } else {
742 dafo |= SAB82532_DAFO_PAR_EVEN;
743 }
744 up->cached_dafo = dafo;
745
746 calc_ebrg(baud, &n, &m);
747
748 up->cached_ebrg = n | (m << 6);
749
750 up->tec_timeout = (10 * 1000000) / baud;
751 up->cec_timeout = up->tec_timeout >> 2;
752
753 /* CTS flow control flags */
754 /* We encode read_status_mask and ignore_status_mask like so:
755 *
756 * ---------------------
757 * | ... | ISR1 | ISR0 |
758 * ---------------------
759 * .. 15 8 7 0
760 */
761
762 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
763 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
764 SAB82532_ISR0_CDSC);
765 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
766 SAB82532_ISR1_ALLS |
767 SAB82532_ISR1_XPR) << 8;
768 if (iflag & INPCK)
769 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
770 SAB82532_ISR0_FERR);
771 if (iflag & (BRKINT | PARMRK))
772 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
773
774 /*
775 * Characteres to ignore
776 */
777 up->port.ignore_status_mask = 0;
778 if (iflag & IGNPAR)
779 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
780 SAB82532_ISR0_FERR);
781 if (iflag & IGNBRK) {
782 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
783 /*
784 * If we're ignoring parity and break indicators,
785 * ignore overruns too (for real raw support).
786 */
787 if (iflag & IGNPAR)
788 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
789 }
790
791 /*
792 * ignore all characters if CREAD is not set
793 */
794 if ((cflag & CREAD) == 0)
795 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
796 SAB82532_ISR0_TCD);
797
798 uart_update_timeout(&up->port, cflag,
799 (up->port.uartclk / (16 * quot)));
800
801 /* Now schedule a register update when the chip's
802 * transmitter is idle.
803 */
804 up->cached_mode |= SAB82532_MODE_RAC;
805 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
806 if (test_bit(SAB82532_XPR, &up->irqflags))
807 sunsab_tx_idle(up);
808 }
809
810 /* port->lock is not held. */
811 static void sunsab_set_termios(struct uart_port *port, struct termios *termios,
812 struct termios *old)
813 {
814 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
815 unsigned long flags;
816 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
817 unsigned int quot = uart_get_divisor(port, baud);
818
819 spin_lock_irqsave(&up->port.lock, flags);
820 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
821 spin_unlock_irqrestore(&up->port.lock, flags);
822 }
823
824 static const char *sunsab_type(struct uart_port *port)
825 {
826 struct uart_sunsab_port *up = (void *)port;
827 static char buf[36];
828
829 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
830 return buf;
831 }
832
833 static void sunsab_release_port(struct uart_port *port)
834 {
835 }
836
837 static int sunsab_request_port(struct uart_port *port)
838 {
839 return 0;
840 }
841
842 static void sunsab_config_port(struct uart_port *port, int flags)
843 {
844 }
845
846 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
847 {
848 return -EINVAL;
849 }
850
851 static struct uart_ops sunsab_pops = {
852 .tx_empty = sunsab_tx_empty,
853 .set_mctrl = sunsab_set_mctrl,
854 .get_mctrl = sunsab_get_mctrl,
855 .stop_tx = sunsab_stop_tx,
856 .start_tx = sunsab_start_tx,
857 .send_xchar = sunsab_send_xchar,
858 .stop_rx = sunsab_stop_rx,
859 .enable_ms = sunsab_enable_ms,
860 .break_ctl = sunsab_break_ctl,
861 .startup = sunsab_startup,
862 .shutdown = sunsab_shutdown,
863 .set_termios = sunsab_set_termios,
864 .type = sunsab_type,
865 .release_port = sunsab_release_port,
866 .request_port = sunsab_request_port,
867 .config_port = sunsab_config_port,
868 .verify_port = sunsab_verify_port,
869 };
870
871 static struct uart_driver sunsab_reg = {
872 .owner = THIS_MODULE,
873 .driver_name = "serial",
874 .devfs_name = "tts/",
875 .dev_name = "ttyS",
876 .major = TTY_MAJOR,
877 };
878
879 static struct uart_sunsab_port *sunsab_ports;
880 static int num_channels;
881
882 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
883
884 static __inline__ void sunsab_console_putchar(struct uart_sunsab_port *up, char c)
885 {
886 unsigned long flags;
887
888 spin_lock_irqsave(&up->port.lock, flags);
889
890 sunsab_tec_wait(up);
891 writeb(c, &up->regs->w.tic);
892
893 spin_unlock_irqrestore(&up->port.lock, flags);
894 }
895
896 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
897 {
898 struct uart_sunsab_port *up = &sunsab_ports[con->index];
899 int i;
900
901 for (i = 0; i < n; i++) {
902 if (*s == '\n')
903 sunsab_console_putchar(up, '\r');
904 sunsab_console_putchar(up, *s++);
905 }
906 sunsab_tec_wait(up);
907 }
908
909 static int sunsab_console_setup(struct console *con, char *options)
910 {
911 struct uart_sunsab_port *up = &sunsab_ports[con->index];
912 unsigned long flags;
913 unsigned int baud, quot;
914
915 printk("Console: ttyS%d (SAB82532)\n",
916 (sunsab_reg.minor - 64) + con->index);
917
918 sunserial_console_termios(con);
919
920 /* Firmware console speed is limited to 150-->38400 baud so
921 * this hackish cflag thing is OK.
922 */
923 switch (con->cflag & CBAUD) {
924 case B150: baud = 150; break;
925 case B300: baud = 300; break;
926 case B600: baud = 600; break;
927 case B1200: baud = 1200; break;
928 case B2400: baud = 2400; break;
929 case B4800: baud = 4800; break;
930 default: case B9600: baud = 9600; break;
931 case B19200: baud = 19200; break;
932 case B38400: baud = 38400; break;
933 };
934
935 /*
936 * Temporary fix.
937 */
938 spin_lock_init(&up->port.lock);
939
940 /*
941 * Initialize the hardware
942 */
943 sunsab_startup(&up->port);
944
945 spin_lock_irqsave(&up->port.lock, flags);
946
947 /*
948 * Finally, enable interrupts
949 */
950 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
951 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
952 writeb(up->interrupt_mask0, &up->regs->w.imr0);
953 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
954 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
955 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
956 SAB82532_IMR1_XPR;
957 writeb(up->interrupt_mask1, &up->regs->w.imr1);
958
959 quot = uart_get_divisor(&up->port, baud);
960 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
961 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
962
963 spin_unlock_irqrestore(&up->port.lock, flags);
964
965 return 0;
966 }
967
968 static struct console sunsab_console = {
969 .name = "ttyS",
970 .write = sunsab_console_write,
971 .device = uart_console_device,
972 .setup = sunsab_console_setup,
973 .flags = CON_PRINTBUFFER,
974 .index = -1,
975 .data = &sunsab_reg,
976 };
977 #define SUNSAB_CONSOLE (&sunsab_console)
978
979 static void __init sunsab_console_init(void)
980 {
981 int i;
982
983 if (con_is_present())
984 return;
985
986 for (i = 0; i < num_channels; i++) {
987 int this_minor = sunsab_reg.minor + i;
988
989 if ((this_minor - 64) == (serial_console - 1))
990 break;
991 }
992 if (i == num_channels)
993 return;
994
995 sunsab_console.index = i;
996 register_console(&sunsab_console);
997 }
998 #else
999 #define SUNSAB_CONSOLE (NULL)
1000 #define sunsab_console_init() do { } while (0)
1001 #endif
1002
1003 static void __init for_each_sab_edev(void (*callback)(struct linux_ebus_device *, void *), void *arg)
1004 {
1005 struct linux_ebus *ebus;
1006 struct linux_ebus_device *edev = NULL;
1007
1008 for_each_ebus(ebus) {
1009 for_each_ebusdev(edev, ebus) {
1010 if (!strcmp(edev->prom_name, "se")) {
1011 callback(edev, arg);
1012 continue;
1013 } else if (!strcmp(edev->prom_name, "serial")) {
1014 char compat[32];
1015 int clen;
1016
1017 /* On RIO this can be an SE, check it. We could
1018 * just check ebus->is_rio, but this is more portable.
1019 */
1020 clen = prom_getproperty(edev->prom_node, "compatible",
1021 compat, sizeof(compat));
1022 if (clen > 0) {
1023 if (strncmp(compat, "sab82532", 8) == 0) {
1024 callback(edev, arg);
1025 continue;
1026 }
1027 }
1028 }
1029 }
1030 }
1031 }
1032
1033 static void __init sab_count_callback(struct linux_ebus_device *edev, void *arg)
1034 {
1035 int *count_p = arg;
1036
1037 (*count_p)++;
1038 }
1039
1040 static void __init sab_attach_callback(struct linux_ebus_device *edev, void *arg)
1041 {
1042 int *instance_p = arg;
1043 struct uart_sunsab_port *up;
1044 unsigned long regs, offset;
1045 int i;
1046
1047 /* Note: ports are located in reverse order */
1048 regs = edev->resource[0].start;
1049 offset = sizeof(union sab82532_async_regs);
1050 for (i = 0; i < 2; i++) {
1051 up = &sunsab_ports[(*instance_p * 2) + 1 - i];
1052
1053 memset(up, 0, sizeof(*up));
1054 up->regs = ioremap(regs + offset, sizeof(union sab82532_async_regs));
1055 up->port.irq = edev->irqs[0];
1056 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
1057 up->port.mapbase = (unsigned long)up->regs;
1058 up->port.iotype = SERIAL_IO_MEM;
1059
1060 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
1061
1062 offset -= sizeof(union sab82532_async_regs);
1063 }
1064
1065 (*instance_p)++;
1066 }
1067
1068 static int __init probe_for_sabs(void)
1069 {
1070 int this_sab = 0;
1071
1072 /* Find device instances. */
1073 for_each_sab_edev(&sab_count_callback, &this_sab);
1074 if (!this_sab)
1075 return -ENODEV;
1076
1077 /* Allocate tables. */
1078 sunsab_ports = kmalloc(sizeof(struct uart_sunsab_port) * this_sab * 2,
1079 GFP_KERNEL);
1080 if (!sunsab_ports)
1081 return -ENOMEM;
1082
1083 num_channels = this_sab * 2;
1084
1085 this_sab = 0;
1086 for_each_sab_edev(&sab_attach_callback, &this_sab);
1087 return 0;
1088 }
1089
1090 static void __init sunsab_init_hw(void)
1091 {
1092 int i;
1093
1094 for (i = 0; i < num_channels; i++) {
1095 struct uart_sunsab_port *up = &sunsab_ports[i];
1096
1097 up->port.line = i;
1098 up->port.ops = &sunsab_pops;
1099 up->port.type = PORT_SUNSAB;
1100 up->port.uartclk = SAB_BASE_BAUD;
1101
1102 up->type = readb(&up->regs->r.vstr) & 0x0f;
1103 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
1104 writeb(0xff, &up->regs->w.pim);
1105 if (up->port.line == 0) {
1106 up->pvr_dsr_bit = (1 << 0);
1107 up->pvr_dtr_bit = (1 << 1);
1108 } else {
1109 up->pvr_dsr_bit = (1 << 3);
1110 up->pvr_dtr_bit = (1 << 2);
1111 }
1112 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1113 writeb(up->cached_pvr, &up->regs->w.pvr);
1114 up->cached_mode = readb(&up->regs->rw.mode);
1115 up->cached_mode |= SAB82532_MODE_FRTS;
1116 writeb(up->cached_mode, &up->regs->rw.mode);
1117 up->cached_mode |= SAB82532_MODE_RTS;
1118 writeb(up->cached_mode, &up->regs->rw.mode);
1119
1120 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1121 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1122
1123 if (!(up->port.line & 0x01)) {
1124 if (request_irq(up->port.irq, sunsab_interrupt,
1125 SA_SHIRQ, "serial(sab82532)", up)) {
1126 printk("sunsab%d: can't get IRQ %x\n",
1127 i, up->port.irq);
1128 continue;
1129 }
1130 }
1131 }
1132 }
1133
1134 static int __init sunsab_init(void)
1135 {
1136 int ret = probe_for_sabs();
1137 int i;
1138
1139 if (ret < 0)
1140 return ret;
1141
1142 sunsab_init_hw();
1143
1144 sunsab_reg.minor = sunserial_current_minor;
1145 sunsab_reg.nr = num_channels;
1146 sunsab_reg.cons = SUNSAB_CONSOLE;
1147
1148 ret = uart_register_driver(&sunsab_reg);
1149 if (ret < 0) {
1150 int i;
1151
1152 for (i = 0; i < num_channels; i++) {
1153 struct uart_sunsab_port *up = &sunsab_ports[i];
1154
1155 if (!(up->port.line & 0x01))
1156 free_irq(up->port.irq, up);
1157 iounmap(up->regs);
1158 }
1159 kfree(sunsab_ports);
1160 sunsab_ports = NULL;
1161
1162 return ret;
1163 }
1164
1165 sunserial_current_minor += num_channels;
1166
1167 sunsab_console_init();
1168
1169 for (i = 0; i < num_channels; i++) {
1170 struct uart_sunsab_port *up = &sunsab_ports[i];
1171
1172 uart_add_one_port(&sunsab_reg, &up->port);
1173 }
1174
1175 return 0;
1176 }
1177
1178 static void __exit sunsab_exit(void)
1179 {
1180 int i;
1181
1182 for (i = 0; i < num_channels; i++) {
1183 struct uart_sunsab_port *up = &sunsab_ports[i];
1184
1185 uart_remove_one_port(&sunsab_reg, &up->port);
1186
1187 if (!(up->port.line & 0x01))
1188 free_irq(up->port.irq, up);
1189 iounmap(up->regs);
1190 }
1191
1192 sunserial_current_minor -= num_channels;
1193 uart_unregister_driver(&sunsab_reg);
1194
1195 kfree(sunsab_ports);
1196 sunsab_ports = NULL;
1197 }
1198
1199 module_init(sunsab_init);
1200 module_exit(sunsab_exit);
1201
1202 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1203 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1204 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards