arch/arm/plat-s3c24xx/pm.c

   1 /* linux/arch/arm/plat-s3c24xx/pm.c
   2  *
   3  * Copyright (c) 2004,2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C24XX Power Manager (Suspend-To-RAM) support
   7  *
   8  * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  23  *
  24  * Parts based on arch/arm/mach-pxa/pm.c
  25  *
  26  * Thanks to Dimitry Andric for debugging
  27 */
  28
  29 #include <linux/init.h>
  30 #include <linux/suspend.h>
  31 #include <linux/errno.h>
  32 #include <linux/time.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/crc32.h>
  35 #include <linux/ioport.h>
  36 #include <linux/delay.h>
  37 #include <linux/serial_core.h>
  38
  39 #include <asm/cacheflush.h>
  40 #include <asm/hardware.h>
  41 #include <asm/io.h>
  42
  43 #include <asm/plat-s3c/regs-serial.h>
  44 #include <asm/arch/regs-clock.h>
  45 #include <asm/arch/regs-gpio.h>
  46 #include <asm/arch/regs-mem.h>
  47 #include <asm/arch/regs-irq.h>
  48
  49 #include <asm/mach/time.h>
  50
  51 #include <asm/plat-s3c24xx/pm.h>
  52
  53 /* for external use */
  54
  55 unsigned long s3c_pm_flags;
  56
  57 #define PFX "s3c24xx-pm: "
  58
  59 static struct sleep_save core_save[] = {
  60         SAVE_ITEM(S3C2410_LOCKTIME),
  61         SAVE_ITEM(S3C2410_CLKCON),
  62
  63         /* we restore the timings here, with the proviso that the board
  64          * brings the system up in an slower, or equal frequency setting
  65          * to the original system.
  66          *
  67          * if we cannot guarantee this, then things are going to go very
  68          * wrong here, as we modify the refresh and both pll settings.
  69          */
  70
  71         SAVE_ITEM(S3C2410_BWSCON),
  72         SAVE_ITEM(S3C2410_BANKCON0),
  73         SAVE_ITEM(S3C2410_BANKCON1),
  74         SAVE_ITEM(S3C2410_BANKCON2),
  75         SAVE_ITEM(S3C2410_BANKCON3),
  76         SAVE_ITEM(S3C2410_BANKCON4),
  77         SAVE_ITEM(S3C2410_BANKCON5),
  78
  79         SAVE_ITEM(S3C2410_CLKDIVN),
  80         SAVE_ITEM(S3C2410_MPLLCON),
  81         SAVE_ITEM(S3C2410_UPLLCON),
  82         SAVE_ITEM(S3C2410_CLKSLOW),
  83         SAVE_ITEM(S3C2410_REFRESH),
  84 };
  85
  86 static struct sleep_save gpio_save[] = {
  87         SAVE_ITEM(S3C2410_GPACON),
  88         SAVE_ITEM(S3C2410_GPADAT),
  89
  90         SAVE_ITEM(S3C2410_GPBCON),
  91         SAVE_ITEM(S3C2410_GPBDAT),
  92         SAVE_ITEM(S3C2410_GPBUP),
  93
  94         SAVE_ITEM(S3C2410_GPCCON),
  95         SAVE_ITEM(S3C2410_GPCDAT),
  96         SAVE_ITEM(S3C2410_GPCUP),
  97
  98         SAVE_ITEM(S3C2410_GPDCON),
  99         SAVE_ITEM(S3C2410_GPDDAT),
 100         SAVE_ITEM(S3C2410_GPDUP),
 101
 102         SAVE_ITEM(S3C2410_GPECON),
 103         SAVE_ITEM(S3C2410_GPEDAT),
 104         SAVE_ITEM(S3C2410_GPEUP),
 105
 106         SAVE_ITEM(S3C2410_GPFCON),
 107         SAVE_ITEM(S3C2410_GPFDAT),
 108         SAVE_ITEM(S3C2410_GPFUP),
 109
 110         SAVE_ITEM(S3C2410_GPGCON),
 111         SAVE_ITEM(S3C2410_GPGDAT),
 112         SAVE_ITEM(S3C2410_GPGUP),
 113
 114         SAVE_ITEM(S3C2410_GPHCON),
 115         SAVE_ITEM(S3C2410_GPHDAT),
 116         SAVE_ITEM(S3C2410_GPHUP),
 117
 118         SAVE_ITEM(S3C2410_DCLKCON),
 119 };
 120
 121 #ifdef CONFIG_S3C2410_PM_DEBUG
 122
 123 #define SAVE_UART(va) \
 124         SAVE_ITEM((va) + S3C2410_ULCON), \
 125         SAVE_ITEM((va) + S3C2410_UCON), \
 126         SAVE_ITEM((va) + S3C2410_UFCON), \
 127         SAVE_ITEM((va) + S3C2410_UMCON), \
 128         SAVE_ITEM((va) + S3C2410_UBRDIV)
 129
 130 static struct sleep_save uart_save[] = {
 131         SAVE_UART(S3C24XX_VA_UART0),
 132         SAVE_UART(S3C24XX_VA_UART1),
 133 #ifndef CONFIG_CPU_S3C2400
 134         SAVE_UART(S3C24XX_VA_UART2),
 135 #endif
 136 };
 137
 138 /* debug
 139  *
 140  * we send the debug to printascii() to allow it to be seen if the
 141  * system never wakes up from the sleep
 142 */
 143
 144 extern void printascii(const char *);
 145
 146 void pm_dbg(const char *fmt, ...)
 147 {
 148         va_list va;
 149         char buff[256];
 150
 151         va_start(va, fmt);
 152         vsprintf(buff, fmt, va);
 153         va_end(va);
 154
 155         printascii(buff);
 156 }
 157
 158 static void s3c2410_pm_debug_init(void)
 159 {
 160         unsigned long tmp = __raw_readl(S3C2410_CLKCON);
 161
 162         /* re-start uart clocks */
 163         tmp |= S3C2410_CLKCON_UART0;
 164         tmp |= S3C2410_CLKCON_UART1;
 165         tmp |= S3C2410_CLKCON_UART2;
 166
 167         __raw_writel(tmp, S3C2410_CLKCON);
 168         udelay(10);
 169 }
 170
 171 #define DBG(fmt...) pm_dbg(fmt)
 172 #else
 173 #define DBG(fmt...) printk(KERN_DEBUG fmt)
 174
 175 #define s3c2410_pm_debug_init() do { } while(0)
 176
 177 static struct sleep_save uart_save[] = {};
 178 #endif
 179
 180 #if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
 181
 182 /* suspend checking code...
 183  *
 184  * this next area does a set of crc checks over all the installed
 185  * memory, so the system can verify if the resume was ok.
 186  *
 187  * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
 188  * increasing it will mean that the area corrupted will be less easy to spot,
 189  * and reducing the size will cause the CRC save area to grow
 190 */
 191
 192 #define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
 193
 194 static u32 crc_size;    /* size needed for the crc block */
 195 static u32 *crcs;       /* allocated over suspend/resume */
 196
 197 typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
 198
 199 /* s3c2410_pm_run_res
 200  *
 201  * go thorugh the given resource list, and look for system ram
 202 */
 203
 204 static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
 205 {
 206         while (ptr != NULL) {
 207                 if (ptr->child != NULL)
 208                         s3c2410_pm_run_res(ptr->child, fn, arg);
 209
 210                 if ((ptr->flags & IORESOURCE_MEM) &&
 211                     strcmp(ptr->name, "System RAM") == 0) {
 212                         DBG("Found system RAM at %08lx..%08lx\n",
 213                             ptr->start, ptr->end);
 214                         arg = (fn)(ptr, arg);
 215                 }
 216
 217                 ptr = ptr->sibling;
 218         }
 219 }
 220
 221 static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
 222 {
 223         s3c2410_pm_run_res(&iomem_resource, fn, arg);
 224 }
 225
 226 static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
 227 {
 228         u32 size = (u32)(res->end - res->start)+1;
 229
 230         size += CHECK_CHUNKSIZE-1;
 231         size /= CHECK_CHUNKSIZE;
 232
 233         DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
 234
 235         *val += size * sizeof(u32);
 236         return val;
 237 }
 238
 239 /* s3c2410_pm_prepare_check
 240  *
 241  * prepare the necessary information for creating the CRCs. This
 242  * must be done before the final save, as it will require memory
 243  * allocating, and thus touching bits of the kernel we do not
 244  * know about.
 245 */
 246
 247 static void s3c2410_pm_check_prepare(void)
 248 {
 249         crc_size = 0;
 250
 251         s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
 252
 253         DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
 254
 255         crcs = kmalloc(crc_size+4, GFP_KERNEL);
 256         if (crcs == NULL)
 257                 printk(KERN_ERR "Cannot allocated CRC save area\n");
 258 }
 259
 260 static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
 261 {
 262         unsigned long addr, left;
 263
 264         for (addr = res->start; addr < res->end;
 265              addr += CHECK_CHUNKSIZE) {
 266                 left = res->end - addr;
 267
 268                 if (left > CHECK_CHUNKSIZE)
 269                         left = CHECK_CHUNKSIZE;
 270
 271                 *val = crc32_le(~0, phys_to_virt(addr), left);
 272                 val++;
 273         }
 274
 275         return val;
 276 }
 277
 278 /* s3c2410_pm_check_store
 279  *
 280  * compute the CRC values for the memory blocks before the final
 281  * sleep.
 282 */
 283
 284 static void s3c2410_pm_check_store(void)
 285 {
 286         if (crcs != NULL)
 287                 s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
 288 }
 289
 290 /* in_region
 291  *
 292  * return TRUE if the area defined by ptr..ptr+size contatins the
 293  * what..what+whatsz
 294 */
 295
 296 static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
 297 {
 298         if ((what+whatsz) < ptr)
 299                 return 0;
 300
 301         if (what > (ptr+size))
 302                 return 0;
 303
 304         return 1;
 305 }
 306
 307 static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
 308 {
 309         void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
 310         unsigned long addr;
 311         unsigned long left;
 312         void *ptr;
 313         u32 calc;
 314
 315         for (addr = res->start; addr < res->end;
 316              addr += CHECK_CHUNKSIZE) {
 317                 left = res->end - addr;
 318
 319                 if (left > CHECK_CHUNKSIZE)
 320                         left = CHECK_CHUNKSIZE;
 321
 322                 ptr = phys_to_virt(addr);
 323
 324                 if (in_region(ptr, left, crcs, crc_size)) {
 325                         DBG("skipping %08lx, has crc block in\n", addr);
 326                         goto skip_check;
 327                 }
 328
 329                 if (in_region(ptr, left, save_at, 32*4 )) {
 330                         DBG("skipping %08lx, has save block in\n", addr);
 331                         goto skip_check;
 332                 }
 333
 334                 /* calculate and check the checksum */
 335
 336                 calc = crc32_le(~0, ptr, left);
 337                 if (calc != *val) {
 338                         printk(KERN_ERR PFX "Restore CRC error at "
 339                                "%08lx (%08x vs %08x)\n", addr, calc, *val);
 340
 341                         DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
 342                             addr, calc, *val);
 343                 }
 344
 345         skip_check:
 346                 val++;
 347         }
 348
 349         return val;
 350 }
 351
 352 /* s3c2410_pm_check_restore
 353  *
 354  * check the CRCs after the restore event and free the memory used
 355  * to hold them
 356 */
 357
 358 static void s3c2410_pm_check_restore(void)
 359 {
 360         if (crcs != NULL) {
 361                 s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
 362                 kfree(crcs);
 363                 crcs = NULL;
 364         }
 365 }
 366
 367 #else
 368
 369 #define s3c2410_pm_check_prepare() do { } while(0)
 370 #define s3c2410_pm_check_restore() do { } while(0)
 371 #define s3c2410_pm_check_store()   do { } while(0)
 372 #endif
 373
 374 /* helper functions to save and restore register state */
 375
 376 void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
 377 {
 378         for (; count > 0; count--, ptr++) {
 379                 ptr->val = __raw_readl(ptr->reg);
 380                 DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
 381         }
 382 }
 383
 384 /* s3c2410_pm_do_restore
 385  *
 386  * restore the system from the given list of saved registers
 387  *
 388  * Note, we do not use DBG() in here, as the system may not have
 389  * restore the UARTs state yet
 390 */
 391
 392 void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
 393 {
 394         for (; count > 0; count--, ptr++) {
 395                 printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
 396                        ptr->reg, ptr->val, __raw_readl(ptr->reg));
 397
 398                 __raw_writel(ptr->val, ptr->reg);
 399         }
 400 }
 401
 402 /* s3c2410_pm_do_restore_core
 403  *
 404  * similar to s3c2410_pm_do_restore_core
 405  *
 406  * WARNING: Do not put any debug in here that may effect memory or use
 407  * peripherals, as things may be changing!
 408 */
 409
 410 static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
 411 {
 412         for (; count > 0; count--, ptr++) {
 413                 __raw_writel(ptr->val, ptr->reg);
 414         }
 415 }
 416
 417 /* s3c2410_pm_show_resume_irqs
 418  *
 419  * print any IRQs asserted at resume time (ie, we woke from)
 420 */
 421
 422 static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
 423                                         unsigned long mask)
 424 {
 425         int i;
 426
 427         which &= ~mask;
 428
 429         for (i = 0; i <= 31; i++) {
 430                 if ((which) & (1L<<i)) {
 431                         DBG("IRQ %d asserted at resume\n", start+i);
 432                 }
 433         }
 434 }
 435
 436 /* s3c2410_pm_check_resume_pin
 437  *
 438  * check to see if the pin is configured correctly for sleep mode, and
 439  * make any necessary adjustments if it is not
 440 */
 441
 442 static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
 443 {
 444         unsigned long irqstate;
 445         unsigned long pinstate;
 446         int irq = s3c2410_gpio_getirq(pin);
 447
 448         if (irqoffs < 4)
 449                 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
 450         else
 451                 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
 452
 453         pinstate = s3c2410_gpio_getcfg(pin);
 454
 455         if (!irqstate) {
 456                 if (pinstate == S3C2410_GPIO_IRQ)
 457                         DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
 458         } else {
 459                 if (pinstate == S3C2410_GPIO_IRQ) {
 460                         DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
 461                         s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
 462                 }
 463         }
 464 }
 465
 466 /* s3c2410_pm_configure_extint
 467  *
 468  * configure all external interrupt pins
 469 */
 470
 471 static void s3c2410_pm_configure_extint(void)
 472 {
 473         int pin;
 474
 475         /* for each of the external interrupts (EINT0..EINT15) we
 476          * need to check wether it is an external interrupt source,
 477          * and then configure it as an input if it is not
 478         */
 479
 480         for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
 481                 s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
 482         }
 483
 484         for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
 485                 s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
 486         }
 487 }
 488
 489 void (*pm_cpu_prep)(void);
 490 void (*pm_cpu_sleep)(void);
 491
 492 #define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
 493
 494 /* s3c2410_pm_enter
 495  *
 496  * central control for sleep/resume process
 497 */
 498
 499 static int s3c2410_pm_enter(suspend_state_t state)
 500 {
 501         unsigned long regs_save[16];
 502
 503         /* ensure the debug is initialised (if enabled) */
 504
 505         s3c2410_pm_debug_init();
 506
 507         DBG("s3c2410_pm_enter(%d)\n", state);
 508
 509         if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
 510                 printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
 511                 return -EINVAL;
 512         }
 513
 514         /* check if we have anything to wake-up with... bad things seem
 515          * to happen if you suspend with no wakeup (system will often
 516          * require a full power-cycle)
 517         */
 518
 519         if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
 520             !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
 521                 printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
 522                 printk(KERN_ERR PFX "Aborting sleep\n");
 523                 return -EINVAL;
 524         }
 525
 526         /* prepare check area if configured */
 527
 528         s3c2410_pm_check_prepare();
 529
 530         /* store the physical address of the register recovery block */
 531
 532         s3c2410_sleep_save_phys = virt_to_phys(regs_save);
 533
 534         DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
 535
 536         /* save all necessary core registers not covered by the drivers */
 537
 538         s3c2410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save));
 539         s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
 540         s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
 541
 542         /* set the irq configuration for wake */
 543
 544         s3c2410_pm_configure_extint();
 545
 546         DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
 547             s3c_irqwake_intmask, s3c_irqwake_eintmask);
 548
 549         __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
 550         __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
 551
 552         /* ack any outstanding external interrupts before we go to sleep */
 553
 554         __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
 555         __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
 556         __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
 557
 558         /* call cpu specific preparation */
 559
 560         pm_cpu_prep();
 561
 562         /* flush cache back to ram */
 563
 564         flush_cache_all();
 565
 566         s3c2410_pm_check_store();
 567
 568         /* send the cpu to sleep... */
 569
 570         __raw_writel(0x00, S3C2410_CLKCON);  /* turn off clocks over sleep */
 571
 572         /* s3c2410_cpu_save will also act as our return point from when
 573          * we resume as it saves its own register state, so use the return
 574          * code to differentiate return from save and return from sleep */
 575
 576         if (s3c2410_cpu_save(regs_save) == 0) {
 577                 flush_cache_all();
 578                 pm_cpu_sleep();
 579         }
 580
 581         /* restore the cpu state */
 582
 583         cpu_init();
 584
 585         /* restore the system state */
 586
 587         s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
 588         s3c2410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save));
 589         s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
 590
 591         s3c2410_pm_debug_init();
 592
 593         /* check what irq (if any) restored the system */
 594
 595         DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
 596             __raw_readl(S3C2410_SRCPND),
 597             __raw_readl(S3C2410_EINTPEND));
 598
 599         s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
 600                                     s3c_irqwake_intmask);
 601
 602         s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
 603                                     s3c_irqwake_eintmask);
 604
 605         DBG("post sleep, preparing to return\n");
 606
 607         s3c2410_pm_check_restore();
 608
 609         /* ok, let's return from sleep */
 610
 611         DBG("S3C2410 PM Resume (post-restore)\n");
 612         return 0;
 613 }
 614
 615 static struct platform_suspend_ops s3c2410_pm_ops = {
 616         .enter          = s3c2410_pm_enter,
 617         .valid          = suspend_valid_only_mem,
 618 };
 619
 620 /* s3c2410_pm_init
 621  *
 622  * Attach the power management functions. This should be called
 623  * from the board specific initialisation if the board supports
 624  * it.
 625 */
 626
 627 int __init s3c2410_pm_init(void)
 628 {
 629         printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
 630
 631         suspend_set_ops(&s3c2410_pm_ops);
 632         return 0;
 633 }