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USB: storage: add last-sector hacks
[linux-2.6/mini2440.git] / drivers / net / tg3.c
blob5e2dbaee125bcc1b520960dcbb6fe74623989a42
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
38 #include <linux/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
44
45 #include <net/checksum.h>
46 #include <net/ip.h>
47
48 #include <asm/system.h>
49 #include <asm/io.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
52
53 #ifdef CONFIG_SPARC
54 #include <asm/idprom.h>
55 #include <asm/prom.h>
56 #endif
57
58 #define BAR_0 0
59 #define BAR_2 2
60
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
63 #else
64 #define TG3_VLAN_TAG_USED 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.97"
72 #define DRV_MODULE_RELDATE "December 10, 2008"
73
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90 #define TG3_TX_TIMEOUT (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
133
134 #define TG3_RAW_IP_ALIGN 2
135
136 /* number of ETHTOOL_GSTATS u64's */
137 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
138
139 #define TG3_NUM_TEST 6
140
141 #define FIRMWARE_TG3 "tigon/tg3.bin"
142 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
143 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
144
145 static char version[] __devinitdata =
146 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
147
148 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
149 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
150 MODULE_LICENSE("GPL");
151 MODULE_VERSION(DRV_MODULE_VERSION);
152 MODULE_FIRMWARE(FIRMWARE_TG3);
153 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
154 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
155
156
157 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
158 module_param(tg3_debug, int, 0);
159 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
160
161 static struct pci_device_id tg3_pci_tbl[] = {
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57720)},
227 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
228 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
229 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
230 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
231 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
232 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
233 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
234 {}
235 };
236
237 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
238
239 static const struct {
240 const char string[ETH_GSTRING_LEN];
241 } ethtool_stats_keys[TG3_NUM_STATS] = {
242 { "rx_octets" },
243 { "rx_fragments" },
244 { "rx_ucast_packets" },
245 { "rx_mcast_packets" },
246 { "rx_bcast_packets" },
247 { "rx_fcs_errors" },
248 { "rx_align_errors" },
249 { "rx_xon_pause_rcvd" },
250 { "rx_xoff_pause_rcvd" },
251 { "rx_mac_ctrl_rcvd" },
252 { "rx_xoff_entered" },
253 { "rx_frame_too_long_errors" },
254 { "rx_jabbers" },
255 { "rx_undersize_packets" },
256 { "rx_in_length_errors" },
257 { "rx_out_length_errors" },
258 { "rx_64_or_less_octet_packets" },
259 { "rx_65_to_127_octet_packets" },
260 { "rx_128_to_255_octet_packets" },
261 { "rx_256_to_511_octet_packets" },
262 { "rx_512_to_1023_octet_packets" },
263 { "rx_1024_to_1522_octet_packets" },
264 { "rx_1523_to_2047_octet_packets" },
265 { "rx_2048_to_4095_octet_packets" },
266 { "rx_4096_to_8191_octet_packets" },
267 { "rx_8192_to_9022_octet_packets" },
268
269 { "tx_octets" },
270 { "tx_collisions" },
271
272 { "tx_xon_sent" },
273 { "tx_xoff_sent" },
274 { "tx_flow_control" },
275 { "tx_mac_errors" },
276 { "tx_single_collisions" },
277 { "tx_mult_collisions" },
278 { "tx_deferred" },
279 { "tx_excessive_collisions" },
280 { "tx_late_collisions" },
281 { "tx_collide_2times" },
282 { "tx_collide_3times" },
283 { "tx_collide_4times" },
284 { "tx_collide_5times" },
285 { "tx_collide_6times" },
286 { "tx_collide_7times" },
287 { "tx_collide_8times" },
288 { "tx_collide_9times" },
289 { "tx_collide_10times" },
290 { "tx_collide_11times" },
291 { "tx_collide_12times" },
292 { "tx_collide_13times" },
293 { "tx_collide_14times" },
294 { "tx_collide_15times" },
295 { "tx_ucast_packets" },
296 { "tx_mcast_packets" },
297 { "tx_bcast_packets" },
298 { "tx_carrier_sense_errors" },
299 { "tx_discards" },
300 { "tx_errors" },
301
302 { "dma_writeq_full" },
303 { "dma_write_prioq_full" },
304 { "rxbds_empty" },
305 { "rx_discards" },
306 { "rx_errors" },
307 { "rx_threshold_hit" },
308
309 { "dma_readq_full" },
310 { "dma_read_prioq_full" },
311 { "tx_comp_queue_full" },
312
313 { "ring_set_send_prod_index" },
314 { "ring_status_update" },
315 { "nic_irqs" },
316 { "nic_avoided_irqs" },
317 { "nic_tx_threshold_hit" }
318 };
319
320 static const struct {
321 const char string[ETH_GSTRING_LEN];
322 } ethtool_test_keys[TG3_NUM_TEST] = {
323 { "nvram test (online) " },
324 { "link test (online) " },
325 { "register test (offline)" },
326 { "memory test (offline)" },
327 { "loopback test (offline)" },
328 { "interrupt test (offline)" },
329 };
330
331 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
332 {
333 writel(val, tp->regs + off);
334 }
335
336 static u32 tg3_read32(struct tg3 *tp, u32 off)
337 {
338 return (readl(tp->regs + off));
339 }
340
341 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
342 {
343 writel(val, tp->aperegs + off);
344 }
345
346 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
347 {
348 return (readl(tp->aperegs + off));
349 }
350
351 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
352 {
353 unsigned long flags;
354
355 spin_lock_irqsave(&tp->indirect_lock, flags);
356 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
357 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
358 spin_unlock_irqrestore(&tp->indirect_lock, flags);
359 }
360
361 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
362 {
363 writel(val, tp->regs + off);
364 readl(tp->regs + off);
365 }
366
367 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
368 {
369 unsigned long flags;
370 u32 val;
371
372 spin_lock_irqsave(&tp->indirect_lock, flags);
373 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
374 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
375 spin_unlock_irqrestore(&tp->indirect_lock, flags);
376 return val;
377 }
378
379 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
380 {
381 unsigned long flags;
382
383 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
384 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
385 TG3_64BIT_REG_LOW, val);
386 return;
387 }
388 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
389 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
390 TG3_64BIT_REG_LOW, val);
391 return;
392 }
393
394 spin_lock_irqsave(&tp->indirect_lock, flags);
395 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
396 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
397 spin_unlock_irqrestore(&tp->indirect_lock, flags);
398
399 /* In indirect mode when disabling interrupts, we also need
400 * to clear the interrupt bit in the GRC local ctrl register.
401 */
402 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
403 (val == 0x1)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
405 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
406 }
407 }
408
409 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
410 {
411 unsigned long flags;
412 u32 val;
413
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
418 return val;
419 }
420
421 /* usec_wait specifies the wait time in usec when writing to certain registers
422 * where it is unsafe to read back the register without some delay.
423 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
424 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
425 */
426 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
427 {
428 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
429 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
430 /* Non-posted methods */
431 tp->write32(tp, off, val);
432 else {
433 /* Posted method */
434 tg3_write32(tp, off, val);
435 if (usec_wait)
436 udelay(usec_wait);
437 tp->read32(tp, off);
438 }
439 /* Wait again after the read for the posted method to guarantee that
440 * the wait time is met.
441 */
442 if (usec_wait)
443 udelay(usec_wait);
444 }
445
446 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
447 {
448 tp->write32_mbox(tp, off, val);
449 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
450 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
451 tp->read32_mbox(tp, off);
452 }
453
454 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
455 {
456 void __iomem *mbox = tp->regs + off;
457 writel(val, mbox);
458 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
459 writel(val, mbox);
460 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
461 readl(mbox);
462 }
463
464 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
465 {
466 return (readl(tp->regs + off + GRCMBOX_BASE));
467 }
468
469 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
470 {
471 writel(val, tp->regs + off + GRCMBOX_BASE);
472 }
473
474 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
475 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
476 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
477 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
478 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
479
480 #define tw32(reg,val) tp->write32(tp, reg, val)
481 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
482 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
483 #define tr32(reg) tp->read32(tp, reg)
484
485 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
486 {
487 unsigned long flags;
488
489 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
490 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
491 return;
492
493 spin_lock_irqsave(&tp->indirect_lock, flags);
494 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
495 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
496 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
497
498 /* Always leave this as zero. */
499 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
500 } else {
501 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
502 tw32_f(TG3PCI_MEM_WIN_DATA, val);
503
504 /* Always leave this as zero. */
505 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
506 }
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
508 }
509
510 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
511 {
512 unsigned long flags;
513
514 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
515 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
516 *val = 0;
517 return;
518 }
519
520 spin_lock_irqsave(&tp->indirect_lock, flags);
521 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
522 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
523 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
524
525 /* Always leave this as zero. */
526 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 } else {
528 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
529 *val = tr32(TG3PCI_MEM_WIN_DATA);
530
531 /* Always leave this as zero. */
532 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
533 }
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
535 }
536
537 static void tg3_ape_lock_init(struct tg3 *tp)
538 {
539 int i;
540
541 /* Make sure the driver hasn't any stale locks. */
542 for (i = 0; i < 8; i++)
543 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
544 APE_LOCK_GRANT_DRIVER);
545 }
546
547 static int tg3_ape_lock(struct tg3 *tp, int locknum)
548 {
549 int i, off;
550 int ret = 0;
551 u32 status;
552
553 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
554 return 0;
555
556 switch (locknum) {
557 case TG3_APE_LOCK_GRC:
558 case TG3_APE_LOCK_MEM:
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 off = 4 * locknum;
565
566 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
567
568 /* Wait for up to 1 millisecond to acquire lock. */
569 for (i = 0; i < 100; i++) {
570 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
571 if (status == APE_LOCK_GRANT_DRIVER)
572 break;
573 udelay(10);
574 }
575
576 if (status != APE_LOCK_GRANT_DRIVER) {
577 /* Revoke the lock request. */
578 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
579 APE_LOCK_GRANT_DRIVER);
580
581 ret = -EBUSY;
582 }
583
584 return ret;
585 }
586
587 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
588 {
589 int off;
590
591 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
592 return;
593
594 switch (locknum) {
595 case TG3_APE_LOCK_GRC:
596 case TG3_APE_LOCK_MEM:
597 break;
598 default:
599 return;
600 }
601
602 off = 4 * locknum;
603 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
604 }
605
606 static void tg3_disable_ints(struct tg3 *tp)
607 {
608 tw32(TG3PCI_MISC_HOST_CTRL,
609 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
610 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
611 }
612
613 static inline void tg3_cond_int(struct tg3 *tp)
614 {
615 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
616 (tp->hw_status->status & SD_STATUS_UPDATED))
617 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
618 else
619 tw32(HOSTCC_MODE, tp->coalesce_mode |
620 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
621 }
622
623 static void tg3_enable_ints(struct tg3 *tp)
624 {
625 tp->irq_sync = 0;
626 wmb();
627
628 tw32(TG3PCI_MISC_HOST_CTRL,
629 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
630 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
631 (tp->last_tag << 24));
632 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
633 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
634 (tp->last_tag << 24));
635 tg3_cond_int(tp);
636 }
637
638 static inline unsigned int tg3_has_work(struct tg3 *tp)
639 {
640 struct tg3_hw_status *sblk = tp->hw_status;
641 unsigned int work_exists = 0;
642
643 /* check for phy events */
644 if (!(tp->tg3_flags &
645 (TG3_FLAG_USE_LINKCHG_REG |
646 TG3_FLAG_POLL_SERDES))) {
647 if (sblk->status & SD_STATUS_LINK_CHG)
648 work_exists = 1;
649 }
650 /* check for RX/TX work to do */
651 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
652 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
653 work_exists = 1;
654
655 return work_exists;
656 }
657
658 /* tg3_restart_ints
659 * similar to tg3_enable_ints, but it accurately determines whether there
660 * is new work pending and can return without flushing the PIO write
661 * which reenables interrupts
662 */
663 static void tg3_restart_ints(struct tg3 *tp)
664 {
665 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
666 tp->last_tag << 24);
667 mmiowb();
668
669 /* When doing tagged status, this work check is unnecessary.
670 * The last_tag we write above tells the chip which piece of
671 * work we've completed.
672 */
673 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
674 tg3_has_work(tp))
675 tw32(HOSTCC_MODE, tp->coalesce_mode |
676 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
677 }
678
679 static inline void tg3_netif_stop(struct tg3 *tp)
680 {
681 tp->dev->trans_start = jiffies; /* prevent tx timeout */
682 napi_disable(&tp->napi);
683 netif_tx_disable(tp->dev);
684 }
685
686 static inline void tg3_netif_start(struct tg3 *tp)
687 {
688 netif_wake_queue(tp->dev);
689 /* NOTE: unconditional netif_wake_queue is only appropriate
690 * so long as all callers are assured to have free tx slots
691 * (such as after tg3_init_hw)
692 */
693 napi_enable(&tp->napi);
694 tp->hw_status->status |= SD_STATUS_UPDATED;
695 tg3_enable_ints(tp);
696 }
697
698 static void tg3_switch_clocks(struct tg3 *tp)
699 {
700 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
701 u32 orig_clock_ctrl;
702
703 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
704 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
705 return;
706
707 orig_clock_ctrl = clock_ctrl;
708 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
709 CLOCK_CTRL_CLKRUN_OENABLE |
710 0x1f);
711 tp->pci_clock_ctrl = clock_ctrl;
712
713 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
714 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
715 tw32_wait_f(TG3PCI_CLOCK_CTRL,
716 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
717 }
718 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
719 tw32_wait_f(TG3PCI_CLOCK_CTRL,
720 clock_ctrl |
721 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
722 40);
723 tw32_wait_f(TG3PCI_CLOCK_CTRL,
724 clock_ctrl | (CLOCK_CTRL_ALTCLK),
725 40);
726 }
727 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
728 }
729
730 #define PHY_BUSY_LOOPS 5000
731
732 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
733 {
734 u32 frame_val;
735 unsigned int loops;
736 int ret;
737
738 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
739 tw32_f(MAC_MI_MODE,
740 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
741 udelay(80);
742 }
743
744 *val = 0x0;
745
746 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
747 MI_COM_PHY_ADDR_MASK);
748 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
749 MI_COM_REG_ADDR_MASK);
750 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
751
752 tw32_f(MAC_MI_COM, frame_val);
753
754 loops = PHY_BUSY_LOOPS;
755 while (loops != 0) {
756 udelay(10);
757 frame_val = tr32(MAC_MI_COM);
758
759 if ((frame_val & MI_COM_BUSY) == 0) {
760 udelay(5);
761 frame_val = tr32(MAC_MI_COM);
762 break;
763 }
764 loops -= 1;
765 }
766
767 ret = -EBUSY;
768 if (loops != 0) {
769 *val = frame_val & MI_COM_DATA_MASK;
770 ret = 0;
771 }
772
773 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
774 tw32_f(MAC_MI_MODE, tp->mi_mode);
775 udelay(80);
776 }
777
778 return ret;
779 }
780
781 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
782 {
783 u32 frame_val;
784 unsigned int loops;
785 int ret;
786
787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
788 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
789 return 0;
790
791 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
792 tw32_f(MAC_MI_MODE,
793 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 udelay(80);
795 }
796
797 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
798 MI_COM_PHY_ADDR_MASK);
799 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
800 MI_COM_REG_ADDR_MASK);
801 frame_val |= (val & MI_COM_DATA_MASK);
802 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
803
804 tw32_f(MAC_MI_COM, frame_val);
805
806 loops = PHY_BUSY_LOOPS;
807 while (loops != 0) {
808 udelay(10);
809 frame_val = tr32(MAC_MI_COM);
810 if ((frame_val & MI_COM_BUSY) == 0) {
811 udelay(5);
812 frame_val = tr32(MAC_MI_COM);
813 break;
814 }
815 loops -= 1;
816 }
817
818 ret = -EBUSY;
819 if (loops != 0)
820 ret = 0;
821
822 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
823 tw32_f(MAC_MI_MODE, tp->mi_mode);
824 udelay(80);
825 }
826
827 return ret;
828 }
829
830 static int tg3_bmcr_reset(struct tg3 *tp)
831 {
832 u32 phy_control;
833 int limit, err;
834
835 /* OK, reset it, and poll the BMCR_RESET bit until it
836 * clears or we time out.
837 */
838 phy_control = BMCR_RESET;
839 err = tg3_writephy(tp, MII_BMCR, phy_control);
840 if (err != 0)
841 return -EBUSY;
842
843 limit = 5000;
844 while (limit--) {
845 err = tg3_readphy(tp, MII_BMCR, &phy_control);
846 if (err != 0)
847 return -EBUSY;
848
849 if ((phy_control & BMCR_RESET) == 0) {
850 udelay(40);
851 break;
852 }
853 udelay(10);
854 }
855 if (limit <= 0)
856 return -EBUSY;
857
858 return 0;
859 }
860
861 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
862 {
863 struct tg3 *tp = (struct tg3 *)bp->priv;
864 u32 val;
865
866 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
867 return -EAGAIN;
868
869 if (tg3_readphy(tp, reg, &val))
870 return -EIO;
871
872 return val;
873 }
874
875 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
876 {
877 struct tg3 *tp = (struct tg3 *)bp->priv;
878
879 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
880 return -EAGAIN;
881
882 if (tg3_writephy(tp, reg, val))
883 return -EIO;
884
885 return 0;
886 }
887
888 static int tg3_mdio_reset(struct mii_bus *bp)
889 {
890 return 0;
891 }
892
893 static void tg3_mdio_config_5785(struct tg3 *tp)
894 {
895 u32 val;
896 struct phy_device *phydev;
897
898 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
899 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
900 case TG3_PHY_ID_BCM50610:
901 val = MAC_PHYCFG2_50610_LED_MODES;
902 break;
903 case TG3_PHY_ID_BCMAC131:
904 val = MAC_PHYCFG2_AC131_LED_MODES;
905 break;
906 case TG3_PHY_ID_RTL8211C:
907 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
908 break;
909 case TG3_PHY_ID_RTL8201E:
910 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
911 break;
912 default:
913 return;
914 }
915
916 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
917 tw32(MAC_PHYCFG2, val);
918
919 val = tr32(MAC_PHYCFG1);
920 val &= ~MAC_PHYCFG1_RGMII_INT;
921 tw32(MAC_PHYCFG1, val);
922
923 return;
924 }
925
926 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
927 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
928 MAC_PHYCFG2_FMODE_MASK_MASK |
929 MAC_PHYCFG2_GMODE_MASK_MASK |
930 MAC_PHYCFG2_ACT_MASK_MASK |
931 MAC_PHYCFG2_QUAL_MASK_MASK |
932 MAC_PHYCFG2_INBAND_ENABLE;
933
934 tw32(MAC_PHYCFG2, val);
935
936 val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
937 MAC_PHYCFG1_RGMII_SND_STAT_EN);
938 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
939 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
940 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
941 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
942 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
943 }
944 tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
945
946 val = tr32(MAC_EXT_RGMII_MODE);
947 val &= ~(MAC_RGMII_MODE_RX_INT_B |
948 MAC_RGMII_MODE_RX_QUALITY |
949 MAC_RGMII_MODE_RX_ACTIVITY |
950 MAC_RGMII_MODE_RX_ENG_DET |
951 MAC_RGMII_MODE_TX_ENABLE |
952 MAC_RGMII_MODE_TX_LOWPWR |
953 MAC_RGMII_MODE_TX_RESET);
954 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
955 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
956 val |= MAC_RGMII_MODE_RX_INT_B |
957 MAC_RGMII_MODE_RX_QUALITY |
958 MAC_RGMII_MODE_RX_ACTIVITY |
959 MAC_RGMII_MODE_RX_ENG_DET;
960 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
961 val |= MAC_RGMII_MODE_TX_ENABLE |
962 MAC_RGMII_MODE_TX_LOWPWR |
963 MAC_RGMII_MODE_TX_RESET;
964 }
965 tw32(MAC_EXT_RGMII_MODE, val);
966 }
967
968 static void tg3_mdio_start(struct tg3 *tp)
969 {
970 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
971 mutex_lock(&tp->mdio_bus->mdio_lock);
972 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
973 mutex_unlock(&tp->mdio_bus->mdio_lock);
974 }
975
976 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
977 tw32_f(MAC_MI_MODE, tp->mi_mode);
978 udelay(80);
979
980 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
982 tg3_mdio_config_5785(tp);
983 }
984
985 static void tg3_mdio_stop(struct tg3 *tp)
986 {
987 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
988 mutex_lock(&tp->mdio_bus->mdio_lock);
989 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
990 mutex_unlock(&tp->mdio_bus->mdio_lock);
991 }
992 }
993
994 static int tg3_mdio_init(struct tg3 *tp)
995 {
996 int i;
997 u32 reg;
998 struct phy_device *phydev;
999
1000 tg3_mdio_start(tp);
1001
1002 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1003 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1004 return 0;
1005
1006 tp->mdio_bus = mdiobus_alloc();
1007 if (tp->mdio_bus == NULL)
1008 return -ENOMEM;
1009
1010 tp->mdio_bus->name = "tg3 mdio bus";
1011 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1012 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1013 tp->mdio_bus->priv = tp;
1014 tp->mdio_bus->parent = &tp->pdev->dev;
1015 tp->mdio_bus->read = &tg3_mdio_read;
1016 tp->mdio_bus->write = &tg3_mdio_write;
1017 tp->mdio_bus->reset = &tg3_mdio_reset;
1018 tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
1019 tp->mdio_bus->irq = &tp->mdio_irq[0];
1020
1021 for (i = 0; i < PHY_MAX_ADDR; i++)
1022 tp->mdio_bus->irq[i] = PHY_POLL;
1023
1024 /* The bus registration will look for all the PHYs on the mdio bus.
1025 * Unfortunately, it does not ensure the PHY is powered up before
1026 * accessing the PHY ID registers. A chip reset is the
1027 * quickest way to bring the device back to an operational state..
1028 */
1029 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1030 tg3_bmcr_reset(tp);
1031
1032 i = mdiobus_register(tp->mdio_bus);
1033 if (i) {
1034 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1035 tp->dev->name, i);
1036 mdiobus_free(tp->mdio_bus);
1037 return i;
1038 }
1039
1040 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1041
1042 if (!phydev || !phydev->drv) {
1043 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1044 mdiobus_unregister(tp->mdio_bus);
1045 mdiobus_free(tp->mdio_bus);
1046 return -ENODEV;
1047 }
1048
1049 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1050 case TG3_PHY_ID_BCM57780:
1051 phydev->interface = PHY_INTERFACE_MODE_GMII;
1052 break;
1053 case TG3_PHY_ID_BCM50610:
1054 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1055 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1056 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1057 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1058 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1059 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1060 /* fallthru */
1061 case TG3_PHY_ID_RTL8211C:
1062 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1063 break;
1064 case TG3_PHY_ID_RTL8201E:
1065 case TG3_PHY_ID_BCMAC131:
1066 phydev->interface = PHY_INTERFACE_MODE_MII;
1067 break;
1068 }
1069
1070 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1071
1072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1073 tg3_mdio_config_5785(tp);
1074
1075 return 0;
1076 }
1077
1078 static void tg3_mdio_fini(struct tg3 *tp)
1079 {
1080 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1081 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1082 mdiobus_unregister(tp->mdio_bus);
1083 mdiobus_free(tp->mdio_bus);
1084 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1085 }
1086 }
1087
1088 /* tp->lock is held. */
1089 static inline void tg3_generate_fw_event(struct tg3 *tp)
1090 {
1091 u32 val;
1092
1093 val = tr32(GRC_RX_CPU_EVENT);
1094 val |= GRC_RX_CPU_DRIVER_EVENT;
1095 tw32_f(GRC_RX_CPU_EVENT, val);
1096
1097 tp->last_event_jiffies = jiffies;
1098 }
1099
1100 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1101
1102 /* tp->lock is held. */
1103 static void tg3_wait_for_event_ack(struct tg3 *tp)
1104 {
1105 int i;
1106 unsigned int delay_cnt;
1107 long time_remain;
1108
1109 /* If enough time has passed, no wait is necessary. */
1110 time_remain = (long)(tp->last_event_jiffies + 1 +
1111 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1112 (long)jiffies;
1113 if (time_remain < 0)
1114 return;
1115
1116 /* Check if we can shorten the wait time. */
1117 delay_cnt = jiffies_to_usecs(time_remain);
1118 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1119 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1120 delay_cnt = (delay_cnt >> 3) + 1;
1121
1122 for (i = 0; i < delay_cnt; i++) {
1123 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1124 break;
1125 udelay(8);
1126 }
1127 }
1128
1129 /* tp->lock is held. */
1130 static void tg3_ump_link_report(struct tg3 *tp)
1131 {
1132 u32 reg;
1133 u32 val;
1134
1135 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1136 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1137 return;
1138
1139 tg3_wait_for_event_ack(tp);
1140
1141 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1142
1143 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1144
1145 val = 0;
1146 if (!tg3_readphy(tp, MII_BMCR, &reg))
1147 val = reg << 16;
1148 if (!tg3_readphy(tp, MII_BMSR, &reg))
1149 val |= (reg & 0xffff);
1150 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1151
1152 val = 0;
1153 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1154 val = reg << 16;
1155 if (!tg3_readphy(tp, MII_LPA, &reg))
1156 val |= (reg & 0xffff);
1157 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1158
1159 val = 0;
1160 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1161 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1162 val = reg << 16;
1163 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1164 val |= (reg & 0xffff);
1165 }
1166 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1167
1168 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1169 val = reg << 16;
1170 else
1171 val = 0;
1172 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1173
1174 tg3_generate_fw_event(tp);
1175 }
1176
1177 static void tg3_link_report(struct tg3 *tp)
1178 {
1179 if (!netif_carrier_ok(tp->dev)) {
1180 if (netif_msg_link(tp))
1181 printk(KERN_INFO PFX "%s: Link is down.\n",
1182 tp->dev->name);
1183 tg3_ump_link_report(tp);
1184 } else if (netif_msg_link(tp)) {
1185 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1186 tp->dev->name,
1187 (tp->link_config.active_speed == SPEED_1000 ?
1188 1000 :
1189 (tp->link_config.active_speed == SPEED_100 ?
1190 100 : 10)),
1191 (tp->link_config.active_duplex == DUPLEX_FULL ?
1192 "full" : "half"));
1193
1194 printk(KERN_INFO PFX
1195 "%s: Flow control is %s for TX and %s for RX.\n",
1196 tp->dev->name,
1197 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1198 "on" : "off",
1199 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1200 "on" : "off");
1201 tg3_ump_link_report(tp);
1202 }
1203 }
1204
1205 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1206 {
1207 u16 miireg;
1208
1209 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1210 miireg = ADVERTISE_PAUSE_CAP;
1211 else if (flow_ctrl & FLOW_CTRL_TX)
1212 miireg = ADVERTISE_PAUSE_ASYM;
1213 else if (flow_ctrl & FLOW_CTRL_RX)
1214 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1215 else
1216 miireg = 0;
1217
1218 return miireg;
1219 }
1220
1221 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1222 {
1223 u16 miireg;
1224
1225 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1226 miireg = ADVERTISE_1000XPAUSE;
1227 else if (flow_ctrl & FLOW_CTRL_TX)
1228 miireg = ADVERTISE_1000XPSE_ASYM;
1229 else if (flow_ctrl & FLOW_CTRL_RX)
1230 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1231 else
1232 miireg = 0;
1233
1234 return miireg;
1235 }
1236
1237 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1238 {
1239 u8 cap = 0;
1240
1241 if (lcladv & ADVERTISE_1000XPAUSE) {
1242 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1243 if (rmtadv & LPA_1000XPAUSE)
1244 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1245 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1246 cap = FLOW_CTRL_RX;
1247 } else {
1248 if (rmtadv & LPA_1000XPAUSE)
1249 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1250 }
1251 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1252 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1253 cap = FLOW_CTRL_TX;
1254 }
1255
1256 return cap;
1257 }
1258
1259 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1260 {
1261 u8 autoneg;
1262 u8 flowctrl = 0;
1263 u32 old_rx_mode = tp->rx_mode;
1264 u32 old_tx_mode = tp->tx_mode;
1265
1266 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1267 autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
1268 else
1269 autoneg = tp->link_config.autoneg;
1270
1271 if (autoneg == AUTONEG_ENABLE &&
1272 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1273 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1274 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1275 else
1276 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1277 } else
1278 flowctrl = tp->link_config.flowctrl;
1279
1280 tp->link_config.active_flowctrl = flowctrl;
1281
1282 if (flowctrl & FLOW_CTRL_RX)
1283 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1284 else
1285 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1286
1287 if (old_rx_mode != tp->rx_mode)
1288 tw32_f(MAC_RX_MODE, tp->rx_mode);
1289
1290 if (flowctrl & FLOW_CTRL_TX)
1291 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1292 else
1293 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1294
1295 if (old_tx_mode != tp->tx_mode)
1296 tw32_f(MAC_TX_MODE, tp->tx_mode);
1297 }
1298
1299 static void tg3_adjust_link(struct net_device *dev)
1300 {
1301 u8 oldflowctrl, linkmesg = 0;
1302 u32 mac_mode, lcl_adv, rmt_adv;
1303 struct tg3 *tp = netdev_priv(dev);
1304 struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1305
1306 spin_lock(&tp->lock);
1307
1308 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1309 MAC_MODE_HALF_DUPLEX);
1310
1311 oldflowctrl = tp->link_config.active_flowctrl;
1312
1313 if (phydev->link) {
1314 lcl_adv = 0;
1315 rmt_adv = 0;
1316
1317 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1318 mac_mode |= MAC_MODE_PORT_MODE_MII;
1319 else
1320 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1321
1322 if (phydev->duplex == DUPLEX_HALF)
1323 mac_mode |= MAC_MODE_HALF_DUPLEX;
1324 else {
1325 lcl_adv = tg3_advert_flowctrl_1000T(
1326 tp->link_config.flowctrl);
1327
1328 if (phydev->pause)
1329 rmt_adv = LPA_PAUSE_CAP;
1330 if (phydev->asym_pause)
1331 rmt_adv |= LPA_PAUSE_ASYM;
1332 }
1333
1334 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1335 } else
1336 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1337
1338 if (mac_mode != tp->mac_mode) {
1339 tp->mac_mode = mac_mode;
1340 tw32_f(MAC_MODE, tp->mac_mode);
1341 udelay(40);
1342 }
1343
1344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1345 if (phydev->speed == SPEED_10)
1346 tw32(MAC_MI_STAT,
1347 MAC_MI_STAT_10MBPS_MODE |
1348 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1349 else
1350 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1351 }
1352
1353 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1354 tw32(MAC_TX_LENGTHS,
1355 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1356 (6 << TX_LENGTHS_IPG_SHIFT) |
1357 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1358 else
1359 tw32(MAC_TX_LENGTHS,
1360 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1361 (6 << TX_LENGTHS_IPG_SHIFT) |
1362 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1363
1364 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1365 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1366 phydev->speed != tp->link_config.active_speed ||
1367 phydev->duplex != tp->link_config.active_duplex ||
1368 oldflowctrl != tp->link_config.active_flowctrl)
1369 linkmesg = 1;
1370
1371 tp->link_config.active_speed = phydev->speed;
1372 tp->link_config.active_duplex = phydev->duplex;
1373
1374 spin_unlock(&tp->lock);
1375
1376 if (linkmesg)
1377 tg3_link_report(tp);
1378 }
1379
1380 static int tg3_phy_init(struct tg3 *tp)
1381 {
1382 struct phy_device *phydev;
1383
1384 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1385 return 0;
1386
1387 /* Bring the PHY back to a known state. */
1388 tg3_bmcr_reset(tp);
1389
1390 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1391
1392 /* Attach the MAC to the PHY. */
1393 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1394 phydev->dev_flags, phydev->interface);
1395 if (IS_ERR(phydev)) {
1396 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1397 return PTR_ERR(phydev);
1398 }
1399
1400 /* Mask with MAC supported features. */
1401 switch (phydev->interface) {
1402 case PHY_INTERFACE_MODE_GMII:
1403 case PHY_INTERFACE_MODE_RGMII:
1404 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1405 phydev->supported &= (PHY_GBIT_FEATURES |
1406 SUPPORTED_Pause |
1407 SUPPORTED_Asym_Pause);
1408 break;
1409 }
1410 /* fallthru */
1411 case PHY_INTERFACE_MODE_MII:
1412 phydev->supported &= (PHY_BASIC_FEATURES |
1413 SUPPORTED_Pause |
1414 SUPPORTED_Asym_Pause);
1415 break;
1416 default:
1417 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1418 return -EINVAL;
1419 }
1420
1421 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1422
1423 phydev->advertising = phydev->supported;
1424
1425 return 0;
1426 }
1427
1428 static void tg3_phy_start(struct tg3 *tp)
1429 {
1430 struct phy_device *phydev;
1431
1432 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1433 return;
1434
1435 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
1436
1437 if (tp->link_config.phy_is_low_power) {
1438 tp->link_config.phy_is_low_power = 0;
1439 phydev->speed = tp->link_config.orig_speed;
1440 phydev->duplex = tp->link_config.orig_duplex;
1441 phydev->autoneg = tp->link_config.orig_autoneg;
1442 phydev->advertising = tp->link_config.orig_advertising;
1443 }
1444
1445 phy_start(phydev);
1446
1447 phy_start_aneg(phydev);
1448 }
1449
1450 static void tg3_phy_stop(struct tg3 *tp)
1451 {
1452 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1453 return;
1454
1455 phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
1456 }
1457
1458 static void tg3_phy_fini(struct tg3 *tp)
1459 {
1460 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1461 phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
1462 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1463 }
1464 }
1465
1466 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1467 {
1468 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1469 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1470 }
1471
1472 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1473 {
1474 u32 reg;
1475
1476 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
1477 return;
1478
1479 reg = MII_TG3_MISC_SHDW_WREN |
1480 MII_TG3_MISC_SHDW_SCR5_SEL |
1481 MII_TG3_MISC_SHDW_SCR5_LPED |
1482 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1483 MII_TG3_MISC_SHDW_SCR5_SDTL |
1484 MII_TG3_MISC_SHDW_SCR5_C125OE;
1485 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1486 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1487
1488 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1489
1490
1491 reg = MII_TG3_MISC_SHDW_WREN |
1492 MII_TG3_MISC_SHDW_APD_SEL |
1493 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1494 if (enable)
1495 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1496
1497 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1498 }
1499
1500 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1501 {
1502 u32 phy;
1503
1504 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1505 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1506 return;
1507
1508 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1509 u32 ephy;
1510
1511 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1512 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1513 ephy | MII_TG3_EPHY_SHADOW_EN);
1514 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1515 if (enable)
1516 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1517 else
1518 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1519 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1520 }
1521 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1522 }
1523 } else {
1524 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1525 MII_TG3_AUXCTL_SHDWSEL_MISC;
1526 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1527 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1528 if (enable)
1529 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1530 else
1531 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1532 phy |= MII_TG3_AUXCTL_MISC_WREN;
1533 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1534 }
1535 }
1536 }
1537
1538 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1539 {
1540 u32 val;
1541
1542 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1543 return;
1544
1545 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1546 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1547 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1548 (val | (1 << 15) | (1 << 4)));
1549 }
1550
1551 static void tg3_phy_apply_otp(struct tg3 *tp)
1552 {
1553 u32 otp, phy;
1554
1555 if (!tp->phy_otp)
1556 return;
1557
1558 otp = tp->phy_otp;
1559
1560 /* Enable SM_DSP clock and tx 6dB coding. */
1561 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1562 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1563 MII_TG3_AUXCTL_ACTL_TX_6DB;
1564 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1565
1566 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1567 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1568 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1569
1570 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1571 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1572 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1573
1574 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1575 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1576 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1577
1578 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1579 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1580
1581 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1582 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1583
1584 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1585 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1586 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1587
1588 /* Turn off SM_DSP clock. */
1589 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1590 MII_TG3_AUXCTL_ACTL_TX_6DB;
1591 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1592 }
1593
1594 static int tg3_wait_macro_done(struct tg3 *tp)
1595 {
1596 int limit = 100;
1597
1598 while (limit--) {
1599 u32 tmp32;
1600
1601 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1602 if ((tmp32 & 0x1000) == 0)
1603 break;
1604 }
1605 }
1606 if (limit <= 0)
1607 return -EBUSY;
1608
1609 return 0;
1610 }
1611
1612 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1613 {
1614 static const u32 test_pat[4][6] = {
1615 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1616 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1617 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1618 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1619 };
1620 int chan;
1621
1622 for (chan = 0; chan < 4; chan++) {
1623 int i;
1624
1625 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1626 (chan * 0x2000) | 0x0200);
1627 tg3_writephy(tp, 0x16, 0x0002);
1628
1629 for (i = 0; i < 6; i++)
1630 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1631 test_pat[chan][i]);
1632
1633 tg3_writephy(tp, 0x16, 0x0202);
1634 if (tg3_wait_macro_done(tp)) {
1635 *resetp = 1;
1636 return -EBUSY;
1637 }
1638
1639 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1640 (chan * 0x2000) | 0x0200);
1641 tg3_writephy(tp, 0x16, 0x0082);
1642 if (tg3_wait_macro_done(tp)) {
1643 *resetp = 1;
1644 return -EBUSY;
1645 }
1646
1647 tg3_writephy(tp, 0x16, 0x0802);
1648 if (tg3_wait_macro_done(tp)) {
1649 *resetp = 1;
1650 return -EBUSY;
1651 }
1652
1653 for (i = 0; i < 6; i += 2) {
1654 u32 low, high;
1655
1656 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1657 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1658 tg3_wait_macro_done(tp)) {
1659 *resetp = 1;
1660 return -EBUSY;
1661 }
1662 low &= 0x7fff;
1663 high &= 0x000f;
1664 if (low != test_pat[chan][i] ||
1665 high != test_pat[chan][i+1]) {
1666 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1667 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1668 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1669
1670 return -EBUSY;
1671 }
1672 }
1673 }
1674
1675 return 0;
1676 }
1677
1678 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1679 {
1680 int chan;
1681
1682 for (chan = 0; chan < 4; chan++) {
1683 int i;
1684
1685 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1686 (chan * 0x2000) | 0x0200);
1687 tg3_writephy(tp, 0x16, 0x0002);
1688 for (i = 0; i < 6; i++)
1689 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1690 tg3_writephy(tp, 0x16, 0x0202);
1691 if (tg3_wait_macro_done(tp))
1692 return -EBUSY;
1693 }
1694
1695 return 0;
1696 }
1697
1698 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1699 {
1700 u32 reg32, phy9_orig;
1701 int retries, do_phy_reset, err;
1702
1703 retries = 10;
1704 do_phy_reset = 1;
1705 do {
1706 if (do_phy_reset) {
1707 err = tg3_bmcr_reset(tp);
1708 if (err)
1709 return err;
1710 do_phy_reset = 0;
1711 }
1712
1713 /* Disable transmitter and interrupt. */
1714 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1715 continue;
1716
1717 reg32 |= 0x3000;
1718 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1719
1720 /* Set full-duplex, 1000 mbps. */
1721 tg3_writephy(tp, MII_BMCR,
1722 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1723
1724 /* Set to master mode. */
1725 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1726 continue;
1727
1728 tg3_writephy(tp, MII_TG3_CTRL,
1729 (MII_TG3_CTRL_AS_MASTER |
1730 MII_TG3_CTRL_ENABLE_AS_MASTER));
1731
1732 /* Enable SM_DSP_CLOCK and 6dB. */
1733 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1734
1735 /* Block the PHY control access. */
1736 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1737 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1738
1739 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1740 if (!err)
1741 break;
1742 } while (--retries);
1743
1744 err = tg3_phy_reset_chanpat(tp);
1745 if (err)
1746 return err;
1747
1748 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1749 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1750
1751 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1752 tg3_writephy(tp, 0x16, 0x0000);
1753
1754 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1755 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1756 /* Set Extended packet length bit for jumbo frames */
1757 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1758 }
1759 else {
1760 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1761 }
1762
1763 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1764
1765 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1766 reg32 &= ~0x3000;
1767 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1768 } else if (!err)
1769 err = -EBUSY;
1770
1771 return err;
1772 }
1773
1774 /* This will reset the tigon3 PHY if there is no valid
1775 * link unless the FORCE argument is non-zero.
1776 */
1777 static int tg3_phy_reset(struct tg3 *tp)
1778 {
1779 u32 cpmuctrl;
1780 u32 phy_status;
1781 int err;
1782
1783 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1784 u32 val;
1785
1786 val = tr32(GRC_MISC_CFG);
1787 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1788 udelay(40);
1789 }
1790 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1791 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1792 if (err != 0)
1793 return -EBUSY;
1794
1795 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1796 netif_carrier_off(tp->dev);
1797 tg3_link_report(tp);
1798 }
1799
1800 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1801 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1803 err = tg3_phy_reset_5703_4_5(tp);
1804 if (err)
1805 return err;
1806 goto out;
1807 }
1808
1809 cpmuctrl = 0;
1810 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1811 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1812 cpmuctrl = tr32(TG3_CPMU_CTRL);
1813 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1814 tw32(TG3_CPMU_CTRL,
1815 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1816 }
1817
1818 err = tg3_bmcr_reset(tp);
1819 if (err)
1820 return err;
1821
1822 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1823 u32 phy;
1824
1825 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1826 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1827
1828 tw32(TG3_CPMU_CTRL, cpmuctrl);
1829 }
1830
1831 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1832 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1833 u32 val;
1834
1835 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1836 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1837 CPMU_LSPD_1000MB_MACCLK_12_5) {
1838 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1839 udelay(40);
1840 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1841 }
1842 }
1843
1844 tg3_phy_apply_otp(tp);
1845
1846 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1847 tg3_phy_toggle_apd(tp, true);
1848 else
1849 tg3_phy_toggle_apd(tp, false);
1850
1851 out:
1852 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1853 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1854 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1855 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1856 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1857 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1858 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1859 }
1860 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1861 tg3_writephy(tp, 0x1c, 0x8d68);
1862 tg3_writephy(tp, 0x1c, 0x8d68);
1863 }
1864 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1865 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1866 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1867 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1868 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1869 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1870 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1871 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1872 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1873 }
1874 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1875 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1876 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1877 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1878 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1879 tg3_writephy(tp, MII_TG3_TEST1,
1880 MII_TG3_TEST1_TRIM_EN | 0x4);
1881 } else
1882 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1883 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1884 }
1885 /* Set Extended packet length bit (bit 14) on all chips that */
1886 /* support jumbo frames */
1887 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1888 /* Cannot do read-modify-write on 5401 */
1889 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1890 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1891 u32 phy_reg;
1892
1893 /* Set bit 14 with read-modify-write to preserve other bits */
1894 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1895 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1896 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1897 }
1898
1899 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1900 * jumbo frames transmission.
1901 */
1902 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1903 u32 phy_reg;
1904
1905 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1906 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1907 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1908 }
1909
1910 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1911 /* adjust output voltage */
1912 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1913 }
1914
1915 tg3_phy_toggle_automdix(tp, 1);
1916 tg3_phy_set_wirespeed(tp);
1917 return 0;
1918 }
1919
1920 static void tg3_frob_aux_power(struct tg3 *tp)
1921 {
1922 struct tg3 *tp_peer = tp;
1923
1924 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1925 return;
1926
1927 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1928 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1929 struct net_device *dev_peer;
1930
1931 dev_peer = pci_get_drvdata(tp->pdev_peer);
1932 /* remove_one() may have been run on the peer. */
1933 if (!dev_peer)
1934 tp_peer = tp;
1935 else
1936 tp_peer = netdev_priv(dev_peer);
1937 }
1938
1939 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1940 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1941 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1942 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1944 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1945 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1946 (GRC_LCLCTRL_GPIO_OE0 |
1947 GRC_LCLCTRL_GPIO_OE1 |
1948 GRC_LCLCTRL_GPIO_OE2 |
1949 GRC_LCLCTRL_GPIO_OUTPUT0 |
1950 GRC_LCLCTRL_GPIO_OUTPUT1),
1951 100);
1952 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1953 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1954 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1955 GRC_LCLCTRL_GPIO_OE1 |
1956 GRC_LCLCTRL_GPIO_OE2 |
1957 GRC_LCLCTRL_GPIO_OUTPUT0 |
1958 GRC_LCLCTRL_GPIO_OUTPUT1 |
1959 tp->grc_local_ctrl;
1960 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1961
1962 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1963 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1964
1965 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1966 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1967 } else {
1968 u32 no_gpio2;
1969 u32 grc_local_ctrl = 0;
1970
1971 if (tp_peer != tp &&
1972 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1973 return;
1974
1975 /* Workaround to prevent overdrawing Amps. */
1976 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1977 ASIC_REV_5714) {
1978 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1979 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1980 grc_local_ctrl, 100);
1981 }
1982
1983 /* On 5753 and variants, GPIO2 cannot be used. */
1984 no_gpio2 = tp->nic_sram_data_cfg &
1985 NIC_SRAM_DATA_CFG_NO_GPIO2;
1986
1987 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1988 GRC_LCLCTRL_GPIO_OE1 |
1989 GRC_LCLCTRL_GPIO_OE2 |
1990 GRC_LCLCTRL_GPIO_OUTPUT1 |
1991 GRC_LCLCTRL_GPIO_OUTPUT2;
1992 if (no_gpio2) {
1993 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1994 GRC_LCLCTRL_GPIO_OUTPUT2);
1995 }
1996 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1997 grc_local_ctrl, 100);
1998
1999 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2000
2001 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2002 grc_local_ctrl, 100);
2003
2004 if (!no_gpio2) {
2005 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2006 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2007 grc_local_ctrl, 100);
2008 }
2009 }
2010 } else {
2011 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2012 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2013 if (tp_peer != tp &&
2014 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2015 return;
2016
2017 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2018 (GRC_LCLCTRL_GPIO_OE1 |
2019 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2020
2021 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2022 GRC_LCLCTRL_GPIO_OE1, 100);
2023
2024 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2025 (GRC_LCLCTRL_GPIO_OE1 |
2026 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2027 }
2028 }
2029 }
2030
2031 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2032 {
2033 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2034 return 1;
2035 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2036 if (speed != SPEED_10)
2037 return 1;
2038 } else if (speed == SPEED_10)
2039 return 1;
2040
2041 return 0;
2042 }
2043
2044 static int tg3_setup_phy(struct tg3 *, int);
2045
2046 #define RESET_KIND_SHUTDOWN 0
2047 #define RESET_KIND_INIT 1
2048 #define RESET_KIND_SUSPEND 2
2049
2050 static void tg3_write_sig_post_reset(struct tg3 *, int);
2051 static int tg3_halt_cpu(struct tg3 *, u32);
2052 static int tg3_nvram_lock(struct tg3 *);
2053 static void tg3_nvram_unlock(struct tg3 *);
2054
2055 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2056 {
2057 u32 val;
2058
2059 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2061 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2062 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2063
2064 sg_dig_ctrl |=
2065 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2066 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2067 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2068 }
2069 return;
2070 }
2071
2072 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2073 tg3_bmcr_reset(tp);
2074 val = tr32(GRC_MISC_CFG);
2075 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2076 udelay(40);
2077 return;
2078 } else if (do_low_power) {
2079 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2080 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2081
2082 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2083 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2084 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2085 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2086 MII_TG3_AUXCTL_PCTL_VREG_11V);
2087 }
2088
2089 /* The PHY should not be powered down on some chips because
2090 * of bugs.
2091 */
2092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2094 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2095 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2096 return;
2097
2098 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2099 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2100 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2101 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2102 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2103 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2104 }
2105
2106 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2107 }
2108
2109 /* tp->lock is held. */
2110 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2111 {
2112 u32 addr_high, addr_low;
2113 int i;
2114
2115 addr_high = ((tp->dev->dev_addr[0] << 8) |
2116 tp->dev->dev_addr[1]);
2117 addr_low = ((tp->dev->dev_addr[2] << 24) |
2118 (tp->dev->dev_addr[3] << 16) |
2119 (tp->dev->dev_addr[4] << 8) |
2120 (tp->dev->dev_addr[5] << 0));
2121 for (i = 0; i < 4; i++) {
2122 if (i == 1 && skip_mac_1)
2123 continue;
2124 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2125 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2126 }
2127
2128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2129 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2130 for (i = 0; i < 12; i++) {
2131 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2132 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2133 }
2134 }
2135
2136 addr_high = (tp->dev->dev_addr[0] +
2137 tp->dev->dev_addr[1] +
2138 tp->dev->dev_addr[2] +
2139 tp->dev->dev_addr[3] +
2140 tp->dev->dev_addr[4] +
2141 tp->dev->dev_addr[5]) &
2142 TX_BACKOFF_SEED_MASK;
2143 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2144 }
2145
2146 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2147 {
2148 u32 misc_host_ctrl;
2149 bool device_should_wake, do_low_power;
2150
2151 /* Make sure register accesses (indirect or otherwise)
2152 * will function correctly.
2153 */
2154 pci_write_config_dword(tp->pdev,
2155 TG3PCI_MISC_HOST_CTRL,
2156 tp->misc_host_ctrl);
2157
2158 switch (state) {
2159 case PCI_D0:
2160 pci_enable_wake(tp->pdev, state, false);
2161 pci_set_power_state(tp->pdev, PCI_D0);
2162
2163 /* Switch out of Vaux if it is a NIC */
2164 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2165 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2166
2167 return 0;
2168
2169 case PCI_D1:
2170 case PCI_D2:
2171 case PCI_D3hot:
2172 break;
2173
2174 default:
2175 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2176 tp->dev->name, state);
2177 return -EINVAL;
2178 }
2179
2180 /* Restore the CLKREQ setting. */
2181 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2182 u16 lnkctl;
2183
2184 pci_read_config_word(tp->pdev,
2185 tp->pcie_cap + PCI_EXP_LNKCTL,
2186 &lnkctl);
2187 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2188 pci_write_config_word(tp->pdev,
2189 tp->pcie_cap + PCI_EXP_LNKCTL,
2190 lnkctl);
2191 }
2192
2193 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2194 tw32(TG3PCI_MISC_HOST_CTRL,
2195 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2196
2197 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2198 device_may_wakeup(&tp->pdev->dev) &&
2199 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2200
2201 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2202 do_low_power = false;
2203 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2204 !tp->link_config.phy_is_low_power) {
2205 struct phy_device *phydev;
2206 u32 phyid, advertising;
2207
2208 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
2209
2210 tp->link_config.phy_is_low_power = 1;
2211
2212 tp->link_config.orig_speed = phydev->speed;
2213 tp->link_config.orig_duplex = phydev->duplex;
2214 tp->link_config.orig_autoneg = phydev->autoneg;
2215 tp->link_config.orig_advertising = phydev->advertising;
2216
2217 advertising = ADVERTISED_TP |
2218 ADVERTISED_Pause |
2219 ADVERTISED_Autoneg |
2220 ADVERTISED_10baseT_Half;
2221
2222 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2223 device_should_wake) {
2224 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2225 advertising |=
2226 ADVERTISED_100baseT_Half |
2227 ADVERTISED_100baseT_Full |
2228 ADVERTISED_10baseT_Full;
2229 else
2230 advertising |= ADVERTISED_10baseT_Full;
2231 }
2232
2233 phydev->advertising = advertising;
2234
2235 phy_start_aneg(phydev);
2236
2237 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2238 if (phyid != TG3_PHY_ID_BCMAC131) {
2239 phyid &= TG3_PHY_OUI_MASK;
2240 if (phyid == TG3_PHY_OUI_1 &&
2241 phyid == TG3_PHY_OUI_2 &&
2242 phyid == TG3_PHY_OUI_3)
2243 do_low_power = true;
2244 }
2245 }
2246 } else {
2247 do_low_power = true;
2248
2249 if (tp->link_config.phy_is_low_power == 0) {
2250 tp->link_config.phy_is_low_power = 1;
2251 tp->link_config.orig_speed = tp->link_config.speed;
2252 tp->link_config.orig_duplex = tp->link_config.duplex;
2253 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2254 }
2255
2256 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2257 tp->link_config.speed = SPEED_10;
2258 tp->link_config.duplex = DUPLEX_HALF;
2259 tp->link_config.autoneg = AUTONEG_ENABLE;
2260 tg3_setup_phy(tp, 0);
2261 }
2262 }
2263
2264 __tg3_set_mac_addr(tp, 0);
2265
2266 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2267 u32 val;
2268
2269 val = tr32(GRC_VCPU_EXT_CTRL);
2270 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2271 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2272 int i;
2273 u32 val;
2274
2275 for (i = 0; i < 200; i++) {
2276 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2277 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2278 break;
2279 msleep(1);
2280 }
2281 }
2282 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2283 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2284 WOL_DRV_STATE_SHUTDOWN |
2285 WOL_DRV_WOL |
2286 WOL_SET_MAGIC_PKT);
2287
2288 if (device_should_wake) {
2289 u32 mac_mode;
2290
2291 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2292 if (do_low_power) {
2293 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2294 udelay(40);
2295 }
2296
2297 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2298 mac_mode = MAC_MODE_PORT_MODE_GMII;
2299 else
2300 mac_mode = MAC_MODE_PORT_MODE_MII;
2301
2302 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2303 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2304 ASIC_REV_5700) {
2305 u32 speed = (tp->tg3_flags &
2306 TG3_FLAG_WOL_SPEED_100MB) ?
2307 SPEED_100 : SPEED_10;
2308 if (tg3_5700_link_polarity(tp, speed))
2309 mac_mode |= MAC_MODE_LINK_POLARITY;
2310 else
2311 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2312 }
2313 } else {
2314 mac_mode = MAC_MODE_PORT_MODE_TBI;
2315 }
2316
2317 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2318 tw32(MAC_LED_CTRL, tp->led_ctrl);
2319
2320 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2321 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2322 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2323 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2324 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2325 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2326
2327 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2328 mac_mode |= tp->mac_mode &
2329 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2330 if (mac_mode & MAC_MODE_APE_TX_EN)
2331 mac_mode |= MAC_MODE_TDE_ENABLE;
2332 }
2333
2334 tw32_f(MAC_MODE, mac_mode);
2335 udelay(100);
2336
2337 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2338 udelay(10);
2339 }
2340
2341 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2342 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2343 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2344 u32 base_val;
2345
2346 base_val = tp->pci_clock_ctrl;
2347 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2348 CLOCK_CTRL_TXCLK_DISABLE);
2349
2350 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2351 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2352 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2353 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2354 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2355 /* do nothing */
2356 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2357 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2358 u32 newbits1, newbits2;
2359
2360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2361 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2362 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2363 CLOCK_CTRL_TXCLK_DISABLE |
2364 CLOCK_CTRL_ALTCLK);
2365 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2366 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2367 newbits1 = CLOCK_CTRL_625_CORE;
2368 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2369 } else {
2370 newbits1 = CLOCK_CTRL_ALTCLK;
2371 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2372 }
2373
2374 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2375 40);
2376
2377 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2378 40);
2379
2380 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2381 u32 newbits3;
2382
2383 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2384 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2385 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2386 CLOCK_CTRL_TXCLK_DISABLE |
2387 CLOCK_CTRL_44MHZ_CORE);
2388 } else {
2389 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2390 }
2391
2392 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2393 tp->pci_clock_ctrl | newbits3, 40);
2394 }
2395 }
2396
2397 if (!(device_should_wake) &&
2398 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2399 tg3_power_down_phy(tp, do_low_power);
2400
2401 tg3_frob_aux_power(tp);
2402
2403 /* Workaround for unstable PLL clock */
2404 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2405 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2406 u32 val = tr32(0x7d00);
2407
2408 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2409 tw32(0x7d00, val);
2410 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2411 int err;
2412
2413 err = tg3_nvram_lock(tp);
2414 tg3_halt_cpu(tp, RX_CPU_BASE);
2415 if (!err)
2416 tg3_nvram_unlock(tp);
2417 }
2418 }
2419
2420 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2421
2422 if (device_should_wake)
2423 pci_enable_wake(tp->pdev, state, true);
2424
2425 /* Finally, set the new power state. */
2426 pci_set_power_state(tp->pdev, state);
2427
2428 return 0;
2429 }
2430
2431 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2432 {
2433 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2434 case MII_TG3_AUX_STAT_10HALF:
2435 *speed = SPEED_10;
2436 *duplex = DUPLEX_HALF;
2437 break;
2438
2439 case MII_TG3_AUX_STAT_10FULL:
2440 *speed = SPEED_10;
2441 *duplex = DUPLEX_FULL;
2442 break;
2443
2444 case MII_TG3_AUX_STAT_100HALF:
2445 *speed = SPEED_100;
2446 *duplex = DUPLEX_HALF;
2447 break;
2448
2449 case MII_TG3_AUX_STAT_100FULL:
2450 *speed = SPEED_100;
2451 *duplex = DUPLEX_FULL;
2452 break;
2453
2454 case MII_TG3_AUX_STAT_1000HALF:
2455 *speed = SPEED_1000;
2456 *duplex = DUPLEX_HALF;
2457 break;
2458
2459 case MII_TG3_AUX_STAT_1000FULL:
2460 *speed = SPEED_1000;
2461 *duplex = DUPLEX_FULL;
2462 break;
2463
2464 default:
2465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2466 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2467 SPEED_10;
2468 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2469 DUPLEX_HALF;
2470 break;
2471 }
2472 *speed = SPEED_INVALID;
2473 *duplex = DUPLEX_INVALID;
2474 break;
2475 }
2476 }
2477
2478 static void tg3_phy_copper_begin(struct tg3 *tp)
2479 {
2480 u32 new_adv;
2481 int i;
2482
2483 if (tp->link_config.phy_is_low_power) {
2484 /* Entering low power mode. Disable gigabit and
2485 * 100baseT advertisements.
2486 */
2487 tg3_writephy(tp, MII_TG3_CTRL, 0);
2488
2489 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2490 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2491 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2492 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2493
2494 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2495 } else if (tp->link_config.speed == SPEED_INVALID) {
2496 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2497 tp->link_config.advertising &=
2498 ~(ADVERTISED_1000baseT_Half |
2499 ADVERTISED_1000baseT_Full);
2500
2501 new_adv = ADVERTISE_CSMA;
2502 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2503 new_adv |= ADVERTISE_10HALF;
2504 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2505 new_adv |= ADVERTISE_10FULL;
2506 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2507 new_adv |= ADVERTISE_100HALF;
2508 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2509 new_adv |= ADVERTISE_100FULL;
2510
2511 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2512
2513 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2514
2515 if (tp->link_config.advertising &
2516 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2517 new_adv = 0;
2518 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2519 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2520 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2521 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2522 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2523 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2524 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2525 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2526 MII_TG3_CTRL_ENABLE_AS_MASTER);
2527 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2528 } else {
2529 tg3_writephy(tp, MII_TG3_CTRL, 0);
2530 }
2531 } else {
2532 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2533 new_adv |= ADVERTISE_CSMA;
2534
2535 /* Asking for a specific link mode. */
2536 if (tp->link_config.speed == SPEED_1000) {
2537 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2538
2539 if (tp->link_config.duplex == DUPLEX_FULL)
2540 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2541 else
2542 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2543 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2544 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2545 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2546 MII_TG3_CTRL_ENABLE_AS_MASTER);
2547 } else {
2548 if (tp->link_config.speed == SPEED_100) {
2549 if (tp->link_config.duplex == DUPLEX_FULL)
2550 new_adv |= ADVERTISE_100FULL;
2551 else
2552 new_adv |= ADVERTISE_100HALF;
2553 } else {
2554 if (tp->link_config.duplex == DUPLEX_FULL)
2555 new_adv |= ADVERTISE_10FULL;
2556 else
2557 new_adv |= ADVERTISE_10HALF;
2558 }
2559 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2560
2561 new_adv = 0;
2562 }
2563
2564 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2565 }
2566
2567 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2568 tp->link_config.speed != SPEED_INVALID) {
2569 u32 bmcr, orig_bmcr;
2570
2571 tp->link_config.active_speed = tp->link_config.speed;
2572 tp->link_config.active_duplex = tp->link_config.duplex;
2573
2574 bmcr = 0;
2575 switch (tp->link_config.speed) {
2576 default:
2577 case SPEED_10:
2578 break;
2579
2580 case SPEED_100:
2581 bmcr |= BMCR_SPEED100;
2582 break;
2583
2584 case SPEED_1000:
2585 bmcr |= TG3_BMCR_SPEED1000;
2586 break;
2587 }
2588
2589 if (tp->link_config.duplex == DUPLEX_FULL)
2590 bmcr |= BMCR_FULLDPLX;
2591
2592 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2593 (bmcr != orig_bmcr)) {
2594 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2595 for (i = 0; i < 1500; i++) {
2596 u32 tmp;
2597
2598 udelay(10);
2599 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2600 tg3_readphy(tp, MII_BMSR, &tmp))
2601 continue;
2602 if (!(tmp & BMSR_LSTATUS)) {
2603 udelay(40);
2604 break;
2605 }
2606 }
2607 tg3_writephy(tp, MII_BMCR, bmcr);
2608 udelay(40);
2609 }
2610 } else {
2611 tg3_writephy(tp, MII_BMCR,
2612 BMCR_ANENABLE | BMCR_ANRESTART);
2613 }
2614 }
2615
2616 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2617 {
2618 int err;
2619
2620 /* Turn off tap power management. */
2621 /* Set Extended packet length bit */
2622 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2623
2624 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2625 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2626
2627 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2628 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2629
2630 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2631 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2632
2633 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2634 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2635
2636 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2637 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2638
2639 udelay(40);
2640
2641 return err;
2642 }
2643
2644 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2645 {
2646 u32 adv_reg, all_mask = 0;
2647
2648 if (mask & ADVERTISED_10baseT_Half)
2649 all_mask |= ADVERTISE_10HALF;
2650 if (mask & ADVERTISED_10baseT_Full)
2651 all_mask |= ADVERTISE_10FULL;
2652 if (mask & ADVERTISED_100baseT_Half)
2653 all_mask |= ADVERTISE_100HALF;
2654 if (mask & ADVERTISED_100baseT_Full)
2655 all_mask |= ADVERTISE_100FULL;
2656
2657 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2658 return 0;
2659
2660 if ((adv_reg & all_mask) != all_mask)
2661 return 0;
2662 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2663 u32 tg3_ctrl;
2664
2665 all_mask = 0;
2666 if (mask & ADVERTISED_1000baseT_Half)
2667 all_mask |= ADVERTISE_1000HALF;
2668 if (mask & ADVERTISED_1000baseT_Full)
2669 all_mask |= ADVERTISE_1000FULL;
2670
2671 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2672 return 0;
2673
2674 if ((tg3_ctrl & all_mask) != all_mask)
2675 return 0;
2676 }
2677 return 1;
2678 }
2679
2680 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2681 {
2682 u32 curadv, reqadv;
2683
2684 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2685 return 1;
2686
2687 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2688 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2689
2690 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2691 if (curadv != reqadv)
2692 return 0;
2693
2694 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2695 tg3_readphy(tp, MII_LPA, rmtadv);
2696 } else {
2697 /* Reprogram the advertisement register, even if it
2698 * does not affect the current link. If the link
2699 * gets renegotiated in the future, we can save an
2700 * additional renegotiation cycle by advertising
2701 * it correctly in the first place.
2702 */
2703 if (curadv != reqadv) {
2704 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2705 ADVERTISE_PAUSE_ASYM);
2706 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2707 }
2708 }
2709
2710 return 1;
2711 }
2712
2713 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2714 {
2715 int current_link_up;
2716 u32 bmsr, dummy;
2717 u32 lcl_adv, rmt_adv;
2718 u16 current_speed;
2719 u8 current_duplex;
2720 int i, err;
2721
2722 tw32(MAC_EVENT, 0);
2723
2724 tw32_f(MAC_STATUS,
2725 (MAC_STATUS_SYNC_CHANGED |
2726 MAC_STATUS_CFG_CHANGED |
2727 MAC_STATUS_MI_COMPLETION |
2728 MAC_STATUS_LNKSTATE_CHANGED));
2729 udelay(40);
2730
2731 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2732 tw32_f(MAC_MI_MODE,
2733 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2734 udelay(80);
2735 }
2736
2737 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2738
2739 /* Some third-party PHYs need to be reset on link going
2740 * down.
2741 */
2742 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2743 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2744 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2745 netif_carrier_ok(tp->dev)) {
2746 tg3_readphy(tp, MII_BMSR, &bmsr);
2747 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2748 !(bmsr & BMSR_LSTATUS))
2749 force_reset = 1;
2750 }
2751 if (force_reset)
2752 tg3_phy_reset(tp);
2753
2754 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2755 tg3_readphy(tp, MII_BMSR, &bmsr);
2756 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2757 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2758 bmsr = 0;
2759
2760 if (!(bmsr & BMSR_LSTATUS)) {
2761 err = tg3_init_5401phy_dsp(tp);
2762 if (err)
2763 return err;
2764
2765 tg3_readphy(tp, MII_BMSR, &bmsr);
2766 for (i = 0; i < 1000; i++) {
2767 udelay(10);
2768 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2769 (bmsr & BMSR_LSTATUS)) {
2770 udelay(40);
2771 break;
2772 }
2773 }
2774
2775 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2776 !(bmsr & BMSR_LSTATUS) &&
2777 tp->link_config.active_speed == SPEED_1000) {
2778 err = tg3_phy_reset(tp);
2779 if (!err)
2780 err = tg3_init_5401phy_dsp(tp);
2781 if (err)
2782 return err;
2783 }
2784 }
2785 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2786 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2787 /* 5701 {A0,B0} CRC bug workaround */
2788 tg3_writephy(tp, 0x15, 0x0a75);
2789 tg3_writephy(tp, 0x1c, 0x8c68);
2790 tg3_writephy(tp, 0x1c, 0x8d68);
2791 tg3_writephy(tp, 0x1c, 0x8c68);
2792 }
2793
2794 /* Clear pending interrupts... */
2795 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2796 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2797
2798 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2799 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2800 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2801 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2802
2803 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2804 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2805 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2806 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2807 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2808 else
2809 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2810 }
2811
2812 current_link_up = 0;
2813 current_speed = SPEED_INVALID;
2814 current_duplex = DUPLEX_INVALID;
2815
2816 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2817 u32 val;
2818
2819 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2820 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2821 if (!(val & (1 << 10))) {
2822 val |= (1 << 10);
2823 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2824 goto relink;
2825 }
2826 }
2827
2828 bmsr = 0;
2829 for (i = 0; i < 100; i++) {
2830 tg3_readphy(tp, MII_BMSR, &bmsr);
2831 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2832 (bmsr & BMSR_LSTATUS))
2833 break;
2834 udelay(40);
2835 }
2836
2837 if (bmsr & BMSR_LSTATUS) {
2838 u32 aux_stat, bmcr;
2839
2840 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2841 for (i = 0; i < 2000; i++) {
2842 udelay(10);
2843 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2844 aux_stat)
2845 break;
2846 }
2847
2848 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2849 &current_speed,
2850 &current_duplex);
2851
2852 bmcr = 0;
2853 for (i = 0; i < 200; i++) {
2854 tg3_readphy(tp, MII_BMCR, &bmcr);
2855 if (tg3_readphy(tp, MII_BMCR, &bmcr))
2856 continue;
2857 if (bmcr && bmcr != 0x7fff)
2858 break;
2859 udelay(10);
2860 }
2861
2862 lcl_adv = 0;
2863 rmt_adv = 0;
2864
2865 tp->link_config.active_speed = current_speed;
2866 tp->link_config.active_duplex = current_duplex;
2867
2868 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2869 if ((bmcr & BMCR_ANENABLE) &&
2870 tg3_copper_is_advertising_all(tp,
2871 tp->link_config.advertising)) {
2872 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2873 &rmt_adv))
2874 current_link_up = 1;
2875 }
2876 } else {
2877 if (!(bmcr & BMCR_ANENABLE) &&
2878 tp->link_config.speed == current_speed &&
2879 tp->link_config.duplex == current_duplex &&
2880 tp->link_config.flowctrl ==
2881 tp->link_config.active_flowctrl) {
2882 current_link_up = 1;
2883 }
2884 }
2885
2886 if (current_link_up == 1 &&
2887 tp->link_config.active_duplex == DUPLEX_FULL)
2888 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2889 }
2890
2891 relink:
2892 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2893 u32 tmp;
2894
2895 tg3_phy_copper_begin(tp);
2896
2897 tg3_readphy(tp, MII_BMSR, &tmp);
2898 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2899 (tmp & BMSR_LSTATUS))
2900 current_link_up = 1;
2901 }
2902
2903 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2904 if (current_link_up == 1) {
2905 if (tp->link_config.active_speed == SPEED_100 ||
2906 tp->link_config.active_speed == SPEED_10)
2907 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2908 else
2909 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2910 } else
2911 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2912
2913 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2914 if (tp->link_config.active_duplex == DUPLEX_HALF)
2915 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2916
2917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2918 if (current_link_up == 1 &&
2919 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2920 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2921 else
2922 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2923 }
2924
2925 /* ??? Without this setting Netgear GA302T PHY does not
2926 * ??? send/receive packets...
2927 */
2928 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2929 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2930 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2931 tw32_f(MAC_MI_MODE, tp->mi_mode);
2932 udelay(80);
2933 }
2934
2935 tw32_f(MAC_MODE, tp->mac_mode);
2936 udelay(40);
2937
2938 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2939 /* Polled via timer. */
2940 tw32_f(MAC_EVENT, 0);
2941 } else {
2942 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2943 }
2944 udelay(40);
2945
2946 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2947 current_link_up == 1 &&
2948 tp->link_config.active_speed == SPEED_1000 &&
2949 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2950 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2951 udelay(120);
2952 tw32_f(MAC_STATUS,
2953 (MAC_STATUS_SYNC_CHANGED |
2954 MAC_STATUS_CFG_CHANGED));
2955 udelay(40);
2956 tg3_write_mem(tp,
2957 NIC_SRAM_FIRMWARE_MBOX,
2958 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2959 }
2960
2961 /* Prevent send BD corruption. */
2962 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2963 u16 oldlnkctl, newlnkctl;
2964
2965 pci_read_config_word(tp->pdev,
2966 tp->pcie_cap + PCI_EXP_LNKCTL,
2967 &oldlnkctl);
2968 if (tp->link_config.active_speed == SPEED_100 ||
2969 tp->link_config.active_speed == SPEED_10)
2970 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
2971 else
2972 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
2973 if (newlnkctl != oldlnkctl)
2974 pci_write_config_word(tp->pdev,
2975 tp->pcie_cap + PCI_EXP_LNKCTL,
2976 newlnkctl);
2977 }
2978
2979 if (current_link_up != netif_carrier_ok(tp->dev)) {
2980 if (current_link_up)
2981 netif_carrier_on(tp->dev);
2982 else
2983 netif_carrier_off(tp->dev);
2984 tg3_link_report(tp);
2985 }
2986
2987 return 0;
2988 }
2989
2990 struct tg3_fiber_aneginfo {
2991 int state;
2992 #define ANEG_STATE_UNKNOWN 0
2993 #define ANEG_STATE_AN_ENABLE 1
2994 #define ANEG_STATE_RESTART_INIT 2
2995 #define ANEG_STATE_RESTART 3
2996 #define ANEG_STATE_DISABLE_LINK_OK 4
2997 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2998 #define ANEG_STATE_ABILITY_DETECT 6
2999 #define ANEG_STATE_ACK_DETECT_INIT 7
3000 #define ANEG_STATE_ACK_DETECT 8
3001 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3002 #define ANEG_STATE_COMPLETE_ACK 10
3003 #define ANEG_STATE_IDLE_DETECT_INIT 11
3004 #define ANEG_STATE_IDLE_DETECT 12
3005 #define ANEG_STATE_LINK_OK 13
3006 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3007 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3008
3009 u32 flags;
3010 #define MR_AN_ENABLE 0x00000001
3011 #define MR_RESTART_AN 0x00000002
3012 #define MR_AN_COMPLETE 0x00000004
3013 #define MR_PAGE_RX 0x00000008
3014 #define MR_NP_LOADED 0x00000010
3015 #define MR_TOGGLE_TX 0x00000020
3016 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3017 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3018 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3019 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3020 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3021 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3022 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3023 #define MR_TOGGLE_RX 0x00002000
3024 #define MR_NP_RX 0x00004000
3025
3026 #define MR_LINK_OK 0x80000000
3027
3028 unsigned long link_time, cur_time;
3029
3030 u32 ability_match_cfg;
3031 int ability_match_count;
3032
3033 char ability_match, idle_match, ack_match;
3034
3035 u32 txconfig, rxconfig;
3036 #define ANEG_CFG_NP 0x00000080
3037 #define ANEG_CFG_ACK 0x00000040
3038 #define ANEG_CFG_RF2 0x00000020
3039 #define ANEG_CFG_RF1 0x00000010
3040 #define ANEG_CFG_PS2 0x00000001
3041 #define ANEG_CFG_PS1 0x00008000
3042 #define ANEG_CFG_HD 0x00004000
3043 #define ANEG_CFG_FD 0x00002000
3044 #define ANEG_CFG_INVAL 0x00001f06
3045
3046 };
3047 #define ANEG_OK 0
3048 #define ANEG_DONE 1
3049 #define ANEG_TIMER_ENAB 2
3050 #define ANEG_FAILED -1
3051
3052 #define ANEG_STATE_SETTLE_TIME 10000
3053
3054 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3055 struct tg3_fiber_aneginfo *ap)
3056 {
3057 u16 flowctrl;
3058 unsigned long delta;
3059 u32 rx_cfg_reg;
3060 int ret;
3061
3062 if (ap->state == ANEG_STATE_UNKNOWN) {
3063 ap->rxconfig = 0;
3064 ap->link_time = 0;
3065 ap->cur_time = 0;
3066 ap->ability_match_cfg = 0;
3067 ap->ability_match_count = 0;
3068 ap->ability_match = 0;
3069 ap->idle_match = 0;
3070 ap->ack_match = 0;
3071 }
3072 ap->cur_time++;
3073
3074 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3075 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3076
3077 if (rx_cfg_reg != ap->ability_match_cfg) {
3078 ap->ability_match_cfg = rx_cfg_reg;
3079 ap->ability_match = 0;
3080 ap->ability_match_count = 0;
3081 } else {
3082 if (++ap->ability_match_count > 1) {
3083 ap->ability_match = 1;
3084 ap->ability_match_cfg = rx_cfg_reg;
3085 }
3086 }
3087 if (rx_cfg_reg & ANEG_CFG_ACK)
3088 ap->ack_match = 1;
3089 else
3090 ap->ack_match = 0;
3091
3092 ap->idle_match = 0;
3093 } else {
3094 ap->idle_match = 1;
3095 ap->ability_match_cfg = 0;
3096 ap->ability_match_count = 0;
3097 ap->ability_match = 0;
3098 ap->ack_match = 0;
3099
3100 rx_cfg_reg = 0;
3101 }
3102
3103 ap->rxconfig = rx_cfg_reg;
3104 ret = ANEG_OK;
3105
3106 switch(ap->state) {
3107 case ANEG_STATE_UNKNOWN:
3108 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3109 ap->state = ANEG_STATE_AN_ENABLE;
3110
3111 /* fallthru */
3112 case ANEG_STATE_AN_ENABLE:
3113 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3114 if (ap->flags & MR_AN_ENABLE) {
3115 ap->link_time = 0;
3116 ap->cur_time = 0;
3117 ap->ability_match_cfg = 0;
3118 ap->ability_match_count = 0;
3119 ap->ability_match = 0;
3120 ap->idle_match = 0;
3121 ap->ack_match = 0;
3122
3123 ap->state = ANEG_STATE_RESTART_INIT;
3124 } else {
3125 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3126 }
3127 break;
3128
3129 case ANEG_STATE_RESTART_INIT:
3130 ap->link_time = ap->cur_time;
3131 ap->flags &= ~(MR_NP_LOADED);
3132 ap->txconfig = 0;
3133 tw32(MAC_TX_AUTO_NEG, 0);
3134 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3135 tw32_f(MAC_MODE, tp->mac_mode);
3136 udelay(40);
3137
3138 ret = ANEG_TIMER_ENAB;
3139 ap->state = ANEG_STATE_RESTART;
3140
3141 /* fallthru */
3142 case ANEG_STATE_RESTART:
3143 delta = ap->cur_time - ap->link_time;
3144 if (delta > ANEG_STATE_SETTLE_TIME) {
3145 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3146 } else {
3147 ret = ANEG_TIMER_ENAB;
3148 }
3149 break;
3150
3151 case ANEG_STATE_DISABLE_LINK_OK:
3152 ret = ANEG_DONE;
3153 break;
3154
3155 case ANEG_STATE_ABILITY_DETECT_INIT:
3156 ap->flags &= ~(MR_TOGGLE_TX);
3157 ap->txconfig = ANEG_CFG_FD;
3158 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3159 if (flowctrl & ADVERTISE_1000XPAUSE)
3160 ap->txconfig |= ANEG_CFG_PS1;
3161 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3162 ap->txconfig |= ANEG_CFG_PS2;
3163 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3164 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3165 tw32_f(MAC_MODE, tp->mac_mode);
3166 udelay(40);
3167
3168 ap->state = ANEG_STATE_ABILITY_DETECT;
3169 break;
3170
3171 case ANEG_STATE_ABILITY_DETECT:
3172 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3173 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3174 }
3175 break;
3176
3177 case ANEG_STATE_ACK_DETECT_INIT:
3178 ap->txconfig |= ANEG_CFG_ACK;
3179 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3180 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3181 tw32_f(MAC_MODE, tp->mac_mode);
3182 udelay(40);
3183
3184 ap->state = ANEG_STATE_ACK_DETECT;
3185
3186 /* fallthru */
3187 case ANEG_STATE_ACK_DETECT:
3188 if (ap->ack_match != 0) {
3189 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3190 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3191 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3192 } else {
3193 ap->state = ANEG_STATE_AN_ENABLE;
3194 }
3195 } else if (ap->ability_match != 0 &&
3196 ap->rxconfig == 0) {
3197 ap->state = ANEG_STATE_AN_ENABLE;
3198 }
3199 break;
3200
3201 case ANEG_STATE_COMPLETE_ACK_INIT:
3202 if (ap->rxconfig & ANEG_CFG_INVAL) {
3203 ret = ANEG_FAILED;
3204 break;
3205 }
3206 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3207 MR_LP_ADV_HALF_DUPLEX |
3208 MR_LP_ADV_SYM_PAUSE |
3209 MR_LP_ADV_ASYM_PAUSE |
3210 MR_LP_ADV_REMOTE_FAULT1 |
3211 MR_LP_ADV_REMOTE_FAULT2 |
3212 MR_LP_ADV_NEXT_PAGE |
3213 MR_TOGGLE_RX |
3214 MR_NP_RX);
3215 if (ap->rxconfig & ANEG_CFG_FD)
3216 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3217 if (ap->rxconfig & ANEG_CFG_HD)
3218 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3219 if (ap->rxconfig & ANEG_CFG_PS1)
3220 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3221 if (ap->rxconfig & ANEG_CFG_PS2)
3222 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3223 if (ap->rxconfig & ANEG_CFG_RF1)
3224 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3225 if (ap->rxconfig & ANEG_CFG_RF2)
3226 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3227 if (ap->rxconfig & ANEG_CFG_NP)
3228 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3229
3230 ap->link_time = ap->cur_time;
3231
3232 ap->flags ^= (MR_TOGGLE_TX);
3233 if (ap->rxconfig & 0x0008)
3234 ap->flags |= MR_TOGGLE_RX;
3235 if (ap->rxconfig & ANEG_CFG_NP)
3236 ap->flags |= MR_NP_RX;
3237 ap->flags |= MR_PAGE_RX;
3238
3239 ap->state = ANEG_STATE_COMPLETE_ACK;
3240 ret = ANEG_TIMER_ENAB;
3241 break;
3242
3243 case ANEG_STATE_COMPLETE_ACK:
3244 if (ap->ability_match != 0 &&
3245 ap->rxconfig == 0) {
3246 ap->state = ANEG_STATE_AN_ENABLE;
3247 break;
3248 }
3249 delta = ap->cur_time - ap->link_time;
3250 if (delta > ANEG_STATE_SETTLE_TIME) {
3251 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3252 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3253 } else {
3254 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3255 !(ap->flags & MR_NP_RX)) {
3256 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3257 } else {
3258 ret = ANEG_FAILED;
3259 }
3260 }
3261 }
3262 break;
3263
3264 case ANEG_STATE_IDLE_DETECT_INIT:
3265 ap->link_time = ap->cur_time;
3266 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3267 tw32_f(MAC_MODE, tp->mac_mode);
3268 udelay(40);
3269
3270 ap->state = ANEG_STATE_IDLE_DETECT;
3271 ret = ANEG_TIMER_ENAB;
3272 break;
3273
3274 case ANEG_STATE_IDLE_DETECT:
3275 if (ap->ability_match != 0 &&
3276 ap->rxconfig == 0) {
3277 ap->state = ANEG_STATE_AN_ENABLE;
3278 break;
3279 }
3280 delta = ap->cur_time - ap->link_time;
3281 if (delta > ANEG_STATE_SETTLE_TIME) {
3282 /* XXX another gem from the Broadcom driver :( */
3283 ap->state = ANEG_STATE_LINK_OK;
3284 }
3285 break;
3286
3287 case ANEG_STATE_LINK_OK:
3288 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3289 ret = ANEG_DONE;
3290 break;
3291
3292 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3293 /* ??? unimplemented */
3294 break;
3295
3296 case ANEG_STATE_NEXT_PAGE_WAIT:
3297 /* ??? unimplemented */
3298 break;
3299
3300 default:
3301 ret = ANEG_FAILED;
3302 break;
3303 }
3304
3305 return ret;
3306 }
3307
3308 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3309 {
3310 int res = 0;
3311 struct tg3_fiber_aneginfo aninfo;
3312 int status = ANEG_FAILED;
3313 unsigned int tick;
3314 u32 tmp;
3315
3316 tw32_f(MAC_TX_AUTO_NEG, 0);
3317
3318 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3319 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3320 udelay(40);
3321
3322 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3323 udelay(40);
3324
3325 memset(&aninfo, 0, sizeof(aninfo));
3326 aninfo.flags |= MR_AN_ENABLE;
3327 aninfo.state = ANEG_STATE_UNKNOWN;
3328 aninfo.cur_time = 0;
3329 tick = 0;
3330 while (++tick < 195000) {
3331 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3332 if (status == ANEG_DONE || status == ANEG_FAILED)
3333 break;
3334
3335 udelay(1);
3336 }
3337
3338 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3339 tw32_f(MAC_MODE, tp->mac_mode);
3340 udelay(40);
3341
3342 *txflags = aninfo.txconfig;
3343 *rxflags = aninfo.flags;
3344
3345 if (status == ANEG_DONE &&
3346 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3347 MR_LP_ADV_FULL_DUPLEX)))
3348 res = 1;
3349
3350 return res;
3351 }
3352
3353 static void tg3_init_bcm8002(struct tg3 *tp)
3354 {
3355 u32 mac_status = tr32(MAC_STATUS);
3356 int i;
3357
3358 /* Reset when initting first time or we have a link. */
3359 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3360 !(mac_status & MAC_STATUS_PCS_SYNCED))
3361 return;
3362
3363 /* Set PLL lock range. */
3364 tg3_writephy(tp, 0x16, 0x8007);
3365
3366 /* SW reset */
3367 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3368
3369 /* Wait for reset to complete. */
3370 /* XXX schedule_timeout() ... */
3371 for (i = 0; i < 500; i++)
3372 udelay(10);
3373
3374 /* Config mode; select PMA/Ch 1 regs. */
3375 tg3_writephy(tp, 0x10, 0x8411);
3376
3377 /* Enable auto-lock and comdet, select txclk for tx. */
3378 tg3_writephy(tp, 0x11, 0x0a10);
3379
3380 tg3_writephy(tp, 0x18, 0x00a0);
3381 tg3_writephy(tp, 0x16, 0x41ff);
3382
3383 /* Assert and deassert POR. */
3384 tg3_writephy(tp, 0x13, 0x0400);
3385 udelay(40);
3386 tg3_writephy(tp, 0x13, 0x0000);
3387
3388 tg3_writephy(tp, 0x11, 0x0a50);
3389 udelay(40);
3390 tg3_writephy(tp, 0x11, 0x0a10);
3391
3392 /* Wait for signal to stabilize */
3393 /* XXX schedule_timeout() ... */
3394 for (i = 0; i < 15000; i++)
3395 udelay(10);
3396
3397 /* Deselect the channel register so we can read the PHYID
3398 * later.
3399 */
3400 tg3_writephy(tp, 0x10, 0x8011);
3401 }
3402
3403 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3404 {
3405 u16 flowctrl;
3406 u32 sg_dig_ctrl, sg_dig_status;
3407 u32 serdes_cfg, expected_sg_dig_ctrl;
3408 int workaround, port_a;
3409 int current_link_up;
3410
3411 serdes_cfg = 0;
3412 expected_sg_dig_ctrl = 0;
3413 workaround = 0;
3414 port_a = 1;
3415 current_link_up = 0;
3416
3417 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3418 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3419 workaround = 1;
3420 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3421 port_a = 0;
3422
3423 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3424 /* preserve bits 20-23 for voltage regulator */
3425 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3426 }
3427
3428 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3429
3430 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3431 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3432 if (workaround) {
3433 u32 val = serdes_cfg;
3434
3435 if (port_a)
3436 val |= 0xc010000;
3437 else
3438 val |= 0x4010000;
3439 tw32_f(MAC_SERDES_CFG, val);
3440 }
3441
3442 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3443 }
3444 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3445 tg3_setup_flow_control(tp, 0, 0);
3446 current_link_up = 1;
3447 }
3448 goto out;
3449 }
3450
3451 /* Want auto-negotiation. */
3452 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3453
3454 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3455 if (flowctrl & ADVERTISE_1000XPAUSE)
3456 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3457 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3458 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3459
3460 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3461 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3462 tp->serdes_counter &&
3463 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3464 MAC_STATUS_RCVD_CFG)) ==
3465 MAC_STATUS_PCS_SYNCED)) {
3466 tp->serdes_counter--;
3467 current_link_up = 1;
3468 goto out;
3469 }
3470 restart_autoneg:
3471 if (workaround)
3472 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3473 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3474 udelay(5);
3475 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3476
3477 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3478 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3479 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3480 MAC_STATUS_SIGNAL_DET)) {
3481 sg_dig_status = tr32(SG_DIG_STATUS);
3482 mac_status = tr32(MAC_STATUS);
3483
3484 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3485 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3486 u32 local_adv = 0, remote_adv = 0;
3487
3488 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3489 local_adv |= ADVERTISE_1000XPAUSE;
3490 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3491 local_adv |= ADVERTISE_1000XPSE_ASYM;
3492
3493 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3494 remote_adv |= LPA_1000XPAUSE;
3495 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3496 remote_adv |= LPA_1000XPAUSE_ASYM;
3497
3498 tg3_setup_flow_control(tp, local_adv, remote_adv);
3499 current_link_up = 1;
3500 tp->serdes_counter = 0;
3501 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3502 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3503 if (tp->serdes_counter)
3504 tp->serdes_counter--;
3505 else {
3506 if (workaround) {
3507 u32 val = serdes_cfg;
3508
3509 if (port_a)
3510 val |= 0xc010000;
3511 else
3512 val |= 0x4010000;
3513
3514 tw32_f(MAC_SERDES_CFG, val);
3515 }
3516
3517 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3518 udelay(40);
3519
3520 /* Link parallel detection - link is up */
3521 /* only if we have PCS_SYNC and not */
3522 /* receiving config code words */
3523 mac_status = tr32(MAC_STATUS);
3524 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3525 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3526 tg3_setup_flow_control(tp, 0, 0);
3527 current_link_up = 1;
3528 tp->tg3_flags2 |=
3529 TG3_FLG2_PARALLEL_DETECT;
3530 tp->serdes_counter =
3531 SERDES_PARALLEL_DET_TIMEOUT;
3532 } else
3533 goto restart_autoneg;
3534 }
3535 }
3536 } else {
3537 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3538 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3539 }
3540
3541 out:
3542 return current_link_up;
3543 }
3544
3545 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3546 {
3547 int current_link_up = 0;
3548
3549 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3550 goto out;
3551
3552 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3553 u32 txflags, rxflags;
3554 int i;
3555
3556 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3557 u32 local_adv = 0, remote_adv = 0;
3558
3559 if (txflags & ANEG_CFG_PS1)
3560 local_adv |= ADVERTISE_1000XPAUSE;
3561 if (txflags & ANEG_CFG_PS2)
3562 local_adv |= ADVERTISE_1000XPSE_ASYM;
3563
3564 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3565 remote_adv |= LPA_1000XPAUSE;
3566 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3567 remote_adv |= LPA_1000XPAUSE_ASYM;
3568
3569 tg3_setup_flow_control(tp, local_adv, remote_adv);
3570
3571 current_link_up = 1;
3572 }
3573 for (i = 0; i < 30; i++) {
3574 udelay(20);
3575 tw32_f(MAC_STATUS,
3576 (MAC_STATUS_SYNC_CHANGED |
3577 MAC_STATUS_CFG_CHANGED));
3578 udelay(40);
3579 if ((tr32(MAC_STATUS) &
3580 (MAC_STATUS_SYNC_CHANGED |
3581 MAC_STATUS_CFG_CHANGED)) == 0)
3582 break;
3583 }
3584
3585 mac_status = tr32(MAC_STATUS);
3586 if (current_link_up == 0 &&
3587 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3588 !(mac_status & MAC_STATUS_RCVD_CFG))
3589 current_link_up = 1;
3590 } else {
3591 tg3_setup_flow_control(tp, 0, 0);
3592
3593 /* Forcing 1000FD link up. */
3594 current_link_up = 1;
3595
3596 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3597 udelay(40);
3598
3599 tw32_f(MAC_MODE, tp->mac_mode);
3600 udelay(40);
3601 }
3602
3603 out:
3604 return current_link_up;
3605 }
3606
3607 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3608 {
3609 u32 orig_pause_cfg;
3610 u16 orig_active_speed;
3611 u8 orig_active_duplex;
3612 u32 mac_status;
3613 int current_link_up;
3614 int i;
3615
3616 orig_pause_cfg = tp->link_config.active_flowctrl;
3617 orig_active_speed = tp->link_config.active_speed;
3618 orig_active_duplex = tp->link_config.active_duplex;
3619
3620 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3621 netif_carrier_ok(tp->dev) &&
3622 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3623 mac_status = tr32(MAC_STATUS);
3624 mac_status &= (MAC_STATUS_PCS_SYNCED |
3625 MAC_STATUS_SIGNAL_DET |
3626 MAC_STATUS_CFG_CHANGED |
3627 MAC_STATUS_RCVD_CFG);
3628 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3629 MAC_STATUS_SIGNAL_DET)) {
3630 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3631 MAC_STATUS_CFG_CHANGED));
3632 return 0;
3633 }
3634 }
3635
3636 tw32_f(MAC_TX_AUTO_NEG, 0);
3637
3638 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3639 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3640 tw32_f(MAC_MODE, tp->mac_mode);
3641 udelay(40);
3642
3643 if (tp->phy_id == PHY_ID_BCM8002)
3644 tg3_init_bcm8002(tp);
3645
3646 /* Enable link change event even when serdes polling. */
3647 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3648 udelay(40);
3649
3650 current_link_up = 0;
3651 mac_status = tr32(MAC_STATUS);
3652
3653 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3654 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3655 else
3656 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3657
3658 tp->hw_status->status =
3659 (SD_STATUS_UPDATED |
3660 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3661
3662 for (i = 0; i < 100; i++) {
3663 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3664 MAC_STATUS_CFG_CHANGED));
3665 udelay(5);
3666 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3667 MAC_STATUS_CFG_CHANGED |
3668 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3669 break;
3670 }
3671
3672 mac_status = tr32(MAC_STATUS);
3673 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3674 current_link_up = 0;
3675 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3676 tp->serdes_counter == 0) {
3677 tw32_f(MAC_MODE, (tp->mac_mode |
3678 MAC_MODE_SEND_CONFIGS));
3679 udelay(1);
3680 tw32_f(MAC_MODE, tp->mac_mode);
3681 }
3682 }
3683
3684 if (current_link_up == 1) {
3685 tp->link_config.active_speed = SPEED_1000;
3686 tp->link_config.active_duplex = DUPLEX_FULL;
3687 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3688 LED_CTRL_LNKLED_OVERRIDE |
3689 LED_CTRL_1000MBPS_ON));
3690 } else {
3691 tp->link_config.active_speed = SPEED_INVALID;
3692 tp->link_config.active_duplex = DUPLEX_INVALID;
3693 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3694 LED_CTRL_LNKLED_OVERRIDE |
3695 LED_CTRL_TRAFFIC_OVERRIDE));
3696 }
3697
3698 if (current_link_up != netif_carrier_ok(tp->dev)) {
3699 if (current_link_up)
3700 netif_carrier_on(tp->dev);
3701 else
3702 netif_carrier_off(tp->dev);
3703 tg3_link_report(tp);
3704 } else {
3705 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3706 if (orig_pause_cfg != now_pause_cfg ||
3707 orig_active_speed != tp->link_config.active_speed ||
3708 orig_active_duplex != tp->link_config.active_duplex)
3709 tg3_link_report(tp);
3710 }
3711
3712 return 0;
3713 }
3714
3715 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3716 {
3717 int current_link_up, err = 0;
3718 u32 bmsr, bmcr;
3719 u16 current_speed;
3720 u8 current_duplex;
3721 u32 local_adv, remote_adv;
3722
3723 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3724 tw32_f(MAC_MODE, tp->mac_mode);
3725 udelay(40);
3726
3727 tw32(MAC_EVENT, 0);
3728
3729 tw32_f(MAC_STATUS,
3730 (MAC_STATUS_SYNC_CHANGED |
3731 MAC_STATUS_CFG_CHANGED |
3732 MAC_STATUS_MI_COMPLETION |
3733 MAC_STATUS_LNKSTATE_CHANGED));
3734 udelay(40);
3735
3736 if (force_reset)
3737 tg3_phy_reset(tp);
3738
3739 current_link_up = 0;
3740 current_speed = SPEED_INVALID;
3741 current_duplex = DUPLEX_INVALID;
3742
3743 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3744 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3745 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3746 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3747 bmsr |= BMSR_LSTATUS;
3748 else
3749 bmsr &= ~BMSR_LSTATUS;
3750 }
3751
3752 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3753
3754 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3755 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3756 /* do nothing, just check for link up at the end */
3757 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3758 u32 adv, new_adv;
3759
3760 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3761 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3762 ADVERTISE_1000XPAUSE |
3763 ADVERTISE_1000XPSE_ASYM |
3764 ADVERTISE_SLCT);
3765
3766 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3767
3768 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3769 new_adv |= ADVERTISE_1000XHALF;
3770 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3771 new_adv |= ADVERTISE_1000XFULL;
3772
3773 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3774 tg3_writephy(tp, MII_ADVERTISE, new_adv);
3775 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3776 tg3_writephy(tp, MII_BMCR, bmcr);
3777
3778 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3779 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3780 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3781
3782 return err;
3783 }
3784 } else {
3785 u32 new_bmcr;
3786
3787 bmcr &= ~BMCR_SPEED1000;
3788 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3789
3790 if (tp->link_config.duplex == DUPLEX_FULL)
3791 new_bmcr |= BMCR_FULLDPLX;
3792
3793 if (new_bmcr != bmcr) {
3794 /* BMCR_SPEED1000 is a reserved bit that needs
3795 * to be set on write.
3796 */
3797 new_bmcr |= BMCR_SPEED1000;
3798
3799 /* Force a linkdown */
3800 if (netif_carrier_ok(tp->dev)) {
3801 u32 adv;
3802
3803 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3804 adv &= ~(ADVERTISE_1000XFULL |
3805 ADVERTISE_1000XHALF |
3806 ADVERTISE_SLCT);
3807 tg3_writephy(tp, MII_ADVERTISE, adv);
3808 tg3_writephy(tp, MII_BMCR, bmcr |
3809 BMCR_ANRESTART |
3810 BMCR_ANENABLE);
3811 udelay(10);
3812 netif_carrier_off(tp->dev);
3813 }
3814 tg3_writephy(tp, MII_BMCR, new_bmcr);
3815 bmcr = new_bmcr;
3816 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3817 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3818 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3819 ASIC_REV_5714) {
3820 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3821 bmsr |= BMSR_LSTATUS;
3822 else
3823 bmsr &= ~BMSR_LSTATUS;
3824 }
3825 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3826 }
3827 }
3828
3829 if (bmsr & BMSR_LSTATUS) {
3830 current_speed = SPEED_1000;
3831 current_link_up = 1;
3832 if (bmcr & BMCR_FULLDPLX)
3833 current_duplex = DUPLEX_FULL;
3834 else
3835 current_duplex = DUPLEX_HALF;
3836
3837 local_adv = 0;
3838 remote_adv = 0;
3839
3840 if (bmcr & BMCR_ANENABLE) {
3841 u32 common;
3842
3843 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3844 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3845 common = local_adv & remote_adv;
3846 if (common & (ADVERTISE_1000XHALF |
3847 ADVERTISE_1000XFULL)) {
3848 if (common & ADVERTISE_1000XFULL)
3849 current_duplex = DUPLEX_FULL;
3850 else
3851 current_duplex = DUPLEX_HALF;
3852 }
3853 else
3854 current_link_up = 0;
3855 }
3856 }
3857
3858 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3859 tg3_setup_flow_control(tp, local_adv, remote_adv);
3860
3861 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3862 if (tp->link_config.active_duplex == DUPLEX_HALF)
3863 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3864
3865 tw32_f(MAC_MODE, tp->mac_mode);
3866 udelay(40);
3867
3868 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3869
3870 tp->link_config.active_speed = current_speed;
3871 tp->link_config.active_duplex = current_duplex;
3872
3873 if (current_link_up != netif_carrier_ok(tp->dev)) {
3874 if (current_link_up)
3875 netif_carrier_on(tp->dev);
3876 else {
3877 netif_carrier_off(tp->dev);
3878 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3879 }
3880 tg3_link_report(tp);
3881 }
3882 return err;
3883 }
3884
3885 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3886 {
3887 if (tp->serdes_counter) {
3888 /* Give autoneg time to complete. */
3889 tp->serdes_counter--;
3890 return;
3891 }
3892 if (!netif_carrier_ok(tp->dev) &&
3893 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3894 u32 bmcr;
3895
3896 tg3_readphy(tp, MII_BMCR, &bmcr);
3897 if (bmcr & BMCR_ANENABLE) {
3898 u32 phy1, phy2;
3899
3900 /* Select shadow register 0x1f */
3901 tg3_writephy(tp, 0x1c, 0x7c00);
3902 tg3_readphy(tp, 0x1c, &phy1);
3903
3904 /* Select expansion interrupt status register */
3905 tg3_writephy(tp, 0x17, 0x0f01);
3906 tg3_readphy(tp, 0x15, &phy2);
3907 tg3_readphy(tp, 0x15, &phy2);
3908
3909 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3910 /* We have signal detect and not receiving
3911 * config code words, link is up by parallel
3912 * detection.
3913 */
3914
3915 bmcr &= ~BMCR_ANENABLE;
3916 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3917 tg3_writephy(tp, MII_BMCR, bmcr);
3918 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3919 }
3920 }
3921 }
3922 else if (netif_carrier_ok(tp->dev) &&
3923 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3924 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3925 u32 phy2;
3926
3927 /* Select expansion interrupt status register */
3928 tg3_writephy(tp, 0x17, 0x0f01);
3929 tg3_readphy(tp, 0x15, &phy2);
3930 if (phy2 & 0x20) {
3931 u32 bmcr;
3932
3933 /* Config code words received, turn on autoneg. */
3934 tg3_readphy(tp, MII_BMCR, &bmcr);
3935 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3936
3937 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3938
3939 }
3940 }
3941 }
3942
3943 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3944 {
3945 int err;
3946
3947 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3948 err = tg3_setup_fiber_phy(tp, force_reset);
3949 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3950 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3951 } else {
3952 err = tg3_setup_copper_phy(tp, force_reset);
3953 }
3954
3955 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
3956 u32 val, scale;
3957
3958 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3959 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3960 scale = 65;
3961 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3962 scale = 6;
3963 else
3964 scale = 12;
3965
3966 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3967 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3968 tw32(GRC_MISC_CFG, val);
3969 }
3970
3971 if (tp->link_config.active_speed == SPEED_1000 &&
3972 tp->link_config.active_duplex == DUPLEX_HALF)
3973 tw32(MAC_TX_LENGTHS,
3974 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3975 (6 << TX_LENGTHS_IPG_SHIFT) |
3976 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3977 else
3978 tw32(MAC_TX_LENGTHS,
3979 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3980 (6 << TX_LENGTHS_IPG_SHIFT) |
3981 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3982
3983 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3984 if (netif_carrier_ok(tp->dev)) {
3985 tw32(HOSTCC_STAT_COAL_TICKS,
3986 tp->coal.stats_block_coalesce_usecs);
3987 } else {
3988 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3989 }
3990 }
3991
3992 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3993 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3994 if (!netif_carrier_ok(tp->dev))
3995 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3996 tp->pwrmgmt_thresh;
3997 else
3998 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3999 tw32(PCIE_PWR_MGMT_THRESH, val);
4000 }
4001
4002 return err;
4003 }
4004
4005 /* This is called whenever we suspect that the system chipset is re-
4006 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4007 * is bogus tx completions. We try to recover by setting the
4008 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4009 * in the workqueue.
4010 */
4011 static void tg3_tx_recover(struct tg3 *tp)
4012 {
4013 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4014 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4015
4016 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4017 "mapped I/O cycles to the network device, attempting to "
4018 "recover. Please report the problem to the driver maintainer "
4019 "and include system chipset information.\n", tp->dev->name);
4020
4021 spin_lock(&tp->lock);
4022 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4023 spin_unlock(&tp->lock);
4024 }
4025
4026 static inline u32 tg3_tx_avail(struct tg3 *tp)
4027 {
4028 smp_mb();
4029 return (tp->tx_pending -
4030 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
4031 }
4032
4033 /* Tigon3 never reports partial packet sends. So we do not
4034 * need special logic to handle SKBs that have not had all
4035 * of their frags sent yet, like SunGEM does.
4036 */
4037 static void tg3_tx(struct tg3 *tp)
4038 {
4039 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
4040 u32 sw_idx = tp->tx_cons;
4041
4042 while (sw_idx != hw_idx) {
4043 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
4044 struct sk_buff *skb = ri->skb;
4045 int i, tx_bug = 0;
4046
4047 if (unlikely(skb == NULL)) {
4048 tg3_tx_recover(tp);
4049 return;
4050 }
4051
4052 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4053
4054 ri->skb = NULL;
4055
4056 sw_idx = NEXT_TX(sw_idx);
4057
4058 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4059 ri = &tp->tx_buffers[sw_idx];
4060 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4061 tx_bug = 1;
4062 sw_idx = NEXT_TX(sw_idx);
4063 }
4064
4065 dev_kfree_skb(skb);
4066
4067 if (unlikely(tx_bug)) {
4068 tg3_tx_recover(tp);
4069 return;
4070 }
4071 }
4072
4073 tp->tx_cons = sw_idx;
4074
4075 /* Need to make the tx_cons update visible to tg3_start_xmit()
4076 * before checking for netif_queue_stopped(). Without the
4077 * memory barrier, there is a small possibility that tg3_start_xmit()
4078 * will miss it and cause the queue to be stopped forever.
4079 */
4080 smp_mb();
4081
4082 if (unlikely(netif_queue_stopped(tp->dev) &&
4083 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
4084 netif_tx_lock(tp->dev);
4085 if (netif_queue_stopped(tp->dev) &&
4086 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
4087 netif_wake_queue(tp->dev);
4088 netif_tx_unlock(tp->dev);
4089 }
4090 }
4091
4092 /* Returns size of skb allocated or < 0 on error.
4093 *
4094 * We only need to fill in the address because the other members
4095 * of the RX descriptor are invariant, see tg3_init_rings.
4096 *
4097 * Note the purposeful assymetry of cpu vs. chip accesses. For
4098 * posting buffers we only dirty the first cache line of the RX
4099 * descriptor (containing the address). Whereas for the RX status
4100 * buffers the cpu only reads the last cacheline of the RX descriptor
4101 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4102 */
4103 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
4104 int src_idx, u32 dest_idx_unmasked)
4105 {
4106 struct tg3_rx_buffer_desc *desc;
4107 struct ring_info *map, *src_map;
4108 struct sk_buff *skb;
4109 dma_addr_t mapping;
4110 int skb_size, dest_idx;
4111
4112 src_map = NULL;
4113 switch (opaque_key) {
4114 case RXD_OPAQUE_RING_STD:
4115 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4116 desc = &tp->rx_std[dest_idx];
4117 map = &tp->rx_std_buffers[dest_idx];
4118 if (src_idx >= 0)
4119 src_map = &tp->rx_std_buffers[src_idx];
4120 skb_size = tp->rx_pkt_buf_sz;
4121 break;
4122
4123 case RXD_OPAQUE_RING_JUMBO:
4124 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4125 desc = &tp->rx_jumbo[dest_idx];
4126 map = &tp->rx_jumbo_buffers[dest_idx];
4127 if (src_idx >= 0)
4128 src_map = &tp->rx_jumbo_buffers[src_idx];
4129 skb_size = RX_JUMBO_PKT_BUF_SZ;
4130 break;
4131
4132 default:
4133 return -EINVAL;
4134 }
4135
4136 /* Do not overwrite any of the map or rp information
4137 * until we are sure we can commit to a new buffer.
4138 *
4139 * Callers depend upon this behavior and assume that
4140 * we leave everything unchanged if we fail.
4141 */
4142 skb = netdev_alloc_skb(tp->dev, skb_size);
4143 if (skb == NULL)
4144 return -ENOMEM;
4145
4146 skb_reserve(skb, tp->rx_offset);
4147
4148 mapping = pci_map_single(tp->pdev, skb->data,
4149 skb_size - tp->rx_offset,
4150 PCI_DMA_FROMDEVICE);
4151
4152 map->skb = skb;
4153 pci_unmap_addr_set(map, mapping, mapping);
4154
4155 if (src_map != NULL)
4156 src_map->skb = NULL;
4157
4158 desc->addr_hi = ((u64)mapping >> 32);
4159 desc->addr_lo = ((u64)mapping & 0xffffffff);
4160
4161 return skb_size;
4162 }
4163
4164 /* We only need to move over in the address because the other
4165 * members of the RX descriptor are invariant. See notes above
4166 * tg3_alloc_rx_skb for full details.
4167 */
4168 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
4169 int src_idx, u32 dest_idx_unmasked)
4170 {
4171 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4172 struct ring_info *src_map, *dest_map;
4173 int dest_idx;
4174
4175 switch (opaque_key) {
4176 case RXD_OPAQUE_RING_STD:
4177 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4178 dest_desc = &tp->rx_std[dest_idx];
4179 dest_map = &tp->rx_std_buffers[dest_idx];
4180 src_desc = &tp->rx_std[src_idx];
4181 src_map = &tp->rx_std_buffers[src_idx];
4182 break;
4183
4184 case RXD_OPAQUE_RING_JUMBO:
4185 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4186 dest_desc = &tp->rx_jumbo[dest_idx];
4187 dest_map = &tp->rx_jumbo_buffers[dest_idx];
4188 src_desc = &tp->rx_jumbo[src_idx];
4189 src_map = &tp->rx_jumbo_buffers[src_idx];
4190 break;
4191
4192 default:
4193 return;
4194 }
4195
4196 dest_map->skb = src_map->skb;
4197 pci_unmap_addr_set(dest_map, mapping,
4198 pci_unmap_addr(src_map, mapping));
4199 dest_desc->addr_hi = src_desc->addr_hi;
4200 dest_desc->addr_lo = src_desc->addr_lo;
4201
4202 src_map->skb = NULL;
4203 }
4204
4205 #if TG3_VLAN_TAG_USED
4206 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4207 {
4208 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4209 }
4210 #endif
4211
4212 /* The RX ring scheme is composed of multiple rings which post fresh
4213 * buffers to the chip, and one special ring the chip uses to report
4214 * status back to the host.
4215 *
4216 * The special ring reports the status of received packets to the
4217 * host. The chip does not write into the original descriptor the
4218 * RX buffer was obtained from. The chip simply takes the original
4219 * descriptor as provided by the host, updates the status and length
4220 * field, then writes this into the next status ring entry.
4221 *
4222 * Each ring the host uses to post buffers to the chip is described
4223 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4224 * it is first placed into the on-chip ram. When the packet's length
4225 * is known, it walks down the TG3_BDINFO entries to select the ring.
4226 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4227 * which is within the range of the new packet's length is chosen.
4228 *
4229 * The "separate ring for rx status" scheme may sound queer, but it makes
4230 * sense from a cache coherency perspective. If only the host writes
4231 * to the buffer post rings, and only the chip writes to the rx status
4232 * rings, then cache lines never move beyond shared-modified state.
4233 * If both the host and chip were to write into the same ring, cache line
4234 * eviction could occur since both entities want it in an exclusive state.
4235 */
4236 static int tg3_rx(struct tg3 *tp, int budget)
4237 {
4238 u32 work_mask, rx_std_posted = 0;
4239 u32 sw_idx = tp->rx_rcb_ptr;
4240 u16 hw_idx;
4241 int received;
4242
4243 hw_idx = tp->hw_status->idx[0].rx_producer;
4244 /*
4245 * We need to order the read of hw_idx and the read of
4246 * the opaque cookie.
4247 */
4248 rmb();
4249 work_mask = 0;
4250 received = 0;
4251 while (sw_idx != hw_idx && budget > 0) {
4252 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4253 unsigned int len;
4254 struct sk_buff *skb;
4255 dma_addr_t dma_addr;
4256 u32 opaque_key, desc_idx, *post_ptr;
4257
4258 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4259 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4260 if (opaque_key == RXD_OPAQUE_RING_STD) {
4261 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4262 mapping);
4263 skb = tp->rx_std_buffers[desc_idx].skb;
4264 post_ptr = &tp->rx_std_ptr;
4265 rx_std_posted++;
4266 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4267 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4268 mapping);
4269 skb = tp->rx_jumbo_buffers[desc_idx].skb;
4270 post_ptr = &tp->rx_jumbo_ptr;
4271 }
4272 else {
4273 goto next_pkt_nopost;
4274 }
4275
4276 work_mask |= opaque_key;
4277
4278 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4279 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4280 drop_it:
4281 tg3_recycle_rx(tp, opaque_key,
4282 desc_idx, *post_ptr);
4283 drop_it_no_recycle:
4284 /* Other statistics kept track of by card. */
4285 tp->net_stats.rx_dropped++;
4286 goto next_pkt;
4287 }
4288
4289 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4290 ETH_FCS_LEN;
4291
4292 if (len > RX_COPY_THRESHOLD
4293 && tp->rx_offset == NET_IP_ALIGN
4294 /* rx_offset will likely not equal NET_IP_ALIGN
4295 * if this is a 5701 card running in PCI-X mode
4296 * [see tg3_get_invariants()]
4297 */
4298 ) {
4299 int skb_size;
4300
4301 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4302 desc_idx, *post_ptr);
4303 if (skb_size < 0)
4304 goto drop_it;
4305
4306 pci_unmap_single(tp->pdev, dma_addr,
4307 skb_size - tp->rx_offset,
4308 PCI_DMA_FROMDEVICE);
4309
4310 skb_put(skb, len);
4311 } else {
4312 struct sk_buff *copy_skb;
4313
4314 tg3_recycle_rx(tp, opaque_key,
4315 desc_idx, *post_ptr);
4316
4317 copy_skb = netdev_alloc_skb(tp->dev,
4318 len + TG3_RAW_IP_ALIGN);
4319 if (copy_skb == NULL)
4320 goto drop_it_no_recycle;
4321
4322 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4323 skb_put(copy_skb, len);
4324 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4325 skb_copy_from_linear_data(skb, copy_skb->data, len);
4326 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4327
4328 /* We'll reuse the original ring buffer. */
4329 skb = copy_skb;
4330 }
4331
4332 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4333 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4334 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4335 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4336 skb->ip_summed = CHECKSUM_UNNECESSARY;
4337 else
4338 skb->ip_summed = CHECKSUM_NONE;
4339
4340 skb->protocol = eth_type_trans(skb, tp->dev);
4341 #if TG3_VLAN_TAG_USED
4342 if (tp->vlgrp != NULL &&
4343 desc->type_flags & RXD_FLAG_VLAN) {
4344 tg3_vlan_rx(tp, skb,
4345 desc->err_vlan & RXD_VLAN_MASK);
4346 } else
4347 #endif
4348 netif_receive_skb(skb);
4349
4350 received++;
4351 budget--;
4352
4353 next_pkt:
4354 (*post_ptr)++;
4355
4356 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4357 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4358
4359 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4360 TG3_64BIT_REG_LOW, idx);
4361 work_mask &= ~RXD_OPAQUE_RING_STD;
4362 rx_std_posted = 0;
4363 }
4364 next_pkt_nopost:
4365 sw_idx++;
4366 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4367
4368 /* Refresh hw_idx to see if there is new work */
4369 if (sw_idx == hw_idx) {
4370 hw_idx = tp->hw_status->idx[0].rx_producer;
4371 rmb();
4372 }
4373 }
4374
4375 /* ACK the status ring. */
4376 tp->rx_rcb_ptr = sw_idx;
4377 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4378
4379 /* Refill RX ring(s). */
4380 if (work_mask & RXD_OPAQUE_RING_STD) {
4381 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4382 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4383 sw_idx);
4384 }
4385 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4386 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4387 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4388 sw_idx);
4389 }
4390 mmiowb();
4391
4392 return received;
4393 }
4394
4395 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4396 {
4397 struct tg3_hw_status *sblk = tp->hw_status;
4398
4399 /* handle link change and other phy events */
4400 if (!(tp->tg3_flags &
4401 (TG3_FLAG_USE_LINKCHG_REG |
4402 TG3_FLAG_POLL_SERDES))) {
4403 if (sblk->status & SD_STATUS_LINK_CHG) {
4404 sblk->status = SD_STATUS_UPDATED |
4405 (sblk->status & ~SD_STATUS_LINK_CHG);
4406 spin_lock(&tp->lock);
4407 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4408 tw32_f(MAC_STATUS,
4409 (MAC_STATUS_SYNC_CHANGED |
4410 MAC_STATUS_CFG_CHANGED |
4411 MAC_STATUS_MI_COMPLETION |
4412 MAC_STATUS_LNKSTATE_CHANGED));
4413 udelay(40);
4414 } else
4415 tg3_setup_phy(tp, 0);
4416 spin_unlock(&tp->lock);
4417 }
4418 }
4419
4420 /* run TX completion thread */
4421 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4422 tg3_tx(tp);
4423 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4424 return work_done;
4425 }
4426
4427 /* run RX thread, within the bounds set by NAPI.
4428 * All RX "locking" is done by ensuring outside
4429 * code synchronizes with tg3->napi.poll()
4430 */
4431 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4432 work_done += tg3_rx(tp, budget - work_done);
4433
4434 return work_done;
4435 }
4436
4437 static int tg3_poll(struct napi_struct *napi, int budget)
4438 {
4439 struct tg3 *tp = container_of(napi, struct tg3, napi);
4440 int work_done = 0;
4441 struct tg3_hw_status *sblk = tp->hw_status;
4442
4443 while (1) {
4444 work_done = tg3_poll_work(tp, work_done, budget);
4445
4446 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4447 goto tx_recovery;
4448
4449 if (unlikely(work_done >= budget))
4450 break;
4451
4452 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4453 /* tp->last_tag is used in tg3_restart_ints() below
4454 * to tell the hw how much work has been processed,
4455 * so we must read it before checking for more work.
4456 */
4457 tp->last_tag = sblk->status_tag;
4458 rmb();
4459 } else
4460 sblk->status &= ~SD_STATUS_UPDATED;
4461
4462 if (likely(!tg3_has_work(tp))) {
4463 netif_rx_complete(napi);
4464 tg3_restart_ints(tp);
4465 break;
4466 }
4467 }
4468
4469 return work_done;
4470
4471 tx_recovery:
4472 /* work_done is guaranteed to be less than budget. */
4473 netif_rx_complete(napi);
4474 schedule_work(&tp->reset_task);
4475 return work_done;
4476 }
4477
4478 static void tg3_irq_quiesce(struct tg3 *tp)
4479 {
4480 BUG_ON(tp->irq_sync);
4481
4482 tp->irq_sync = 1;
4483 smp_mb();
4484
4485 synchronize_irq(tp->pdev->irq);
4486 }
4487
4488 static inline int tg3_irq_sync(struct tg3 *tp)
4489 {
4490 return tp->irq_sync;
4491 }
4492
4493 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4494 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4495 * with as well. Most of the time, this is not necessary except when
4496 * shutting down the device.
4497 */
4498 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4499 {
4500 spin_lock_bh(&tp->lock);
4501 if (irq_sync)
4502 tg3_irq_quiesce(tp);
4503 }
4504
4505 static inline void tg3_full_unlock(struct tg3 *tp)
4506 {
4507 spin_unlock_bh(&tp->lock);
4508 }
4509
4510 /* One-shot MSI handler - Chip automatically disables interrupt
4511 * after sending MSI so driver doesn't have to do it.
4512 */
4513 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4514 {
4515 struct net_device *dev = dev_id;
4516 struct tg3 *tp = netdev_priv(dev);
4517
4518 prefetch(tp->hw_status);
4519 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4520
4521 if (likely(!tg3_irq_sync(tp)))
4522 netif_rx_schedule(&tp->napi);
4523
4524 return IRQ_HANDLED;
4525 }
4526
4527 /* MSI ISR - No need to check for interrupt sharing and no need to
4528 * flush status block and interrupt mailbox. PCI ordering rules
4529 * guarantee that MSI will arrive after the status block.
4530 */
4531 static irqreturn_t tg3_msi(int irq, void *dev_id)
4532 {
4533 struct net_device *dev = dev_id;
4534 struct tg3 *tp = netdev_priv(dev);
4535
4536 prefetch(tp->hw_status);
4537 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4538 /*
4539 * Writing any value to intr-mbox-0 clears PCI INTA# and
4540 * chip-internal interrupt pending events.
4541 * Writing non-zero to intr-mbox-0 additional tells the
4542 * NIC to stop sending us irqs, engaging "in-intr-handler"
4543 * event coalescing.
4544 */
4545 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4546 if (likely(!tg3_irq_sync(tp)))
4547 netif_rx_schedule(&tp->napi);
4548
4549 return IRQ_RETVAL(1);
4550 }
4551
4552 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4553 {
4554 struct net_device *dev = dev_id;
4555 struct tg3 *tp = netdev_priv(dev);
4556 struct tg3_hw_status *sblk = tp->hw_status;
4557 unsigned int handled = 1;
4558
4559 /* In INTx mode, it is possible for the interrupt to arrive at
4560 * the CPU before the status block posted prior to the interrupt.
4561 * Reading the PCI State register will confirm whether the
4562 * interrupt is ours and will flush the status block.
4563 */
4564 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4565 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4566 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4567 handled = 0;
4568 goto out;
4569 }
4570 }
4571
4572 /*
4573 * Writing any value to intr-mbox-0 clears PCI INTA# and
4574 * chip-internal interrupt pending events.
4575 * Writing non-zero to intr-mbox-0 additional tells the
4576 * NIC to stop sending us irqs, engaging "in-intr-handler"
4577 * event coalescing.
4578 *
4579 * Flush the mailbox to de-assert the IRQ immediately to prevent
4580 * spurious interrupts. The flush impacts performance but
4581 * excessive spurious interrupts can be worse in some cases.
4582 */
4583 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4584 if (tg3_irq_sync(tp))
4585 goto out;
4586 sblk->status &= ~SD_STATUS_UPDATED;
4587 if (likely(tg3_has_work(tp))) {
4588 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4589 netif_rx_schedule(&tp->napi);
4590 } else {
4591 /* No work, shared interrupt perhaps? re-enable
4592 * interrupts, and flush that PCI write
4593 */
4594 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4595 0x00000000);
4596 }
4597 out:
4598 return IRQ_RETVAL(handled);
4599 }
4600
4601 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4602 {
4603 struct net_device *dev = dev_id;
4604 struct tg3 *tp = netdev_priv(dev);
4605 struct tg3_hw_status *sblk = tp->hw_status;
4606 unsigned int handled = 1;
4607
4608 /* In INTx mode, it is possible for the interrupt to arrive at
4609 * the CPU before the status block posted prior to the interrupt.
4610 * Reading the PCI State register will confirm whether the
4611 * interrupt is ours and will flush the status block.
4612 */
4613 if (unlikely(sblk->status_tag == tp->last_tag)) {
4614 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4615 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4616 handled = 0;
4617 goto out;
4618 }
4619 }
4620
4621 /*
4622 * writing any value to intr-mbox-0 clears PCI INTA# and
4623 * chip-internal interrupt pending events.
4624 * writing non-zero to intr-mbox-0 additional tells the
4625 * NIC to stop sending us irqs, engaging "in-intr-handler"
4626 * event coalescing.
4627 *
4628 * Flush the mailbox to de-assert the IRQ immediately to prevent
4629 * spurious interrupts. The flush impacts performance but
4630 * excessive spurious interrupts can be worse in some cases.
4631 */
4632 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4633 if (tg3_irq_sync(tp))
4634 goto out;
4635 if (netif_rx_schedule_prep(&tp->napi)) {
4636 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4637 /* Update last_tag to mark that this status has been
4638 * seen. Because interrupt may be shared, we may be
4639 * racing with tg3_poll(), so only update last_tag
4640 * if tg3_poll() is not scheduled.
4641 */
4642 tp->last_tag = sblk->status_tag;
4643 __netif_rx_schedule(&tp->napi);
4644 }
4645 out:
4646 return IRQ_RETVAL(handled);
4647 }
4648
4649 /* ISR for interrupt test */
4650 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4651 {
4652 struct net_device *dev = dev_id;
4653 struct tg3 *tp = netdev_priv(dev);
4654 struct tg3_hw_status *sblk = tp->hw_status;
4655
4656 if ((sblk->status & SD_STATUS_UPDATED) ||
4657 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4658 tg3_disable_ints(tp);
4659 return IRQ_RETVAL(1);
4660 }
4661 return IRQ_RETVAL(0);
4662 }
4663
4664 static int tg3_init_hw(struct tg3 *, int);
4665 static int tg3_halt(struct tg3 *, int, int);
4666
4667 /* Restart hardware after configuration changes, self-test, etc.
4668 * Invoked with tp->lock held.
4669 */
4670 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4671 __releases(tp->lock)
4672 __acquires(tp->lock)
4673 {
4674 int err;
4675
4676 err = tg3_init_hw(tp, reset_phy);
4677 if (err) {
4678 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4679 "aborting.\n", tp->dev->name);
4680 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4681 tg3_full_unlock(tp);
4682 del_timer_sync(&tp->timer);
4683 tp->irq_sync = 0;
4684 napi_enable(&tp->napi);
4685 dev_close(tp->dev);
4686 tg3_full_lock(tp, 0);
4687 }
4688 return err;
4689 }
4690
4691 #ifdef CONFIG_NET_POLL_CONTROLLER
4692 static void tg3_poll_controller(struct net_device *dev)
4693 {
4694 struct tg3 *tp = netdev_priv(dev);
4695
4696 tg3_interrupt(tp->pdev->irq, dev);
4697 }
4698 #endif
4699
4700 static void tg3_reset_task(struct work_struct *work)
4701 {
4702 struct tg3 *tp = container_of(work, struct tg3, reset_task);
4703 int err;
4704 unsigned int restart_timer;
4705
4706 tg3_full_lock(tp, 0);
4707
4708 if (!netif_running(tp->dev)) {
4709 tg3_full_unlock(tp);
4710 return;
4711 }
4712
4713 tg3_full_unlock(tp);
4714
4715 tg3_phy_stop(tp);
4716
4717 tg3_netif_stop(tp);
4718
4719 tg3_full_lock(tp, 1);
4720
4721 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4722 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4723
4724 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4725 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4726 tp->write32_rx_mbox = tg3_write_flush_reg32;
4727 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4728 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4729 }
4730
4731 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4732 err = tg3_init_hw(tp, 1);
4733 if (err)
4734 goto out;
4735
4736 tg3_netif_start(tp);
4737
4738 if (restart_timer)
4739 mod_timer(&tp->timer, jiffies + 1);
4740
4741 out:
4742 tg3_full_unlock(tp);
4743
4744 if (!err)
4745 tg3_phy_start(tp);
4746 }
4747
4748 static void tg3_dump_short_state(struct tg3 *tp)
4749 {
4750 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4751 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4752 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4753 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4754 }
4755
4756 static void tg3_tx_timeout(struct net_device *dev)
4757 {
4758 struct tg3 *tp = netdev_priv(dev);
4759
4760 if (netif_msg_tx_err(tp)) {
4761 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4762 dev->name);
4763 tg3_dump_short_state(tp);
4764 }
4765
4766 schedule_work(&tp->reset_task);
4767 }
4768
4769 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4770 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4771 {
4772 u32 base = (u32) mapping & 0xffffffff;
4773
4774 return ((base > 0xffffdcc0) &&
4775 (base + len + 8 < base));
4776 }
4777
4778 /* Test for DMA addresses > 40-bit */
4779 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4780 int len)
4781 {
4782 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4783 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4784 return (((u64) mapping + len) > DMA_40BIT_MASK);
4785 return 0;
4786 #else
4787 return 0;
4788 #endif
4789 }
4790
4791 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4792
4793 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4794 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4795 u32 last_plus_one, u32 *start,
4796 u32 base_flags, u32 mss)
4797 {
4798 struct sk_buff *new_skb;
4799 dma_addr_t new_addr = 0;
4800 u32 entry = *start;
4801 int i, ret = 0;
4802
4803 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4804 new_skb = skb_copy(skb, GFP_ATOMIC);
4805 else {
4806 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4807
4808 new_skb = skb_copy_expand(skb,
4809 skb_headroom(skb) + more_headroom,
4810 skb_tailroom(skb), GFP_ATOMIC);
4811 }
4812
4813 if (!new_skb) {
4814 ret = -1;
4815 } else {
4816 /* New SKB is guaranteed to be linear. */
4817 entry = *start;
4818 ret = skb_dma_map(&tp->pdev->dev, new_skb, DMA_TO_DEVICE);
4819 new_addr = skb_shinfo(new_skb)->dma_maps[0];
4820
4821 /* Make sure new skb does not cross any 4G boundaries.
4822 * Drop the packet if it does.
4823 */
4824 if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
4825 if (!ret)
4826 skb_dma_unmap(&tp->pdev->dev, new_skb,
4827 DMA_TO_DEVICE);
4828 ret = -1;
4829 dev_kfree_skb(new_skb);
4830 new_skb = NULL;
4831 } else {
4832 tg3_set_txd(tp, entry, new_addr, new_skb->len,
4833 base_flags, 1 | (mss << 1));
4834 *start = NEXT_TX(entry);
4835 }
4836 }
4837
4838 /* Now clean up the sw ring entries. */
4839 i = 0;
4840 while (entry != last_plus_one) {
4841 if (i == 0) {
4842 tp->tx_buffers[entry].skb = new_skb;
4843 } else {
4844 tp->tx_buffers[entry].skb = NULL;
4845 }
4846 entry = NEXT_TX(entry);
4847 i++;
4848 }
4849
4850 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
4851 dev_kfree_skb(skb);
4852
4853 return ret;
4854 }
4855
4856 static void tg3_set_txd(struct tg3 *tp, int entry,
4857 dma_addr_t mapping, int len, u32 flags,
4858 u32 mss_and_is_end)
4859 {
4860 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4861 int is_end = (mss_and_is_end & 0x1);
4862 u32 mss = (mss_and_is_end >> 1);
4863 u32 vlan_tag = 0;
4864
4865 if (is_end)
4866 flags |= TXD_FLAG_END;
4867 if (flags & TXD_FLAG_VLAN) {
4868 vlan_tag = flags >> 16;
4869 flags &= 0xffff;
4870 }
4871 vlan_tag |= (mss << TXD_MSS_SHIFT);
4872
4873 txd->addr_hi = ((u64) mapping >> 32);
4874 txd->addr_lo = ((u64) mapping & 0xffffffff);
4875 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4876 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4877 }
4878
4879 /* hard_start_xmit for devices that don't have any bugs and
4880 * support TG3_FLG2_HW_TSO_2 only.
4881 */
4882 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4883 {
4884 struct tg3 *tp = netdev_priv(dev);
4885 u32 len, entry, base_flags, mss;
4886 struct skb_shared_info *sp;
4887 dma_addr_t mapping;
4888
4889 len = skb_headlen(skb);
4890
4891 /* We are running in BH disabled context with netif_tx_lock
4892 * and TX reclaim runs via tp->napi.poll inside of a software
4893 * interrupt. Furthermore, IRQ processing runs lockless so we have
4894 * no IRQ context deadlocks to worry about either. Rejoice!
4895 */
4896 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4897 if (!netif_queue_stopped(dev)) {
4898 netif_stop_queue(dev);
4899
4900 /* This is a hard error, log it. */
4901 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4902 "queue awake!\n", dev->name);
4903 }
4904 return NETDEV_TX_BUSY;
4905 }
4906
4907 entry = tp->tx_prod;
4908 base_flags = 0;
4909 mss = 0;
4910 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4911 int tcp_opt_len, ip_tcp_len;
4912
4913 if (skb_header_cloned(skb) &&
4914 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4915 dev_kfree_skb(skb);
4916 goto out_unlock;
4917 }
4918
4919 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4920 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4921 else {
4922 struct iphdr *iph = ip_hdr(skb);
4923
4924 tcp_opt_len = tcp_optlen(skb);
4925 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4926
4927 iph->check = 0;
4928 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4929 mss |= (ip_tcp_len + tcp_opt_len) << 9;
4930 }
4931
4932 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4933 TXD_FLAG_CPU_POST_DMA);
4934
4935 tcp_hdr(skb)->check = 0;
4936
4937 }
4938 else if (skb->ip_summed == CHECKSUM_PARTIAL)
4939 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4940 #if TG3_VLAN_TAG_USED
4941 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4942 base_flags |= (TXD_FLAG_VLAN |
4943 (vlan_tx_tag_get(skb) << 16));
4944 #endif
4945
4946 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
4947 dev_kfree_skb(skb);
4948 goto out_unlock;
4949 }
4950
4951 sp = skb_shinfo(skb);
4952
4953 mapping = sp->dma_maps[0];
4954
4955 tp->tx_buffers[entry].skb = skb;
4956
4957 tg3_set_txd(tp, entry, mapping, len, base_flags,
4958 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4959
4960 entry = NEXT_TX(entry);
4961
4962 /* Now loop through additional data fragments, and queue them. */
4963 if (skb_shinfo(skb)->nr_frags > 0) {
4964 unsigned int i, last;
4965
4966 last = skb_shinfo(skb)->nr_frags - 1;
4967 for (i = 0; i <= last; i++) {
4968 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4969
4970 len = frag->size;
4971 mapping = sp->dma_maps[i + 1];
4972 tp->tx_buffers[entry].skb = NULL;
4973
4974 tg3_set_txd(tp, entry, mapping, len,
4975 base_flags, (i == last) | (mss << 1));
4976
4977 entry = NEXT_TX(entry);
4978 }
4979 }
4980
4981 /* Packets are ready, update Tx producer idx local and on card. */
4982 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4983
4984 tp->tx_prod = entry;
4985 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4986 netif_stop_queue(dev);
4987 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4988 netif_wake_queue(tp->dev);
4989 }
4990
4991 out_unlock:
4992 mmiowb();
4993
4994 dev->trans_start = jiffies;
4995
4996 return NETDEV_TX_OK;
4997 }
4998
4999 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
5000
5001 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5002 * TSO header is greater than 80 bytes.
5003 */
5004 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5005 {
5006 struct sk_buff *segs, *nskb;
5007
5008 /* Estimate the number of fragments in the worst case */
5009 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
5010 netif_stop_queue(tp->dev);
5011 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
5012 return NETDEV_TX_BUSY;
5013
5014 netif_wake_queue(tp->dev);
5015 }
5016
5017 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5018 if (IS_ERR(segs))
5019 goto tg3_tso_bug_end;
5020
5021 do {
5022 nskb = segs;
5023 segs = segs->next;
5024 nskb->next = NULL;
5025 tg3_start_xmit_dma_bug(nskb, tp->dev);
5026 } while (segs);
5027
5028 tg3_tso_bug_end:
5029 dev_kfree_skb(skb);
5030
5031 return NETDEV_TX_OK;
5032 }
5033
5034 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5035 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5036 */
5037 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
5038 {
5039 struct tg3 *tp = netdev_priv(dev);
5040 u32 len, entry, base_flags, mss;
5041 struct skb_shared_info *sp;
5042 int would_hit_hwbug;
5043 dma_addr_t mapping;
5044
5045 len = skb_headlen(skb);
5046
5047 /* We are running in BH disabled context with netif_tx_lock
5048 * and TX reclaim runs via tp->napi.poll inside of a software
5049 * interrupt. Furthermore, IRQ processing runs lockless so we have
5050 * no IRQ context deadlocks to worry about either. Rejoice!
5051 */
5052 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
5053 if (!netif_queue_stopped(dev)) {
5054 netif_stop_queue(dev);
5055
5056 /* This is a hard error, log it. */
5057 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5058 "queue awake!\n", dev->name);
5059 }
5060 return NETDEV_TX_BUSY;
5061 }
5062
5063 entry = tp->tx_prod;
5064 base_flags = 0;
5065 if (skb->ip_summed == CHECKSUM_PARTIAL)
5066 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5067 mss = 0;
5068 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5069 struct iphdr *iph;
5070 int tcp_opt_len, ip_tcp_len, hdr_len;
5071
5072 if (skb_header_cloned(skb) &&
5073 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5074 dev_kfree_skb(skb);
5075 goto out_unlock;
5076 }
5077
5078 tcp_opt_len = tcp_optlen(skb);
5079 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5080
5081 hdr_len = ip_tcp_len + tcp_opt_len;
5082 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5083 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5084 return (tg3_tso_bug(tp, skb));
5085
5086 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5087 TXD_FLAG_CPU_POST_DMA);
5088
5089 iph = ip_hdr(skb);
5090 iph->check = 0;
5091 iph->tot_len = htons(mss + hdr_len);
5092 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5093 tcp_hdr(skb)->check = 0;
5094 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5095 } else
5096 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5097 iph->daddr, 0,
5098 IPPROTO_TCP,
5099 0);
5100
5101 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
5102 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
5103 if (tcp_opt_len || iph->ihl > 5) {
5104 int tsflags;
5105
5106 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5107 mss |= (tsflags << 11);
5108 }
5109 } else {
5110 if (tcp_opt_len || iph->ihl > 5) {
5111 int tsflags;
5112
5113 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5114 base_flags |= tsflags << 12;
5115 }
5116 }
5117 }
5118 #if TG3_VLAN_TAG_USED
5119 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5120 base_flags |= (TXD_FLAG_VLAN |
5121 (vlan_tx_tag_get(skb) << 16));
5122 #endif
5123
5124 if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
5125 dev_kfree_skb(skb);
5126 goto out_unlock;
5127 }
5128
5129 sp = skb_shinfo(skb);
5130
5131 mapping = sp->dma_maps[0];
5132
5133 tp->tx_buffers[entry].skb = skb;
5134
5135 would_hit_hwbug = 0;
5136
5137 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5138 would_hit_hwbug = 1;
5139 else if (tg3_4g_overflow_test(mapping, len))
5140 would_hit_hwbug = 1;
5141
5142 tg3_set_txd(tp, entry, mapping, len, base_flags,
5143 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5144
5145 entry = NEXT_TX(entry);
5146
5147 /* Now loop through additional data fragments, and queue them. */
5148 if (skb_shinfo(skb)->nr_frags > 0) {
5149 unsigned int i, last;
5150
5151 last = skb_shinfo(skb)->nr_frags - 1;
5152 for (i = 0; i <= last; i++) {
5153 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5154
5155 len = frag->size;
5156 mapping = sp->dma_maps[i + 1];
5157
5158 tp->tx_buffers[entry].skb = NULL;
5159
5160 if (tg3_4g_overflow_test(mapping, len))
5161 would_hit_hwbug = 1;
5162
5163 if (tg3_40bit_overflow_test(tp, mapping, len))
5164 would_hit_hwbug = 1;
5165
5166 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5167 tg3_set_txd(tp, entry, mapping, len,
5168 base_flags, (i == last)|(mss << 1));
5169 else
5170 tg3_set_txd(tp, entry, mapping, len,
5171 base_flags, (i == last));
5172
5173 entry = NEXT_TX(entry);
5174 }
5175 }
5176
5177 if (would_hit_hwbug) {
5178 u32 last_plus_one = entry;
5179 u32 start;
5180
5181 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5182 start &= (TG3_TX_RING_SIZE - 1);
5183
5184 /* If the workaround fails due to memory/mapping
5185 * failure, silently drop this packet.
5186 */
5187 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
5188 &start, base_flags, mss))
5189 goto out_unlock;
5190
5191 entry = start;
5192 }
5193
5194 /* Packets are ready, update Tx producer idx local and on card. */
5195 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5196
5197 tp->tx_prod = entry;
5198 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5199 netif_stop_queue(dev);
5200 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5201 netif_wake_queue(tp->dev);
5202 }
5203
5204 out_unlock:
5205 mmiowb();
5206
5207 dev->trans_start = jiffies;
5208
5209 return NETDEV_TX_OK;
5210 }
5211
5212 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5213 int new_mtu)
5214 {
5215 dev->mtu = new_mtu;
5216
5217 if (new_mtu > ETH_DATA_LEN) {
5218 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5219 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5220 ethtool_op_set_tso(dev, 0);
5221 }
5222 else
5223 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5224 } else {
5225 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5226 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5227 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5228 }
5229 }
5230
5231 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5232 {
5233 struct tg3 *tp = netdev_priv(dev);
5234 int err;
5235
5236 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5237 return -EINVAL;
5238
5239 if (!netif_running(dev)) {
5240 /* We'll just catch it later when the
5241 * device is up'd.
5242 */
5243 tg3_set_mtu(dev, tp, new_mtu);
5244 return 0;
5245 }
5246
5247 tg3_phy_stop(tp);
5248
5249 tg3_netif_stop(tp);
5250
5251 tg3_full_lock(tp, 1);
5252
5253 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5254
5255 tg3_set_mtu(dev, tp, new_mtu);
5256
5257 err = tg3_restart_hw(tp, 0);
5258
5259 if (!err)
5260 tg3_netif_start(tp);
5261
5262 tg3_full_unlock(tp);
5263
5264 if (!err)
5265 tg3_phy_start(tp);
5266
5267 return err;
5268 }
5269
5270 /* Free up pending packets in all rx/tx rings.
5271 *
5272 * The chip has been shut down and the driver detached from
5273 * the networking, so no interrupts or new tx packets will
5274 * end up in the driver. tp->{tx,}lock is not held and we are not
5275 * in an interrupt context and thus may sleep.
5276 */
5277 static void tg3_free_rings(struct tg3 *tp)
5278 {
5279 struct ring_info *rxp;
5280 int i;
5281
5282 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5283 rxp = &tp->rx_std_buffers[i];
5284
5285 if (rxp->skb == NULL)
5286 continue;
5287 pci_unmap_single(tp->pdev,
5288 pci_unmap_addr(rxp, mapping),
5289 tp->rx_pkt_buf_sz - tp->rx_offset,
5290 PCI_DMA_FROMDEVICE);
5291 dev_kfree_skb_any(rxp->skb);
5292 rxp->skb = NULL;
5293 }
5294
5295 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5296 rxp = &tp->rx_jumbo_buffers[i];
5297
5298 if (rxp->skb == NULL)
5299 continue;
5300 pci_unmap_single(tp->pdev,
5301 pci_unmap_addr(rxp, mapping),
5302 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5303 PCI_DMA_FROMDEVICE);
5304 dev_kfree_skb_any(rxp->skb);
5305 rxp->skb = NULL;
5306 }
5307
5308 for (i = 0; i < TG3_TX_RING_SIZE; ) {
5309 struct tx_ring_info *txp;
5310 struct sk_buff *skb;
5311
5312 txp = &tp->tx_buffers[i];
5313 skb = txp->skb;
5314
5315 if (skb == NULL) {
5316 i++;
5317 continue;
5318 }
5319
5320 skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
5321
5322 txp->skb = NULL;
5323
5324 i += skb_shinfo(skb)->nr_frags + 1;
5325
5326 dev_kfree_skb_any(skb);
5327 }
5328 }
5329
5330 /* Initialize tx/rx rings for packet processing.
5331 *
5332 * The chip has been shut down and the driver detached from
5333 * the networking, so no interrupts or new tx packets will
5334 * end up in the driver. tp->{tx,}lock are held and thus
5335 * we may not sleep.
5336 */
5337 static int tg3_init_rings(struct tg3 *tp)
5338 {
5339 u32 i;
5340
5341 /* Free up all the SKBs. */
5342 tg3_free_rings(tp);
5343
5344 /* Zero out all descriptors. */
5345 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5346 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5347 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5348 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5349
5350 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5351 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5352 (tp->dev->mtu > ETH_DATA_LEN))
5353 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5354
5355 /* Initialize invariants of the rings, we only set this
5356 * stuff once. This works because the card does not
5357 * write into the rx buffer posting rings.
5358 */
5359 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5360 struct tg3_rx_buffer_desc *rxd;
5361
5362 rxd = &tp->rx_std[i];
5363 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5364 << RXD_LEN_SHIFT;
5365 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5366 rxd->opaque = (RXD_OPAQUE_RING_STD |
5367 (i << RXD_OPAQUE_INDEX_SHIFT));
5368 }
5369
5370 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5371 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5372 struct tg3_rx_buffer_desc *rxd;
5373
5374 rxd = &tp->rx_jumbo[i];
5375 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5376 << RXD_LEN_SHIFT;
5377 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5378 RXD_FLAG_JUMBO;
5379 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5380 (i << RXD_OPAQUE_INDEX_SHIFT));
5381 }
5382 }
5383
5384 /* Now allocate fresh SKBs for each rx ring. */
5385 for (i = 0; i < tp->rx_pending; i++) {
5386 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5387 printk(KERN_WARNING PFX
5388 "%s: Using a smaller RX standard ring, "
5389 "only %d out of %d buffers were allocated "
5390 "successfully.\n",
5391 tp->dev->name, i, tp->rx_pending);
5392 if (i == 0)
5393 return -ENOMEM;
5394 tp->rx_pending = i;
5395 break;
5396 }
5397 }
5398
5399 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5400 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5401 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5402 -1, i) < 0) {
5403 printk(KERN_WARNING PFX
5404 "%s: Using a smaller RX jumbo ring, "
5405 "only %d out of %d buffers were "
5406 "allocated successfully.\n",
5407 tp->dev->name, i, tp->rx_jumbo_pending);
5408 if (i == 0) {
5409 tg3_free_rings(tp);
5410 return -ENOMEM;
5411 }
5412 tp->rx_jumbo_pending = i;
5413 break;
5414 }
5415 }
5416 }
5417 return 0;
5418 }
5419
5420 /*
5421 * Must not be invoked with interrupt sources disabled and
5422 * the hardware shutdown down.
5423 */
5424 static void tg3_free_consistent(struct tg3 *tp)
5425 {
5426 kfree(tp->rx_std_buffers);
5427 tp->rx_std_buffers = NULL;
5428 if (tp->rx_std) {
5429 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5430 tp->rx_std, tp->rx_std_mapping);
5431 tp->rx_std = NULL;
5432 }
5433 if (tp->rx_jumbo) {
5434 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5435 tp->rx_jumbo, tp->rx_jumbo_mapping);
5436 tp->rx_jumbo = NULL;
5437 }
5438 if (tp->rx_rcb) {
5439 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5440 tp->rx_rcb, tp->rx_rcb_mapping);
5441 tp->rx_rcb = NULL;
5442 }
5443 if (tp->tx_ring) {
5444 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5445 tp->tx_ring, tp->tx_desc_mapping);
5446 tp->tx_ring = NULL;
5447 }
5448 if (tp->hw_status) {
5449 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5450 tp->hw_status, tp->status_mapping);
5451 tp->hw_status = NULL;
5452 }
5453 if (tp->hw_stats) {
5454 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5455 tp->hw_stats, tp->stats_mapping);
5456 tp->hw_stats = NULL;
5457 }
5458 }
5459
5460 /*
5461 * Must not be invoked with interrupt sources disabled and
5462 * the hardware shutdown down. Can sleep.
5463 */
5464 static int tg3_alloc_consistent(struct tg3 *tp)
5465 {
5466 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5467 (TG3_RX_RING_SIZE +
5468 TG3_RX_JUMBO_RING_SIZE)) +
5469 (sizeof(struct tx_ring_info) *
5470 TG3_TX_RING_SIZE),
5471 GFP_KERNEL);
5472 if (!tp->rx_std_buffers)
5473 return -ENOMEM;
5474
5475 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5476 tp->tx_buffers = (struct tx_ring_info *)
5477 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5478
5479 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5480 &tp->rx_std_mapping);
5481 if (!tp->rx_std)
5482 goto err_out;
5483
5484 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5485 &tp->rx_jumbo_mapping);
5486
5487 if (!tp->rx_jumbo)
5488 goto err_out;
5489
5490 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5491 &tp->rx_rcb_mapping);
5492 if (!tp->rx_rcb)
5493 goto err_out;
5494
5495 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5496 &tp->tx_desc_mapping);
5497 if (!tp->tx_ring)
5498 goto err_out;
5499
5500 tp->hw_status = pci_alloc_consistent(tp->pdev,
5501 TG3_HW_STATUS_SIZE,
5502 &tp->status_mapping);
5503 if (!tp->hw_status)
5504 goto err_out;
5505
5506 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5507 sizeof(struct tg3_hw_stats),
5508 &tp->stats_mapping);
5509 if (!tp->hw_stats)
5510 goto err_out;
5511
5512 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5513 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5514
5515 return 0;
5516
5517 err_out:
5518 tg3_free_consistent(tp);
5519 return -ENOMEM;
5520 }
5521
5522 #define MAX_WAIT_CNT 1000
5523
5524 /* To stop a block, clear the enable bit and poll till it
5525 * clears. tp->lock is held.
5526 */
5527 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5528 {
5529 unsigned int i;
5530 u32 val;
5531
5532 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5533 switch (ofs) {
5534 case RCVLSC_MODE:
5535 case DMAC_MODE:
5536 case MBFREE_MODE:
5537 case BUFMGR_MODE:
5538 case MEMARB_MODE:
5539 /* We can't enable/disable these bits of the
5540 * 5705/5750, just say success.
5541 */
5542 return 0;
5543
5544 default:
5545 break;
5546 }
5547 }
5548
5549 val = tr32(ofs);
5550 val &= ~enable_bit;
5551 tw32_f(ofs, val);
5552
5553 for (i = 0; i < MAX_WAIT_CNT; i++) {
5554 udelay(100);
5555 val = tr32(ofs);
5556 if ((val & enable_bit) == 0)
5557 break;
5558 }
5559
5560 if (i == MAX_WAIT_CNT && !silent) {
5561 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5562 "ofs=%lx enable_bit=%x\n",
5563 ofs, enable_bit);
5564 return -ENODEV;
5565 }
5566
5567 return 0;
5568 }
5569
5570 /* tp->lock is held. */
5571 static int tg3_abort_hw(struct tg3 *tp, int silent)
5572 {
5573 int i, err;
5574
5575 tg3_disable_ints(tp);
5576
5577 tp->rx_mode &= ~RX_MODE_ENABLE;
5578 tw32_f(MAC_RX_MODE, tp->rx_mode);
5579 udelay(10);
5580
5581 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5582 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5583 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5584 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5585 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5586 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5587
5588 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5589 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5590 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5591 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5592 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5593 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5594 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5595
5596 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5597 tw32_f(MAC_MODE, tp->mac_mode);
5598 udelay(40);
5599
5600 tp->tx_mode &= ~TX_MODE_ENABLE;
5601 tw32_f(MAC_TX_MODE, tp->tx_mode);
5602
5603 for (i = 0; i < MAX_WAIT_CNT; i++) {
5604 udelay(100);
5605 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5606 break;
5607 }
5608 if (i >= MAX_WAIT_CNT) {
5609 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5610 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5611 tp->dev->name, tr32(MAC_TX_MODE));
5612 err |= -ENODEV;
5613 }
5614
5615 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5616 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5617 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5618
5619 tw32(FTQ_RESET, 0xffffffff);
5620 tw32(FTQ_RESET, 0x00000000);
5621
5622 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5623 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5624
5625 if (tp->hw_status)
5626 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5627 if (tp->hw_stats)
5628 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5629
5630 return err;
5631 }
5632
5633 /* tp->lock is held. */
5634 static int tg3_nvram_lock(struct tg3 *tp)
5635 {
5636 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5637 int i;
5638
5639 if (tp->nvram_lock_cnt == 0) {
5640 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5641 for (i = 0; i < 8000; i++) {
5642 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5643 break;
5644 udelay(20);
5645 }
5646 if (i == 8000) {
5647 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5648 return -ENODEV;
5649 }
5650 }
5651 tp->nvram_lock_cnt++;
5652 }
5653 return 0;
5654 }
5655
5656 /* tp->lock is held. */
5657 static void tg3_nvram_unlock(struct tg3 *tp)
5658 {
5659 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5660 if (tp->nvram_lock_cnt > 0)
5661 tp->nvram_lock_cnt--;
5662 if (tp->nvram_lock_cnt == 0)
5663 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5664 }
5665 }
5666
5667 /* tp->lock is held. */
5668 static void tg3_enable_nvram_access(struct tg3 *tp)
5669 {
5670 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5671 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5672 u32 nvaccess = tr32(NVRAM_ACCESS);
5673
5674 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5675 }
5676 }
5677
5678 /* tp->lock is held. */
5679 static void tg3_disable_nvram_access(struct tg3 *tp)
5680 {
5681 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5682 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5683 u32 nvaccess = tr32(NVRAM_ACCESS);
5684
5685 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5686 }
5687 }
5688
5689 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5690 {
5691 int i;
5692 u32 apedata;
5693
5694 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5695 if (apedata != APE_SEG_SIG_MAGIC)
5696 return;
5697
5698 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5699 if (!(apedata & APE_FW_STATUS_READY))
5700 return;
5701
5702 /* Wait for up to 1 millisecond for APE to service previous event. */
5703 for (i = 0; i < 10; i++) {
5704 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5705 return;
5706
5707 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5708
5709 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5710 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5711 event | APE_EVENT_STATUS_EVENT_PENDING);
5712
5713 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5714
5715 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5716 break;
5717
5718 udelay(100);
5719 }
5720
5721 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5722 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5723 }
5724
5725 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5726 {
5727 u32 event;
5728 u32 apedata;
5729
5730 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5731 return;
5732
5733 switch (kind) {
5734 case RESET_KIND_INIT:
5735 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5736 APE_HOST_SEG_SIG_MAGIC);
5737 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5738 APE_HOST_SEG_LEN_MAGIC);
5739 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5740 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5741 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5742 APE_HOST_DRIVER_ID_MAGIC);
5743 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5744 APE_HOST_BEHAV_NO_PHYLOCK);
5745
5746 event = APE_EVENT_STATUS_STATE_START;
5747 break;
5748 case RESET_KIND_SHUTDOWN:
5749 /* With the interface we are currently using,
5750 * APE does not track driver state. Wiping
5751 * out the HOST SEGMENT SIGNATURE forces
5752 * the APE to assume OS absent status.
5753 */
5754 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
5755
5756 event = APE_EVENT_STATUS_STATE_UNLOAD;
5757 break;
5758 case RESET_KIND_SUSPEND:
5759 event = APE_EVENT_STATUS_STATE_SUSPEND;
5760 break;
5761 default:
5762 return;
5763 }
5764
5765 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5766
5767 tg3_ape_send_event(tp, event);
5768 }
5769
5770 /* tp->lock is held. */
5771 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5772 {
5773 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5774 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5775
5776 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5777 switch (kind) {
5778 case RESET_KIND_INIT:
5779 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5780 DRV_STATE_START);
5781 break;
5782
5783 case RESET_KIND_SHUTDOWN:
5784 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5785 DRV_STATE_UNLOAD);
5786 break;
5787
5788 case RESET_KIND_SUSPEND:
5789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5790 DRV_STATE_SUSPEND);
5791 break;
5792
5793 default:
5794 break;
5795 }
5796 }
5797
5798 if (kind == RESET_KIND_INIT ||
5799 kind == RESET_KIND_SUSPEND)
5800 tg3_ape_driver_state_change(tp, kind);
5801 }
5802
5803 /* tp->lock is held. */
5804 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5805 {
5806 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5807 switch (kind) {
5808 case RESET_KIND_INIT:
5809 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5810 DRV_STATE_START_DONE);
5811 break;
5812
5813 case RESET_KIND_SHUTDOWN:
5814 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5815 DRV_STATE_UNLOAD_DONE);
5816 break;
5817
5818 default:
5819 break;
5820 }
5821 }
5822
5823 if (kind == RESET_KIND_SHUTDOWN)
5824 tg3_ape_driver_state_change(tp, kind);
5825 }
5826
5827 /* tp->lock is held. */
5828 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5829 {
5830 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5831 switch (kind) {
5832 case RESET_KIND_INIT:
5833 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5834 DRV_STATE_START);
5835 break;
5836
5837 case RESET_KIND_SHUTDOWN:
5838 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5839 DRV_STATE_UNLOAD);
5840 break;
5841
5842 case RESET_KIND_SUSPEND:
5843 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5844 DRV_STATE_SUSPEND);
5845 break;
5846
5847 default:
5848 break;
5849 }
5850 }
5851 }
5852
5853 static int tg3_poll_fw(struct tg3 *tp)
5854 {
5855 int i;
5856 u32 val;
5857
5858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5859 /* Wait up to 20ms for init done. */
5860 for (i = 0; i < 200; i++) {
5861 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5862 return 0;
5863 udelay(100);
5864 }
5865 return -ENODEV;
5866 }
5867
5868 /* Wait for firmware initialization to complete. */
5869 for (i = 0; i < 100000; i++) {
5870 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5871 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5872 break;
5873 udelay(10);
5874 }
5875
5876 /* Chip might not be fitted with firmware. Some Sun onboard
5877 * parts are configured like that. So don't signal the timeout
5878 * of the above loop as an error, but do report the lack of
5879 * running firmware once.
5880 */
5881 if (i >= 100000 &&
5882 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5883 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5884
5885 printk(KERN_INFO PFX "%s: No firmware running.\n",
5886 tp->dev->name);
5887 }
5888
5889 return 0;
5890 }
5891
5892 /* Save PCI command register before chip reset */
5893 static void tg3_save_pci_state(struct tg3 *tp)
5894 {
5895 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5896 }
5897
5898 /* Restore PCI state after chip reset */
5899 static void tg3_restore_pci_state(struct tg3 *tp)
5900 {
5901 u32 val;
5902
5903 /* Re-enable indirect register accesses. */
5904 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5905 tp->misc_host_ctrl);
5906
5907 /* Set MAX PCI retry to zero. */
5908 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5909 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5910 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5911 val |= PCISTATE_RETRY_SAME_DMA;
5912 /* Allow reads and writes to the APE register and memory space. */
5913 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5914 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5915 PCISTATE_ALLOW_APE_SHMEM_WR;
5916 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5917
5918 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5919
5920 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
5921 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5922 pcie_set_readrq(tp->pdev, 4096);
5923 else {
5924 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5925 tp->pci_cacheline_sz);
5926 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5927 tp->pci_lat_timer);
5928 }
5929 }
5930
5931 /* Make sure PCI-X relaxed ordering bit is clear. */
5932 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
5933 u16 pcix_cmd;
5934
5935 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5936 &pcix_cmd);
5937 pcix_cmd &= ~PCI_X_CMD_ERO;
5938 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5939 pcix_cmd);
5940 }
5941
5942 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5943
5944 /* Chip reset on 5780 will reset MSI enable bit,
5945 * so need to restore it.
5946 */
5947 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5948 u16 ctrl;
5949
5950 pci_read_config_word(tp->pdev,
5951 tp->msi_cap + PCI_MSI_FLAGS,
5952 &ctrl);
5953 pci_write_config_word(tp->pdev,
5954 tp->msi_cap + PCI_MSI_FLAGS,
5955 ctrl | PCI_MSI_FLAGS_ENABLE);
5956 val = tr32(MSGINT_MODE);
5957 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5958 }
5959 }
5960 }
5961
5962 static void tg3_stop_fw(struct tg3 *);
5963
5964 /* tp->lock is held. */
5965 static int tg3_chip_reset(struct tg3 *tp)
5966 {
5967 u32 val;
5968 void (*write_op)(struct tg3 *, u32, u32);
5969 int err;
5970
5971 tg3_nvram_lock(tp);
5972
5973 tg3_mdio_stop(tp);
5974
5975 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
5976
5977 /* No matching tg3_nvram_unlock() after this because
5978 * chip reset below will undo the nvram lock.
5979 */
5980 tp->nvram_lock_cnt = 0;
5981
5982 /* GRC_MISC_CFG core clock reset will clear the memory
5983 * enable bit in PCI register 4 and the MSI enable bit
5984 * on some chips, so we save relevant registers here.
5985 */
5986 tg3_save_pci_state(tp);
5987
5988 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5989 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
5990 tw32(GRC_FASTBOOT_PC, 0);
5991
5992 /*
5993 * We must avoid the readl() that normally takes place.
5994 * It locks machines, causes machine checks, and other
5995 * fun things. So, temporarily disable the 5701
5996 * hardware workaround, while we do the reset.
5997 */
5998 write_op = tp->write32;
5999 if (write_op == tg3_write_flush_reg32)
6000 tp->write32 = tg3_write32;
6001
6002 /* Prevent the irq handler from reading or writing PCI registers
6003 * during chip reset when the memory enable bit in the PCI command
6004 * register may be cleared. The chip does not generate interrupt
6005 * at this time, but the irq handler may still be called due to irq
6006 * sharing or irqpoll.
6007 */
6008 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6009 if (tp->hw_status) {
6010 tp->hw_status->status = 0;
6011 tp->hw_status->status_tag = 0;
6012 }
6013 tp->last_tag = 0;
6014 smp_mb();
6015 synchronize_irq(tp->pdev->irq);
6016
6017 /* do the reset */
6018 val = GRC_MISC_CFG_CORECLK_RESET;
6019
6020 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6021 if (tr32(0x7e2c) == 0x60) {
6022 tw32(0x7e2c, 0x20);
6023 }
6024 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6025 tw32(GRC_MISC_CFG, (1 << 29));
6026 val |= (1 << 29);
6027 }
6028 }
6029
6030 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6031 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6032 tw32(GRC_VCPU_EXT_CTRL,
6033 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6034 }
6035
6036 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6037 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6038 tw32(GRC_MISC_CFG, val);
6039
6040 /* restore 5701 hardware bug workaround write method */
6041 tp->write32 = write_op;
6042
6043 /* Unfortunately, we have to delay before the PCI read back.
6044 * Some 575X chips even will not respond to a PCI cfg access
6045 * when the reset command is given to the chip.
6046 *
6047 * How do these hardware designers expect things to work
6048 * properly if the PCI write is posted for a long period
6049 * of time? It is always necessary to have some method by
6050 * which a register read back can occur to push the write
6051 * out which does the reset.
6052 *
6053 * For most tg3 variants the trick below was working.
6054 * Ho hum...
6055 */
6056 udelay(120);
6057
6058 /* Flush PCI posted writes. The normal MMIO registers
6059 * are inaccessible at this time so this is the only
6060 * way to make this reliably (actually, this is no longer
6061 * the case, see above). I tried to use indirect
6062 * register read/write but this upset some 5701 variants.
6063 */
6064 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6065
6066 udelay(120);
6067
6068 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6069 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6070 int i;
6071 u32 cfg_val;
6072
6073 /* Wait for link training to complete. */
6074 for (i = 0; i < 5000; i++)
6075 udelay(100);
6076
6077 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6078 pci_write_config_dword(tp->pdev, 0xc4,
6079 cfg_val | (1 << 15));
6080 }
6081
6082 /* Set PCIE max payload size to 128 bytes and
6083 * clear the "no snoop" and "relaxed ordering" bits.
6084 */
6085 pci_write_config_word(tp->pdev,
6086 tp->pcie_cap + PCI_EXP_DEVCTL,
6087 0);
6088
6089 pcie_set_readrq(tp->pdev, 4096);
6090
6091 /* Clear error status */
6092 pci_write_config_word(tp->pdev,
6093 tp->pcie_cap + PCI_EXP_DEVSTA,
6094 PCI_EXP_DEVSTA_CED |
6095 PCI_EXP_DEVSTA_NFED |
6096 PCI_EXP_DEVSTA_FED |
6097 PCI_EXP_DEVSTA_URD);
6098 }
6099
6100 tg3_restore_pci_state(tp);
6101
6102 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6103
6104 val = 0;
6105 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6106 val = tr32(MEMARB_MODE);
6107 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6108
6109 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6110 tg3_stop_fw(tp);
6111 tw32(0x5000, 0x400);
6112 }
6113
6114 tw32(GRC_MODE, tp->grc_mode);
6115
6116 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6117 val = tr32(0xc4);
6118
6119 tw32(0xc4, val | (1 << 15));
6120 }
6121
6122 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6123 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6124 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6125 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6126 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6127 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6128 }
6129
6130 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6131 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6132 tw32_f(MAC_MODE, tp->mac_mode);
6133 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6134 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6135 tw32_f(MAC_MODE, tp->mac_mode);
6136 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6137 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6138 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6139 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6140 tw32_f(MAC_MODE, tp->mac_mode);
6141 } else
6142 tw32_f(MAC_MODE, 0);
6143 udelay(40);
6144
6145 tg3_mdio_start(tp);
6146
6147 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6148
6149 err = tg3_poll_fw(tp);
6150 if (err)
6151 return err;
6152
6153 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6154 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6155 val = tr32(0x7c00);
6156
6157 tw32(0x7c00, val | (1 << 25));
6158 }
6159
6160 /* Reprobe ASF enable state. */
6161 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6162 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6163 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6164 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6165 u32 nic_cfg;
6166
6167 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6168 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6169 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6170 tp->last_event_jiffies = jiffies;
6171 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6172 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
6173 }
6174 }
6175
6176 return 0;
6177 }
6178
6179 /* tp->lock is held. */
6180 static void tg3_stop_fw(struct tg3 *tp)
6181 {
6182 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
6183 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
6184 /* Wait for RX cpu to ACK the previous event. */
6185 tg3_wait_for_event_ack(tp);
6186
6187 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
6188
6189 tg3_generate_fw_event(tp);
6190
6191 /* Wait for RX cpu to ACK this event. */
6192 tg3_wait_for_event_ack(tp);
6193 }
6194 }
6195
6196 /* tp->lock is held. */
6197 static int tg3_halt(struct tg3 *tp, int kind, int silent)
6198 {
6199 int err;
6200
6201 tg3_stop_fw(tp);
6202
6203 tg3_write_sig_pre_reset(tp, kind);
6204
6205 tg3_abort_hw(tp, silent);
6206 err = tg3_chip_reset(tp);
6207
6208 tg3_write_sig_legacy(tp, kind);
6209 tg3_write_sig_post_reset(tp, kind);
6210
6211 if (err)
6212 return err;
6213
6214 return 0;
6215 }
6216
6217 #define RX_CPU_SCRATCH_BASE 0x30000
6218 #define RX_CPU_SCRATCH_SIZE 0x04000
6219 #define TX_CPU_SCRATCH_BASE 0x34000
6220 #define TX_CPU_SCRATCH_SIZE 0x04000
6221
6222 /* tp->lock is held. */
6223 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6224 {
6225 int i;
6226
6227 BUG_ON(offset == TX_CPU_BASE &&
6228 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6229
6230 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6231 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6232
6233 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6234 return 0;
6235 }
6236 if (offset == RX_CPU_BASE) {
6237 for (i = 0; i < 10000; i++) {
6238 tw32(offset + CPU_STATE, 0xffffffff);
6239 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6240 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6241 break;
6242 }
6243
6244 tw32(offset + CPU_STATE, 0xffffffff);
6245 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
6246 udelay(10);
6247 } else {
6248 for (i = 0; i < 10000; i++) {
6249 tw32(offset + CPU_STATE, 0xffffffff);
6250 tw32(offset + CPU_MODE, CPU_MODE_HALT);
6251 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6252 break;
6253 }
6254 }
6255
6256 if (i >= 10000) {
6257 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6258 "and %s CPU\n",
6259 tp->dev->name,
6260 (offset == RX_CPU_BASE ? "RX" : "TX"));
6261 return -ENODEV;
6262 }
6263
6264 /* Clear firmware's nvram arbitration. */
6265 if (tp->tg3_flags & TG3_FLAG_NVRAM)
6266 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6267 return 0;
6268 }
6269
6270 struct fw_info {
6271 unsigned int fw_base;
6272 unsigned int fw_len;
6273 const __be32 *fw_data;
6274 };
6275
6276 /* tp->lock is held. */
6277 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6278 int cpu_scratch_size, struct fw_info *info)
6279 {
6280 int err, lock_err, i;
6281 void (*write_op)(struct tg3 *, u32, u32);
6282
6283 if (cpu_base == TX_CPU_BASE &&
6284 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6285 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6286 "TX cpu firmware on %s which is 5705.\n",
6287 tp->dev->name);
6288 return -EINVAL;
6289 }
6290
6291 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6292 write_op = tg3_write_mem;
6293 else
6294 write_op = tg3_write_indirect_reg32;
6295
6296 /* It is possible that bootcode is still loading at this point.
6297 * Get the nvram lock first before halting the cpu.
6298 */
6299 lock_err = tg3_nvram_lock(tp);
6300 err = tg3_halt_cpu(tp, cpu_base);
6301 if (!lock_err)
6302 tg3_nvram_unlock(tp);
6303 if (err)
6304 goto out;
6305
6306 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6307 write_op(tp, cpu_scratch_base + i, 0);
6308 tw32(cpu_base + CPU_STATE, 0xffffffff);
6309 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6310 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
6311 write_op(tp, (cpu_scratch_base +
6312 (info->fw_base & 0xffff) +
6313 (i * sizeof(u32))),
6314 be32_to_cpu(info->fw_data[i]));
6315
6316 err = 0;
6317
6318 out:
6319 return err;
6320 }
6321
6322 /* tp->lock is held. */
6323 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6324 {
6325 struct fw_info info;
6326 const __be32 *fw_data;
6327 int err, i;
6328
6329 fw_data = (void *)tp->fw->data;
6330
6331 /* Firmware blob starts with version numbers, followed by
6332 start address and length. We are setting complete length.
6333 length = end_address_of_bss - start_address_of_text.
6334 Remainder is the blob to be loaded contiguously
6335 from start address. */
6336
6337 info.fw_base = be32_to_cpu(fw_data[1]);
6338 info.fw_len = tp->fw->size - 12;
6339 info.fw_data = &fw_data[3];
6340
6341 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6342 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6343 &info);
6344 if (err)
6345 return err;
6346
6347 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6348 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6349 &info);
6350 if (err)
6351 return err;
6352
6353 /* Now startup only the RX cpu. */
6354 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6355 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6356
6357 for (i = 0; i < 5; i++) {
6358 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
6359 break;
6360 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6361 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
6362 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
6363 udelay(1000);
6364 }
6365 if (i >= 5) {
6366 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6367 "to set RX CPU PC, is %08x should be %08x\n",
6368 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6369 info.fw_base);
6370 return -ENODEV;
6371 }
6372 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6373 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
6374
6375 return 0;
6376 }
6377
6378 /* 5705 needs a special version of the TSO firmware. */
6379
6380 /* tp->lock is held. */
6381 static int tg3_load_tso_firmware(struct tg3 *tp)
6382 {
6383 struct fw_info info;
6384 const __be32 *fw_data;
6385 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6386 int err, i;
6387
6388 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6389 return 0;
6390
6391 fw_data = (void *)tp->fw->data;
6392
6393 /* Firmware blob starts with version numbers, followed by
6394 start address and length. We are setting complete length.
6395 length = end_address_of_bss - start_address_of_text.
6396 Remainder is the blob to be loaded contiguously
6397 from start address. */
6398
6399 info.fw_base = be32_to_cpu(fw_data[1]);
6400 cpu_scratch_size = tp->fw_len;
6401 info.fw_len = tp->fw->size - 12;
6402 info.fw_data = &fw_data[3];
6403
6404 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6405 cpu_base = RX_CPU_BASE;
6406 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6407 } else {
6408 cpu_base = TX_CPU_BASE;
6409 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6410 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6411 }
6412
6413 err = tg3_load_firmware_cpu(tp, cpu_base,
6414 cpu_scratch_base, cpu_scratch_size,
6415 &info);
6416 if (err)
6417 return err;
6418
6419 /* Now startup the cpu. */
6420 tw32(cpu_base + CPU_STATE, 0xffffffff);
6421 tw32_f(cpu_base + CPU_PC, info.fw_base);
6422
6423 for (i = 0; i < 5; i++) {
6424 if (tr32(cpu_base + CPU_PC) == info.fw_base)
6425 break;
6426 tw32(cpu_base + CPU_STATE, 0xffffffff);
6427 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
6428 tw32_f(cpu_base + CPU_PC, info.fw_base);
6429 udelay(1000);
6430 }
6431 if (i >= 5) {
6432 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6433 "to set CPU PC, is %08x should be %08x\n",
6434 tp->dev->name, tr32(cpu_base + CPU_PC),
6435 info.fw_base);
6436 return -ENODEV;
6437 }
6438 tw32(cpu_base + CPU_STATE, 0xffffffff);
6439 tw32_f(cpu_base + CPU_MODE, 0x00000000);
6440 return 0;
6441 }
6442
6443
6444 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6445 {
6446 struct tg3 *tp = netdev_priv(dev);
6447 struct sockaddr *addr = p;
6448 int err = 0, skip_mac_1 = 0;
6449
6450 if (!is_valid_ether_addr(addr->sa_data))
6451 return -EINVAL;
6452
6453 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6454
6455 if (!netif_running(dev))
6456 return 0;
6457
6458 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6459 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6460
6461 addr0_high = tr32(MAC_ADDR_0_HIGH);
6462 addr0_low = tr32(MAC_ADDR_0_LOW);
6463 addr1_high = tr32(MAC_ADDR_1_HIGH);
6464 addr1_low = tr32(MAC_ADDR_1_LOW);
6465
6466 /* Skip MAC addr 1 if ASF is using it. */
6467 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6468 !(addr1_high == 0 && addr1_low == 0))
6469 skip_mac_1 = 1;
6470 }
6471 spin_lock_bh(&tp->lock);
6472 __tg3_set_mac_addr(tp, skip_mac_1);
6473 spin_unlock_bh(&tp->lock);
6474
6475 return err;
6476 }
6477
6478 /* tp->lock is held. */
6479 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6480 dma_addr_t mapping, u32 maxlen_flags,
6481 u32 nic_addr)
6482 {
6483 tg3_write_mem(tp,
6484 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6485 ((u64) mapping >> 32));
6486 tg3_write_mem(tp,
6487 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6488 ((u64) mapping & 0xffffffff));
6489 tg3_write_mem(tp,
6490 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6491 maxlen_flags);
6492
6493 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6494 tg3_write_mem(tp,
6495 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6496 nic_addr);
6497 }
6498
6499 static void __tg3_set_rx_mode(struct net_device *);
6500 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6501 {
6502 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6503 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6504 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6505 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6506 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6507 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6508 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6509 }
6510 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6511 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6512 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6513 u32 val = ec->stats_block_coalesce_usecs;
6514
6515 if (!netif_carrier_ok(tp->dev))
6516 val = 0;
6517
6518 tw32(HOSTCC_STAT_COAL_TICKS, val);
6519 }
6520 }
6521
6522 /* tp->lock is held. */
6523 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6524 {
6525 u32 val, rdmac_mode;
6526 int i, err, limit;
6527
6528 tg3_disable_ints(tp);
6529
6530 tg3_stop_fw(tp);
6531
6532 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6533
6534 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6535 tg3_abort_hw(tp, 1);
6536 }
6537
6538 if (reset_phy &&
6539 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
6540 tg3_phy_reset(tp);
6541
6542 err = tg3_chip_reset(tp);
6543 if (err)
6544 return err;
6545
6546 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6547
6548 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
6549 val = tr32(TG3_CPMU_CTRL);
6550 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
6551 tw32(TG3_CPMU_CTRL, val);
6552
6553 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
6554 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
6555 val |= CPMU_LSPD_10MB_MACCLK_6_25;
6556 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
6557
6558 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
6559 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
6560 val |= CPMU_LNK_AWARE_MACCLK_6_25;
6561 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
6562
6563 val = tr32(TG3_CPMU_HST_ACC);
6564 val &= ~CPMU_HST_ACC_MACCLK_MASK;
6565 val |= CPMU_HST_ACC_MACCLK_6_25;
6566 tw32(TG3_CPMU_HST_ACC, val);
6567 }
6568
6569 /* This works around an issue with Athlon chipsets on
6570 * B3 tigon3 silicon. This bit has no effect on any
6571 * other revision. But do not set this on PCI Express
6572 * chips and don't even touch the clocks if the CPMU is present.
6573 */
6574 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
6575 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6576 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6577 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6578 }
6579
6580 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6581 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6582 val = tr32(TG3PCI_PCISTATE);
6583 val |= PCISTATE_RETRY_SAME_DMA;
6584 tw32(TG3PCI_PCISTATE, val);
6585 }
6586
6587 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6588 /* Allow reads and writes to the
6589 * APE register and memory space.
6590 */
6591 val = tr32(TG3PCI_PCISTATE);
6592 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6593 PCISTATE_ALLOW_APE_SHMEM_WR;
6594 tw32(TG3PCI_PCISTATE, val);
6595 }
6596
6597 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6598 /* Enable some hw fixes. */
6599 val = tr32(TG3PCI_MSI_DATA);
6600 val |= (1 << 26) | (1 << 28) | (1 << 29);
6601 tw32(TG3PCI_MSI_DATA, val);
6602 }
6603
6604 /* Descriptor ring init may make accesses to the
6605 * NIC SRAM area to setup the TX descriptors, so we
6606 * can only do this after the hardware has been
6607 * successfully reset.
6608 */
6609 err = tg3_init_rings(tp);
6610 if (err)
6611 return err;
6612
6613 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
6614 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
6615 /* This value is determined during the probe time DMA
6616 * engine test, tg3_test_dma.
6617 */
6618 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6619 }
6620
6621 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6622 GRC_MODE_4X_NIC_SEND_RINGS |
6623 GRC_MODE_NO_TX_PHDR_CSUM |
6624 GRC_MODE_NO_RX_PHDR_CSUM);
6625 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6626
6627 /* Pseudo-header checksum is done by hardware logic and not
6628 * the offload processers, so make the chip do the pseudo-
6629 * header checksums on receive. For transmit it is more
6630 * convenient to do the pseudo-header checksum in software
6631 * as Linux does that on transmit for us in all cases.
6632 */
6633 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6634
6635 tw32(GRC_MODE,
6636 tp->grc_mode |
6637 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6638
6639 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6640 val = tr32(GRC_MISC_CFG);
6641 val &= ~0xff;
6642 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6643 tw32(GRC_MISC_CFG, val);
6644
6645 /* Initialize MBUF/DESC pool. */
6646 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6647 /* Do nothing. */
6648 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6649 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6650 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6651 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6652 else
6653 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6654 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6655 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6656 }
6657 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6658 int fw_len;
6659
6660 fw_len = tp->fw_len;
6661 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6662 tw32(BUFMGR_MB_POOL_ADDR,
6663 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6664 tw32(BUFMGR_MB_POOL_SIZE,
6665 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6666 }
6667
6668 if (tp->dev->mtu <= ETH_DATA_LEN) {
6669 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6670 tp->bufmgr_config.mbuf_read_dma_low_water);
6671 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6672 tp->bufmgr_config.mbuf_mac_rx_low_water);
6673 tw32(BUFMGR_MB_HIGH_WATER,
6674 tp->bufmgr_config.mbuf_high_water);
6675 } else {
6676 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6677 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6678 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6679 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6680 tw32(BUFMGR_MB_HIGH_WATER,
6681 tp->bufmgr_config.mbuf_high_water_jumbo);
6682 }
6683 tw32(BUFMGR_DMA_LOW_WATER,
6684 tp->bufmgr_config.dma_low_water);
6685 tw32(BUFMGR_DMA_HIGH_WATER,
6686 tp->bufmgr_config.dma_high_water);
6687
6688 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6689 for (i = 0; i < 2000; i++) {
6690 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6691 break;
6692 udelay(10);
6693 }
6694 if (i >= 2000) {
6695 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6696 tp->dev->name);
6697 return -ENODEV;
6698 }
6699
6700 /* Setup replenish threshold. */
6701 val = tp->rx_pending / 8;
6702 if (val == 0)
6703 val = 1;
6704 else if (val > tp->rx_std_max_post)
6705 val = tp->rx_std_max_post;
6706 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6707 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6708 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6709
6710 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6711 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6712 }
6713
6714 tw32(RCVBDI_STD_THRESH, val);
6715
6716 /* Initialize TG3_BDINFO's at:
6717 * RCVDBDI_STD_BD: standard eth size rx ring
6718 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6719 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6720 *
6721 * like so:
6722 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6723 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6724 * ring attribute flags
6725 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6726 *
6727 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6728 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6729 *
6730 * The size of each ring is fixed in the firmware, but the location is
6731 * configurable.
6732 */
6733 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6734 ((u64) tp->rx_std_mapping >> 32));
6735 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6736 ((u64) tp->rx_std_mapping & 0xffffffff));
6737 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6738 NIC_SRAM_RX_BUFFER_DESC);
6739
6740 /* Don't even try to program the JUMBO/MINI buffer descriptor
6741 * configs on 5705.
6742 */
6743 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6744 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6745 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6746 } else {
6747 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6748 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6749
6750 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6751 BDINFO_FLAGS_DISABLED);
6752
6753 /* Setup replenish threshold. */
6754 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6755
6756 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6757 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6758 ((u64) tp->rx_jumbo_mapping >> 32));
6759 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6760 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6761 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6762 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6763 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6764 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6765 } else {
6766 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6767 BDINFO_FLAGS_DISABLED);
6768 }
6769
6770 }
6771
6772 /* There is only one send ring on 5705/5750, no need to explicitly
6773 * disable the others.
6774 */
6775 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6776 /* Clear out send RCB ring in SRAM. */
6777 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6778 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6779 BDINFO_FLAGS_DISABLED);
6780 }
6781
6782 tp->tx_prod = 0;
6783 tp->tx_cons = 0;
6784 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6785 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6786
6787 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6788 tp->tx_desc_mapping,
6789 (TG3_TX_RING_SIZE <<
6790 BDINFO_FLAGS_MAXLEN_SHIFT),
6791 NIC_SRAM_TX_BUFFER_DESC);
6792
6793 /* There is only one receive return ring on 5705/5750, no need
6794 * to explicitly disable the others.
6795 */
6796 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6797 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6798 i += TG3_BDINFO_SIZE) {
6799 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6800 BDINFO_FLAGS_DISABLED);
6801 }
6802 }
6803
6804 tp->rx_rcb_ptr = 0;
6805 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6806
6807 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6808 tp->rx_rcb_mapping,
6809 (TG3_RX_RCB_RING_SIZE(tp) <<
6810 BDINFO_FLAGS_MAXLEN_SHIFT),
6811 0);
6812
6813 tp->rx_std_ptr = tp->rx_pending;
6814 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6815 tp->rx_std_ptr);
6816
6817 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6818 tp->rx_jumbo_pending : 0;
6819 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6820 tp->rx_jumbo_ptr);
6821
6822 /* Initialize MAC address and backoff seed. */
6823 __tg3_set_mac_addr(tp, 0);
6824
6825 /* MTU + ethernet header + FCS + optional VLAN tag */
6826 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6827
6828 /* The slot time is changed by tg3_setup_phy if we
6829 * run at gigabit with half duplex.
6830 */
6831 tw32(MAC_TX_LENGTHS,
6832 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6833 (6 << TX_LENGTHS_IPG_SHIFT) |
6834 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6835
6836 /* Receive rules. */
6837 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6838 tw32(RCVLPC_CONFIG, 0x0181);
6839
6840 /* Calculate RDMAC_MODE setting early, we need it to determine
6841 * the RCVLPC_STATE_ENABLE mask.
6842 */
6843 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6844 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6845 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6846 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6847 RDMAC_MODE_LNGREAD_ENAB);
6848
6849 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
6850 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
6851 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
6852 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
6853 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
6854 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
6855
6856 /* If statement applies to 5705 and 5750 PCI devices only */
6857 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6858 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6859 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6860 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6861 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6862 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6863 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6864 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6865 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6866 }
6867 }
6868
6869 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6870 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6871
6872 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6873 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
6874
6875 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
6876 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
6877 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
6878
6879 /* Receive/send statistics. */
6880 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6881 val = tr32(RCVLPC_STATS_ENABLE);
6882 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6883 tw32(RCVLPC_STATS_ENABLE, val);
6884 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6885 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6886 val = tr32(RCVLPC_STATS_ENABLE);
6887 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6888 tw32(RCVLPC_STATS_ENABLE, val);
6889 } else {
6890 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6891 }
6892 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6893 tw32(SNDDATAI_STATSENAB, 0xffffff);
6894 tw32(SNDDATAI_STATSCTRL,
6895 (SNDDATAI_SCTRL_ENABLE |
6896 SNDDATAI_SCTRL_FASTUPD));
6897
6898 /* Setup host coalescing engine. */
6899 tw32(HOSTCC_MODE, 0);
6900 for (i = 0; i < 2000; i++) {
6901 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6902 break;
6903 udelay(10);
6904 }
6905
6906 __tg3_set_coalesce(tp, &tp->coal);
6907
6908 /* set status block DMA address */
6909 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6910 ((u64) tp->status_mapping >> 32));
6911 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6912 ((u64) tp->status_mapping & 0xffffffff));
6913
6914 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6915 /* Status/statistics block address. See tg3_timer,
6916 * the tg3_periodic_fetch_stats call there, and
6917 * tg3_get_stats to see how this works for 5705/5750 chips.
6918 */
6919 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6920 ((u64) tp->stats_mapping >> 32));
6921 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6922 ((u64) tp->stats_mapping & 0xffffffff));
6923 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6924 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6925 }
6926
6927 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6928
6929 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6930 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6931 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6932 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6933
6934 /* Clear statistics/status block in chip, and status block in ram. */
6935 for (i = NIC_SRAM_STATS_BLK;
6936 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6937 i += sizeof(u32)) {
6938 tg3_write_mem(tp, i, 0);
6939 udelay(40);
6940 }
6941 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6942
6943 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6944 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6945 /* reset to prevent losing 1st rx packet intermittently */
6946 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6947 udelay(10);
6948 }
6949
6950 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6951 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
6952 else
6953 tp->mac_mode = 0;
6954 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6955 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6956 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6957 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6958 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6959 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6960 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6961 udelay(40);
6962
6963 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6964 * If TG3_FLG2_IS_NIC is zero, we should read the
6965 * register to preserve the GPIO settings for LOMs. The GPIOs,
6966 * whether used as inputs or outputs, are set by boot code after
6967 * reset.
6968 */
6969 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6970 u32 gpio_mask;
6971
6972 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6973 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6974 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6975
6976 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6977 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6978 GRC_LCLCTRL_GPIO_OUTPUT3;
6979
6980 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6981 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6982
6983 tp->grc_local_ctrl &= ~gpio_mask;
6984 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6985
6986 /* GPIO1 must be driven high for eeprom write protect */
6987 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6988 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6989 GRC_LCLCTRL_GPIO_OUTPUT1);
6990 }
6991 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6992 udelay(100);
6993
6994 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6995 tp->last_tag = 0;
6996
6997 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6998 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6999 udelay(40);
7000 }
7001
7002 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7003 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7004 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7005 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7006 WDMAC_MODE_LNGREAD_ENAB);
7007
7008 /* If statement applies to 5705 and 5750 PCI devices only */
7009 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7010 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7012 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7013 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7014 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7015 /* nothing */
7016 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7017 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7018 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7019 val |= WDMAC_MODE_RX_ACCEL;
7020 }
7021 }
7022
7023 /* Enable host coalescing bug fix */
7024 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7025 val |= WDMAC_MODE_STATUS_TAG_FIX;
7026
7027 tw32_f(WDMAC_MODE, val);
7028 udelay(40);
7029
7030 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7031 u16 pcix_cmd;
7032
7033 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7034 &pcix_cmd);
7035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7036 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7037 pcix_cmd |= PCI_X_CMD_READ_2K;
7038 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7039 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7040 pcix_cmd |= PCI_X_CMD_READ_2K;
7041 }
7042 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7043 pcix_cmd);
7044 }
7045
7046 tw32_f(RDMAC_MODE, rdmac_mode);
7047 udelay(40);
7048
7049 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7050 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7051 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7052
7053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7054 tw32(SNDDATAC_MODE,
7055 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7056 else
7057 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7058
7059 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7060 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7061 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7062 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7063 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7064 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7065 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7066 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7067
7068 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7069 err = tg3_load_5701_a0_firmware_fix(tp);
7070 if (err)
7071 return err;
7072 }
7073
7074 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7075 err = tg3_load_tso_firmware(tp);
7076 if (err)
7077 return err;
7078 }
7079
7080 tp->tx_mode = TX_MODE_ENABLE;
7081 tw32_f(MAC_TX_MODE, tp->tx_mode);
7082 udelay(100);
7083
7084 tp->rx_mode = RX_MODE_ENABLE;
7085 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
7086 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7087
7088 tw32_f(MAC_RX_MODE, tp->rx_mode);
7089 udelay(10);
7090
7091 tw32(MAC_LED_CTRL, tp->led_ctrl);
7092
7093 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7094 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7095 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7096 udelay(10);
7097 }
7098 tw32_f(MAC_RX_MODE, tp->rx_mode);
7099 udelay(10);
7100
7101 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7102 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7103 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7104 /* Set drive transmission level to 1.2V */
7105 /* only if the signal pre-emphasis bit is not set */
7106 val = tr32(MAC_SERDES_CFG);
7107 val &= 0xfffff000;
7108 val |= 0x880;
7109 tw32(MAC_SERDES_CFG, val);
7110 }
7111 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7112 tw32(MAC_SERDES_CFG, 0x616000);
7113 }
7114
7115 /* Prevent chip from dropping frames when flow control
7116 * is enabled.
7117 */
7118 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7119
7120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7121 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7122 /* Use hardware link auto-negotiation */
7123 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7124 }
7125
7126 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7127 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7128 u32 tmp;
7129
7130 tmp = tr32(SERDES_RX_CTRL);
7131 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7132 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7133 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7134 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7135 }
7136
7137 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7138 if (tp->link_config.phy_is_low_power) {
7139 tp->link_config.phy_is_low_power = 0;
7140 tp->link_config.speed = tp->link_config.orig_speed;
7141 tp->link_config.duplex = tp->link_config.orig_duplex;
7142 tp->link_config.autoneg = tp->link_config.orig_autoneg;
7143 }
7144
7145 err = tg3_setup_phy(tp, 0);
7146 if (err)
7147 return err;
7148
7149 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7150 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7151 u32 tmp;
7152
7153 /* Clear CRC stats. */
7154 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7155 tg3_writephy(tp, MII_TG3_TEST1,
7156 tmp | MII_TG3_TEST1_CRC_EN);
7157 tg3_readphy(tp, 0x14, &tmp);
7158 }
7159 }
7160 }
7161
7162 __tg3_set_rx_mode(tp->dev);
7163
7164 /* Initialize receive rules. */
7165 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
7166 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7167 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
7168 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7169
7170 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7171 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7172 limit = 8;
7173 else
7174 limit = 16;
7175 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7176 limit -= 4;
7177 switch (limit) {
7178 case 16:
7179 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
7180 case 15:
7181 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
7182 case 14:
7183 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
7184 case 13:
7185 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
7186 case 12:
7187 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
7188 case 11:
7189 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
7190 case 10:
7191 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
7192 case 9:
7193 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
7194 case 8:
7195 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
7196 case 7:
7197 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
7198 case 6:
7199 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
7200 case 5:
7201 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
7202 case 4:
7203 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7204 case 3:
7205 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7206 case 2:
7207 case 1:
7208
7209 default:
7210 break;
7211 }
7212
7213 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7214 /* Write our heartbeat update interval to APE. */
7215 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7216 APE_HOST_HEARTBEAT_INT_DISABLE);
7217
7218 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7219
7220 return 0;
7221 }
7222
7223 /* Called at device open time to get the chip ready for
7224 * packet processing. Invoked with tp->lock held.
7225 */
7226 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7227 {
7228 tg3_switch_clocks(tp);
7229
7230 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7231
7232 return tg3_reset_hw(tp, reset_phy);
7233 }
7234
7235 #define TG3_STAT_ADD32(PSTAT, REG) \
7236 do { u32 __val = tr32(REG); \
7237 (PSTAT)->low += __val; \
7238 if ((PSTAT)->low < __val) \
7239 (PSTAT)->high += 1; \
7240 } while (0)
7241
7242 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7243 {
7244 struct tg3_hw_stats *sp = tp->hw_stats;
7245
7246 if (!netif_carrier_ok(tp->dev))
7247 return;
7248
7249 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7250 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7251 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7252 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7253 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7254 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7255 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7256 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7257 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7258 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7259 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7260 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7261 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7262
7263 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7264 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7265 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7266 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7267 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7268 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7269 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7270 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7271 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7272 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7273 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7274 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7275 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7276 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7277
7278 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7279 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7280 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7281 }
7282
7283 static void tg3_timer(unsigned long __opaque)
7284 {
7285 struct tg3 *tp = (struct tg3 *) __opaque;
7286
7287 if (tp->irq_sync)
7288 goto restart_timer;
7289
7290 spin_lock(&tp->lock);
7291
7292 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7293 /* All of this garbage is because when using non-tagged
7294 * IRQ status the mailbox/status_block protocol the chip
7295 * uses with the cpu is race prone.
7296 */
7297 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7298 tw32(GRC_LOCAL_CTRL,
7299 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7300 } else {
7301 tw32(HOSTCC_MODE, tp->coalesce_mode |
7302 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7303 }
7304
7305 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7306 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7307 spin_unlock(&tp->lock);
7308 schedule_work(&tp->reset_task);
7309 return;
7310 }
7311 }
7312
7313 /* This part only runs once per second. */
7314 if (!--tp->timer_counter) {
7315 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7316 tg3_periodic_fetch_stats(tp);
7317
7318 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7319 u32 mac_stat;
7320 int phy_event;
7321
7322 mac_stat = tr32(MAC_STATUS);
7323
7324 phy_event = 0;
7325 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7326 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7327 phy_event = 1;
7328 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7329 phy_event = 1;
7330
7331 if (phy_event)
7332 tg3_setup_phy(tp, 0);
7333 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7334 u32 mac_stat = tr32(MAC_STATUS);
7335 int need_setup = 0;
7336
7337 if (netif_carrier_ok(tp->dev) &&
7338 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7339 need_setup = 1;
7340 }
7341 if (! netif_carrier_ok(tp->dev) &&
7342 (mac_stat & (MAC_STATUS_PCS_SYNCED |
7343 MAC_STATUS_SIGNAL_DET))) {
7344 need_setup = 1;
7345 }
7346 if (need_setup) {
7347 if (!tp->serdes_counter) {
7348 tw32_f(MAC_MODE,
7349 (tp->mac_mode &
7350 ~MAC_MODE_PORT_MODE_MASK));
7351 udelay(40);
7352 tw32_f(MAC_MODE, tp->mac_mode);
7353 udelay(40);
7354 }
7355 tg3_setup_phy(tp, 0);
7356 }
7357 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7358 tg3_serdes_parallel_detect(tp);
7359
7360 tp->timer_counter = tp->timer_multiplier;
7361 }
7362
7363 /* Heartbeat is only sent once every 2 seconds.
7364 *
7365 * The heartbeat is to tell the ASF firmware that the host
7366 * driver is still alive. In the event that the OS crashes,
7367 * ASF needs to reset the hardware to free up the FIFO space
7368 * that may be filled with rx packets destined for the host.
7369 * If the FIFO is full, ASF will no longer function properly.
7370 *
7371 * Unintended resets have been reported on real time kernels
7372 * where the timer doesn't run on time. Netpoll will also have
7373 * same problem.
7374 *
7375 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7376 * to check the ring condition when the heartbeat is expiring
7377 * before doing the reset. This will prevent most unintended
7378 * resets.
7379 */
7380 if (!--tp->asf_counter) {
7381 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7382 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7383 tg3_wait_for_event_ack(tp);
7384
7385 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7386 FWCMD_NICDRV_ALIVE3);
7387 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7388 /* 5 seconds timeout */
7389 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7390
7391 tg3_generate_fw_event(tp);
7392 }
7393 tp->asf_counter = tp->asf_multiplier;
7394 }
7395
7396 spin_unlock(&tp->lock);
7397
7398 restart_timer:
7399 tp->timer.expires = jiffies + tp->timer_offset;
7400 add_timer(&tp->timer);
7401 }
7402
7403 static int tg3_request_irq(struct tg3 *tp)
7404 {
7405 irq_handler_t fn;
7406 unsigned long flags;
7407 struct net_device *dev = tp->dev;
7408
7409 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7410 fn = tg3_msi;
7411 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7412 fn = tg3_msi_1shot;
7413 flags = IRQF_SAMPLE_RANDOM;
7414 } else {
7415 fn = tg3_interrupt;
7416 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7417 fn = tg3_interrupt_tagged;
7418 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7419 }
7420 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7421 }
7422
7423 static int tg3_test_interrupt(struct tg3 *tp)
7424 {
7425 struct net_device *dev = tp->dev;
7426 int err, i, intr_ok = 0;
7427
7428 if (!netif_running(dev))
7429 return -ENODEV;
7430
7431 tg3_disable_ints(tp);
7432
7433 free_irq(tp->pdev->irq, dev);
7434
7435 err = request_irq(tp->pdev->irq, tg3_test_isr,
7436 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7437 if (err)
7438 return err;
7439
7440 tp->hw_status->status &= ~SD_STATUS_UPDATED;
7441 tg3_enable_ints(tp);
7442
7443 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7444 HOSTCC_MODE_NOW);
7445
7446 for (i = 0; i < 5; i++) {
7447 u32 int_mbox, misc_host_ctrl;
7448
7449 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7450 TG3_64BIT_REG_LOW);
7451 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7452
7453 if ((int_mbox != 0) ||
7454 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7455 intr_ok = 1;
7456 break;
7457 }
7458
7459 msleep(10);
7460 }
7461
7462 tg3_disable_ints(tp);
7463
7464 free_irq(tp->pdev->irq, dev);
7465
7466 err = tg3_request_irq(tp);
7467
7468 if (err)
7469 return err;
7470
7471 if (intr_ok)
7472 return 0;
7473
7474 return -EIO;
7475 }
7476
7477 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7478 * successfully restored
7479 */
7480 static int tg3_test_msi(struct tg3 *tp)
7481 {
7482 struct net_device *dev = tp->dev;
7483 int err;
7484 u16 pci_cmd;
7485
7486 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7487 return 0;
7488
7489 /* Turn off SERR reporting in case MSI terminates with Master
7490 * Abort.
7491 */
7492 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7493 pci_write_config_word(tp->pdev, PCI_COMMAND,
7494 pci_cmd & ~PCI_COMMAND_SERR);
7495
7496 err = tg3_test_interrupt(tp);
7497
7498 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7499
7500 if (!err)
7501 return 0;
7502
7503 /* other failures */
7504 if (err != -EIO)
7505 return err;
7506
7507 /* MSI test failed, go back to INTx mode */
7508 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7509 "switching to INTx mode. Please report this failure to "
7510 "the PCI maintainer and include system chipset information.\n",
7511 tp->dev->name);
7512
7513 free_irq(tp->pdev->irq, dev);
7514 pci_disable_msi(tp->pdev);
7515
7516 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7517
7518 err = tg3_request_irq(tp);
7519 if (err)
7520 return err;
7521
7522 /* Need to reset the chip because the MSI cycle may have terminated
7523 * with Master Abort.
7524 */
7525 tg3_full_lock(tp, 1);
7526
7527 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7528 err = tg3_init_hw(tp, 1);
7529
7530 tg3_full_unlock(tp);
7531
7532 if (err)
7533 free_irq(tp->pdev->irq, dev);
7534
7535 return err;
7536 }
7537
7538 static int tg3_open(struct net_device *dev)
7539 {
7540 struct tg3 *tp = netdev_priv(dev);
7541 int err;
7542
7543 netif_carrier_off(tp->dev);
7544
7545 err = tg3_set_power_state(tp, PCI_D0);
7546 if (err)
7547 return err;
7548
7549 tg3_full_lock(tp, 0);
7550
7551 tg3_disable_ints(tp);
7552 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7553
7554 tg3_full_unlock(tp);
7555
7556 /* The placement of this call is tied
7557 * to the setup and use of Host TX descriptors.
7558 */
7559 err = tg3_alloc_consistent(tp);
7560 if (err)
7561 return err;
7562
7563 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7564 /* All MSI supporting chips should support tagged
7565 * status. Assert that this is the case.
7566 */
7567 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7568 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7569 "Not using MSI.\n", tp->dev->name);
7570 } else if (pci_enable_msi(tp->pdev) == 0) {
7571 u32 msi_mode;
7572
7573 msi_mode = tr32(MSGINT_MODE);
7574 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7575 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7576 }
7577 }
7578 err = tg3_request_irq(tp);
7579
7580 if (err) {
7581 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7582 pci_disable_msi(tp->pdev);
7583 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7584 }
7585 tg3_free_consistent(tp);
7586 return err;
7587 }
7588
7589 napi_enable(&tp->napi);
7590
7591 tg3_full_lock(tp, 0);
7592
7593 err = tg3_init_hw(tp, 1);
7594 if (err) {
7595 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7596 tg3_free_rings(tp);
7597 } else {
7598 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7599 tp->timer_offset = HZ;
7600 else
7601 tp->timer_offset = HZ / 10;
7602
7603 BUG_ON(tp->timer_offset > HZ);
7604 tp->timer_counter = tp->timer_multiplier =
7605 (HZ / tp->timer_offset);
7606 tp->asf_counter = tp->asf_multiplier =
7607 ((HZ / tp->timer_offset) * 2);
7608
7609 init_timer(&tp->timer);
7610 tp->timer.expires = jiffies + tp->timer_offset;
7611 tp->timer.data = (unsigned long) tp;
7612 tp->timer.function = tg3_timer;
7613 }
7614
7615 tg3_full_unlock(tp);
7616
7617 if (err) {
7618 napi_disable(&tp->napi);
7619 free_irq(tp->pdev->irq, dev);
7620 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7621 pci_disable_msi(tp->pdev);
7622 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7623 }
7624 tg3_free_consistent(tp);
7625 return err;
7626 }
7627
7628 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7629 err = tg3_test_msi(tp);
7630
7631 if (err) {
7632 tg3_full_lock(tp, 0);
7633
7634 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7635 pci_disable_msi(tp->pdev);
7636 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7637 }
7638 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7639 tg3_free_rings(tp);
7640 tg3_free_consistent(tp);
7641
7642 tg3_full_unlock(tp);
7643
7644 napi_disable(&tp->napi);
7645
7646 return err;
7647 }
7648
7649 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7650 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7651 u32 val = tr32(PCIE_TRANSACTION_CFG);
7652
7653 tw32(PCIE_TRANSACTION_CFG,
7654 val | PCIE_TRANS_CFG_1SHOT_MSI);
7655 }
7656 }
7657 }
7658
7659 tg3_phy_start(tp);
7660
7661 tg3_full_lock(tp, 0);
7662
7663 add_timer(&tp->timer);
7664 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7665 tg3_enable_ints(tp);
7666
7667 tg3_full_unlock(tp);
7668
7669 netif_start_queue(dev);
7670
7671 return 0;
7672 }
7673
7674 #if 0
7675 /*static*/ void tg3_dump_state(struct tg3 *tp)
7676 {
7677 u32 val32, val32_2, val32_3, val32_4, val32_5;
7678 u16 val16;
7679 int i;
7680
7681 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7682 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7683 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7684 val16, val32);
7685
7686 /* MAC block */
7687 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7688 tr32(MAC_MODE), tr32(MAC_STATUS));
7689 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7690 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7691 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7692 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7693 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7694 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7695
7696 /* Send data initiator control block */
7697 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7698 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7699 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7700 tr32(SNDDATAI_STATSCTRL));
7701
7702 /* Send data completion control block */
7703 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7704
7705 /* Send BD ring selector block */
7706 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7707 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7708
7709 /* Send BD initiator control block */
7710 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7711 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7712
7713 /* Send BD completion control block */
7714 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7715
7716 /* Receive list placement control block */
7717 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7718 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7719 printk(" RCVLPC_STATSCTRL[%08x]\n",
7720 tr32(RCVLPC_STATSCTRL));
7721
7722 /* Receive data and receive BD initiator control block */
7723 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7724 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7725
7726 /* Receive data completion control block */
7727 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7728 tr32(RCVDCC_MODE));
7729
7730 /* Receive BD initiator control block */
7731 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7732 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7733
7734 /* Receive BD completion control block */
7735 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7736 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7737
7738 /* Receive list selector control block */
7739 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7740 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7741
7742 /* Mbuf cluster free block */
7743 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7744 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7745
7746 /* Host coalescing control block */
7747 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7748 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7749 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7750 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7751 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7752 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7753 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7754 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7755 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7756 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7757 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7758 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7759
7760 /* Memory arbiter control block */
7761 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7762 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7763
7764 /* Buffer manager control block */
7765 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7766 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7767 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7768 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7769 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7770 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7771 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7772 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7773
7774 /* Read DMA control block */
7775 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7776 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7777
7778 /* Write DMA control block */
7779 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7780 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7781
7782 /* DMA completion block */
7783 printk("DEBUG: DMAC_MODE[%08x]\n",
7784 tr32(DMAC_MODE));
7785
7786 /* GRC block */
7787 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7788 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7789 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7790 tr32(GRC_LOCAL_CTRL));
7791
7792 /* TG3_BDINFOs */
7793 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7794 tr32(RCVDBDI_JUMBO_BD + 0x0),
7795 tr32(RCVDBDI_JUMBO_BD + 0x4),
7796 tr32(RCVDBDI_JUMBO_BD + 0x8),
7797 tr32(RCVDBDI_JUMBO_BD + 0xc));
7798 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7799 tr32(RCVDBDI_STD_BD + 0x0),
7800 tr32(RCVDBDI_STD_BD + 0x4),
7801 tr32(RCVDBDI_STD_BD + 0x8),
7802 tr32(RCVDBDI_STD_BD + 0xc));
7803 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7804 tr32(RCVDBDI_MINI_BD + 0x0),
7805 tr32(RCVDBDI_MINI_BD + 0x4),
7806 tr32(RCVDBDI_MINI_BD + 0x8),
7807 tr32(RCVDBDI_MINI_BD + 0xc));
7808
7809 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7810 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7811 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7812 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7813 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7814 val32, val32_2, val32_3, val32_4);
7815
7816 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7817 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7818 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7819 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7820 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7821 val32, val32_2, val32_3, val32_4);
7822
7823 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7824 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7825 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7826 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7827 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7828 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7829 val32, val32_2, val32_3, val32_4, val32_5);
7830
7831 /* SW status block */
7832 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7833 tp->hw_status->status,
7834 tp->hw_status->status_tag,
7835 tp->hw_status->rx_jumbo_consumer,
7836 tp->hw_status->rx_consumer,
7837 tp->hw_status->rx_mini_consumer,
7838 tp->hw_status->idx[0].rx_producer,
7839 tp->hw_status->idx[0].tx_consumer);
7840
7841 /* SW statistics block */
7842 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7843 ((u32 *)tp->hw_stats)[0],
7844 ((u32 *)tp->hw_stats)[1],
7845 ((u32 *)tp->hw_stats)[2],
7846 ((u32 *)tp->hw_stats)[3]);
7847
7848 /* Mailboxes */
7849 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7850 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7851 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7852 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7853 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7854
7855 /* NIC side send descriptors. */
7856 for (i = 0; i < 6; i++) {
7857 unsigned long txd;
7858
7859 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7860 + (i * sizeof(struct tg3_tx_buffer_desc));
7861 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7862 i,
7863 readl(txd + 0x0), readl(txd + 0x4),
7864 readl(txd + 0x8), readl(txd + 0xc));
7865 }
7866
7867 /* NIC side RX descriptors. */
7868 for (i = 0; i < 6; i++) {
7869 unsigned long rxd;
7870
7871 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7872 + (i * sizeof(struct tg3_rx_buffer_desc));
7873 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7874 i,
7875 readl(rxd + 0x0), readl(rxd + 0x4),
7876 readl(rxd + 0x8), readl(rxd + 0xc));
7877 rxd += (4 * sizeof(u32));
7878 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7879 i,
7880 readl(rxd + 0x0), readl(rxd + 0x4),
7881 readl(rxd + 0x8), readl(rxd + 0xc));
7882 }
7883
7884 for (i = 0; i < 6; i++) {
7885 unsigned long rxd;
7886
7887 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7888 + (i * sizeof(struct tg3_rx_buffer_desc));
7889 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7890 i,
7891 readl(rxd + 0x0), readl(rxd + 0x4),
7892 readl(rxd + 0x8), readl(rxd + 0xc));
7893 rxd += (4 * sizeof(u32));
7894 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7895 i,
7896 readl(rxd + 0x0), readl(rxd + 0x4),
7897 readl(rxd + 0x8), readl(rxd + 0xc));
7898 }
7899 }
7900 #endif
7901
7902 static struct net_device_stats *tg3_get_stats(struct net_device *);
7903 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7904
7905 static int tg3_close(struct net_device *dev)
7906 {
7907 struct tg3 *tp = netdev_priv(dev);
7908
7909 napi_disable(&tp->napi);
7910 cancel_work_sync(&tp->reset_task);
7911
7912 netif_stop_queue(dev);
7913
7914 del_timer_sync(&tp->timer);
7915
7916 tg3_full_lock(tp, 1);
7917 #if 0
7918 tg3_dump_state(tp);
7919 #endif
7920
7921 tg3_disable_ints(tp);
7922
7923 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7924 tg3_free_rings(tp);
7925 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7926
7927 tg3_full_unlock(tp);
7928
7929 free_irq(tp->pdev->irq, dev);
7930 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7931 pci_disable_msi(tp->pdev);
7932 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7933 }
7934
7935 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7936 sizeof(tp->net_stats_prev));
7937 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7938 sizeof(tp->estats_prev));
7939
7940 tg3_free_consistent(tp);
7941
7942 tg3_set_power_state(tp, PCI_D3hot);
7943
7944 netif_carrier_off(tp->dev);
7945
7946 return 0;
7947 }
7948
7949 static inline unsigned long get_stat64(tg3_stat64_t *val)
7950 {
7951 unsigned long ret;
7952
7953 #if (BITS_PER_LONG == 32)
7954 ret = val->low;
7955 #else
7956 ret = ((u64)val->high << 32) | ((u64)val->low);
7957 #endif
7958 return ret;
7959 }
7960
7961 static inline u64 get_estat64(tg3_stat64_t *val)
7962 {
7963 return ((u64)val->high << 32) | ((u64)val->low);
7964 }
7965
7966 static unsigned long calc_crc_errors(struct tg3 *tp)
7967 {
7968 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7969
7970 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7971 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7972 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7973 u32 val;
7974
7975 spin_lock_bh(&tp->lock);
7976 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7977 tg3_writephy(tp, MII_TG3_TEST1,
7978 val | MII_TG3_TEST1_CRC_EN);
7979 tg3_readphy(tp, 0x14, &val);
7980 } else
7981 val = 0;
7982 spin_unlock_bh(&tp->lock);
7983
7984 tp->phy_crc_errors += val;
7985
7986 return tp->phy_crc_errors;
7987 }
7988
7989 return get_stat64(&hw_stats->rx_fcs_errors);
7990 }
7991
7992 #define ESTAT_ADD(member) \
7993 estats->member = old_estats->member + \
7994 get_estat64(&hw_stats->member)
7995
7996 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7997 {
7998 struct tg3_ethtool_stats *estats = &tp->estats;
7999 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8000 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8001
8002 if (!hw_stats)
8003 return old_estats;
8004
8005 ESTAT_ADD(rx_octets);
8006 ESTAT_ADD(rx_fragments);
8007 ESTAT_ADD(rx_ucast_packets);
8008 ESTAT_ADD(rx_mcast_packets);
8009 ESTAT_ADD(rx_bcast_packets);
8010 ESTAT_ADD(rx_fcs_errors);
8011 ESTAT_ADD(rx_align_errors);
8012 ESTAT_ADD(rx_xon_pause_rcvd);
8013 ESTAT_ADD(rx_xoff_pause_rcvd);
8014 ESTAT_ADD(rx_mac_ctrl_rcvd);
8015 ESTAT_ADD(rx_xoff_entered);
8016 ESTAT_ADD(rx_frame_too_long_errors);
8017 ESTAT_ADD(rx_jabbers);
8018 ESTAT_ADD(rx_undersize_packets);
8019 ESTAT_ADD(rx_in_length_errors);
8020 ESTAT_ADD(rx_out_length_errors);
8021 ESTAT_ADD(rx_64_or_less_octet_packets);
8022 ESTAT_ADD(rx_65_to_127_octet_packets);
8023 ESTAT_ADD(rx_128_to_255_octet_packets);
8024 ESTAT_ADD(rx_256_to_511_octet_packets);
8025 ESTAT_ADD(rx_512_to_1023_octet_packets);
8026 ESTAT_ADD(rx_1024_to_1522_octet_packets);
8027 ESTAT_ADD(rx_1523_to_2047_octet_packets);
8028 ESTAT_ADD(rx_2048_to_4095_octet_packets);
8029 ESTAT_ADD(rx_4096_to_8191_octet_packets);
8030 ESTAT_ADD(rx_8192_to_9022_octet_packets);
8031
8032 ESTAT_ADD(tx_octets);
8033 ESTAT_ADD(tx_collisions);
8034 ESTAT_ADD(tx_xon_sent);
8035 ESTAT_ADD(tx_xoff_sent);
8036 ESTAT_ADD(tx_flow_control);
8037 ESTAT_ADD(tx_mac_errors);
8038 ESTAT_ADD(tx_single_collisions);
8039 ESTAT_ADD(tx_mult_collisions);
8040 ESTAT_ADD(tx_deferred);
8041 ESTAT_ADD(tx_excessive_collisions);
8042 ESTAT_ADD(tx_late_collisions);
8043 ESTAT_ADD(tx_collide_2times);
8044 ESTAT_ADD(tx_collide_3times);
8045 ESTAT_ADD(tx_collide_4times);
8046 ESTAT_ADD(tx_collide_5times);
8047 ESTAT_ADD(tx_collide_6times);
8048 ESTAT_ADD(tx_collide_7times);
8049 ESTAT_ADD(tx_collide_8times);
8050 ESTAT_ADD(tx_collide_9times);
8051 ESTAT_ADD(tx_collide_10times);
8052 ESTAT_ADD(tx_collide_11times);
8053 ESTAT_ADD(tx_collide_12times);
8054 ESTAT_ADD(tx_collide_13times);
8055 ESTAT_ADD(tx_collide_14times);
8056 ESTAT_ADD(tx_collide_15times);
8057 ESTAT_ADD(tx_ucast_packets);
8058 ESTAT_ADD(tx_mcast_packets);
8059 ESTAT_ADD(tx_bcast_packets);
8060 ESTAT_ADD(tx_carrier_sense_errors);
8061 ESTAT_ADD(tx_discards);
8062 ESTAT_ADD(tx_errors);
8063
8064 ESTAT_ADD(dma_writeq_full);
8065 ESTAT_ADD(dma_write_prioq_full);
8066 ESTAT_ADD(rxbds_empty);
8067 ESTAT_ADD(rx_discards);
8068 ESTAT_ADD(rx_errors);
8069 ESTAT_ADD(rx_threshold_hit);
8070
8071 ESTAT_ADD(dma_readq_full);
8072 ESTAT_ADD(dma_read_prioq_full);
8073 ESTAT_ADD(tx_comp_queue_full);
8074
8075 ESTAT_ADD(ring_set_send_prod_index);
8076 ESTAT_ADD(ring_status_update);
8077 ESTAT_ADD(nic_irqs);
8078 ESTAT_ADD(nic_avoided_irqs);
8079 ESTAT_ADD(nic_tx_threshold_hit);
8080
8081 return estats;
8082 }
8083
8084 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8085 {
8086 struct tg3 *tp = netdev_priv(dev);
8087 struct net_device_stats *stats = &tp->net_stats;
8088 struct net_device_stats *old_stats = &tp->net_stats_prev;
8089 struct tg3_hw_stats *hw_stats = tp->hw_stats;
8090
8091 if (!hw_stats)
8092 return old_stats;
8093
8094 stats->rx_packets = old_stats->rx_packets +
8095 get_stat64(&hw_stats->rx_ucast_packets) +
8096 get_stat64(&hw_stats->rx_mcast_packets) +
8097 get_stat64(&hw_stats->rx_bcast_packets);
8098
8099 stats->tx_packets = old_stats->tx_packets +
8100 get_stat64(&hw_stats->tx_ucast_packets) +
8101 get_stat64(&hw_stats->tx_mcast_packets) +
8102 get_stat64(&hw_stats->tx_bcast_packets);
8103
8104 stats->rx_bytes = old_stats->rx_bytes +
8105 get_stat64(&hw_stats->rx_octets);
8106 stats->tx_bytes = old_stats->tx_bytes +
8107 get_stat64(&hw_stats->tx_octets);
8108
8109 stats->rx_errors = old_stats->rx_errors +
8110 get_stat64(&hw_stats->rx_errors);
8111 stats->tx_errors = old_stats->tx_errors +
8112 get_stat64(&hw_stats->tx_errors) +
8113 get_stat64(&hw_stats->tx_mac_errors) +
8114 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8115 get_stat64(&hw_stats->tx_discards);
8116
8117 stats->multicast = old_stats->multicast +
8118 get_stat64(&hw_stats->rx_mcast_packets);
8119 stats->collisions = old_stats->collisions +
8120 get_stat64(&hw_stats->tx_collisions);
8121
8122 stats->rx_length_errors = old_stats->rx_length_errors +
8123 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8124 get_stat64(&hw_stats->rx_undersize_packets);
8125
8126 stats->rx_over_errors = old_stats->rx_over_errors +
8127 get_stat64(&hw_stats->rxbds_empty);
8128 stats->rx_frame_errors = old_stats->rx_frame_errors +
8129 get_stat64(&hw_stats->rx_align_errors);
8130 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8131 get_stat64(&hw_stats->tx_discards);
8132 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8133 get_stat64(&hw_stats->tx_carrier_sense_errors);
8134
8135 stats->rx_crc_errors = old_stats->rx_crc_errors +
8136 calc_crc_errors(tp);
8137
8138 stats->rx_missed_errors = old_stats->rx_missed_errors +
8139 get_stat64(&hw_stats->rx_discards);
8140
8141 return stats;
8142 }
8143
8144 static inline u32 calc_crc(unsigned char *buf, int len)
8145 {
8146 u32 reg;
8147 u32 tmp;
8148 int j, k;
8149
8150 reg = 0xffffffff;
8151
8152 for (j = 0; j < len; j++) {
8153 reg ^= buf[j];
8154
8155 for (k = 0; k < 8; k++) {
8156 tmp = reg & 0x01;
8157
8158 reg >>= 1;
8159
8160 if (tmp) {
8161 reg ^= 0xedb88320;
8162 }
8163 }
8164 }
8165
8166 return ~reg;
8167 }
8168
8169 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8170 {
8171 /* accept or reject all multicast frames */
8172 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8173 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8174 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8175 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8176 }
8177
8178 static void __tg3_set_rx_mode(struct net_device *dev)
8179 {
8180 struct tg3 *tp = netdev_priv(dev);
8181 u32 rx_mode;
8182
8183 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8184 RX_MODE_KEEP_VLAN_TAG);
8185
8186 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8187 * flag clear.
8188 */
8189 #if TG3_VLAN_TAG_USED
8190 if (!tp->vlgrp &&
8191 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8192 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8193 #else
8194 /* By definition, VLAN is disabled always in this
8195 * case.
8196 */
8197 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8198 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8199 #endif
8200
8201 if (dev->flags & IFF_PROMISC) {
8202 /* Promiscuous mode. */
8203 rx_mode |= RX_MODE_PROMISC;
8204 } else if (dev->flags & IFF_ALLMULTI) {
8205 /* Accept all multicast. */
8206 tg3_set_multi (tp, 1);
8207 } else if (dev->mc_count < 1) {
8208 /* Reject all multicast. */
8209 tg3_set_multi (tp, 0);
8210 } else {
8211 /* Accept one or more multicast(s). */
8212 struct dev_mc_list *mclist;
8213 unsigned int i;
8214 u32 mc_filter[4] = { 0, };
8215 u32 regidx;
8216 u32 bit;
8217 u32 crc;
8218
8219 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8220 i++, mclist = mclist->next) {
8221
8222 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8223 bit = ~crc & 0x7f;
8224 regidx = (bit & 0x60) >> 5;
8225 bit &= 0x1f;
8226 mc_filter[regidx] |= (1 << bit);
8227 }
8228
8229 tw32(MAC_HASH_REG_0, mc_filter[0]);
8230 tw32(MAC_HASH_REG_1, mc_filter[1]);
8231 tw32(MAC_HASH_REG_2, mc_filter[2]);
8232 tw32(MAC_HASH_REG_3, mc_filter[3]);
8233 }
8234
8235 if (rx_mode != tp->rx_mode) {
8236 tp->rx_mode = rx_mode;
8237 tw32_f(MAC_RX_MODE, rx_mode);
8238 udelay(10);
8239 }
8240 }
8241
8242 static void tg3_set_rx_mode(struct net_device *dev)
8243 {
8244 struct tg3 *tp = netdev_priv(dev);
8245
8246 if (!netif_running(dev))
8247 return;
8248
8249 tg3_full_lock(tp, 0);
8250 __tg3_set_rx_mode(dev);
8251 tg3_full_unlock(tp);
8252 }
8253
8254 #define TG3_REGDUMP_LEN (32 * 1024)
8255
8256 static int tg3_get_regs_len(struct net_device *dev)
8257 {
8258 return TG3_REGDUMP_LEN;
8259 }
8260
8261 static void tg3_get_regs(struct net_device *dev,
8262 struct ethtool_regs *regs, void *_p)
8263 {
8264 u32 *p = _p;
8265 struct tg3 *tp = netdev_priv(dev);
8266 u8 *orig_p = _p;
8267 int i;
8268
8269 regs->version = 0;
8270
8271 memset(p, 0, TG3_REGDUMP_LEN);
8272
8273 if (tp->link_config.phy_is_low_power)
8274 return;
8275
8276 tg3_full_lock(tp, 0);
8277
8278 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8279 #define GET_REG32_LOOP(base,len) \
8280 do { p = (u32 *)(orig_p + (base)); \
8281 for (i = 0; i < len; i += 4) \
8282 __GET_REG32((base) + i); \
8283 } while (0)
8284 #define GET_REG32_1(reg) \
8285 do { p = (u32 *)(orig_p + (reg)); \
8286 __GET_REG32((reg)); \
8287 } while (0)
8288
8289 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8290 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8291 GET_REG32_LOOP(MAC_MODE, 0x4f0);
8292 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8293 GET_REG32_1(SNDDATAC_MODE);
8294 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8295 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8296 GET_REG32_1(SNDBDC_MODE);
8297 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8298 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8299 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8300 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8301 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8302 GET_REG32_1(RCVDCC_MODE);
8303 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8304 GET_REG32_LOOP(RCVCC_MODE, 0x14);
8305 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8306 GET_REG32_1(MBFREE_MODE);
8307 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8308 GET_REG32_LOOP(MEMARB_MODE, 0x10);
8309 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8310 GET_REG32_LOOP(RDMAC_MODE, 0x08);
8311 GET_REG32_LOOP(WDMAC_MODE, 0x08);
8312 GET_REG32_1(RX_CPU_MODE);
8313 GET_REG32_1(RX_CPU_STATE);
8314 GET_REG32_1(RX_CPU_PGMCTR);
8315 GET_REG32_1(RX_CPU_HWBKPT);
8316 GET_REG32_1(TX_CPU_MODE);
8317 GET_REG32_1(TX_CPU_STATE);
8318 GET_REG32_1(TX_CPU_PGMCTR);
8319 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8320 GET_REG32_LOOP(FTQ_RESET, 0x120);
8321 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8322 GET_REG32_1(DMAC_MODE);
8323 GET_REG32_LOOP(GRC_MODE, 0x4c);
8324 if (tp->tg3_flags & TG3_FLAG_NVRAM)
8325 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8326
8327 #undef __GET_REG32
8328 #undef GET_REG32_LOOP
8329 #undef GET_REG32_1
8330
8331 tg3_full_unlock(tp);
8332 }
8333
8334 static int tg3_get_eeprom_len(struct net_device *dev)
8335 {
8336 struct tg3 *tp = netdev_priv(dev);
8337
8338 return tp->nvram_size;
8339 }
8340
8341 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
8342 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
8343 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
8344
8345 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8346 {
8347 struct tg3 *tp = netdev_priv(dev);
8348 int ret;
8349 u8 *pd;
8350 u32 i, offset, len, b_offset, b_count;
8351 __le32 val;
8352
8353 if (tp->link_config.phy_is_low_power)
8354 return -EAGAIN;
8355
8356 offset = eeprom->offset;
8357 len = eeprom->len;
8358 eeprom->len = 0;
8359
8360 eeprom->magic = TG3_EEPROM_MAGIC;
8361
8362 if (offset & 3) {
8363 /* adjustments to start on required 4 byte boundary */
8364 b_offset = offset & 3;
8365 b_count = 4 - b_offset;
8366 if (b_count > len) {
8367 /* i.e. offset=1 len=2 */
8368 b_count = len;
8369 }
8370 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
8371 if (ret)
8372 return ret;
8373 memcpy(data, ((char*)&val) + b_offset, b_count);
8374 len -= b_count;
8375 offset += b_count;
8376 eeprom->len += b_count;
8377 }
8378
8379 /* read bytes upto the last 4 byte boundary */
8380 pd = &data[eeprom->len];
8381 for (i = 0; i < (len - (len & 3)); i += 4) {
8382 ret = tg3_nvram_read_le(tp, offset + i, &val);
8383 if (ret) {
8384 eeprom->len += i;
8385 return ret;
8386 }
8387 memcpy(pd + i, &val, 4);
8388 }
8389 eeprom->len += i;
8390
8391 if (len & 3) {
8392 /* read last bytes not ending on 4 byte boundary */
8393 pd = &data[eeprom->len];
8394 b_count = len & 3;
8395 b_offset = offset + len - b_count;
8396 ret = tg3_nvram_read_le(tp, b_offset, &val);
8397 if (ret)
8398 return ret;
8399 memcpy(pd, &val, b_count);
8400 eeprom->len += b_count;
8401 }
8402 return 0;
8403 }
8404
8405 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8406
8407 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8408 {
8409 struct tg3 *tp = netdev_priv(dev);
8410 int ret;
8411 u32 offset, len, b_offset, odd_len;
8412 u8 *buf;
8413 __le32 start, end;
8414
8415 if (tp->link_config.phy_is_low_power)
8416 return -EAGAIN;
8417
8418 if (eeprom->magic != TG3_EEPROM_MAGIC)
8419 return -EINVAL;
8420
8421 offset = eeprom->offset;
8422 len = eeprom->len;
8423
8424 if ((b_offset = (offset & 3))) {
8425 /* adjustments to start on required 4 byte boundary */
8426 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
8427 if (ret)
8428 return ret;
8429 len += b_offset;
8430 offset &= ~3;
8431 if (len < 4)
8432 len = 4;
8433 }
8434
8435 odd_len = 0;
8436 if (len & 3) {
8437 /* adjustments to end on required 4 byte boundary */
8438 odd_len = 1;
8439 len = (len + 3) & ~3;
8440 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
8441 if (ret)
8442 return ret;
8443 }
8444
8445 buf = data;
8446 if (b_offset || odd_len) {
8447 buf = kmalloc(len, GFP_KERNEL);
8448 if (!buf)
8449 return -ENOMEM;
8450 if (b_offset)
8451 memcpy(buf, &start, 4);
8452 if (odd_len)
8453 memcpy(buf+len-4, &end, 4);
8454 memcpy(buf + b_offset, data, eeprom->len);
8455 }
8456
8457 ret = tg3_nvram_write_block(tp, offset, len, buf);
8458
8459 if (buf != data)
8460 kfree(buf);
8461
8462 return ret;
8463 }
8464
8465 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8466 {
8467 struct tg3 *tp = netdev_priv(dev);
8468
8469 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8470 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8471 return -EAGAIN;
8472 return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8473 }
8474
8475 cmd->supported = (SUPPORTED_Autoneg);
8476
8477 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8478 cmd->supported |= (SUPPORTED_1000baseT_Half |
8479 SUPPORTED_1000baseT_Full);
8480
8481 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8482 cmd->supported |= (SUPPORTED_100baseT_Half |
8483 SUPPORTED_100baseT_Full |
8484 SUPPORTED_10baseT_Half |
8485 SUPPORTED_10baseT_Full |
8486 SUPPORTED_TP);
8487 cmd->port = PORT_TP;
8488 } else {
8489 cmd->supported |= SUPPORTED_FIBRE;
8490 cmd->port = PORT_FIBRE;
8491 }
8492
8493 cmd->advertising = tp->link_config.advertising;
8494 if (netif_running(dev)) {
8495 cmd->speed = tp->link_config.active_speed;
8496 cmd->duplex = tp->link_config.active_duplex;
8497 }
8498 cmd->phy_address = PHY_ADDR;
8499 cmd->transceiver = 0;
8500 cmd->autoneg = tp->link_config.autoneg;
8501 cmd->maxtxpkt = 0;
8502 cmd->maxrxpkt = 0;
8503 return 0;
8504 }
8505
8506 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8507 {
8508 struct tg3 *tp = netdev_priv(dev);
8509
8510 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8511 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8512 return -EAGAIN;
8513 return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
8514 }
8515
8516 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8517 /* These are the only valid advertisement bits allowed. */
8518 if (cmd->autoneg == AUTONEG_ENABLE &&
8519 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8520 ADVERTISED_1000baseT_Full |
8521 ADVERTISED_Autoneg |
8522 ADVERTISED_FIBRE)))
8523 return -EINVAL;
8524 /* Fiber can only do SPEED_1000. */
8525 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8526 (cmd->speed != SPEED_1000))
8527 return -EINVAL;
8528 /* Copper cannot force SPEED_1000. */
8529 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8530 (cmd->speed == SPEED_1000))
8531 return -EINVAL;
8532 else if ((cmd->speed == SPEED_1000) &&
8533 (tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8534 return -EINVAL;
8535
8536 tg3_full_lock(tp, 0);
8537
8538 tp->link_config.autoneg = cmd->autoneg;
8539 if (cmd->autoneg == AUTONEG_ENABLE) {
8540 tp->link_config.advertising = (cmd->advertising |
8541 ADVERTISED_Autoneg);
8542 tp->link_config.speed = SPEED_INVALID;
8543 tp->link_config.duplex = DUPLEX_INVALID;
8544 } else {
8545 tp->link_config.advertising = 0;
8546 tp->link_config.speed = cmd->speed;
8547 tp->link_config.duplex = cmd->duplex;
8548 }
8549
8550 tp->link_config.orig_speed = tp->link_config.speed;
8551 tp->link_config.orig_duplex = tp->link_config.duplex;
8552 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8553
8554 if (netif_running(dev))
8555 tg3_setup_phy(tp, 1);
8556
8557 tg3_full_unlock(tp);
8558
8559 return 0;
8560 }
8561
8562 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8563 {
8564 struct tg3 *tp = netdev_priv(dev);
8565
8566 strcpy(info->driver, DRV_MODULE_NAME);
8567 strcpy(info->version, DRV_MODULE_VERSION);
8568 strcpy(info->fw_version, tp->fw_ver);
8569 strcpy(info->bus_info, pci_name(tp->pdev));
8570 }
8571
8572 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8573 {
8574 struct tg3 *tp = netdev_priv(dev);
8575
8576 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
8577 device_can_wakeup(&tp->pdev->dev))
8578 wol->supported = WAKE_MAGIC;
8579 else
8580 wol->supported = 0;
8581 wol->wolopts = 0;
8582 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
8583 device_can_wakeup(&tp->pdev->dev))
8584 wol->wolopts = WAKE_MAGIC;
8585 memset(&wol->sopass, 0, sizeof(wol->sopass));
8586 }
8587
8588 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8589 {
8590 struct tg3 *tp = netdev_priv(dev);
8591 struct device *dp = &tp->pdev->dev;
8592
8593 if (wol->wolopts & ~WAKE_MAGIC)
8594 return -EINVAL;
8595 if ((wol->wolopts & WAKE_MAGIC) &&
8596 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
8597 return -EINVAL;
8598
8599 spin_lock_bh(&tp->lock);
8600 if (wol->wolopts & WAKE_MAGIC) {
8601 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8602 device_set_wakeup_enable(dp, true);
8603 } else {
8604 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8605 device_set_wakeup_enable(dp, false);
8606 }
8607 spin_unlock_bh(&tp->lock);
8608
8609 return 0;
8610 }
8611
8612 static u32 tg3_get_msglevel(struct net_device *dev)
8613 {
8614 struct tg3 *tp = netdev_priv(dev);
8615 return tp->msg_enable;
8616 }
8617
8618 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8619 {
8620 struct tg3 *tp = netdev_priv(dev);
8621 tp->msg_enable = value;
8622 }
8623
8624 static int tg3_set_tso(struct net_device *dev, u32 value)
8625 {
8626 struct tg3 *tp = netdev_priv(dev);
8627
8628 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8629 if (value)
8630 return -EINVAL;
8631 return 0;
8632 }
8633 if ((dev->features & NETIF_F_IPV6_CSUM) &&
8634 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)) {
8635 if (value) {
8636 dev->features |= NETIF_F_TSO6;
8637 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8638 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
8639 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
8640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8641 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8642 dev->features |= NETIF_F_TSO_ECN;
8643 } else
8644 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
8645 }
8646 return ethtool_op_set_tso(dev, value);
8647 }
8648
8649 static int tg3_nway_reset(struct net_device *dev)
8650 {
8651 struct tg3 *tp = netdev_priv(dev);
8652 int r;
8653
8654 if (!netif_running(dev))
8655 return -EAGAIN;
8656
8657 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8658 return -EINVAL;
8659
8660 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8661 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8662 return -EAGAIN;
8663 r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
8664 } else {
8665 u32 bmcr;
8666
8667 spin_lock_bh(&tp->lock);
8668 r = -EINVAL;
8669 tg3_readphy(tp, MII_BMCR, &bmcr);
8670 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8671 ((bmcr & BMCR_ANENABLE) ||
8672 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8673 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8674 BMCR_ANENABLE);
8675 r = 0;
8676 }
8677 spin_unlock_bh(&tp->lock);
8678 }
8679
8680 return r;
8681 }
8682
8683 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8684 {
8685 struct tg3 *tp = netdev_priv(dev);
8686
8687 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8688 ering->rx_mini_max_pending = 0;
8689 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8690 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8691 else
8692 ering->rx_jumbo_max_pending = 0;
8693
8694 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8695
8696 ering->rx_pending = tp->rx_pending;
8697 ering->rx_mini_pending = 0;
8698 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8699 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8700 else
8701 ering->rx_jumbo_pending = 0;
8702
8703 ering->tx_pending = tp->tx_pending;
8704 }
8705
8706 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8707 {
8708 struct tg3 *tp = netdev_priv(dev);
8709 int irq_sync = 0, err = 0;
8710
8711 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8712 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8713 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8714 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8715 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8716 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8717 return -EINVAL;
8718
8719 if (netif_running(dev)) {
8720 tg3_phy_stop(tp);
8721 tg3_netif_stop(tp);
8722 irq_sync = 1;
8723 }
8724
8725 tg3_full_lock(tp, irq_sync);
8726
8727 tp->rx_pending = ering->rx_pending;
8728
8729 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8730 tp->rx_pending > 63)
8731 tp->rx_pending = 63;
8732 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8733 tp->tx_pending = ering->tx_pending;
8734
8735 if (netif_running(dev)) {
8736 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8737 err = tg3_restart_hw(tp, 1);
8738 if (!err)
8739 tg3_netif_start(tp);
8740 }
8741
8742 tg3_full_unlock(tp);
8743
8744 if (irq_sync && !err)
8745 tg3_phy_start(tp);
8746
8747 return err;
8748 }
8749
8750 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8751 {
8752 struct tg3 *tp = netdev_priv(dev);
8753
8754 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8755
8756 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
8757 epause->rx_pause = 1;
8758 else
8759 epause->rx_pause = 0;
8760
8761 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
8762 epause->tx_pause = 1;
8763 else
8764 epause->tx_pause = 0;
8765 }
8766
8767 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8768 {
8769 struct tg3 *tp = netdev_priv(dev);
8770 int err = 0;
8771
8772 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8773 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8774 return -EAGAIN;
8775
8776 if (epause->autoneg) {
8777 u32 newadv;
8778 struct phy_device *phydev;
8779
8780 phydev = tp->mdio_bus->phy_map[PHY_ADDR];
8781
8782 if (epause->rx_pause) {
8783 if (epause->tx_pause)
8784 newadv = ADVERTISED_Pause;
8785 else
8786 newadv = ADVERTISED_Pause |
8787 ADVERTISED_Asym_Pause;
8788 } else if (epause->tx_pause) {
8789 newadv = ADVERTISED_Asym_Pause;
8790 } else
8791 newadv = 0;
8792
8793 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
8794 u32 oldadv = phydev->advertising &
8795 (ADVERTISED_Pause |
8796 ADVERTISED_Asym_Pause);
8797 if (oldadv != newadv) {
8798 phydev->advertising &=
8799 ~(ADVERTISED_Pause |
8800 ADVERTISED_Asym_Pause);
8801 phydev->advertising |= newadv;
8802 err = phy_start_aneg(phydev);
8803 }
8804 } else {
8805 tp->link_config.advertising &=
8806 ~(ADVERTISED_Pause |
8807 ADVERTISED_Asym_Pause);
8808 tp->link_config.advertising |= newadv;
8809 }
8810 } else {
8811 if (epause->rx_pause)
8812 tp->link_config.flowctrl |= FLOW_CTRL_RX;
8813 else
8814 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
8815
8816 if (epause->tx_pause)
8817 tp->link_config.flowctrl |= FLOW_CTRL_TX;
8818 else
8819 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
8820
8821 if (netif_running(dev))
8822 tg3_setup_flow_control(tp, 0, 0);
8823 }
8824 } else {
8825 int irq_sync = 0;
8826
8827 if (netif_running(dev)) {
8828 tg3_netif_stop(tp);
8829 irq_sync = 1;
8830 }
8831
8832 tg3_full_lock(tp, irq_sync);
8833
8834 if (epause->autoneg)
8835 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8836 else
8837 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8838 if (epause->rx_pause)
8839 tp->link_config.flowctrl |= FLOW_CTRL_RX;
8840 else
8841 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
8842 if (epause->tx_pause)
8843 tp->link_config.flowctrl |= FLOW_CTRL_TX;
8844 else
8845 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
8846
8847 if (netif_running(dev)) {
8848 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8849 err = tg3_restart_hw(tp, 1);
8850 if (!err)
8851 tg3_netif_start(tp);
8852 }
8853
8854 tg3_full_unlock(tp);
8855 }
8856
8857 return err;
8858 }
8859
8860 static u32 tg3_get_rx_csum(struct net_device *dev)
8861 {
8862 struct tg3 *tp = netdev_priv(dev);
8863 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8864 }
8865
8866 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8867 {
8868 struct tg3 *tp = netdev_priv(dev);
8869
8870 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8871 if (data != 0)
8872 return -EINVAL;
8873 return 0;
8874 }
8875
8876 spin_lock_bh(&tp->lock);
8877 if (data)
8878 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8879 else
8880 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8881 spin_unlock_bh(&tp->lock);
8882
8883 return 0;
8884 }
8885
8886 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8887 {
8888 struct tg3 *tp = netdev_priv(dev);
8889
8890 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8891 if (data != 0)
8892 return -EINVAL;
8893 return 0;
8894 }
8895
8896 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8897 ethtool_op_set_tx_ipv6_csum(dev, data);
8898 else
8899 ethtool_op_set_tx_csum(dev, data);
8900
8901 return 0;
8902 }
8903
8904 static int tg3_get_sset_count (struct net_device *dev, int sset)
8905 {
8906 switch (sset) {
8907 case ETH_SS_TEST:
8908 return TG3_NUM_TEST;
8909 case ETH_SS_STATS:
8910 return TG3_NUM_STATS;
8911 default:
8912 return -EOPNOTSUPP;
8913 }
8914 }
8915
8916 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8917 {
8918 switch (stringset) {
8919 case ETH_SS_STATS:
8920 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8921 break;
8922 case ETH_SS_TEST:
8923 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8924 break;
8925 default:
8926 WARN_ON(1); /* we need a WARN() */
8927 break;
8928 }
8929 }
8930
8931 static int tg3_phys_id(struct net_device *dev, u32 data)
8932 {
8933 struct tg3 *tp = netdev_priv(dev);
8934 int i;
8935
8936 if (!netif_running(tp->dev))
8937 return -EAGAIN;
8938
8939 if (data == 0)
8940 data = UINT_MAX / 2;
8941
8942 for (i = 0; i < (data * 2); i++) {
8943 if ((i % 2) == 0)
8944 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8945 LED_CTRL_1000MBPS_ON |
8946 LED_CTRL_100MBPS_ON |
8947 LED_CTRL_10MBPS_ON |
8948 LED_CTRL_TRAFFIC_OVERRIDE |
8949 LED_CTRL_TRAFFIC_BLINK |
8950 LED_CTRL_TRAFFIC_LED);
8951
8952 else
8953 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8954 LED_CTRL_TRAFFIC_OVERRIDE);
8955
8956 if (msleep_interruptible(500))
8957 break;
8958 }
8959 tw32(MAC_LED_CTRL, tp->led_ctrl);
8960 return 0;
8961 }
8962
8963 static void tg3_get_ethtool_stats (struct net_device *dev,
8964 struct ethtool_stats *estats, u64 *tmp_stats)
8965 {
8966 struct tg3 *tp = netdev_priv(dev);
8967 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8968 }
8969
8970 #define NVRAM_TEST_SIZE 0x100
8971 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
8972 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
8973 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
8974 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8975 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8976
8977 static int tg3_test_nvram(struct tg3 *tp)
8978 {
8979 u32 csum, magic;
8980 __le32 *buf;
8981 int i, j, k, err = 0, size;
8982
8983 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8984 return -EIO;
8985
8986 if (magic == TG3_EEPROM_MAGIC)
8987 size = NVRAM_TEST_SIZE;
8988 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8989 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
8990 TG3_EEPROM_SB_FORMAT_1) {
8991 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
8992 case TG3_EEPROM_SB_REVISION_0:
8993 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
8994 break;
8995 case TG3_EEPROM_SB_REVISION_2:
8996 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
8997 break;
8998 case TG3_EEPROM_SB_REVISION_3:
8999 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9000 break;
9001 default:
9002 return 0;
9003 }
9004 } else
9005 return 0;
9006 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9007 size = NVRAM_SELFBOOT_HW_SIZE;
9008 else
9009 return -EIO;
9010
9011 buf = kmalloc(size, GFP_KERNEL);
9012 if (buf == NULL)
9013 return -ENOMEM;
9014
9015 err = -EIO;
9016 for (i = 0, j = 0; i < size; i += 4, j++) {
9017 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
9018 break;
9019 }
9020 if (i < size)
9021 goto out;
9022
9023 /* Selfboot format */
9024 magic = swab32(le32_to_cpu(buf[0]));
9025 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9026 TG3_EEPROM_MAGIC_FW) {
9027 u8 *buf8 = (u8 *) buf, csum8 = 0;
9028
9029 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9030 TG3_EEPROM_SB_REVISION_2) {
9031 /* For rev 2, the csum doesn't include the MBA. */
9032 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9033 csum8 += buf8[i];
9034 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9035 csum8 += buf8[i];
9036 } else {
9037 for (i = 0; i < size; i++)
9038 csum8 += buf8[i];
9039 }
9040
9041 if (csum8 == 0) {
9042 err = 0;
9043 goto out;
9044 }
9045
9046 err = -EIO;
9047 goto out;
9048 }
9049
9050 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9051 TG3_EEPROM_MAGIC_HW) {
9052 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9053 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9054 u8 *buf8 = (u8 *) buf;
9055
9056 /* Separate the parity bits and the data bytes. */
9057 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9058 if ((i == 0) || (i == 8)) {
9059 int l;
9060 u8 msk;
9061
9062 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9063 parity[k++] = buf8[i] & msk;
9064 i++;
9065 }
9066 else if (i == 16) {
9067 int l;
9068 u8 msk;
9069
9070 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9071 parity[k++] = buf8[i] & msk;
9072 i++;
9073
9074 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9075 parity[k++] = buf8[i] & msk;
9076 i++;
9077 }
9078 data[j++] = buf8[i];
9079 }
9080
9081 err = -EIO;
9082 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9083 u8 hw8 = hweight8(data[i]);
9084
9085 if ((hw8 & 0x1) && parity[i])
9086 goto out;
9087 else if (!(hw8 & 0x1) && !parity[i])
9088 goto out;
9089 }
9090 err = 0;
9091 goto out;
9092 }
9093
9094 /* Bootstrap checksum at offset 0x10 */
9095 csum = calc_crc((unsigned char *) buf, 0x10);
9096 if(csum != le32_to_cpu(buf[0x10/4]))
9097 goto out;
9098
9099 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9100 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9101 if (csum != le32_to_cpu(buf[0xfc/4]))
9102 goto out;
9103
9104 err = 0;
9105
9106 out:
9107 kfree(buf);
9108 return err;
9109 }
9110
9111 #define TG3_SERDES_TIMEOUT_SEC 2
9112 #define TG3_COPPER_TIMEOUT_SEC 6
9113
9114 static int tg3_test_link(struct tg3 *tp)
9115 {
9116 int i, max;
9117
9118 if (!netif_running(tp->dev))
9119 return -ENODEV;
9120
9121 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9122 max = TG3_SERDES_TIMEOUT_SEC;
9123 else
9124 max = TG3_COPPER_TIMEOUT_SEC;
9125
9126 for (i = 0; i < max; i++) {
9127 if (netif_carrier_ok(tp->dev))
9128 return 0;
9129
9130 if (msleep_interruptible(1000))
9131 break;
9132 }
9133
9134 return -EIO;
9135 }
9136
9137 /* Only test the commonly used registers */
9138 static int tg3_test_registers(struct tg3 *tp)
9139 {
9140 int i, is_5705, is_5750;
9141 u32 offset, read_mask, write_mask, val, save_val, read_val;
9142 static struct {
9143 u16 offset;
9144 u16 flags;
9145 #define TG3_FL_5705 0x1
9146 #define TG3_FL_NOT_5705 0x2
9147 #define TG3_FL_NOT_5788 0x4
9148 #define TG3_FL_NOT_5750 0x8
9149 u32 read_mask;
9150 u32 write_mask;
9151 } reg_tbl[] = {
9152 /* MAC Control Registers */
9153 { MAC_MODE, TG3_FL_NOT_5705,
9154 0x00000000, 0x00ef6f8c },
9155 { MAC_MODE, TG3_FL_5705,
9156 0x00000000, 0x01ef6b8c },
9157 { MAC_STATUS, TG3_FL_NOT_5705,
9158 0x03800107, 0x00000000 },
9159 { MAC_STATUS, TG3_FL_5705,
9160 0x03800100, 0x00000000 },
9161 { MAC_ADDR_0_HIGH, 0x0000,
9162 0x00000000, 0x0000ffff },
9163 { MAC_ADDR_0_LOW, 0x0000,
9164 0x00000000, 0xffffffff },
9165 { MAC_RX_MTU_SIZE, 0x0000,
9166 0x00000000, 0x0000ffff },
9167 { MAC_TX_MODE, 0x0000,
9168 0x00000000, 0x00000070 },
9169 { MAC_TX_LENGTHS, 0x0000,
9170 0x00000000, 0x00003fff },
9171 { MAC_RX_MODE, TG3_FL_NOT_5705,
9172 0x00000000, 0x000007fc },
9173 { MAC_RX_MODE, TG3_FL_5705,
9174 0x00000000, 0x000007dc },
9175 { MAC_HASH_REG_0, 0x0000,
9176 0x00000000, 0xffffffff },
9177 { MAC_HASH_REG_1, 0x0000,
9178 0x00000000, 0xffffffff },
9179 { MAC_HASH_REG_2, 0x0000,
9180 0x00000000, 0xffffffff },
9181 { MAC_HASH_REG_3, 0x0000,
9182 0x00000000, 0xffffffff },
9183
9184 /* Receive Data and Receive BD Initiator Control Registers. */
9185 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9186 0x00000000, 0xffffffff },
9187 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9188 0x00000000, 0xffffffff },
9189 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9190 0x00000000, 0x00000003 },
9191 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9192 0x00000000, 0xffffffff },
9193 { RCVDBDI_STD_BD+0, 0x0000,
9194 0x00000000, 0xffffffff },
9195 { RCVDBDI_STD_BD+4, 0x0000,
9196 0x00000000, 0xffffffff },
9197 { RCVDBDI_STD_BD+8, 0x0000,
9198 0x00000000, 0xffff0002 },
9199 { RCVDBDI_STD_BD+0xc, 0x0000,
9200 0x00000000, 0xffffffff },
9201
9202 /* Receive BD Initiator Control Registers. */
9203 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9204 0x00000000, 0xffffffff },
9205 { RCVBDI_STD_THRESH, TG3_FL_5705,
9206 0x00000000, 0x000003ff },
9207 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9208 0x00000000, 0xffffffff },
9209
9210 /* Host Coalescing Control Registers. */
9211 { HOSTCC_MODE, TG3_FL_NOT_5705,
9212 0x00000000, 0x00000004 },
9213 { HOSTCC_MODE, TG3_FL_5705,
9214 0x00000000, 0x000000f6 },
9215 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9216 0x00000000, 0xffffffff },
9217 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9218 0x00000000, 0x000003ff },
9219 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9220 0x00000000, 0xffffffff },
9221 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9222 0x00000000, 0x000003ff },
9223 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9224 0x00000000, 0xffffffff },
9225 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9226 0x00000000, 0x000000ff },
9227 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9228 0x00000000, 0xffffffff },
9229 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9230 0x00000000, 0x000000ff },
9231 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9232 0x00000000, 0xffffffff },
9233 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9234 0x00000000, 0xffffffff },
9235 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9236 0x00000000, 0xffffffff },
9237 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9238 0x00000000, 0x000000ff },
9239 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9240 0x00000000, 0xffffffff },
9241 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9242 0x00000000, 0x000000ff },
9243 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9244 0x00000000, 0xffffffff },
9245 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9246 0x00000000, 0xffffffff },
9247 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9248 0x00000000, 0xffffffff },
9249 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9250 0x00000000, 0xffffffff },
9251 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9252 0x00000000, 0xffffffff },
9253 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9254 0xffffffff, 0x00000000 },
9255 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9256 0xffffffff, 0x00000000 },
9257
9258 /* Buffer Manager Control Registers. */
9259 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9260 0x00000000, 0x007fff80 },
9261 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9262 0x00000000, 0x007fffff },
9263 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9264 0x00000000, 0x0000003f },
9265 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9266 0x00000000, 0x000001ff },
9267 { BUFMGR_MB_HIGH_WATER, 0x0000,
9268 0x00000000, 0x000001ff },
9269 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9270 0xffffffff, 0x00000000 },
9271 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9272 0xffffffff, 0x00000000 },
9273
9274 /* Mailbox Registers */
9275 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9276 0x00000000, 0x000001ff },
9277 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9278 0x00000000, 0x000001ff },
9279 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9280 0x00000000, 0x000007ff },
9281 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9282 0x00000000, 0x000001ff },
9283
9284 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9285 };
9286
9287 is_5705 = is_5750 = 0;
9288 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9289 is_5705 = 1;
9290 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9291 is_5750 = 1;
9292 }
9293
9294 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9295 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9296 continue;
9297
9298 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9299 continue;
9300
9301 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9302 (reg_tbl[i].flags & TG3_FL_NOT_5788))
9303 continue;
9304
9305 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9306 continue;
9307
9308 offset = (u32) reg_tbl[i].offset;
9309 read_mask = reg_tbl[i].read_mask;
9310 write_mask = reg_tbl[i].write_mask;
9311
9312 /* Save the original register content */
9313 save_val = tr32(offset);
9314
9315 /* Determine the read-only value. */
9316 read_val = save_val & read_mask;
9317
9318 /* Write zero to the register, then make sure the read-only bits
9319 * are not changed and the read/write bits are all zeros.
9320 */
9321 tw32(offset, 0);
9322
9323 val = tr32(offset);
9324
9325 /* Test the read-only and read/write bits. */
9326 if (((val & read_mask) != read_val) || (val & write_mask))
9327 goto out;
9328
9329 /* Write ones to all the bits defined by RdMask and WrMask, then
9330 * make sure the read-only bits are not changed and the
9331 * read/write bits are all ones.
9332 */
9333 tw32(offset, read_mask | write_mask);
9334
9335 val = tr32(offset);
9336
9337 /* Test the read-only bits. */
9338 if ((val & read_mask) != read_val)
9339 goto out;
9340
9341 /* Test the read/write bits. */
9342 if ((val & write_mask) != write_mask)
9343 goto out;
9344
9345 tw32(offset, save_val);
9346 }
9347
9348 return 0;
9349
9350 out:
9351 if (netif_msg_hw(tp))
9352 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9353 offset);
9354 tw32(offset, save_val);
9355 return -EIO;
9356 }
9357
9358 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9359 {
9360 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9361 int i;
9362 u32 j;
9363
9364 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9365 for (j = 0; j < len; j += 4) {
9366 u32 val;
9367
9368 tg3_write_mem(tp, offset + j, test_pattern[i]);
9369 tg3_read_mem(tp, offset + j, &val);
9370 if (val != test_pattern[i])
9371 return -EIO;
9372 }
9373 }
9374 return 0;
9375 }
9376
9377 static int tg3_test_memory(struct tg3 *tp)
9378 {
9379 static struct mem_entry {
9380 u32 offset;
9381 u32 len;
9382 } mem_tbl_570x[] = {
9383 { 0x00000000, 0x00b50},
9384 { 0x00002000, 0x1c000},
9385 { 0xffffffff, 0x00000}
9386 }, mem_tbl_5705[] = {
9387 { 0x00000100, 0x0000c},
9388 { 0x00000200, 0x00008},
9389 { 0x00004000, 0x00800},
9390 { 0x00006000, 0x01000},
9391 { 0x00008000, 0x02000},
9392 { 0x00010000, 0x0e000},
9393 { 0xffffffff, 0x00000}
9394 }, mem_tbl_5755[] = {
9395 { 0x00000200, 0x00008},
9396 { 0x00004000, 0x00800},
9397 { 0x00006000, 0x00800},
9398 { 0x00008000, 0x02000},
9399 { 0x00010000, 0x0c000},
9400 { 0xffffffff, 0x00000}
9401 }, mem_tbl_5906[] = {
9402 { 0x00000200, 0x00008},
9403 { 0x00004000, 0x00400},
9404 { 0x00006000, 0x00400},
9405 { 0x00008000, 0x01000},
9406 { 0x00010000, 0x01000},
9407 { 0xffffffff, 0x00000}
9408 };
9409 struct mem_entry *mem_tbl;
9410 int err = 0;
9411 int i;
9412
9413 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
9414 mem_tbl = mem_tbl_5755;
9415 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9416 mem_tbl = mem_tbl_5906;
9417 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9418 mem_tbl = mem_tbl_5705;
9419 else
9420 mem_tbl = mem_tbl_570x;
9421
9422 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9423 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9424 mem_tbl[i].len)) != 0)
9425 break;
9426 }
9427
9428 return err;
9429 }
9430
9431 #define TG3_MAC_LOOPBACK 0
9432 #define TG3_PHY_LOOPBACK 1
9433
9434 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9435 {
9436 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9437 u32 desc_idx;
9438 struct sk_buff *skb, *rx_skb;
9439 u8 *tx_data;
9440 dma_addr_t map;
9441 int num_pkts, tx_len, rx_len, i, err;
9442 struct tg3_rx_buffer_desc *desc;
9443
9444 if (loopback_mode == TG3_MAC_LOOPBACK) {
9445 /* HW errata - mac loopback fails in some cases on 5780.
9446 * Normal traffic and PHY loopback are not affected by
9447 * errata.
9448 */
9449 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9450 return 0;
9451
9452 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9453 MAC_MODE_PORT_INT_LPBACK;
9454 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9455 mac_mode |= MAC_MODE_LINK_POLARITY;
9456 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9457 mac_mode |= MAC_MODE_PORT_MODE_MII;
9458 else
9459 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9460 tw32(MAC_MODE, mac_mode);
9461 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9462 u32 val;
9463
9464 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9465 u32 phytest;
9466
9467 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9468 u32 phy;
9469
9470 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9471 phytest | MII_TG3_EPHY_SHADOW_EN);
9472 if (!tg3_readphy(tp, 0x1b, &phy))
9473 tg3_writephy(tp, 0x1b, phy & ~0x20);
9474 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9475 }
9476 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9477 } else
9478 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9479
9480 tg3_phy_toggle_automdix(tp, 0);
9481
9482 tg3_writephy(tp, MII_BMCR, val);
9483 udelay(40);
9484
9485 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9486 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9487 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9488 mac_mode |= MAC_MODE_PORT_MODE_MII;
9489 } else
9490 mac_mode |= MAC_MODE_PORT_MODE_GMII;
9491
9492 /* reset to prevent losing 1st rx packet intermittently */
9493 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9494 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9495 udelay(10);
9496 tw32_f(MAC_RX_MODE, tp->rx_mode);
9497 }
9498 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9499 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9500 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9501 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9502 mac_mode |= MAC_MODE_LINK_POLARITY;
9503 tg3_writephy(tp, MII_TG3_EXT_CTRL,
9504 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9505 }
9506 tw32(MAC_MODE, mac_mode);
9507 }
9508 else
9509 return -EINVAL;
9510
9511 err = -EIO;
9512
9513 tx_len = 1514;
9514 skb = netdev_alloc_skb(tp->dev, tx_len);
9515 if (!skb)
9516 return -ENOMEM;
9517
9518 tx_data = skb_put(skb, tx_len);
9519 memcpy(tx_data, tp->dev->dev_addr, 6);
9520 memset(tx_data + 6, 0x0, 8);
9521
9522 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
9523
9524 for (i = 14; i < tx_len; i++)
9525 tx_data[i] = (u8) (i & 0xff);
9526
9527 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
9528
9529 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9530 HOSTCC_MODE_NOW);
9531
9532 udelay(10);
9533
9534 rx_start_idx = tp->hw_status->idx[0].rx_producer;
9535
9536 num_pkts = 0;
9537
9538 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
9539
9540 tp->tx_prod++;
9541 num_pkts++;
9542
9543 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
9544 tp->tx_prod);
9545 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
9546
9547 udelay(10);
9548
9549 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
9550 for (i = 0; i < 25; i++) {
9551 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9552 HOSTCC_MODE_NOW);
9553
9554 udelay(10);
9555
9556 tx_idx = tp->hw_status->idx[0].tx_consumer;
9557 rx_idx = tp->hw_status->idx[0].rx_producer;
9558 if ((tx_idx == tp->tx_prod) &&
9559 (rx_idx == (rx_start_idx + num_pkts)))
9560 break;
9561 }
9562
9563 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
9564 dev_kfree_skb(skb);
9565
9566 if (tx_idx != tp->tx_prod)
9567 goto out;
9568
9569 if (rx_idx != rx_start_idx + num_pkts)
9570 goto out;
9571
9572 desc = &tp->rx_rcb[rx_start_idx];
9573 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9574 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9575 if (opaque_key != RXD_OPAQUE_RING_STD)
9576 goto out;
9577
9578 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9579 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9580 goto out;
9581
9582 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9583 if (rx_len != tx_len)
9584 goto out;
9585
9586 rx_skb = tp->rx_std_buffers[desc_idx].skb;
9587
9588 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9589 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9590
9591 for (i = 14; i < tx_len; i++) {
9592 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9593 goto out;
9594 }
9595 err = 0;
9596
9597 /* tg3_free_rings will unmap and free the rx_skb */
9598 out:
9599 return err;
9600 }
9601
9602 #define TG3_MAC_LOOPBACK_FAILED 1
9603 #define TG3_PHY_LOOPBACK_FAILED 2
9604 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9605 TG3_PHY_LOOPBACK_FAILED)
9606
9607 static int tg3_test_loopback(struct tg3 *tp)
9608 {
9609 int err = 0;
9610 u32 cpmuctrl = 0;
9611
9612 if (!netif_running(tp->dev))
9613 return TG3_LOOPBACK_FAILED;
9614
9615 err = tg3_reset_hw(tp, 1);
9616 if (err)
9617 return TG3_LOOPBACK_FAILED;
9618
9619 /* Turn off gphy autopowerdown. */
9620 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9621 tg3_phy_toggle_apd(tp, false);
9622
9623 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9624 int i;
9625 u32 status;
9626
9627 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
9628
9629 /* Wait for up to 40 microseconds to acquire lock. */
9630 for (i = 0; i < 4; i++) {
9631 status = tr32(TG3_CPMU_MUTEX_GNT);
9632 if (status == CPMU_MUTEX_GNT_DRIVER)
9633 break;
9634 udelay(10);
9635 }
9636
9637 if (status != CPMU_MUTEX_GNT_DRIVER)
9638 return TG3_LOOPBACK_FAILED;
9639
9640 /* Turn off link-based power management. */
9641 cpmuctrl = tr32(TG3_CPMU_CTRL);
9642 tw32(TG3_CPMU_CTRL,
9643 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
9644 CPMU_CTRL_LINK_AWARE_MODE));
9645 }
9646
9647 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9648 err |= TG3_MAC_LOOPBACK_FAILED;
9649
9650 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
9651 tw32(TG3_CPMU_CTRL, cpmuctrl);
9652
9653 /* Release the mutex */
9654 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
9655 }
9656
9657 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9658 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
9659 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9660 err |= TG3_PHY_LOOPBACK_FAILED;
9661 }
9662
9663 /* Re-enable gphy autopowerdown. */
9664 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
9665 tg3_phy_toggle_apd(tp, true);
9666
9667 return err;
9668 }
9669
9670 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9671 u64 *data)
9672 {
9673 struct tg3 *tp = netdev_priv(dev);
9674
9675 if (tp->link_config.phy_is_low_power)
9676 tg3_set_power_state(tp, PCI_D0);
9677
9678 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9679
9680 if (tg3_test_nvram(tp) != 0) {
9681 etest->flags |= ETH_TEST_FL_FAILED;
9682 data[0] = 1;
9683 }
9684 if (tg3_test_link(tp) != 0) {
9685 etest->flags |= ETH_TEST_FL_FAILED;
9686 data[1] = 1;
9687 }
9688 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9689 int err, err2 = 0, irq_sync = 0;
9690
9691 if (netif_running(dev)) {
9692 tg3_phy_stop(tp);
9693 tg3_netif_stop(tp);
9694 irq_sync = 1;
9695 }
9696
9697 tg3_full_lock(tp, irq_sync);
9698
9699 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9700 err = tg3_nvram_lock(tp);
9701 tg3_halt_cpu(tp, RX_CPU_BASE);
9702 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9703 tg3_halt_cpu(tp, TX_CPU_BASE);
9704 if (!err)
9705 tg3_nvram_unlock(tp);
9706
9707 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9708 tg3_phy_reset(tp);
9709
9710 if (tg3_test_registers(tp) != 0) {
9711 etest->flags |= ETH_TEST_FL_FAILED;
9712 data[2] = 1;
9713 }
9714 if (tg3_test_memory(tp) != 0) {
9715 etest->flags |= ETH_TEST_FL_FAILED;
9716 data[3] = 1;
9717 }
9718 if ((data[4] = tg3_test_loopback(tp)) != 0)
9719 etest->flags |= ETH_TEST_FL_FAILED;
9720
9721 tg3_full_unlock(tp);
9722
9723 if (tg3_test_interrupt(tp) != 0) {
9724 etest->flags |= ETH_TEST_FL_FAILED;
9725 data[5] = 1;
9726 }
9727
9728 tg3_full_lock(tp, 0);
9729
9730 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9731 if (netif_running(dev)) {
9732 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9733 err2 = tg3_restart_hw(tp, 1);
9734 if (!err2)
9735 tg3_netif_start(tp);
9736 }
9737
9738 tg3_full_unlock(tp);
9739
9740 if (irq_sync && !err2)
9741 tg3_phy_start(tp);
9742 }
9743 if (tp->link_config.phy_is_low_power)
9744 tg3_set_power_state(tp, PCI_D3hot);
9745
9746 }
9747
9748 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9749 {
9750 struct mii_ioctl_data *data = if_mii(ifr);
9751 struct tg3 *tp = netdev_priv(dev);
9752 int err;
9753
9754 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9755 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9756 return -EAGAIN;
9757 return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
9758 }
9759
9760 switch(cmd) {
9761 case SIOCGMIIPHY:
9762 data->phy_id = PHY_ADDR;
9763
9764 /* fallthru */
9765 case SIOCGMIIREG: {
9766 u32 mii_regval;
9767
9768 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9769 break; /* We have no PHY */
9770
9771 if (tp->link_config.phy_is_low_power)
9772 return -EAGAIN;
9773
9774 spin_lock_bh(&tp->lock);
9775 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9776 spin_unlock_bh(&tp->lock);
9777
9778 data->val_out = mii_regval;
9779
9780 return err;
9781 }
9782
9783 case SIOCSMIIREG:
9784 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9785 break; /* We have no PHY */
9786
9787 if (!capable(CAP_NET_ADMIN))
9788 return -EPERM;
9789
9790 if (tp->link_config.phy_is_low_power)
9791 return -EAGAIN;
9792
9793 spin_lock_bh(&tp->lock);
9794 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9795 spin_unlock_bh(&tp->lock);
9796
9797 return err;
9798
9799 default:
9800 /* do nothing */
9801 break;
9802 }
9803 return -EOPNOTSUPP;
9804 }
9805
9806 #if TG3_VLAN_TAG_USED
9807 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9808 {
9809 struct tg3 *tp = netdev_priv(dev);
9810
9811 if (netif_running(dev))
9812 tg3_netif_stop(tp);
9813
9814 tg3_full_lock(tp, 0);
9815
9816 tp->vlgrp = grp;
9817
9818 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9819 __tg3_set_rx_mode(dev);
9820
9821 if (netif_running(dev))
9822 tg3_netif_start(tp);
9823
9824 tg3_full_unlock(tp);
9825 }
9826 #endif
9827
9828 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9829 {
9830 struct tg3 *tp = netdev_priv(dev);
9831
9832 memcpy(ec, &tp->coal, sizeof(*ec));
9833 return 0;
9834 }
9835
9836 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9837 {
9838 struct tg3 *tp = netdev_priv(dev);
9839 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9840 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9841
9842 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9843 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9844 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9845 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9846 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9847 }
9848
9849 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9850 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9851 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9852 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9853 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9854 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9855 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9856 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9857 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9858 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9859 return -EINVAL;
9860
9861 /* No rx interrupts will be generated if both are zero */
9862 if ((ec->rx_coalesce_usecs == 0) &&
9863 (ec->rx_max_coalesced_frames == 0))
9864 return -EINVAL;
9865
9866 /* No tx interrupts will be generated if both are zero */
9867 if ((ec->tx_coalesce_usecs == 0) &&
9868 (ec->tx_max_coalesced_frames == 0))
9869 return -EINVAL;
9870
9871 /* Only copy relevant parameters, ignore all others. */
9872 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9873 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9874 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9875 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9876 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9877 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9878 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9879 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9880 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9881
9882 if (netif_running(dev)) {
9883 tg3_full_lock(tp, 0);
9884 __tg3_set_coalesce(tp, &tp->coal);
9885 tg3_full_unlock(tp);
9886 }
9887 return 0;
9888 }
9889
9890 static const struct ethtool_ops tg3_ethtool_ops = {
9891 .get_settings = tg3_get_settings,
9892 .set_settings = tg3_set_settings,
9893 .get_drvinfo = tg3_get_drvinfo,
9894 .get_regs_len = tg3_get_regs_len,
9895 .get_regs = tg3_get_regs,
9896 .get_wol = tg3_get_wol,
9897 .set_wol = tg3_set_wol,
9898 .get_msglevel = tg3_get_msglevel,
9899 .set_msglevel = tg3_set_msglevel,
9900 .nway_reset = tg3_nway_reset,
9901 .get_link = ethtool_op_get_link,
9902 .get_eeprom_len = tg3_get_eeprom_len,
9903 .get_eeprom = tg3_get_eeprom,
9904 .set_eeprom = tg3_set_eeprom,
9905 .get_ringparam = tg3_get_ringparam,
9906 .set_ringparam = tg3_set_ringparam,
9907 .get_pauseparam = tg3_get_pauseparam,
9908 .set_pauseparam = tg3_set_pauseparam,
9909 .get_rx_csum = tg3_get_rx_csum,
9910 .set_rx_csum = tg3_set_rx_csum,
9911 .set_tx_csum = tg3_set_tx_csum,
9912 .set_sg = ethtool_op_set_sg,
9913 .set_tso = tg3_set_tso,
9914 .self_test = tg3_self_test,
9915 .get_strings = tg3_get_strings,
9916 .phys_id = tg3_phys_id,
9917 .get_ethtool_stats = tg3_get_ethtool_stats,
9918 .get_coalesce = tg3_get_coalesce,
9919 .set_coalesce = tg3_set_coalesce,
9920 .get_sset_count = tg3_get_sset_count,
9921 };
9922
9923 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9924 {
9925 u32 cursize, val, magic;
9926
9927 tp->nvram_size = EEPROM_CHIP_SIZE;
9928
9929 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9930 return;
9931
9932 if ((magic != TG3_EEPROM_MAGIC) &&
9933 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9934 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9935 return;
9936
9937 /*
9938 * Size the chip by reading offsets at increasing powers of two.
9939 * When we encounter our validation signature, we know the addressing
9940 * has wrapped around, and thus have our chip size.
9941 */
9942 cursize = 0x10;
9943
9944 while (cursize < tp->nvram_size) {
9945 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9946 return;
9947
9948 if (val == magic)
9949 break;
9950
9951 cursize <<= 1;
9952 }
9953
9954 tp->nvram_size = cursize;
9955 }
9956
9957 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9958 {
9959 u32 val;
9960
9961 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9962 return;
9963
9964 /* Selfboot format */
9965 if (val != TG3_EEPROM_MAGIC) {
9966 tg3_get_eeprom_size(tp);
9967 return;
9968 }
9969
9970 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9971 if (val != 0) {
9972 tp->nvram_size = (val >> 16) * 1024;
9973 return;
9974 }
9975 }
9976 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
9977 }
9978
9979 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9980 {
9981 u32 nvcfg1;
9982
9983 nvcfg1 = tr32(NVRAM_CFG1);
9984 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9985 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9986 }
9987 else {
9988 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9989 tw32(NVRAM_CFG1, nvcfg1);
9990 }
9991
9992 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9993 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9994 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9995 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9996 tp->nvram_jedecnum = JEDEC_ATMEL;
9997 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9998 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9999 break;
10000 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10001 tp->nvram_jedecnum = JEDEC_ATMEL;
10002 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10003 break;
10004 case FLASH_VENDOR_ATMEL_EEPROM:
10005 tp->nvram_jedecnum = JEDEC_ATMEL;
10006 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10007 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10008 break;
10009 case FLASH_VENDOR_ST:
10010 tp->nvram_jedecnum = JEDEC_ST;
10011 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10012 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10013 break;
10014 case FLASH_VENDOR_SAIFUN:
10015 tp->nvram_jedecnum = JEDEC_SAIFUN;
10016 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10017 break;
10018 case FLASH_VENDOR_SST_SMALL:
10019 case FLASH_VENDOR_SST_LARGE:
10020 tp->nvram_jedecnum = JEDEC_SST;
10021 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10022 break;
10023 }
10024 }
10025 else {
10026 tp->nvram_jedecnum = JEDEC_ATMEL;
10027 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10028 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10029 }
10030 }
10031
10032 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10033 {
10034 u32 nvcfg1;
10035
10036 nvcfg1 = tr32(NVRAM_CFG1);
10037
10038 /* NVRAM protection for TPM */
10039 if (nvcfg1 & (1 << 27))
10040 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10041
10042 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10043 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10044 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10045 tp->nvram_jedecnum = JEDEC_ATMEL;
10046 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10047 break;
10048 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10049 tp->nvram_jedecnum = JEDEC_ATMEL;
10050 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10051 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10052 break;
10053 case FLASH_5752VENDOR_ST_M45PE10:
10054 case FLASH_5752VENDOR_ST_M45PE20:
10055 case FLASH_5752VENDOR_ST_M45PE40:
10056 tp->nvram_jedecnum = JEDEC_ST;
10057 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10058 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10059 break;
10060 }
10061
10062 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10063 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10064 case FLASH_5752PAGE_SIZE_256:
10065 tp->nvram_pagesize = 256;
10066 break;
10067 case FLASH_5752PAGE_SIZE_512:
10068 tp->nvram_pagesize = 512;
10069 break;
10070 case FLASH_5752PAGE_SIZE_1K:
10071 tp->nvram_pagesize = 1024;
10072 break;
10073 case FLASH_5752PAGE_SIZE_2K:
10074 tp->nvram_pagesize = 2048;
10075 break;
10076 case FLASH_5752PAGE_SIZE_4K:
10077 tp->nvram_pagesize = 4096;
10078 break;
10079 case FLASH_5752PAGE_SIZE_264:
10080 tp->nvram_pagesize = 264;
10081 break;
10082 }
10083 }
10084 else {
10085 /* For eeprom, set pagesize to maximum eeprom size */
10086 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10087
10088 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10089 tw32(NVRAM_CFG1, nvcfg1);
10090 }
10091 }
10092
10093 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10094 {
10095 u32 nvcfg1, protect = 0;
10096
10097 nvcfg1 = tr32(NVRAM_CFG1);
10098
10099 /* NVRAM protection for TPM */
10100 if (nvcfg1 & (1 << 27)) {
10101 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10102 protect = 1;
10103 }
10104
10105 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10106 switch (nvcfg1) {
10107 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10108 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10109 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10110 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10111 tp->nvram_jedecnum = JEDEC_ATMEL;
10112 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10113 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10114 tp->nvram_pagesize = 264;
10115 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10116 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10117 tp->nvram_size = (protect ? 0x3e200 :
10118 TG3_NVRAM_SIZE_512KB);
10119 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10120 tp->nvram_size = (protect ? 0x1f200 :
10121 TG3_NVRAM_SIZE_256KB);
10122 else
10123 tp->nvram_size = (protect ? 0x1f200 :
10124 TG3_NVRAM_SIZE_128KB);
10125 break;
10126 case FLASH_5752VENDOR_ST_M45PE10:
10127 case FLASH_5752VENDOR_ST_M45PE20:
10128 case FLASH_5752VENDOR_ST_M45PE40:
10129 tp->nvram_jedecnum = JEDEC_ST;
10130 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10131 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10132 tp->nvram_pagesize = 256;
10133 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10134 tp->nvram_size = (protect ?
10135 TG3_NVRAM_SIZE_64KB :
10136 TG3_NVRAM_SIZE_128KB);
10137 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10138 tp->nvram_size = (protect ?
10139 TG3_NVRAM_SIZE_64KB :
10140 TG3_NVRAM_SIZE_256KB);
10141 else
10142 tp->nvram_size = (protect ?
10143 TG3_NVRAM_SIZE_128KB :
10144 TG3_NVRAM_SIZE_512KB);
10145 break;
10146 }
10147 }
10148
10149 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10150 {
10151 u32 nvcfg1;
10152
10153 nvcfg1 = tr32(NVRAM_CFG1);
10154
10155 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10156 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10157 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10158 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10159 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10160 tp->nvram_jedecnum = JEDEC_ATMEL;
10161 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10162 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10163
10164 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10165 tw32(NVRAM_CFG1, nvcfg1);
10166 break;
10167 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10168 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10169 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10170 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10171 tp->nvram_jedecnum = JEDEC_ATMEL;
10172 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10173 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10174 tp->nvram_pagesize = 264;
10175 break;
10176 case FLASH_5752VENDOR_ST_M45PE10:
10177 case FLASH_5752VENDOR_ST_M45PE20:
10178 case FLASH_5752VENDOR_ST_M45PE40:
10179 tp->nvram_jedecnum = JEDEC_ST;
10180 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10181 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10182 tp->nvram_pagesize = 256;
10183 break;
10184 }
10185 }
10186
10187 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10188 {
10189 u32 nvcfg1, protect = 0;
10190
10191 nvcfg1 = tr32(NVRAM_CFG1);
10192
10193 /* NVRAM protection for TPM */
10194 if (nvcfg1 & (1 << 27)) {
10195 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10196 protect = 1;
10197 }
10198
10199 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10200 switch (nvcfg1) {
10201 case FLASH_5761VENDOR_ATMEL_ADB021D:
10202 case FLASH_5761VENDOR_ATMEL_ADB041D:
10203 case FLASH_5761VENDOR_ATMEL_ADB081D:
10204 case FLASH_5761VENDOR_ATMEL_ADB161D:
10205 case FLASH_5761VENDOR_ATMEL_MDB021D:
10206 case FLASH_5761VENDOR_ATMEL_MDB041D:
10207 case FLASH_5761VENDOR_ATMEL_MDB081D:
10208 case FLASH_5761VENDOR_ATMEL_MDB161D:
10209 tp->nvram_jedecnum = JEDEC_ATMEL;
10210 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10211 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10212 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10213 tp->nvram_pagesize = 256;
10214 break;
10215 case FLASH_5761VENDOR_ST_A_M45PE20:
10216 case FLASH_5761VENDOR_ST_A_M45PE40:
10217 case FLASH_5761VENDOR_ST_A_M45PE80:
10218 case FLASH_5761VENDOR_ST_A_M45PE16:
10219 case FLASH_5761VENDOR_ST_M_M45PE20:
10220 case FLASH_5761VENDOR_ST_M_M45PE40:
10221 case FLASH_5761VENDOR_ST_M_M45PE80:
10222 case FLASH_5761VENDOR_ST_M_M45PE16:
10223 tp->nvram_jedecnum = JEDEC_ST;
10224 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10225 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10226 tp->nvram_pagesize = 256;
10227 break;
10228 }
10229
10230 if (protect) {
10231 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10232 } else {
10233 switch (nvcfg1) {
10234 case FLASH_5761VENDOR_ATMEL_ADB161D:
10235 case FLASH_5761VENDOR_ATMEL_MDB161D:
10236 case FLASH_5761VENDOR_ST_A_M45PE16:
10237 case FLASH_5761VENDOR_ST_M_M45PE16:
10238 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10239 break;
10240 case FLASH_5761VENDOR_ATMEL_ADB081D:
10241 case FLASH_5761VENDOR_ATMEL_MDB081D:
10242 case FLASH_5761VENDOR_ST_A_M45PE80:
10243 case FLASH_5761VENDOR_ST_M_M45PE80:
10244 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10245 break;
10246 case FLASH_5761VENDOR_ATMEL_ADB041D:
10247 case FLASH_5761VENDOR_ATMEL_MDB041D:
10248 case FLASH_5761VENDOR_ST_A_M45PE40:
10249 case FLASH_5761VENDOR_ST_M_M45PE40:
10250 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10251 break;
10252 case FLASH_5761VENDOR_ATMEL_ADB021D:
10253 case FLASH_5761VENDOR_ATMEL_MDB021D:
10254 case FLASH_5761VENDOR_ST_A_M45PE20:
10255 case FLASH_5761VENDOR_ST_M_M45PE20:
10256 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10257 break;
10258 }
10259 }
10260 }
10261
10262 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10263 {
10264 tp->nvram_jedecnum = JEDEC_ATMEL;
10265 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10266 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10267 }
10268
10269 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
10270 {
10271 u32 nvcfg1;
10272
10273 nvcfg1 = tr32(NVRAM_CFG1);
10274
10275 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10276 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10277 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10278 tp->nvram_jedecnum = JEDEC_ATMEL;
10279 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10280 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10281
10282 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10283 tw32(NVRAM_CFG1, nvcfg1);
10284 return;
10285 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10286 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10287 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10288 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10289 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10290 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10291 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10292 tp->nvram_jedecnum = JEDEC_ATMEL;
10293 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10294 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10295
10296 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10297 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10298 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
10299 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
10300 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10301 break;
10302 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
10303 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
10304 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10305 break;
10306 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
10307 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
10308 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10309 break;
10310 }
10311 break;
10312 case FLASH_5752VENDOR_ST_M45PE10:
10313 case FLASH_5752VENDOR_ST_M45PE20:
10314 case FLASH_5752VENDOR_ST_M45PE40:
10315 tp->nvram_jedecnum = JEDEC_ST;
10316 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10317 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10318
10319 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10320 case FLASH_5752VENDOR_ST_M45PE10:
10321 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
10322 break;
10323 case FLASH_5752VENDOR_ST_M45PE20:
10324 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10325 break;
10326 case FLASH_5752VENDOR_ST_M45PE40:
10327 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10328 break;
10329 }
10330 break;
10331 default:
10332 return;
10333 }
10334
10335 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10336 case FLASH_5752PAGE_SIZE_256:
10337 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10338 tp->nvram_pagesize = 256;
10339 break;
10340 case FLASH_5752PAGE_SIZE_512:
10341 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10342 tp->nvram_pagesize = 512;
10343 break;
10344 case FLASH_5752PAGE_SIZE_1K:
10345 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10346 tp->nvram_pagesize = 1024;
10347 break;
10348 case FLASH_5752PAGE_SIZE_2K:
10349 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10350 tp->nvram_pagesize = 2048;
10351 break;
10352 case FLASH_5752PAGE_SIZE_4K:
10353 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10354 tp->nvram_pagesize = 4096;
10355 break;
10356 case FLASH_5752PAGE_SIZE_264:
10357 tp->nvram_pagesize = 264;
10358 break;
10359 case FLASH_5752PAGE_SIZE_528:
10360 tp->nvram_pagesize = 528;
10361 break;
10362 }
10363 }
10364
10365 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10366 static void __devinit tg3_nvram_init(struct tg3 *tp)
10367 {
10368 tw32_f(GRC_EEPROM_ADDR,
10369 (EEPROM_ADDR_FSM_RESET |
10370 (EEPROM_DEFAULT_CLOCK_PERIOD <<
10371 EEPROM_ADDR_CLKPERD_SHIFT)));
10372
10373 msleep(1);
10374
10375 /* Enable seeprom accesses. */
10376 tw32_f(GRC_LOCAL_CTRL,
10377 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10378 udelay(100);
10379
10380 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10381 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10382 tp->tg3_flags |= TG3_FLAG_NVRAM;
10383
10384 if (tg3_nvram_lock(tp)) {
10385 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10386 "tg3_nvram_init failed.\n", tp->dev->name);
10387 return;
10388 }
10389 tg3_enable_nvram_access(tp);
10390
10391 tp->nvram_size = 0;
10392
10393 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10394 tg3_get_5752_nvram_info(tp);
10395 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10396 tg3_get_5755_nvram_info(tp);
10397 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10398 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10399 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10400 tg3_get_5787_nvram_info(tp);
10401 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10402 tg3_get_5761_nvram_info(tp);
10403 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10404 tg3_get_5906_nvram_info(tp);
10405 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10406 tg3_get_57780_nvram_info(tp);
10407 else
10408 tg3_get_nvram_info(tp);
10409
10410 if (tp->nvram_size == 0)
10411 tg3_get_nvram_size(tp);
10412
10413 tg3_disable_nvram_access(tp);
10414 tg3_nvram_unlock(tp);
10415
10416 } else {
10417 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10418
10419 tg3_get_eeprom_size(tp);
10420 }
10421 }
10422
10423 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10424 u32 offset, u32 *val)
10425 {
10426 u32 tmp;
10427 int i;
10428
10429 if (offset > EEPROM_ADDR_ADDR_MASK ||
10430 (offset % 4) != 0)
10431 return -EINVAL;
10432
10433 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10434 EEPROM_ADDR_DEVID_MASK |
10435 EEPROM_ADDR_READ);
10436 tw32(GRC_EEPROM_ADDR,
10437 tmp |
10438 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10439 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10440 EEPROM_ADDR_ADDR_MASK) |
10441 EEPROM_ADDR_READ | EEPROM_ADDR_START);
10442
10443 for (i = 0; i < 1000; i++) {
10444 tmp = tr32(GRC_EEPROM_ADDR);
10445
10446 if (tmp & EEPROM_ADDR_COMPLETE)
10447 break;
10448 msleep(1);
10449 }
10450 if (!(tmp & EEPROM_ADDR_COMPLETE))
10451 return -EBUSY;
10452
10453 *val = tr32(GRC_EEPROM_DATA);
10454 return 0;
10455 }
10456
10457 #define NVRAM_CMD_TIMEOUT 10000
10458
10459 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10460 {
10461 int i;
10462
10463 tw32(NVRAM_CMD, nvram_cmd);
10464 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10465 udelay(10);
10466 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10467 udelay(10);
10468 break;
10469 }
10470 }
10471 if (i == NVRAM_CMD_TIMEOUT) {
10472 return -EBUSY;
10473 }
10474 return 0;
10475 }
10476
10477 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10478 {
10479 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10480 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10481 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10482 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10483 (tp->nvram_jedecnum == JEDEC_ATMEL))
10484
10485 addr = ((addr / tp->nvram_pagesize) <<
10486 ATMEL_AT45DB0X1B_PAGE_POS) +
10487 (addr % tp->nvram_pagesize);
10488
10489 return addr;
10490 }
10491
10492 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10493 {
10494 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10495 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10496 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10497 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10498 (tp->nvram_jedecnum == JEDEC_ATMEL))
10499
10500 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10501 tp->nvram_pagesize) +
10502 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10503
10504 return addr;
10505 }
10506
10507 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10508 {
10509 int ret;
10510
10511 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10512 return tg3_nvram_read_using_eeprom(tp, offset, val);
10513
10514 offset = tg3_nvram_phys_addr(tp, offset);
10515
10516 if (offset > NVRAM_ADDR_MSK)
10517 return -EINVAL;
10518
10519 ret = tg3_nvram_lock(tp);
10520 if (ret)
10521 return ret;
10522
10523 tg3_enable_nvram_access(tp);
10524
10525 tw32(NVRAM_ADDR, offset);
10526 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10527 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10528
10529 if (ret == 0)
10530 *val = swab32(tr32(NVRAM_RDDATA));
10531
10532 tg3_disable_nvram_access(tp);
10533
10534 tg3_nvram_unlock(tp);
10535
10536 return ret;
10537 }
10538
10539 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10540 {
10541 u32 v;
10542 int res = tg3_nvram_read(tp, offset, &v);
10543 if (!res)
10544 *val = cpu_to_le32(v);
10545 return res;
10546 }
10547
10548 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10549 {
10550 int err;
10551 u32 tmp;
10552
10553 err = tg3_nvram_read(tp, offset, &tmp);
10554 *val = swab32(tmp);
10555 return err;
10556 }
10557
10558 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10559 u32 offset, u32 len, u8 *buf)
10560 {
10561 int i, j, rc = 0;
10562 u32 val;
10563
10564 for (i = 0; i < len; i += 4) {
10565 u32 addr;
10566 __le32 data;
10567
10568 addr = offset + i;
10569
10570 memcpy(&data, buf + i, 4);
10571
10572 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
10573
10574 val = tr32(GRC_EEPROM_ADDR);
10575 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10576
10577 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10578 EEPROM_ADDR_READ);
10579 tw32(GRC_EEPROM_ADDR, val |
10580 (0 << EEPROM_ADDR_DEVID_SHIFT) |
10581 (addr & EEPROM_ADDR_ADDR_MASK) |
10582 EEPROM_ADDR_START |
10583 EEPROM_ADDR_WRITE);
10584
10585 for (j = 0; j < 1000; j++) {
10586 val = tr32(GRC_EEPROM_ADDR);
10587
10588 if (val & EEPROM_ADDR_COMPLETE)
10589 break;
10590 msleep(1);
10591 }
10592 if (!(val & EEPROM_ADDR_COMPLETE)) {
10593 rc = -EBUSY;
10594 break;
10595 }
10596 }
10597
10598 return rc;
10599 }
10600
10601 /* offset and length are dword aligned */
10602 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10603 u8 *buf)
10604 {
10605 int ret = 0;
10606 u32 pagesize = tp->nvram_pagesize;
10607 u32 pagemask = pagesize - 1;
10608 u32 nvram_cmd;
10609 u8 *tmp;
10610
10611 tmp = kmalloc(pagesize, GFP_KERNEL);
10612 if (tmp == NULL)
10613 return -ENOMEM;
10614
10615 while (len) {
10616 int j;
10617 u32 phy_addr, page_off, size;
10618
10619 phy_addr = offset & ~pagemask;
10620
10621 for (j = 0; j < pagesize; j += 4) {
10622 if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
10623 (__le32 *) (tmp + j))))
10624 break;
10625 }
10626 if (ret)
10627 break;
10628
10629 page_off = offset & pagemask;
10630 size = pagesize;
10631 if (len < size)
10632 size = len;
10633
10634 len -= size;
10635
10636 memcpy(tmp + page_off, buf, size);
10637
10638 offset = offset + (pagesize - page_off);
10639
10640 tg3_enable_nvram_access(tp);
10641
10642 /*
10643 * Before we can erase the flash page, we need
10644 * to issue a special "write enable" command.
10645 */
10646 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10647
10648 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10649 break;
10650
10651 /* Erase the target page */
10652 tw32(NVRAM_ADDR, phy_addr);
10653
10654 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
10655 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
10656
10657 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10658 break;
10659
10660 /* Issue another write enable to start the write. */
10661 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10662
10663 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
10664 break;
10665
10666 for (j = 0; j < pagesize; j += 4) {
10667 __be32 data;
10668
10669 data = *((__be32 *) (tmp + j));
10670 /* swab32(le32_to_cpu(data)), actually */
10671 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10672
10673 tw32(NVRAM_ADDR, phy_addr + j);
10674
10675 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
10676 NVRAM_CMD_WR;
10677
10678 if (j == 0)
10679 nvram_cmd |= NVRAM_CMD_FIRST;
10680 else if (j == (pagesize - 4))
10681 nvram_cmd |= NVRAM_CMD_LAST;
10682
10683 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10684 break;
10685 }
10686 if (ret)
10687 break;
10688 }
10689
10690 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
10691 tg3_nvram_exec_cmd(tp, nvram_cmd);
10692
10693 kfree(tmp);
10694
10695 return ret;
10696 }
10697
10698 /* offset and length are dword aligned */
10699 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
10700 u8 *buf)
10701 {
10702 int i, ret = 0;
10703
10704 for (i = 0; i < len; i += 4, offset += 4) {
10705 u32 page_off, phy_addr, nvram_cmd;
10706 __be32 data;
10707
10708 memcpy(&data, buf + i, 4);
10709 tw32(NVRAM_WRDATA, be32_to_cpu(data));
10710
10711 page_off = offset % tp->nvram_pagesize;
10712
10713 phy_addr = tg3_nvram_phys_addr(tp, offset);
10714
10715 tw32(NVRAM_ADDR, phy_addr);
10716
10717 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
10718
10719 if ((page_off == 0) || (i == 0))
10720 nvram_cmd |= NVRAM_CMD_FIRST;
10721 if (page_off == (tp->nvram_pagesize - 4))
10722 nvram_cmd |= NVRAM_CMD_LAST;
10723
10724 if (i == (len - 4))
10725 nvram_cmd |= NVRAM_CMD_LAST;
10726
10727 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10728 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
10729 (tp->nvram_jedecnum == JEDEC_ST) &&
10730 (nvram_cmd & NVRAM_CMD_FIRST)) {
10731
10732 if ((ret = tg3_nvram_exec_cmd(tp,
10733 NVRAM_CMD_WREN | NVRAM_CMD_GO |
10734 NVRAM_CMD_DONE)))
10735
10736 break;
10737 }
10738 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10739 /* We always do complete word writes to eeprom. */
10740 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
10741 }
10742
10743 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
10744 break;
10745 }
10746 return ret;
10747 }
10748
10749 /* offset and length are dword aligned */
10750 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
10751 {
10752 int ret;
10753
10754 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10755 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
10756 ~GRC_LCLCTRL_GPIO_OUTPUT1);
10757 udelay(40);
10758 }
10759
10760 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
10761 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
10762 }
10763 else {
10764 u32 grc_mode;
10765
10766 ret = tg3_nvram_lock(tp);
10767 if (ret)
10768 return ret;
10769
10770 tg3_enable_nvram_access(tp);
10771 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
10772 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
10773 tw32(NVRAM_WRITE1, 0x406);
10774
10775 grc_mode = tr32(GRC_MODE);
10776 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
10777
10778 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
10779 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
10780
10781 ret = tg3_nvram_write_block_buffered(tp, offset, len,
10782 buf);
10783 }
10784 else {
10785 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
10786 buf);
10787 }
10788
10789 grc_mode = tr32(GRC_MODE);
10790 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
10791
10792 tg3_disable_nvram_access(tp);
10793 tg3_nvram_unlock(tp);
10794 }
10795
10796 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
10797 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10798 udelay(40);
10799 }
10800
10801 return ret;
10802 }
10803
10804 struct subsys_tbl_ent {
10805 u16 subsys_vendor, subsys_devid;
10806 u32 phy_id;
10807 };
10808
10809 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
10810 /* Broadcom boards. */
10811 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
10812 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
10813 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
10814 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
10815 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
10816 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
10817 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
10818 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10819 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10820 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10821 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10822
10823 /* 3com boards. */
10824 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10825 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10826 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
10827 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10828 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10829
10830 /* DELL boards. */
10831 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10832 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10833 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10834 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10835
10836 /* Compaq boards. */
10837 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10838 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10839 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
10840 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10841 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10842
10843 /* IBM boards. */
10844 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10845 };
10846
10847 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10848 {
10849 int i;
10850
10851 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10852 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10853 tp->pdev->subsystem_vendor) &&
10854 (subsys_id_to_phy_id[i].subsys_devid ==
10855 tp->pdev->subsystem_device))
10856 return &subsys_id_to_phy_id[i];
10857 }
10858 return NULL;
10859 }
10860
10861 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10862 {
10863 u32 val;
10864 u16 pmcsr;
10865
10866 /* On some early chips the SRAM cannot be accessed in D3hot state,
10867 * so need make sure we're in D0.
10868 */
10869 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10870 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10871 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10872 msleep(1);
10873
10874 /* Make sure register accesses (indirect or otherwise)
10875 * will function correctly.
10876 */
10877 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10878 tp->misc_host_ctrl);
10879
10880 /* The memory arbiter has to be enabled in order for SRAM accesses
10881 * to succeed. Normally on powerup the tg3 chip firmware will make
10882 * sure it is enabled, but other entities such as system netboot
10883 * code might disable it.
10884 */
10885 val = tr32(MEMARB_MODE);
10886 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10887
10888 tp->phy_id = PHY_ID_INVALID;
10889 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10890
10891 /* Assume an onboard device and WOL capable by default. */
10892 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10893
10894 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10895 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10896 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10897 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10898 }
10899 val = tr32(VCPU_CFGSHDW);
10900 if (val & VCPU_CFGSHDW_ASPM_DBNC)
10901 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10902 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
10903 (val & VCPU_CFGSHDW_WOL_MAGPKT))
10904 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
10905 goto done;
10906 }
10907
10908 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10909 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10910 u32 nic_cfg, led_cfg;
10911 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
10912 int eeprom_phy_serdes = 0;
10913
10914 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10915 tp->nic_sram_data_cfg = nic_cfg;
10916
10917 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10918 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10919 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10920 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10921 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10922 (ver > 0) && (ver < 0x100))
10923 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10924
10925 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10926 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
10927
10928 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10929 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10930 eeprom_phy_serdes = 1;
10931
10932 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10933 if (nic_phy_id != 0) {
10934 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10935 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10936
10937 eeprom_phy_id = (id1 >> 16) << 10;
10938 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10939 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10940 } else
10941 eeprom_phy_id = 0;
10942
10943 tp->phy_id = eeprom_phy_id;
10944 if (eeprom_phy_serdes) {
10945 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10946 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10947 else
10948 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10949 }
10950
10951 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10952 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10953 SHASTA_EXT_LED_MODE_MASK);
10954 else
10955 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10956
10957 switch (led_cfg) {
10958 default:
10959 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10960 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10961 break;
10962
10963 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10964 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10965 break;
10966
10967 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10968 tp->led_ctrl = LED_CTRL_MODE_MAC;
10969
10970 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10971 * read on some older 5700/5701 bootcode.
10972 */
10973 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10974 ASIC_REV_5700 ||
10975 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10976 ASIC_REV_5701)
10977 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10978
10979 break;
10980
10981 case SHASTA_EXT_LED_SHARED:
10982 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10983 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10984 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10985 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10986 LED_CTRL_MODE_PHY_2);
10987 break;
10988
10989 case SHASTA_EXT_LED_MAC:
10990 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10991 break;
10992
10993 case SHASTA_EXT_LED_COMBO:
10994 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10995 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10996 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10997 LED_CTRL_MODE_PHY_2);
10998 break;
10999
11000 }
11001
11002 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11003 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11004 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11005 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11006
11007 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11008 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11009
11010 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11011 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11012 if ((tp->pdev->subsystem_vendor ==
11013 PCI_VENDOR_ID_ARIMA) &&
11014 (tp->pdev->subsystem_device == 0x205a ||
11015 tp->pdev->subsystem_device == 0x2063))
11016 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11017 } else {
11018 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11019 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11020 }
11021
11022 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11023 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11024 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11025 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11026 }
11027
11028 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
11029 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11030 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11031
11032 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11033 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11034 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11035
11036 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
11037 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
11038 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11039
11040 if (cfg2 & (1 << 17))
11041 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11042
11043 /* serdes signal pre-emphasis in register 0x590 set by */
11044 /* bootcode if bit 18 is set */
11045 if (cfg2 & (1 << 18))
11046 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11047
11048 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
11049 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
11050 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
11051 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
11052
11053 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11054 u32 cfg3;
11055
11056 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11057 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11058 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11059 }
11060
11061 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11062 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11063 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11064 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11065 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11066 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11067 }
11068 done:
11069 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
11070 device_set_wakeup_enable(&tp->pdev->dev,
11071 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
11072 }
11073
11074 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11075 {
11076 int i;
11077 u32 val;
11078
11079 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11080 tw32(OTP_CTRL, cmd);
11081
11082 /* Wait for up to 1 ms for command to execute. */
11083 for (i = 0; i < 100; i++) {
11084 val = tr32(OTP_STATUS);
11085 if (val & OTP_STATUS_CMD_DONE)
11086 break;
11087 udelay(10);
11088 }
11089
11090 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11091 }
11092
11093 /* Read the gphy configuration from the OTP region of the chip. The gphy
11094 * configuration is a 32-bit value that straddles the alignment boundary.
11095 * We do two 32-bit reads and then shift and merge the results.
11096 */
11097 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11098 {
11099 u32 bhalf_otp, thalf_otp;
11100
11101 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11102
11103 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11104 return 0;
11105
11106 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11107
11108 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11109 return 0;
11110
11111 thalf_otp = tr32(OTP_READ_DATA);
11112
11113 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11114
11115 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11116 return 0;
11117
11118 bhalf_otp = tr32(OTP_READ_DATA);
11119
11120 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11121 }
11122
11123 static int __devinit tg3_phy_probe(struct tg3 *tp)
11124 {
11125 u32 hw_phy_id_1, hw_phy_id_2;
11126 u32 hw_phy_id, hw_phy_id_masked;
11127 int err;
11128
11129 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11130 return tg3_phy_init(tp);
11131
11132 /* Reading the PHY ID register can conflict with ASF
11133 * firwmare access to the PHY hardware.
11134 */
11135 err = 0;
11136 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11137 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11138 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11139 } else {
11140 /* Now read the physical PHY_ID from the chip and verify
11141 * that it is sane. If it doesn't look good, we fall back
11142 * to either the hard-coded table based PHY_ID and failing
11143 * that the value found in the eeprom area.
11144 */
11145 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11146 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11147
11148 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
11149 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11150 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
11151
11152 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11153 }
11154
11155 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11156 tp->phy_id = hw_phy_id;
11157 if (hw_phy_id_masked == PHY_ID_BCM8002)
11158 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11159 else
11160 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11161 } else {
11162 if (tp->phy_id != PHY_ID_INVALID) {
11163 /* Do nothing, phy ID already set up in
11164 * tg3_get_eeprom_hw_cfg().
11165 */
11166 } else {
11167 struct subsys_tbl_ent *p;
11168
11169 /* No eeprom signature? Try the hardcoded
11170 * subsys device table.
11171 */
11172 p = lookup_by_subsys(tp);
11173 if (!p)
11174 return -ENODEV;
11175
11176 tp->phy_id = p->phy_id;
11177 if (!tp->phy_id ||
11178 tp->phy_id == PHY_ID_BCM8002)
11179 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11180 }
11181 }
11182
11183 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11184 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11185 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11186 u32 bmsr, adv_reg, tg3_ctrl, mask;
11187
11188 tg3_readphy(tp, MII_BMSR, &bmsr);
11189 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11190 (bmsr & BMSR_LSTATUS))
11191 goto skip_phy_reset;
11192
11193 err = tg3_phy_reset(tp);
11194 if (err)
11195 return err;
11196
11197 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11198 ADVERTISE_100HALF | ADVERTISE_100FULL |
11199 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11200 tg3_ctrl = 0;
11201 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11202 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11203 MII_TG3_CTRL_ADV_1000_FULL);
11204 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11205 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11206 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11207 MII_TG3_CTRL_ENABLE_AS_MASTER);
11208 }
11209
11210 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11211 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11212 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11213 if (!tg3_copper_is_advertising_all(tp, mask)) {
11214 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11215
11216 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11217 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11218
11219 tg3_writephy(tp, MII_BMCR,
11220 BMCR_ANENABLE | BMCR_ANRESTART);
11221 }
11222 tg3_phy_set_wirespeed(tp);
11223
11224 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11225 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11226 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11227 }
11228
11229 skip_phy_reset:
11230 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11231 err = tg3_init_5401phy_dsp(tp);
11232 if (err)
11233 return err;
11234 }
11235
11236 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11237 err = tg3_init_5401phy_dsp(tp);
11238 }
11239
11240 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11241 tp->link_config.advertising =
11242 (ADVERTISED_1000baseT_Half |
11243 ADVERTISED_1000baseT_Full |
11244 ADVERTISED_Autoneg |
11245 ADVERTISED_FIBRE);
11246 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11247 tp->link_config.advertising &=
11248 ~(ADVERTISED_1000baseT_Half |
11249 ADVERTISED_1000baseT_Full);
11250
11251 return err;
11252 }
11253
11254 static void __devinit tg3_read_partno(struct tg3 *tp)
11255 {
11256 unsigned char vpd_data[256];
11257 unsigned int i;
11258 u32 magic;
11259
11260 if (tg3_nvram_read_swab(tp, 0x0, &magic))
11261 goto out_not_found;
11262
11263 if (magic == TG3_EEPROM_MAGIC) {
11264 for (i = 0; i < 256; i += 4) {
11265 u32 tmp;
11266
11267 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11268 goto out_not_found;
11269
11270 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
11271 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
11272 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11273 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11274 }
11275 } else {
11276 int vpd_cap;
11277
11278 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11279 for (i = 0; i < 256; i += 4) {
11280 u32 tmp, j = 0;
11281 __le32 v;
11282 u16 tmp16;
11283
11284 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11285 i);
11286 while (j++ < 100) {
11287 pci_read_config_word(tp->pdev, vpd_cap +
11288 PCI_VPD_ADDR, &tmp16);
11289 if (tmp16 & 0x8000)
11290 break;
11291 msleep(1);
11292 }
11293 if (!(tmp16 & 0x8000))
11294 goto out_not_found;
11295
11296 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11297 &tmp);
11298 v = cpu_to_le32(tmp);
11299 memcpy(&vpd_data[i], &v, 4);
11300 }
11301 }
11302
11303 /* Now parse and find the part number. */
11304 for (i = 0; i < 254; ) {
11305 unsigned char val = vpd_data[i];
11306 unsigned int block_end;
11307
11308 if (val == 0x82 || val == 0x91) {
11309 i = (i + 3 +
11310 (vpd_data[i + 1] +
11311 (vpd_data[i + 2] << 8)));
11312 continue;
11313 }
11314
11315 if (val != 0x90)
11316 goto out_not_found;
11317
11318 block_end = (i + 3 +
11319 (vpd_data[i + 1] +
11320 (vpd_data[i + 2] << 8)));
11321 i += 3;
11322
11323 if (block_end > 256)
11324 goto out_not_found;
11325
11326 while (i < (block_end - 2)) {
11327 if (vpd_data[i + 0] == 'P' &&
11328 vpd_data[i + 1] == 'N') {
11329 int partno_len = vpd_data[i + 2];
11330
11331 i += 3;
11332 if (partno_len > 24 || (partno_len + i) > 256)
11333 goto out_not_found;
11334
11335 memcpy(tp->board_part_number,
11336 &vpd_data[i], partno_len);
11337
11338 /* Success. */
11339 return;
11340 }
11341 i += 3 + vpd_data[i + 2];
11342 }
11343
11344 /* Part number not found. */
11345 goto out_not_found;
11346 }
11347
11348 out_not_found:
11349 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11350 strcpy(tp->board_part_number, "BCM95906");
11351 else
11352 strcpy(tp->board_part_number, "none");
11353 }
11354
11355 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11356 {
11357 u32 val;
11358
11359 if (tg3_nvram_read_swab(tp, offset, &val) ||
11360 (val & 0xfc000000) != 0x0c000000 ||
11361 tg3_nvram_read_swab(tp, offset + 4, &val) ||
11362 val != 0)
11363 return 0;
11364
11365 return 1;
11366 }
11367
11368 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
11369 {
11370 u32 offset, major, minor, build;
11371
11372 tp->fw_ver[0] = 's';
11373 tp->fw_ver[1] = 'b';
11374 tp->fw_ver[2] = '\0';
11375
11376 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
11377 return;
11378
11379 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
11380 case TG3_EEPROM_SB_REVISION_0:
11381 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
11382 break;
11383 case TG3_EEPROM_SB_REVISION_2:
11384 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
11385 break;
11386 case TG3_EEPROM_SB_REVISION_3:
11387 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
11388 break;
11389 default:
11390 return;
11391 }
11392
11393 if (tg3_nvram_read_swab(tp, offset, &val))
11394 return;
11395
11396 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
11397 TG3_EEPROM_SB_EDH_BLD_SHFT;
11398 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
11399 TG3_EEPROM_SB_EDH_MAJ_SHFT;
11400 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
11401
11402 if (minor > 99 || build > 26)
11403 return;
11404
11405 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
11406
11407 if (build > 0) {
11408 tp->fw_ver[8] = 'a' + build - 1;
11409 tp->fw_ver[9] = '\0';
11410 }
11411 }
11412
11413 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11414 {
11415 u32 val, offset, start;
11416 u32 ver_offset;
11417 int i, bcnt;
11418
11419 if (tg3_nvram_read_swab(tp, 0, &val))
11420 return;
11421
11422 if (val != TG3_EEPROM_MAGIC) {
11423 if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
11424 tg3_read_sb_ver(tp, val);
11425
11426 return;
11427 }
11428
11429 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11430 tg3_nvram_read_swab(tp, 0x4, &start))
11431 return;
11432
11433 offset = tg3_nvram_logical_addr(tp, offset);
11434
11435 if (!tg3_fw_img_is_valid(tp, offset) ||
11436 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
11437 return;
11438
11439 offset = offset + ver_offset - start;
11440 for (i = 0; i < 16; i += 4) {
11441 __le32 v;
11442 if (tg3_nvram_read_le(tp, offset + i, &v))
11443 return;
11444
11445 memcpy(tp->fw_ver + i, &v, 4);
11446 }
11447
11448 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11449 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11450 return;
11451
11452 for (offset = TG3_NVM_DIR_START;
11453 offset < TG3_NVM_DIR_END;
11454 offset += TG3_NVM_DIRENT_SIZE) {
11455 if (tg3_nvram_read_swab(tp, offset, &val))
11456 return;
11457
11458 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11459 break;
11460 }
11461
11462 if (offset == TG3_NVM_DIR_END)
11463 return;
11464
11465 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11466 start = 0x08000000;
11467 else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11468 return;
11469
11470 if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11471 !tg3_fw_img_is_valid(tp, offset) ||
11472 tg3_nvram_read_swab(tp, offset + 8, &val))
11473 return;
11474
11475 offset += val - start;
11476
11477 bcnt = strlen(tp->fw_ver);
11478
11479 tp->fw_ver[bcnt++] = ',';
11480 tp->fw_ver[bcnt++] = ' ';
11481
11482 for (i = 0; i < 4; i++) {
11483 __le32 v;
11484 if (tg3_nvram_read_le(tp, offset, &v))
11485 return;
11486
11487 offset += sizeof(v);
11488
11489 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11490 memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
11491 break;
11492 }
11493
11494 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11495 bcnt += sizeof(v);
11496 }
11497
11498 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11499 }
11500
11501 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11502
11503 static int __devinit tg3_get_invariants(struct tg3 *tp)
11504 {
11505 static struct pci_device_id write_reorder_chipsets[] = {
11506 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11507 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11508 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11509 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11510 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11511 PCI_DEVICE_ID_VIA_8385_0) },
11512 { },
11513 };
11514 u32 misc_ctrl_reg;
11515 u32 pci_state_reg, grc_misc_cfg;
11516 u32 val;
11517 u16 pci_cmd;
11518 int err;
11519
11520 /* Force memory write invalidate off. If we leave it on,
11521 * then on 5700_BX chips we have to enable a workaround.
11522 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11523 * to match the cacheline size. The Broadcom driver have this
11524 * workaround but turns MWI off all the times so never uses
11525 * it. This seems to suggest that the workaround is insufficient.
11526 */
11527 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11528 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11529 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11530
11531 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11532 * has the register indirect write enable bit set before
11533 * we try to access any of the MMIO registers. It is also
11534 * critical that the PCI-X hw workaround situation is decided
11535 * before that as well.
11536 */
11537 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11538 &misc_ctrl_reg);
11539
11540 tp->pci_chip_rev_id = (misc_ctrl_reg >>
11541 MISC_HOST_CTRL_CHIPREV_SHIFT);
11542 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11543 u32 prod_id_asic_rev;
11544
11545 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11546 &prod_id_asic_rev);
11547 tp->pci_chip_rev_id = prod_id_asic_rev;
11548 }
11549
11550 /* Wrong chip ID in 5752 A0. This code can be removed later
11551 * as A0 is not in production.
11552 */
11553 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11554 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11555
11556 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11557 * we need to disable memory and use config. cycles
11558 * only to access all registers. The 5702/03 chips
11559 * can mistakenly decode the special cycles from the
11560 * ICH chipsets as memory write cycles, causing corruption
11561 * of register and memory space. Only certain ICH bridges
11562 * will drive special cycles with non-zero data during the
11563 * address phase which can fall within the 5703's address
11564 * range. This is not an ICH bug as the PCI spec allows
11565 * non-zero address during special cycles. However, only
11566 * these ICH bridges are known to drive non-zero addresses
11567 * during special cycles.
11568 *
11569 * Since special cycles do not cross PCI bridges, we only
11570 * enable this workaround if the 5703 is on the secondary
11571 * bus of these ICH bridges.
11572 */
11573 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11574 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11575 static struct tg3_dev_id {
11576 u32 vendor;
11577 u32 device;
11578 u32 rev;
11579 } ich_chipsets[] = {
11580 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11581 PCI_ANY_ID },
11582 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11583 PCI_ANY_ID },
11584 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11585 0xa },
11586 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11587 PCI_ANY_ID },
11588 { },
11589 };
11590 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11591 struct pci_dev *bridge = NULL;
11592
11593 while (pci_id->vendor != 0) {
11594 bridge = pci_get_device(pci_id->vendor, pci_id->device,
11595 bridge);
11596 if (!bridge) {
11597 pci_id++;
11598 continue;
11599 }
11600 if (pci_id->rev != PCI_ANY_ID) {
11601 if (bridge->revision > pci_id->rev)
11602 continue;
11603 }
11604 if (bridge->subordinate &&
11605 (bridge->subordinate->number ==
11606 tp->pdev->bus->number)) {
11607
11608 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11609 pci_dev_put(bridge);
11610 break;
11611 }
11612 }
11613 }
11614
11615 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11616 static struct tg3_dev_id {
11617 u32 vendor;
11618 u32 device;
11619 } bridge_chipsets[] = {
11620 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11621 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11622 { },
11623 };
11624 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11625 struct pci_dev *bridge = NULL;
11626
11627 while (pci_id->vendor != 0) {
11628 bridge = pci_get_device(pci_id->vendor,
11629 pci_id->device,
11630 bridge);
11631 if (!bridge) {
11632 pci_id++;
11633 continue;
11634 }
11635 if (bridge->subordinate &&
11636 (bridge->subordinate->number <=
11637 tp->pdev->bus->number) &&
11638 (bridge->subordinate->subordinate >=
11639 tp->pdev->bus->number)) {
11640 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11641 pci_dev_put(bridge);
11642 break;
11643 }
11644 }
11645 }
11646
11647 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11648 * DMA addresses > 40-bit. This bridge may have other additional
11649 * 57xx devices behind it in some 4-port NIC designs for example.
11650 * Any tg3 device found behind the bridge will also need the 40-bit
11651 * DMA workaround.
11652 */
11653 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11654 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11655 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11656 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11657 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11658 }
11659 else {
11660 struct pci_dev *bridge = NULL;
11661
11662 do {
11663 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
11664 PCI_DEVICE_ID_SERVERWORKS_EPB,
11665 bridge);
11666 if (bridge && bridge->subordinate &&
11667 (bridge->subordinate->number <=
11668 tp->pdev->bus->number) &&
11669 (bridge->subordinate->subordinate >=
11670 tp->pdev->bus->number)) {
11671 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11672 pci_dev_put(bridge);
11673 break;
11674 }
11675 } while (bridge);
11676 }
11677
11678 /* Initialize misc host control in PCI block. */
11679 tp->misc_host_ctrl |= (misc_ctrl_reg &
11680 MISC_HOST_CTRL_CHIPREV);
11681 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11682 tp->misc_host_ctrl);
11683
11684 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11685 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11686 tp->pdev_peer = tg3_find_peer(tp);
11687
11688 /* Intentionally exclude ASIC_REV_5906 */
11689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11690 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11691 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11692 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11693 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11694 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11695 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
11696
11697 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11698 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11700 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11701 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11702 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
11703
11704 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
11705 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
11706 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
11707
11708 /* 5700 B0 chips do not support checksumming correctly due
11709 * to hardware bugs.
11710 */
11711 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
11712 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
11713 else {
11714 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11715 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11716 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
11717 tp->dev->features |= NETIF_F_IPV6_CSUM;
11718 }
11719
11720 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
11721 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
11722 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
11723 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
11724 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
11725 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
11726 tp->pdev_peer == tp->pdev))
11727 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
11728
11729 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
11730 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11731 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
11732 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
11733 } else {
11734 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
11735 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11736 ASIC_REV_5750 &&
11737 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
11738 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
11739 }
11740 }
11741
11742 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11743 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11744 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
11745
11746 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
11747 &pci_state_reg);
11748
11749 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
11750 if (tp->pcie_cap != 0) {
11751 u16 lnkctl;
11752
11753 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11754
11755 pcie_set_readrq(tp->pdev, 4096);
11756
11757 pci_read_config_word(tp->pdev,
11758 tp->pcie_cap + PCI_EXP_LNKCTL,
11759 &lnkctl);
11760 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
11761 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11762 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
11763 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11764 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11765 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11766 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
11767 }
11768 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
11769 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
11770 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
11771 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11772 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
11773 if (!tp->pcix_cap) {
11774 printk(KERN_ERR PFX "Cannot find PCI-X "
11775 "capability, aborting.\n");
11776 return -EIO;
11777 }
11778
11779 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
11780 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
11781 }
11782
11783 /* If we have an AMD 762 or VIA K8T800 chipset, write
11784 * reordering to the mailbox registers done by the host
11785 * controller can cause major troubles. We read back from
11786 * every mailbox register write to force the writes to be
11787 * posted to the chip in order.
11788 */
11789 if (pci_dev_present(write_reorder_chipsets) &&
11790 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11791 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
11792
11793 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
11794 &tp->pci_cacheline_sz);
11795 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11796 &tp->pci_lat_timer);
11797 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
11798 tp->pci_lat_timer < 64) {
11799 tp->pci_lat_timer = 64;
11800 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
11801 tp->pci_lat_timer);
11802 }
11803
11804 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
11805 /* 5700 BX chips need to have their TX producer index
11806 * mailboxes written twice to workaround a bug.
11807 */
11808 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
11809
11810 /* If we are in PCI-X mode, enable register write workaround.
11811 *
11812 * The workaround is to use indirect register accesses
11813 * for all chip writes not to mailbox registers.
11814 */
11815 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11816 u32 pm_reg;
11817
11818 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
11819
11820 /* The chip can have it's power management PCI config
11821 * space registers clobbered due to this bug.
11822 * So explicitly force the chip into D0 here.
11823 */
11824 pci_read_config_dword(tp->pdev,
11825 tp->pm_cap + PCI_PM_CTRL,
11826 &pm_reg);
11827 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
11828 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
11829 pci_write_config_dword(tp->pdev,
11830 tp->pm_cap + PCI_PM_CTRL,
11831 pm_reg);
11832
11833 /* Also, force SERR#/PERR# in PCI command. */
11834 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11835 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
11836 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11837 }
11838 }
11839
11840 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
11841 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
11842 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
11843 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
11844
11845 /* Chip-specific fixup from Broadcom driver */
11846 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
11847 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
11848 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
11849 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
11850 }
11851
11852 /* Default fast path register access methods */
11853 tp->read32 = tg3_read32;
11854 tp->write32 = tg3_write32;
11855 tp->read32_mbox = tg3_read32;
11856 tp->write32_mbox = tg3_write32;
11857 tp->write32_tx_mbox = tg3_write32;
11858 tp->write32_rx_mbox = tg3_write32;
11859
11860 /* Various workaround register access methods */
11861 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
11862 tp->write32 = tg3_write_indirect_reg32;
11863 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11864 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
11865 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
11866 /*
11867 * Back to back register writes can cause problems on these
11868 * chips, the workaround is to read back all reg writes
11869 * except those to mailbox regs.
11870 *
11871 * See tg3_write_indirect_reg32().
11872 */
11873 tp->write32 = tg3_write_flush_reg32;
11874 }
11875
11876
11877 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
11878 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
11879 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11880 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
11881 tp->write32_rx_mbox = tg3_write_flush_reg32;
11882 }
11883
11884 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
11885 tp->read32 = tg3_read_indirect_reg32;
11886 tp->write32 = tg3_write_indirect_reg32;
11887 tp->read32_mbox = tg3_read_indirect_mbox;
11888 tp->write32_mbox = tg3_write_indirect_mbox;
11889 tp->write32_tx_mbox = tg3_write_indirect_mbox;
11890 tp->write32_rx_mbox = tg3_write_indirect_mbox;
11891
11892 iounmap(tp->regs);
11893 tp->regs = NULL;
11894
11895 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11896 pci_cmd &= ~PCI_COMMAND_MEMORY;
11897 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11898 }
11899 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11900 tp->read32_mbox = tg3_read32_mbox_5906;
11901 tp->write32_mbox = tg3_write32_mbox_5906;
11902 tp->write32_tx_mbox = tg3_write32_mbox_5906;
11903 tp->write32_rx_mbox = tg3_write32_mbox_5906;
11904 }
11905
11906 if (tp->write32 == tg3_write_indirect_reg32 ||
11907 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11908 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11909 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
11910 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
11911
11912 /* Get eeprom hw config before calling tg3_set_power_state().
11913 * In particular, the TG3_FLG2_IS_NIC flag must be
11914 * determined before calling tg3_set_power_state() so that
11915 * we know whether or not to switch out of Vaux power.
11916 * When the flag is set, it means that GPIO1 is used for eeprom
11917 * write protect and also implies that it is a LOM where GPIOs
11918 * are not used to switch power.
11919 */
11920 tg3_get_eeprom_hw_cfg(tp);
11921
11922 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
11923 /* Allow reads and writes to the
11924 * APE register and memory space.
11925 */
11926 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
11927 PCISTATE_ALLOW_APE_SHMEM_WR;
11928 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
11929 pci_state_reg);
11930 }
11931
11932 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11933 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
11934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
11935 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11936 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
11937
11938 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
11939 * GPIO1 driven high will bring 5700's external PHY out of reset.
11940 * It is also used as eeprom write protect on LOMs.
11941 */
11942 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
11943 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11944 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
11945 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
11946 GRC_LCLCTRL_GPIO_OUTPUT1);
11947 /* Unused GPIO3 must be driven as output on 5752 because there
11948 * are no pull-up resistors on unused GPIO pins.
11949 */
11950 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11951 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
11952
11953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
11955 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
11956
11957 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
11958 /* Turn off the debug UART. */
11959 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
11960 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
11961 /* Keep VMain power. */
11962 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
11963 GRC_LCLCTRL_GPIO_OUTPUT0;
11964 }
11965
11966 /* Force the chip into D0. */
11967 err = tg3_set_power_state(tp, PCI_D0);
11968 if (err) {
11969 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
11970 pci_name(tp->pdev));
11971 return err;
11972 }
11973
11974 /* Derive initial jumbo mode from MTU assigned in
11975 * ether_setup() via the alloc_etherdev() call
11976 */
11977 if (tp->dev->mtu > ETH_DATA_LEN &&
11978 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
11979 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
11980
11981 /* Determine WakeOnLan speed to use. */
11982 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11983 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11984 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
11985 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
11986 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
11987 } else {
11988 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
11989 }
11990
11991 /* A few boards don't want Ethernet@WireSpeed phy feature */
11992 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
11993 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
11994 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
11995 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
11996 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
11997 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
11998 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
11999
12000 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12001 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12002 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12003 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12004 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12005
12006 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
12007 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12008 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12009 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
12010 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12012 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12014 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12015 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12016 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12017 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12018 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12019 } else
12020 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12021 }
12022
12023 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12024 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12025 tp->phy_otp = tg3_read_otp_phycfg(tp);
12026 if (tp->phy_otp == 0)
12027 tp->phy_otp = TG3_OTP_DEFAULT;
12028 }
12029
12030 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12031 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12032 else
12033 tp->mi_mode = MAC_MI_MODE_BASE;
12034
12035 tp->coalesce_mode = 0;
12036 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12037 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12038 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12039
12040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12042 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12043
12044 err = tg3_mdio_init(tp);
12045 if (err)
12046 return err;
12047
12048 /* Initialize data/descriptor byte/word swapping. */
12049 val = tr32(GRC_MODE);
12050 val &= GRC_MODE_HOST_STACKUP;
12051 tw32(GRC_MODE, val | tp->grc_mode);
12052
12053 tg3_switch_clocks(tp);
12054
12055 /* Clear this out for sanity. */
12056 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12057
12058 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12059 &pci_state_reg);
12060 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12061 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12062 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12063
12064 if (chiprevid == CHIPREV_ID_5701_A0 ||
12065 chiprevid == CHIPREV_ID_5701_B0 ||
12066 chiprevid == CHIPREV_ID_5701_B2 ||
12067 chiprevid == CHIPREV_ID_5701_B5) {
12068 void __iomem *sram_base;
12069
12070 /* Write some dummy words into the SRAM status block
12071 * area, see if it reads back correctly. If the return
12072 * value is bad, force enable the PCIX workaround.
12073 */
12074 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12075
12076 writel(0x00000000, sram_base);
12077 writel(0x00000000, sram_base + 4);
12078 writel(0xffffffff, sram_base + 4);
12079 if (readl(sram_base) != 0x00000000)
12080 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12081 }
12082 }
12083
12084 udelay(50);
12085 tg3_nvram_init(tp);
12086
12087 grc_misc_cfg = tr32(GRC_MISC_CFG);
12088 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12089
12090 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12091 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12092 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12093 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12094
12095 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12096 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12097 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12098 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12099 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12100 HOSTCC_MODE_CLRTICK_TXBD);
12101
12102 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12103 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12104 tp->misc_host_ctrl);
12105 }
12106
12107 /* Preserve the APE MAC_MODE bits */
12108 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
12109 tp->mac_mode = tr32(MAC_MODE) |
12110 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
12111 else
12112 tp->mac_mode = TG3_DEF_MAC_MODE;
12113
12114 /* these are limited to 10/100 only */
12115 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12116 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12117 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12118 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12119 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12120 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12121 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12122 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12123 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12124 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12125 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12126 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
12127 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12128 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12129
12130 err = tg3_phy_probe(tp);
12131 if (err) {
12132 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12133 pci_name(tp->pdev), err);
12134 /* ... but do not return immediately ... */
12135 tg3_mdio_fini(tp);
12136 }
12137
12138 tg3_read_partno(tp);
12139 tg3_read_fw_ver(tp);
12140
12141 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12142 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12143 } else {
12144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12145 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12146 else
12147 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12148 }
12149
12150 /* 5700 {AX,BX} chips have a broken status block link
12151 * change bit implementation, so we must use the
12152 * status register in those cases.
12153 */
12154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12155 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12156 else
12157 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12158
12159 /* The led_ctrl is set during tg3_phy_probe, here we might
12160 * have to force the link status polling mechanism based
12161 * upon subsystem IDs.
12162 */
12163 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12164 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12165 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12166 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12167 TG3_FLAG_USE_LINKCHG_REG);
12168 }
12169
12170 /* For all SERDES we poll the MAC status register. */
12171 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12172 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12173 else
12174 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12175
12176 tp->rx_offset = NET_IP_ALIGN;
12177 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12178 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12179 tp->rx_offset = 0;
12180
12181 tp->rx_std_max_post = TG3_RX_RING_SIZE;
12182
12183 /* Increment the rx prod index on the rx std ring by at most
12184 * 8 for these chips to workaround hw errata.
12185 */
12186 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12187 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12188 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12189 tp->rx_std_max_post = 8;
12190
12191 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12192 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12193 PCIE_PWR_MGMT_L1_THRESH_MSK;
12194
12195 return err;
12196 }
12197
12198 #ifdef CONFIG_SPARC
12199 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12200 {
12201 struct net_device *dev = tp->dev;
12202 struct pci_dev *pdev = tp->pdev;
12203 struct device_node *dp = pci_device_to_OF_node(pdev);
12204 const unsigned char *addr;
12205 int len;
12206
12207 addr = of_get_property(dp, "local-mac-address", &len);
12208 if (addr && len == 6) {
12209 memcpy(dev->dev_addr, addr, 6);
12210 memcpy(dev->perm_addr, dev->dev_addr, 6);
12211 return 0;
12212 }
12213 return -ENODEV;
12214 }
12215
12216 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12217 {
12218 struct net_device *dev = tp->dev;
12219
12220 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12221 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12222 return 0;
12223 }
12224 #endif
12225
12226 static int __devinit tg3_get_device_address(struct tg3 *tp)
12227 {
12228 struct net_device *dev = tp->dev;
12229 u32 hi, lo, mac_offset;
12230 int addr_ok = 0;
12231
12232 #ifdef CONFIG_SPARC
12233 if (!tg3_get_macaddr_sparc(tp))
12234 return 0;
12235 #endif
12236
12237 mac_offset = 0x7c;
12238 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12239 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12240 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12241 mac_offset = 0xcc;
12242 if (tg3_nvram_lock(tp))
12243 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12244 else
12245 tg3_nvram_unlock(tp);
12246 }
12247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12248 mac_offset = 0x10;
12249
12250 /* First try to get it from MAC address mailbox. */
12251 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12252 if ((hi >> 16) == 0x484b) {
12253 dev->dev_addr[0] = (hi >> 8) & 0xff;
12254 dev->dev_addr[1] = (hi >> 0) & 0xff;
12255
12256 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12257 dev->dev_addr[2] = (lo >> 24) & 0xff;
12258 dev->dev_addr[3] = (lo >> 16) & 0xff;
12259 dev->dev_addr[4] = (lo >> 8) & 0xff;
12260 dev->dev_addr[5] = (lo >> 0) & 0xff;
12261
12262 /* Some old bootcode may report a 0 MAC address in SRAM */
12263 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12264 }
12265 if (!addr_ok) {
12266 /* Next, try NVRAM. */
12267 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
12268 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12269 dev->dev_addr[0] = ((hi >> 16) & 0xff);
12270 dev->dev_addr[1] = ((hi >> 24) & 0xff);
12271 dev->dev_addr[2] = ((lo >> 0) & 0xff);
12272 dev->dev_addr[3] = ((lo >> 8) & 0xff);
12273 dev->dev_addr[4] = ((lo >> 16) & 0xff);
12274 dev->dev_addr[5] = ((lo >> 24) & 0xff);
12275 }
12276 /* Finally just fetch it out of the MAC control regs. */
12277 else {
12278 hi = tr32(MAC_ADDR_0_HIGH);
12279 lo = tr32(MAC_ADDR_0_LOW);
12280
12281 dev->dev_addr[5] = lo & 0xff;
12282 dev->dev_addr[4] = (lo >> 8) & 0xff;
12283 dev->dev_addr[3] = (lo >> 16) & 0xff;
12284 dev->dev_addr[2] = (lo >> 24) & 0xff;
12285 dev->dev_addr[1] = hi & 0xff;
12286 dev->dev_addr[0] = (hi >> 8) & 0xff;
12287 }
12288 }
12289
12290 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12291 #ifdef CONFIG_SPARC
12292 if (!tg3_get_default_macaddr_sparc(tp))
12293 return 0;
12294 #endif
12295 return -EINVAL;
12296 }
12297 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12298 return 0;
12299 }
12300
12301 #define BOUNDARY_SINGLE_CACHELINE 1
12302 #define BOUNDARY_MULTI_CACHELINE 2
12303
12304 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12305 {
12306 int cacheline_size;
12307 u8 byte;
12308 int goal;
12309
12310 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12311 if (byte == 0)
12312 cacheline_size = 1024;
12313 else
12314 cacheline_size = (int) byte * 4;
12315
12316 /* On 5703 and later chips, the boundary bits have no
12317 * effect.
12318 */
12319 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12320 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12321 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12322 goto out;
12323
12324 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12325 goal = BOUNDARY_MULTI_CACHELINE;
12326 #else
12327 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12328 goal = BOUNDARY_SINGLE_CACHELINE;
12329 #else
12330 goal = 0;
12331 #endif
12332 #endif
12333
12334 if (!goal)
12335 goto out;
12336
12337 /* PCI controllers on most RISC systems tend to disconnect
12338 * when a device tries to burst across a cache-line boundary.
12339 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12340 *
12341 * Unfortunately, for PCI-E there are only limited
12342 * write-side controls for this, and thus for reads
12343 * we will still get the disconnects. We'll also waste
12344 * these PCI cycles for both read and write for chips
12345 * other than 5700 and 5701 which do not implement the
12346 * boundary bits.
12347 */
12348 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12349 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12350 switch (cacheline_size) {
12351 case 16:
12352 case 32:
12353 case 64:
12354 case 128:
12355 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12356 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12357 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12358 } else {
12359 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12360 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12361 }
12362 break;
12363
12364 case 256:
12365 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12366 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12367 break;
12368
12369 default:
12370 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12371 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12372 break;
12373 }
12374 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12375 switch (cacheline_size) {
12376 case 16:
12377 case 32:
12378 case 64:
12379 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12380 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12381 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12382 break;
12383 }
12384 /* fallthrough */
12385 case 128:
12386 default:
12387 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12388 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12389 break;
12390 }
12391 } else {
12392 switch (cacheline_size) {
12393 case 16:
12394 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12395 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12396 DMA_RWCTRL_WRITE_BNDRY_16);
12397 break;
12398 }
12399 /* fallthrough */
12400 case 32:
12401 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12402 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12403 DMA_RWCTRL_WRITE_BNDRY_32);
12404 break;
12405 }
12406 /* fallthrough */
12407 case 64:
12408 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12409 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12410 DMA_RWCTRL_WRITE_BNDRY_64);
12411 break;
12412 }
12413 /* fallthrough */
12414 case 128:
12415 if (goal == BOUNDARY_SINGLE_CACHELINE) {
12416 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12417 DMA_RWCTRL_WRITE_BNDRY_128);
12418 break;
12419 }
12420 /* fallthrough */
12421 case 256:
12422 val |= (DMA_RWCTRL_READ_BNDRY_256 |
12423 DMA_RWCTRL_WRITE_BNDRY_256);
12424 break;
12425 case 512:
12426 val |= (DMA_RWCTRL_READ_BNDRY_512 |
12427 DMA_RWCTRL_WRITE_BNDRY_512);
12428 break;
12429 case 1024:
12430 default:
12431 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12432 DMA_RWCTRL_WRITE_BNDRY_1024);
12433 break;
12434 }
12435 }
12436
12437 out:
12438 return val;
12439 }
12440
12441 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12442 {
12443 struct tg3_internal_buffer_desc test_desc;
12444 u32 sram_dma_descs;
12445 int i, ret;
12446
12447 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12448
12449 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12450 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12451 tw32(RDMAC_STATUS, 0);
12452 tw32(WDMAC_STATUS, 0);
12453
12454 tw32(BUFMGR_MODE, 0);
12455 tw32(FTQ_RESET, 0);
12456
12457 test_desc.addr_hi = ((u64) buf_dma) >> 32;
12458 test_desc.addr_lo = buf_dma & 0xffffffff;
12459 test_desc.nic_mbuf = 0x00002100;
12460 test_desc.len = size;
12461
12462 /*
12463 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12464 * the *second* time the tg3 driver was getting loaded after an
12465 * initial scan.
12466 *
12467 * Broadcom tells me:
12468 * ...the DMA engine is connected to the GRC block and a DMA
12469 * reset may affect the GRC block in some unpredictable way...
12470 * The behavior of resets to individual blocks has not been tested.
12471 *
12472 * Broadcom noted the GRC reset will also reset all sub-components.
12473 */
12474 if (to_device) {
12475 test_desc.cqid_sqid = (13 << 8) | 2;
12476
12477 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12478 udelay(40);
12479 } else {
12480 test_desc.cqid_sqid = (16 << 8) | 7;
12481
12482 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12483 udelay(40);
12484 }
12485 test_desc.flags = 0x00000005;
12486
12487 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12488 u32 val;
12489
12490 val = *(((u32 *)&test_desc) + i);
12491 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12492 sram_dma_descs + (i * sizeof(u32)));
12493 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12494 }
12495 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12496
12497 if (to_device) {
12498 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12499 } else {
12500 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12501 }
12502
12503 ret = -ENODEV;
12504 for (i = 0; i < 40; i++) {
12505 u32 val;
12506
12507 if (to_device)
12508 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12509 else
12510 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12511 if ((val & 0xffff) == sram_dma_descs) {
12512 ret = 0;
12513 break;
12514 }
12515
12516 udelay(100);
12517 }
12518
12519 return ret;
12520 }
12521
12522 #define TEST_BUFFER_SIZE 0x2000
12523
12524 static int __devinit tg3_test_dma(struct tg3 *tp)
12525 {
12526 dma_addr_t buf_dma;
12527 u32 *buf, saved_dma_rwctrl;
12528 int ret;
12529
12530 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12531 if (!buf) {
12532 ret = -ENOMEM;
12533 goto out_nofree;
12534 }
12535
12536 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12537 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12538
12539 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12540
12541 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12542 /* DMA read watermark not used on PCIE */
12543 tp->dma_rwctrl |= 0x00180000;
12544 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12545 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12546 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12547 tp->dma_rwctrl |= 0x003f0000;
12548 else
12549 tp->dma_rwctrl |= 0x003f000f;
12550 } else {
12551 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12552 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12553 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12554 u32 read_water = 0x7;
12555
12556 /* If the 5704 is behind the EPB bridge, we can
12557 * do the less restrictive ONE_DMA workaround for
12558 * better performance.
12559 */
12560 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12561 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12562 tp->dma_rwctrl |= 0x8000;
12563 else if (ccval == 0x6 || ccval == 0x7)
12564 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12565
12566 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12567 read_water = 4;
12568 /* Set bit 23 to enable PCIX hw bug fix */
12569 tp->dma_rwctrl |=
12570 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12571 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12572 (1 << 23);
12573 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12574 /* 5780 always in PCIX mode */
12575 tp->dma_rwctrl |= 0x00144000;
12576 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12577 /* 5714 always in PCIX mode */
12578 tp->dma_rwctrl |= 0x00148000;
12579 } else {
12580 tp->dma_rwctrl |= 0x001b000f;
12581 }
12582 }
12583
12584 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12585 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12586 tp->dma_rwctrl &= 0xfffffff0;
12587
12588 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12589 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12590 /* Remove this if it causes problems for some boards. */
12591 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12592
12593 /* On 5700/5701 chips, we need to set this bit.
12594 * Otherwise the chip will issue cacheline transactions
12595 * to streamable DMA memory with not all the byte
12596 * enables turned on. This is an error on several
12597 * RISC PCI controllers, in particular sparc64.
12598 *
12599 * On 5703/5704 chips, this bit has been reassigned
12600 * a different meaning. In particular, it is used
12601 * on those chips to enable a PCI-X workaround.
12602 */
12603 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12604 }
12605
12606 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12607
12608 #if 0
12609 /* Unneeded, already done by tg3_get_invariants. */
12610 tg3_switch_clocks(tp);
12611 #endif
12612
12613 ret = 0;
12614 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12615 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12616 goto out;
12617
12618 /* It is best to perform DMA test with maximum write burst size
12619 * to expose the 5700/5701 write DMA bug.
12620 */
12621 saved_dma_rwctrl = tp->dma_rwctrl;
12622 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12623 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12624
12625 while (1) {
12626 u32 *p = buf, i;
12627
12628 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12629 p[i] = i;
12630
12631 /* Send the buffer to the chip. */
12632 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12633 if (ret) {
12634 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12635 break;
12636 }
12637
12638 #if 0
12639 /* validate data reached card RAM correctly. */
12640 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12641 u32 val;
12642 tg3_read_mem(tp, 0x2100 + (i*4), &val);
12643 if (le32_to_cpu(val) != p[i]) {
12644 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
12645 /* ret = -ENODEV here? */
12646 }
12647 p[i] = 0;
12648 }
12649 #endif
12650 /* Now read it back. */
12651 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12652 if (ret) {
12653 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12654
12655 break;
12656 }
12657
12658 /* Verify it. */
12659 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12660 if (p[i] == i)
12661 continue;
12662
12663 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12664 DMA_RWCTRL_WRITE_BNDRY_16) {
12665 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12666 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12667 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12668 break;
12669 } else {
12670 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
12671 ret = -ENODEV;
12672 goto out;
12673 }
12674 }
12675
12676 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
12677 /* Success. */
12678 ret = 0;
12679 break;
12680 }
12681 }
12682 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
12683 DMA_RWCTRL_WRITE_BNDRY_16) {
12684 static struct pci_device_id dma_wait_state_chipsets[] = {
12685 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
12686 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
12687 { },
12688 };
12689
12690 /* DMA test passed without adjusting DMA boundary,
12691 * now look for chipsets that are known to expose the
12692 * DMA bug without failing the test.
12693 */
12694 if (pci_dev_present(dma_wait_state_chipsets)) {
12695 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12696 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
12697 }
12698 else
12699 /* Safe to use the calculated DMA boundary. */
12700 tp->dma_rwctrl = saved_dma_rwctrl;
12701
12702 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12703 }
12704
12705 out:
12706 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
12707 out_nofree:
12708 return ret;
12709 }
12710
12711 static void __devinit tg3_init_link_config(struct tg3 *tp)
12712 {
12713 tp->link_config.advertising =
12714 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12715 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12716 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
12717 ADVERTISED_Autoneg | ADVERTISED_MII);
12718 tp->link_config.speed = SPEED_INVALID;
12719 tp->link_config.duplex = DUPLEX_INVALID;
12720 tp->link_config.autoneg = AUTONEG_ENABLE;
12721 tp->link_config.active_speed = SPEED_INVALID;
12722 tp->link_config.active_duplex = DUPLEX_INVALID;
12723 tp->link_config.phy_is_low_power = 0;
12724 tp->link_config.orig_speed = SPEED_INVALID;
12725 tp->link_config.orig_duplex = DUPLEX_INVALID;
12726 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12727 }
12728
12729 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
12730 {
12731 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12732 tp->bufmgr_config.mbuf_read_dma_low_water =
12733 DEFAULT_MB_RDMA_LOW_WATER_5705;
12734 tp->bufmgr_config.mbuf_mac_rx_low_water =
12735 DEFAULT_MB_MACRX_LOW_WATER_5705;
12736 tp->bufmgr_config.mbuf_high_water =
12737 DEFAULT_MB_HIGH_WATER_5705;
12738 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12739 tp->bufmgr_config.mbuf_mac_rx_low_water =
12740 DEFAULT_MB_MACRX_LOW_WATER_5906;
12741 tp->bufmgr_config.mbuf_high_water =
12742 DEFAULT_MB_HIGH_WATER_5906;
12743 }
12744
12745 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12746 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
12747 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12748 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
12749 tp->bufmgr_config.mbuf_high_water_jumbo =
12750 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
12751 } else {
12752 tp->bufmgr_config.mbuf_read_dma_low_water =
12753 DEFAULT_MB_RDMA_LOW_WATER;
12754 tp->bufmgr_config.mbuf_mac_rx_low_water =
12755 DEFAULT_MB_MACRX_LOW_WATER;
12756 tp->bufmgr_config.mbuf_high_water =
12757 DEFAULT_MB_HIGH_WATER;
12758
12759 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
12760 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
12761 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
12762 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
12763 tp->bufmgr_config.mbuf_high_water_jumbo =
12764 DEFAULT_MB_HIGH_WATER_JUMBO;
12765 }
12766
12767 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
12768 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
12769 }
12770
12771 static char * __devinit tg3_phy_string(struct tg3 *tp)
12772 {
12773 switch (tp->phy_id & PHY_ID_MASK) {
12774 case PHY_ID_BCM5400: return "5400";
12775 case PHY_ID_BCM5401: return "5401";
12776 case PHY_ID_BCM5411: return "5411";
12777 case PHY_ID_BCM5701: return "5701";
12778 case PHY_ID_BCM5703: return "5703";
12779 case PHY_ID_BCM5704: return "5704";
12780 case PHY_ID_BCM5705: return "5705";
12781 case PHY_ID_BCM5750: return "5750";
12782 case PHY_ID_BCM5752: return "5752";
12783 case PHY_ID_BCM5714: return "5714";
12784 case PHY_ID_BCM5780: return "5780";
12785 case PHY_ID_BCM5755: return "5755";
12786 case PHY_ID_BCM5787: return "5787";
12787 case PHY_ID_BCM5784: return "5784";
12788 case PHY_ID_BCM5756: return "5722/5756";
12789 case PHY_ID_BCM5906: return "5906";
12790 case PHY_ID_BCM5761: return "5761";
12791 case PHY_ID_BCM8002: return "8002/serdes";
12792 case 0: return "serdes";
12793 default: return "unknown";
12794 }
12795 }
12796
12797 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
12798 {
12799 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12800 strcpy(str, "PCI Express");
12801 return str;
12802 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
12803 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
12804
12805 strcpy(str, "PCIX:");
12806
12807 if ((clock_ctrl == 7) ||
12808 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
12809 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
12810 strcat(str, "133MHz");
12811 else if (clock_ctrl == 0)
12812 strcat(str, "33MHz");
12813 else if (clock_ctrl == 2)
12814 strcat(str, "50MHz");
12815 else if (clock_ctrl == 4)
12816 strcat(str, "66MHz");
12817 else if (clock_ctrl == 6)
12818 strcat(str, "100MHz");
12819 } else {
12820 strcpy(str, "PCI:");
12821 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
12822 strcat(str, "66MHz");
12823 else
12824 strcat(str, "33MHz");
12825 }
12826 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
12827 strcat(str, ":32-bit");
12828 else
12829 strcat(str, ":64-bit");
12830 return str;
12831 }
12832
12833 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
12834 {
12835 struct pci_dev *peer;
12836 unsigned int func, devnr = tp->pdev->devfn & ~7;
12837
12838 for (func = 0; func < 8; func++) {
12839 peer = pci_get_slot(tp->pdev->bus, devnr | func);
12840 if (peer && peer != tp->pdev)
12841 break;
12842 pci_dev_put(peer);
12843 }
12844 /* 5704 can be configured in single-port mode, set peer to
12845 * tp->pdev in that case.
12846 */
12847 if (!peer) {
12848 peer = tp->pdev;
12849 return peer;
12850 }
12851
12852 /*
12853 * We don't need to keep the refcount elevated; there's no way
12854 * to remove one half of this device without removing the other
12855 */
12856 pci_dev_put(peer);
12857
12858 return peer;
12859 }
12860
12861 static void __devinit tg3_init_coal(struct tg3 *tp)
12862 {
12863 struct ethtool_coalesce *ec = &tp->coal;
12864
12865 memset(ec, 0, sizeof(*ec));
12866 ec->cmd = ETHTOOL_GCOALESCE;
12867 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
12868 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
12869 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
12870 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
12871 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
12872 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
12873 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
12874 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
12875 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
12876
12877 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
12878 HOSTCC_MODE_CLRTICK_TXBD)) {
12879 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
12880 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
12881 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
12882 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
12883 }
12884
12885 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12886 ec->rx_coalesce_usecs_irq = 0;
12887 ec->tx_coalesce_usecs_irq = 0;
12888 ec->stats_block_coalesce_usecs = 0;
12889 }
12890 }
12891
12892 static const struct net_device_ops tg3_netdev_ops = {
12893 .ndo_open = tg3_open,
12894 .ndo_stop = tg3_close,
12895 .ndo_start_xmit = tg3_start_xmit,
12896 .ndo_get_stats = tg3_get_stats,
12897 .ndo_validate_addr = eth_validate_addr,
12898 .ndo_set_multicast_list = tg3_set_rx_mode,
12899 .ndo_set_mac_address = tg3_set_mac_addr,
12900 .ndo_do_ioctl = tg3_ioctl,
12901 .ndo_tx_timeout = tg3_tx_timeout,
12902 .ndo_change_mtu = tg3_change_mtu,
12903 #if TG3_VLAN_TAG_USED
12904 .ndo_vlan_rx_register = tg3_vlan_rx_register,
12905 #endif
12906 #ifdef CONFIG_NET_POLL_CONTROLLER
12907 .ndo_poll_controller = tg3_poll_controller,
12908 #endif
12909 };
12910
12911 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
12912 .ndo_open = tg3_open,
12913 .ndo_stop = tg3_close,
12914 .ndo_start_xmit = tg3_start_xmit_dma_bug,
12915 .ndo_get_stats = tg3_get_stats,
12916 .ndo_validate_addr = eth_validate_addr,
12917 .ndo_set_multicast_list = tg3_set_rx_mode,
12918 .ndo_set_mac_address = tg3_set_mac_addr,
12919 .ndo_do_ioctl = tg3_ioctl,
12920 .ndo_tx_timeout = tg3_tx_timeout,
12921 .ndo_change_mtu = tg3_change_mtu,
12922 #if TG3_VLAN_TAG_USED
12923 .ndo_vlan_rx_register = tg3_vlan_rx_register,
12924 #endif
12925 #ifdef CONFIG_NET_POLL_CONTROLLER
12926 .ndo_poll_controller = tg3_poll_controller,
12927 #endif
12928 };
12929
12930 static int __devinit tg3_init_one(struct pci_dev *pdev,
12931 const struct pci_device_id *ent)
12932 {
12933 static int tg3_version_printed = 0;
12934 struct net_device *dev;
12935 struct tg3 *tp;
12936 int err, pm_cap;
12937 const char *fw_name = NULL;
12938 char str[40];
12939 u64 dma_mask, persist_dma_mask;
12940
12941 if (tg3_version_printed++ == 0)
12942 printk(KERN_INFO "%s", version);
12943
12944 err = pci_enable_device(pdev);
12945 if (err) {
12946 printk(KERN_ERR PFX "Cannot enable PCI device, "
12947 "aborting.\n");
12948 return err;
12949 }
12950
12951 err = pci_request_regions(pdev, DRV_MODULE_NAME);
12952 if (err) {
12953 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
12954 "aborting.\n");
12955 goto err_out_disable_pdev;
12956 }
12957
12958 pci_set_master(pdev);
12959
12960 /* Find power-management capability. */
12961 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
12962 if (pm_cap == 0) {
12963 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
12964 "aborting.\n");
12965 err = -EIO;
12966 goto err_out_free_res;
12967 }
12968
12969 dev = alloc_etherdev(sizeof(*tp));
12970 if (!dev) {
12971 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
12972 err = -ENOMEM;
12973 goto err_out_free_res;
12974 }
12975
12976 SET_NETDEV_DEV(dev, &pdev->dev);
12977
12978 #if TG3_VLAN_TAG_USED
12979 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
12980 #endif
12981
12982 tp = netdev_priv(dev);
12983 tp->pdev = pdev;
12984 tp->dev = dev;
12985 tp->pm_cap = pm_cap;
12986 tp->rx_mode = TG3_DEF_RX_MODE;
12987 tp->tx_mode = TG3_DEF_TX_MODE;
12988
12989 if (tg3_debug > 0)
12990 tp->msg_enable = tg3_debug;
12991 else
12992 tp->msg_enable = TG3_DEF_MSG_ENABLE;
12993
12994 /* The word/byte swap controls here control register access byte
12995 * swapping. DMA data byte swapping is controlled in the GRC_MODE
12996 * setting below.
12997 */
12998 tp->misc_host_ctrl =
12999 MISC_HOST_CTRL_MASK_PCI_INT |
13000 MISC_HOST_CTRL_WORD_SWAP |
13001 MISC_HOST_CTRL_INDIR_ACCESS |
13002 MISC_HOST_CTRL_PCISTATE_RW;
13003
13004 /* The NONFRM (non-frame) byte/word swap controls take effect
13005 * on descriptor entries, anything which isn't packet data.
13006 *
13007 * The StrongARM chips on the board (one for tx, one for rx)
13008 * are running in big-endian mode.
13009 */
13010 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13011 GRC_MODE_WSWAP_NONFRM_DATA);
13012 #ifdef __BIG_ENDIAN
13013 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13014 #endif
13015 spin_lock_init(&tp->lock);
13016 spin_lock_init(&tp->indirect_lock);
13017 INIT_WORK(&tp->reset_task, tg3_reset_task);
13018
13019 tp->regs = pci_ioremap_bar(pdev, BAR_0);
13020 if (!tp->regs) {
13021 printk(KERN_ERR PFX "Cannot map device registers, "
13022 "aborting.\n");
13023 err = -ENOMEM;
13024 goto err_out_free_dev;
13025 }
13026
13027 tg3_init_link_config(tp);
13028
13029 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13030 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13031 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13032
13033 netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13034 dev->ethtool_ops = &tg3_ethtool_ops;
13035 dev->watchdog_timeo = TG3_TX_TIMEOUT;
13036 dev->irq = pdev->irq;
13037
13038 err = tg3_get_invariants(tp);
13039 if (err) {
13040 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13041 "aborting.\n");
13042 goto err_out_iounmap;
13043 }
13044
13045 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13047 dev->netdev_ops = &tg3_netdev_ops;
13048 else
13049 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
13050
13051
13052 /* The EPB bridge inside 5714, 5715, and 5780 and any
13053 * device behind the EPB cannot support DMA addresses > 40-bit.
13054 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13055 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13056 * do DMA address check in tg3_start_xmit().
13057 */
13058 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13059 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13060 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13061 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13062 #ifdef CONFIG_HIGHMEM
13063 dma_mask = DMA_64BIT_MASK;
13064 #endif
13065 } else
13066 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13067
13068 /* Configure DMA attributes. */
13069 if (dma_mask > DMA_32BIT_MASK) {
13070 err = pci_set_dma_mask(pdev, dma_mask);
13071 if (!err) {
13072 dev->features |= NETIF_F_HIGHDMA;
13073 err = pci_set_consistent_dma_mask(pdev,
13074 persist_dma_mask);
13075 if (err < 0) {
13076 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13077 "DMA for consistent allocations\n");
13078 goto err_out_iounmap;
13079 }
13080 }
13081 }
13082 if (err || dma_mask == DMA_32BIT_MASK) {
13083 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13084 if (err) {
13085 printk(KERN_ERR PFX "No usable DMA configuration, "
13086 "aborting.\n");
13087 goto err_out_iounmap;
13088 }
13089 }
13090
13091 tg3_init_bufmgr_config(tp);
13092
13093 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13094 fw_name = FIRMWARE_TG3;
13095
13096 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13097 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13098 }
13099 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13101 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13103 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13104 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13105 } else {
13106 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13107 }
13108 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
13109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13110 fw_name = FIRMWARE_TG3TSO5;
13111 else
13112 fw_name = FIRMWARE_TG3TSO;
13113 }
13114
13115 if (fw_name) {
13116 const __be32 *fw_data;
13117
13118 err = request_firmware(&tp->fw, fw_name, &tp->pdev->dev);
13119 if (err) {
13120 printk(KERN_ERR "tg3: Failed to load firmware \"%s\"\n",
13121 fw_name);
13122 goto err_out_iounmap;
13123 }
13124
13125 fw_data = (void *)tp->fw->data;
13126
13127 /* Firmware blob starts with version numbers, followed by
13128 start address and _full_ length including BSS sections
13129 (which must be longer than the actual data, of course */
13130
13131 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
13132 if (tp->fw_len < (tp->fw->size - 12)) {
13133 printk(KERN_ERR "tg3: bogus length %d in \"%s\"\n",
13134 tp->fw_len, fw_name);
13135 err = -EINVAL;
13136 goto err_out_fw;
13137 }
13138 }
13139
13140 /* TSO is on by default on chips that support hardware TSO.
13141 * Firmware TSO on older chips gives lower performance, so it
13142 * is off by default, but can be enabled using ethtool.
13143 */
13144 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13145 if (dev->features & NETIF_F_IP_CSUM)
13146 dev->features |= NETIF_F_TSO;
13147 if ((dev->features & NETIF_F_IPV6_CSUM) &&
13148 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2))
13149 dev->features |= NETIF_F_TSO6;
13150 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13151 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13152 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13153 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13154 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13155 dev->features |= NETIF_F_TSO_ECN;
13156 }
13157
13158
13159 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13160 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13161 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13162 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13163 tp->rx_pending = 63;
13164 }
13165
13166 err = tg3_get_device_address(tp);
13167 if (err) {
13168 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13169 "aborting.\n");
13170 goto err_out_fw;
13171 }
13172
13173 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13174 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
13175 if (!tp->aperegs) {
13176 printk(KERN_ERR PFX "Cannot map APE registers, "
13177 "aborting.\n");
13178 err = -ENOMEM;
13179 goto err_out_fw;
13180 }
13181
13182 tg3_ape_lock_init(tp);
13183 }
13184
13185 /*
13186 * Reset chip in case UNDI or EFI driver did not shutdown
13187 * DMA self test will enable WDMAC and we'll see (spurious)
13188 * pending DMA on the PCI bus at that point.
13189 */
13190 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13191 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13192 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13193 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13194 }
13195
13196 err = tg3_test_dma(tp);
13197 if (err) {
13198 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13199 goto err_out_apeunmap;
13200 }
13201
13202 /* flow control autonegotiation is default behavior */
13203 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13204 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13205
13206 tg3_init_coal(tp);
13207
13208 pci_set_drvdata(pdev, dev);
13209
13210 err = register_netdev(dev);
13211 if (err) {
13212 printk(KERN_ERR PFX "Cannot register net device, "
13213 "aborting.\n");
13214 goto err_out_apeunmap;
13215 }
13216
13217 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13218 dev->name,
13219 tp->board_part_number,
13220 tp->pci_chip_rev_id,
13221 tg3_bus_string(tp, str),
13222 dev->dev_addr);
13223
13224 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
13225 printk(KERN_INFO
13226 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13227 tp->dev->name,
13228 tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
13229 dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
13230 else
13231 printk(KERN_INFO
13232 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13233 tp->dev->name, tg3_phy_string(tp),
13234 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13235 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13236 "10/100/1000Base-T")),
13237 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
13238
13239 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13240 dev->name,
13241 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13242 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13243 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13244 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13245 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13246 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13247 dev->name, tp->dma_rwctrl,
13248 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13249 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13250
13251 return 0;
13252
13253 err_out_apeunmap:
13254 if (tp->aperegs) {
13255 iounmap(tp->aperegs);
13256 tp->aperegs = NULL;
13257 }
13258
13259 err_out_fw:
13260 if (tp->fw)
13261 release_firmware(tp->fw);
13262
13263 err_out_iounmap:
13264 if (tp->regs) {
13265 iounmap(tp->regs);
13266 tp->regs = NULL;
13267 }
13268
13269 err_out_free_dev:
13270 free_netdev(dev);
13271
13272 err_out_free_res:
13273 pci_release_regions(pdev);
13274
13275 err_out_disable_pdev:
13276 pci_disable_device(pdev);
13277 pci_set_drvdata(pdev, NULL);
13278 return err;
13279 }
13280
13281 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13282 {
13283 struct net_device *dev = pci_get_drvdata(pdev);
13284
13285 if (dev) {
13286 struct tg3 *tp = netdev_priv(dev);
13287
13288 if (tp->fw)
13289 release_firmware(tp->fw);
13290
13291 flush_scheduled_work();
13292
13293 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13294 tg3_phy_fini(tp);
13295 tg3_mdio_fini(tp);
13296 }
13297
13298 unregister_netdev(dev);
13299 if (tp->aperegs) {
13300 iounmap(tp->aperegs);
13301 tp->aperegs = NULL;
13302 }
13303 if (tp->regs) {
13304 iounmap(tp->regs);
13305 tp->regs = NULL;
13306 }
13307 free_netdev(dev);
13308 pci_release_regions(pdev);
13309 pci_disable_device(pdev);
13310 pci_set_drvdata(pdev, NULL);
13311 }
13312 }
13313
13314 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13315 {
13316 struct net_device *dev = pci_get_drvdata(pdev);
13317 struct tg3 *tp = netdev_priv(dev);
13318 pci_power_t target_state;
13319 int err;
13320
13321 /* PCI register 4 needs to be saved whether netif_running() or not.
13322 * MSI address and data need to be saved if using MSI and
13323 * netif_running().
13324 */
13325 pci_save_state(pdev);
13326
13327 if (!netif_running(dev))
13328 return 0;
13329
13330 flush_scheduled_work();
13331 tg3_phy_stop(tp);
13332 tg3_netif_stop(tp);
13333
13334 del_timer_sync(&tp->timer);
13335
13336 tg3_full_lock(tp, 1);
13337 tg3_disable_ints(tp);
13338 tg3_full_unlock(tp);
13339
13340 netif_device_detach(dev);
13341
13342 tg3_full_lock(tp, 0);
13343 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13344 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13345 tg3_full_unlock(tp);
13346
13347 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
13348
13349 err = tg3_set_power_state(tp, target_state);
13350 if (err) {
13351 int err2;
13352
13353 tg3_full_lock(tp, 0);
13354
13355 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13356 err2 = tg3_restart_hw(tp, 1);
13357 if (err2)
13358 goto out;
13359
13360 tp->timer.expires = jiffies + tp->timer_offset;
13361 add_timer(&tp->timer);
13362
13363 netif_device_attach(dev);
13364 tg3_netif_start(tp);
13365
13366 out:
13367 tg3_full_unlock(tp);
13368
13369 if (!err2)
13370 tg3_phy_start(tp);
13371 }
13372
13373 return err;
13374 }
13375
13376 static int tg3_resume(struct pci_dev *pdev)
13377 {
13378 struct net_device *dev = pci_get_drvdata(pdev);
13379 struct tg3 *tp = netdev_priv(dev);
13380 int err;
13381
13382 pci_restore_state(tp->pdev);
13383
13384 if (!netif_running(dev))
13385 return 0;
13386
13387 err = tg3_set_power_state(tp, PCI_D0);
13388 if (err)
13389 return err;
13390
13391 netif_device_attach(dev);
13392
13393 tg3_full_lock(tp, 0);
13394
13395 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13396 err = tg3_restart_hw(tp, 1);
13397 if (err)
13398 goto out;
13399
13400 tp->timer.expires = jiffies + tp->timer_offset;
13401 add_timer(&tp->timer);
13402
13403 tg3_netif_start(tp);
13404
13405 out:
13406 tg3_full_unlock(tp);
13407
13408 if (!err)
13409 tg3_phy_start(tp);
13410
13411 return err;
13412 }
13413
13414 static struct pci_driver tg3_driver = {
13415 .name = DRV_MODULE_NAME,
13416 .id_table = tg3_pci_tbl,
13417 .probe = tg3_init_one,
13418 .remove = __devexit_p(tg3_remove_one),
13419 .suspend = tg3_suspend,
13420 .resume = tg3_resume
13421 };
13422
13423 static int __init tg3_init(void)
13424 {
13425 return pci_register_driver(&tg3_driver);
13426 }
13427
13428 static void __exit tg3_cleanup(void)
13429 {
13430 pci_unregister_driver(&tg3_driver);
13431 }
13432
13433 module_init(tg3_init);
13434 module_exit(tg3_cleanup);
Support for the Chinese Samsung S3C2440 based development boards