arch/x86/pci/visws.c

   1 /*
   2  *      Low-Level PCI Support for SGI Visual Workstation
   3  *
   4  *      (c) 1999--2000 Martin Mares <mj@ucw.cz>
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/pci.h>
   9 #include <linux/init.h>
  10
  11 #include <asm/setup.h>
  12 #include <asm/visws/cobalt.h>
  13 #include <asm/visws/lithium.h>
  14
  15 #include "pci.h"
  16
  17 static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
  18 static void pci_visws_disable_irq(struct pci_dev *dev) { }
  19
  20 /* int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq; */
  21 /* void (*pcibios_disable_irq)(struct pci_dev *dev) = &pci_visws_disable_irq; */
  22
  23 /* void __init pcibios_penalize_isa_irq(int irq, int active) {} */
  24
  25
  26 unsigned int pci_bus0, pci_bus1;
  27
  28 static inline u8 bridge_swizzle(u8 pin, u8 slot)
  29 {
  30         return (((pin - 1) + slot) % 4) + 1;
  31 }
  32
  33 static u8 __init visws_swizzle(struct pci_dev *dev, u8 *pinp)
  34 {
  35         u8 pin = *pinp;
  36
  37         while (dev->bus->self) {        /* Move up the chain of bridges. */
  38                 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
  39                 dev = dev->bus->self;
  40         }
  41         *pinp = pin;
  42
  43         return PCI_SLOT(dev->devfn);
  44 }
  45
  46 static int __init visws_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  47 {
  48         int irq, bus = dev->bus->number;
  49
  50         pin--;
  51
  52         /* Nothing useful at PIIX4 pin 1 */
  53         if (bus == pci_bus0 && slot == 4 && pin == 0)
  54                 return -1;
  55
  56         /* PIIX4 USB is on Bus 0, Slot 4, Line 3 */
  57         if (bus == pci_bus0 && slot == 4 && pin == 3) {
  58                 irq = CO_IRQ(CO_APIC_PIIX4_USB);
  59                 goto out;
  60         }
  61
  62         /* First pin spread down 1 APIC entry per slot */
  63         if (pin == 0) {
  64                 irq = CO_IRQ((bus == pci_bus0 ? CO_APIC_PCIB_BASE0 :
  65                                                 CO_APIC_PCIA_BASE0) + slot);
  66                 goto out;
  67         }
  68
  69         /* lines 1,2,3 from any slot is shared in this twirly pattern */
  70         if (bus == pci_bus1) {
  71                 /* lines 1-3 from devices 0 1 rotate over 2 apic entries */
  72                 irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((slot + (pin - 1)) % 2));
  73         } else { /* bus == pci_bus0 */
  74                 /* lines 1-3 from devices 0-3 rotate over 3 apic entries */
  75                 if (slot == 0)
  76                         slot = 3; /* same pattern */
  77                 irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((3 - slot) + (pin - 1) % 3));
  78         }
  79 out:
  80         printk(KERN_DEBUG "PCI: Bus %d Slot %d Line %d -> IRQ %d\n", bus, slot, pin, irq);
  81         return irq;
  82 }
  83
  84 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
  85 {
  86         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
  87 }
  88
  89 int __init pci_visws_init(void)
  90 {
  91         if (!is_visws_box())
  92                 return -1;
  93
  94         pcibios_enable_irq = &pci_visws_enable_irq;
  95         pcibios_disable_irq = &pci_visws_disable_irq;
  96
  97         /* The VISWS supports configuration access type 1 only */
  98         pci_probe = (pci_probe | PCI_PROBE_CONF1) &
  99                     ~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);
 100
 101         pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
 102         pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
 103
 104         printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
 105                 "bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
 106
 107         raw_pci_ops = &pci_direct_conf1;
 108         pci_scan_bus_with_sysdata(pci_bus0);
 109         pci_scan_bus_with_sysdata(pci_bus1);
 110         pci_fixup_irqs(visws_swizzle, visws_map_irq);
 111         pcibios_resource_survey();
 112         return 0;
 113 }