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zd1201: convert to internal net_device_stats
[linux-2.6/mini2440.git] / arch / arm / plat-omap / gpio.c
blobf856a90b264e3939042371fda8652d22ab2da9ba
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/io.h>
21
22 #include <mach/hardware.h>
23 #include <asm/irq.h>
24 #include <mach/irqs.h>
25 #include <mach/gpio.h>
26 #include <asm/mach/irq.h>
27
28 /*
29 * OMAP1510 GPIO registers
30 */
31 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
32 #define OMAP1510_GPIO_DATA_INPUT 0x00
33 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
34 #define OMAP1510_GPIO_DIR_CONTROL 0x08
35 #define OMAP1510_GPIO_INT_CONTROL 0x0c
36 #define OMAP1510_GPIO_INT_MASK 0x10
37 #define OMAP1510_GPIO_INT_STATUS 0x14
38 #define OMAP1510_GPIO_PIN_CONTROL 0x18
39
40 #define OMAP1510_IH_GPIO_BASE 64
41
42 /*
43 * OMAP1610 specific GPIO registers
44 */
45 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
66
67 /*
68 * OMAP730 specific GPIO registers
69 */
70 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
76 #define OMAP730_GPIO_DATA_INPUT 0x00
77 #define OMAP730_GPIO_DATA_OUTPUT 0x04
78 #define OMAP730_GPIO_DIR_CONTROL 0x08
79 #define OMAP730_GPIO_INT_CONTROL 0x0c
80 #define OMAP730_GPIO_INT_MASK 0x10
81 #define OMAP730_GPIO_INT_STATUS 0x14
82
83 /*
84 * omap24xx specific GPIO registers
85 */
86 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
90
91 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
96
97 #define OMAP24XX_GPIO_REVISION 0x0000
98 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
99 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
100 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
101 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
103 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
104 #define OMAP24XX_GPIO_WAKE_EN 0x0020
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
121
122 /*
123 * omap34xx specific GPIO registers
124 */
125
126 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
127 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
128 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
129 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
130 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
131 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
132
133 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
134
135 struct gpio_bank {
136 void __iomem *base;
137 u16 irq;
138 u16 virtual_irq_start;
139 int method;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
141 u32 suspend_wakeup;
142 u32 saved_wakeup;
143 #endif
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
147
148 u32 saved_datain;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
151 #endif
152 u32 level_mask;
153 spinlock_t lock;
154 struct gpio_chip chip;
155 struct clk *dbck;
156 };
157
158 #define METHOD_MPUIO 0
159 #define METHOD_GPIO_1510 1
160 #define METHOD_GPIO_1610 2
161 #define METHOD_GPIO_730 3
162 #define METHOD_GPIO_24XX 4
163
164 #ifdef CONFIG_ARCH_OMAP16XX
165 static struct gpio_bank gpio_bank_1610[5] = {
166 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
167 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
169 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
170 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
171 };
172 #endif
173
174 #ifdef CONFIG_ARCH_OMAP15XX
175 static struct gpio_bank gpio_bank_1510[2] = {
176 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
177 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
178 };
179 #endif
180
181 #ifdef CONFIG_ARCH_OMAP730
182 static struct gpio_bank gpio_bank_730[7] = {
183 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
184 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
185 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
186 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
187 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
188 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
189 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
190 };
191 #endif
192
193 #ifdef CONFIG_ARCH_OMAP24XX
194
195 static struct gpio_bank gpio_bank_242x[4] = {
196 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
198 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
199 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
200 };
201
202 static struct gpio_bank gpio_bank_243x[5] = {
203 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
206 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
207 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
208 };
209
210 #endif
211
212 #ifdef CONFIG_ARCH_OMAP34XX
213 static struct gpio_bank gpio_bank_34xx[6] = {
214 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
218 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
219 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
220 };
221
222 #endif
223
224 static struct gpio_bank *gpio_bank;
225 static int gpio_bank_count;
226
227 static inline struct gpio_bank *get_gpio_bank(int gpio)
228 {
229 if (cpu_is_omap15xx()) {
230 if (OMAP_GPIO_IS_MPUIO(gpio))
231 return &gpio_bank[0];
232 return &gpio_bank[1];
233 }
234 if (cpu_is_omap16xx()) {
235 if (OMAP_GPIO_IS_MPUIO(gpio))
236 return &gpio_bank[0];
237 return &gpio_bank[1 + (gpio >> 4)];
238 }
239 if (cpu_is_omap730()) {
240 if (OMAP_GPIO_IS_MPUIO(gpio))
241 return &gpio_bank[0];
242 return &gpio_bank[1 + (gpio >> 5)];
243 }
244 if (cpu_is_omap24xx())
245 return &gpio_bank[gpio >> 5];
246 if (cpu_is_omap34xx())
247 return &gpio_bank[gpio >> 5];
248 BUG();
249 return NULL;
250 }
251
252 static inline int get_gpio_index(int gpio)
253 {
254 if (cpu_is_omap730())
255 return gpio & 0x1f;
256 if (cpu_is_omap24xx())
257 return gpio & 0x1f;
258 if (cpu_is_omap34xx())
259 return gpio & 0x1f;
260 return gpio & 0x0f;
261 }
262
263 static inline int gpio_valid(int gpio)
264 {
265 if (gpio < 0)
266 return -1;
267 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
268 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
269 return -1;
270 return 0;
271 }
272 if (cpu_is_omap15xx() && gpio < 16)
273 return 0;
274 if ((cpu_is_omap16xx()) && gpio < 64)
275 return 0;
276 if (cpu_is_omap730() && gpio < 192)
277 return 0;
278 if (cpu_is_omap24xx() && gpio < 128)
279 return 0;
280 if (cpu_is_omap34xx() && gpio < 160)
281 return 0;
282 return -1;
283 }
284
285 static int check_gpio(int gpio)
286 {
287 if (unlikely(gpio_valid(gpio)) < 0) {
288 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
289 dump_stack();
290 return -1;
291 }
292 return 0;
293 }
294
295 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
296 {
297 void __iomem *reg = bank->base;
298 u32 l;
299
300 switch (bank->method) {
301 #ifdef CONFIG_ARCH_OMAP1
302 case METHOD_MPUIO:
303 reg += OMAP_MPUIO_IO_CNTL;
304 break;
305 #endif
306 #ifdef CONFIG_ARCH_OMAP15XX
307 case METHOD_GPIO_1510:
308 reg += OMAP1510_GPIO_DIR_CONTROL;
309 break;
310 #endif
311 #ifdef CONFIG_ARCH_OMAP16XX
312 case METHOD_GPIO_1610:
313 reg += OMAP1610_GPIO_DIRECTION;
314 break;
315 #endif
316 #ifdef CONFIG_ARCH_OMAP730
317 case METHOD_GPIO_730:
318 reg += OMAP730_GPIO_DIR_CONTROL;
319 break;
320 #endif
321 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
322 case METHOD_GPIO_24XX:
323 reg += OMAP24XX_GPIO_OE;
324 break;
325 #endif
326 default:
327 WARN_ON(1);
328 return;
329 }
330 l = __raw_readl(reg);
331 if (is_input)
332 l |= 1 << gpio;
333 else
334 l &= ~(1 << gpio);
335 __raw_writel(l, reg);
336 }
337
338 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
339 {
340 void __iomem *reg = bank->base;
341 u32 l = 0;
342
343 switch (bank->method) {
344 #ifdef CONFIG_ARCH_OMAP1
345 case METHOD_MPUIO:
346 reg += OMAP_MPUIO_OUTPUT;
347 l = __raw_readl(reg);
348 if (enable)
349 l |= 1 << gpio;
350 else
351 l &= ~(1 << gpio);
352 break;
353 #endif
354 #ifdef CONFIG_ARCH_OMAP15XX
355 case METHOD_GPIO_1510:
356 reg += OMAP1510_GPIO_DATA_OUTPUT;
357 l = __raw_readl(reg);
358 if (enable)
359 l |= 1 << gpio;
360 else
361 l &= ~(1 << gpio);
362 break;
363 #endif
364 #ifdef CONFIG_ARCH_OMAP16XX
365 case METHOD_GPIO_1610:
366 if (enable)
367 reg += OMAP1610_GPIO_SET_DATAOUT;
368 else
369 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
370 l = 1 << gpio;
371 break;
372 #endif
373 #ifdef CONFIG_ARCH_OMAP730
374 case METHOD_GPIO_730:
375 reg += OMAP730_GPIO_DATA_OUTPUT;
376 l = __raw_readl(reg);
377 if (enable)
378 l |= 1 << gpio;
379 else
380 l &= ~(1 << gpio);
381 break;
382 #endif
383 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
384 case METHOD_GPIO_24XX:
385 if (enable)
386 reg += OMAP24XX_GPIO_SETDATAOUT;
387 else
388 reg += OMAP24XX_GPIO_CLEARDATAOUT;
389 l = 1 << gpio;
390 break;
391 #endif
392 default:
393 WARN_ON(1);
394 return;
395 }
396 __raw_writel(l, reg);
397 }
398
399 static int __omap_get_gpio_datain(int gpio)
400 {
401 struct gpio_bank *bank;
402 void __iomem *reg;
403
404 if (check_gpio(gpio) < 0)
405 return -EINVAL;
406 bank = get_gpio_bank(gpio);
407 reg = bank->base;
408 switch (bank->method) {
409 #ifdef CONFIG_ARCH_OMAP1
410 case METHOD_MPUIO:
411 reg += OMAP_MPUIO_INPUT_LATCH;
412 break;
413 #endif
414 #ifdef CONFIG_ARCH_OMAP15XX
415 case METHOD_GPIO_1510:
416 reg += OMAP1510_GPIO_DATA_INPUT;
417 break;
418 #endif
419 #ifdef CONFIG_ARCH_OMAP16XX
420 case METHOD_GPIO_1610:
421 reg += OMAP1610_GPIO_DATAIN;
422 break;
423 #endif
424 #ifdef CONFIG_ARCH_OMAP730
425 case METHOD_GPIO_730:
426 reg += OMAP730_GPIO_DATA_INPUT;
427 break;
428 #endif
429 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
430 case METHOD_GPIO_24XX:
431 reg += OMAP24XX_GPIO_DATAIN;
432 break;
433 #endif
434 default:
435 return -EINVAL;
436 }
437 return (__raw_readl(reg)
438 & (1 << get_gpio_index(gpio))) != 0;
439 }
440
441 #define MOD_REG_BIT(reg, bit_mask, set) \
442 do { \
443 int l = __raw_readl(base + reg); \
444 if (set) l |= bit_mask; \
445 else l &= ~bit_mask; \
446 __raw_writel(l, base + reg); \
447 } while(0)
448
449 void omap_set_gpio_debounce(int gpio, int enable)
450 {
451 struct gpio_bank *bank;
452 void __iomem *reg;
453 unsigned long flags;
454 u32 val, l = 1 << get_gpio_index(gpio);
455
456 if (cpu_class_is_omap1())
457 return;
458
459 bank = get_gpio_bank(gpio);
460 reg = bank->base;
461 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
462
463 spin_lock_irqsave(&bank->lock, flags);
464 val = __raw_readl(reg);
465
466 if (enable && !(val & l))
467 val |= l;
468 else if (!enable && (val & l))
469 val &= ~l;
470 else
471 goto done;
472
473 if (cpu_is_omap34xx()) {
474 if (enable)
475 clk_enable(bank->dbck);
476 else
477 clk_disable(bank->dbck);
478 }
479
480 __raw_writel(val, reg);
481 done:
482 spin_unlock_irqrestore(&bank->lock, flags);
483 }
484 EXPORT_SYMBOL(omap_set_gpio_debounce);
485
486 void omap_set_gpio_debounce_time(int gpio, int enc_time)
487 {
488 struct gpio_bank *bank;
489 void __iomem *reg;
490
491 if (cpu_class_is_omap1())
492 return;
493
494 bank = get_gpio_bank(gpio);
495 reg = bank->base;
496
497 enc_time &= 0xff;
498 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
499 __raw_writel(enc_time, reg);
500 }
501 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
502
503 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
504 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
505 int trigger)
506 {
507 void __iomem *base = bank->base;
508 u32 gpio_bit = 1 << gpio;
509
510 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
511 trigger & IRQ_TYPE_LEVEL_LOW);
512 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
513 trigger & IRQ_TYPE_LEVEL_HIGH);
514 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
515 trigger & IRQ_TYPE_EDGE_RISING);
516 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
517 trigger & IRQ_TYPE_EDGE_FALLING);
518
519 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
520 if (trigger != 0)
521 __raw_writel(1 << gpio, bank->base
522 + OMAP24XX_GPIO_SETWKUENA);
523 else
524 __raw_writel(1 << gpio, bank->base
525 + OMAP24XX_GPIO_CLEARWKUENA);
526 } else {
527 if (trigger != 0)
528 bank->enabled_non_wakeup_gpios |= gpio_bit;
529 else
530 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
531 }
532
533 bank->level_mask =
534 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
535 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
536 }
537 #endif
538
539 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
540 {
541 void __iomem *reg = bank->base;
542 u32 l = 0;
543
544 switch (bank->method) {
545 #ifdef CONFIG_ARCH_OMAP1
546 case METHOD_MPUIO:
547 reg += OMAP_MPUIO_GPIO_INT_EDGE;
548 l = __raw_readl(reg);
549 if (trigger & IRQ_TYPE_EDGE_RISING)
550 l |= 1 << gpio;
551 else if (trigger & IRQ_TYPE_EDGE_FALLING)
552 l &= ~(1 << gpio);
553 else
554 goto bad;
555 break;
556 #endif
557 #ifdef CONFIG_ARCH_OMAP15XX
558 case METHOD_GPIO_1510:
559 reg += OMAP1510_GPIO_INT_CONTROL;
560 l = __raw_readl(reg);
561 if (trigger & IRQ_TYPE_EDGE_RISING)
562 l |= 1 << gpio;
563 else if (trigger & IRQ_TYPE_EDGE_FALLING)
564 l &= ~(1 << gpio);
565 else
566 goto bad;
567 break;
568 #endif
569 #ifdef CONFIG_ARCH_OMAP16XX
570 case METHOD_GPIO_1610:
571 if (gpio & 0x08)
572 reg += OMAP1610_GPIO_EDGE_CTRL2;
573 else
574 reg += OMAP1610_GPIO_EDGE_CTRL1;
575 gpio &= 0x07;
576 l = __raw_readl(reg);
577 l &= ~(3 << (gpio << 1));
578 if (trigger & IRQ_TYPE_EDGE_RISING)
579 l |= 2 << (gpio << 1);
580 if (trigger & IRQ_TYPE_EDGE_FALLING)
581 l |= 1 << (gpio << 1);
582 if (trigger)
583 /* Enable wake-up during idle for dynamic tick */
584 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
585 else
586 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
587 break;
588 #endif
589 #ifdef CONFIG_ARCH_OMAP730
590 case METHOD_GPIO_730:
591 reg += OMAP730_GPIO_INT_CONTROL;
592 l = __raw_readl(reg);
593 if (trigger & IRQ_TYPE_EDGE_RISING)
594 l |= 1 << gpio;
595 else if (trigger & IRQ_TYPE_EDGE_FALLING)
596 l &= ~(1 << gpio);
597 else
598 goto bad;
599 break;
600 #endif
601 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
602 case METHOD_GPIO_24XX:
603 set_24xx_gpio_triggering(bank, gpio, trigger);
604 break;
605 #endif
606 default:
607 goto bad;
608 }
609 __raw_writel(l, reg);
610 return 0;
611 bad:
612 return -EINVAL;
613 }
614
615 static int gpio_irq_type(unsigned irq, unsigned type)
616 {
617 struct gpio_bank *bank;
618 unsigned gpio;
619 int retval;
620 unsigned long flags;
621
622 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
623 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
624 else
625 gpio = irq - IH_GPIO_BASE;
626
627 if (check_gpio(gpio) < 0)
628 return -EINVAL;
629
630 if (type & ~IRQ_TYPE_SENSE_MASK)
631 return -EINVAL;
632
633 /* OMAP1 allows only only edge triggering */
634 if (!cpu_class_is_omap2()
635 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
636 return -EINVAL;
637
638 bank = get_irq_chip_data(irq);
639 spin_lock_irqsave(&bank->lock, flags);
640 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
641 if (retval == 0) {
642 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
643 irq_desc[irq].status |= type;
644 }
645 spin_unlock_irqrestore(&bank->lock, flags);
646
647 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
648 __set_irq_handler_unlocked(irq, handle_level_irq);
649 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
650 __set_irq_handler_unlocked(irq, handle_edge_irq);
651
652 return retval;
653 }
654
655 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
656 {
657 void __iomem *reg = bank->base;
658
659 switch (bank->method) {
660 #ifdef CONFIG_ARCH_OMAP1
661 case METHOD_MPUIO:
662 /* MPUIO irqstatus is reset by reading the status register,
663 * so do nothing here */
664 return;
665 #endif
666 #ifdef CONFIG_ARCH_OMAP15XX
667 case METHOD_GPIO_1510:
668 reg += OMAP1510_GPIO_INT_STATUS;
669 break;
670 #endif
671 #ifdef CONFIG_ARCH_OMAP16XX
672 case METHOD_GPIO_1610:
673 reg += OMAP1610_GPIO_IRQSTATUS1;
674 break;
675 #endif
676 #ifdef CONFIG_ARCH_OMAP730
677 case METHOD_GPIO_730:
678 reg += OMAP730_GPIO_INT_STATUS;
679 break;
680 #endif
681 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
682 case METHOD_GPIO_24XX:
683 reg += OMAP24XX_GPIO_IRQSTATUS1;
684 break;
685 #endif
686 default:
687 WARN_ON(1);
688 return;
689 }
690 __raw_writel(gpio_mask, reg);
691
692 /* Workaround for clearing DSP GPIO interrupts to allow retention */
693 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
694 if (cpu_is_omap24xx() || cpu_is_omap34xx())
695 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
696 #endif
697 }
698
699 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
700 {
701 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
702 }
703
704 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
705 {
706 void __iomem *reg = bank->base;
707 int inv = 0;
708 u32 l;
709 u32 mask;
710
711 switch (bank->method) {
712 #ifdef CONFIG_ARCH_OMAP1
713 case METHOD_MPUIO:
714 reg += OMAP_MPUIO_GPIO_MASKIT;
715 mask = 0xffff;
716 inv = 1;
717 break;
718 #endif
719 #ifdef CONFIG_ARCH_OMAP15XX
720 case METHOD_GPIO_1510:
721 reg += OMAP1510_GPIO_INT_MASK;
722 mask = 0xffff;
723 inv = 1;
724 break;
725 #endif
726 #ifdef CONFIG_ARCH_OMAP16XX
727 case METHOD_GPIO_1610:
728 reg += OMAP1610_GPIO_IRQENABLE1;
729 mask = 0xffff;
730 break;
731 #endif
732 #ifdef CONFIG_ARCH_OMAP730
733 case METHOD_GPIO_730:
734 reg += OMAP730_GPIO_INT_MASK;
735 mask = 0xffffffff;
736 inv = 1;
737 break;
738 #endif
739 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
740 case METHOD_GPIO_24XX:
741 reg += OMAP24XX_GPIO_IRQENABLE1;
742 mask = 0xffffffff;
743 break;
744 #endif
745 default:
746 WARN_ON(1);
747 return 0;
748 }
749
750 l = __raw_readl(reg);
751 if (inv)
752 l = ~l;
753 l &= mask;
754 return l;
755 }
756
757 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
758 {
759 void __iomem *reg = bank->base;
760 u32 l;
761
762 switch (bank->method) {
763 #ifdef CONFIG_ARCH_OMAP1
764 case METHOD_MPUIO:
765 reg += OMAP_MPUIO_GPIO_MASKIT;
766 l = __raw_readl(reg);
767 if (enable)
768 l &= ~(gpio_mask);
769 else
770 l |= gpio_mask;
771 break;
772 #endif
773 #ifdef CONFIG_ARCH_OMAP15XX
774 case METHOD_GPIO_1510:
775 reg += OMAP1510_GPIO_INT_MASK;
776 l = __raw_readl(reg);
777 if (enable)
778 l &= ~(gpio_mask);
779 else
780 l |= gpio_mask;
781 break;
782 #endif
783 #ifdef CONFIG_ARCH_OMAP16XX
784 case METHOD_GPIO_1610:
785 if (enable)
786 reg += OMAP1610_GPIO_SET_IRQENABLE1;
787 else
788 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
789 l = gpio_mask;
790 break;
791 #endif
792 #ifdef CONFIG_ARCH_OMAP730
793 case METHOD_GPIO_730:
794 reg += OMAP730_GPIO_INT_MASK;
795 l = __raw_readl(reg);
796 if (enable)
797 l &= ~(gpio_mask);
798 else
799 l |= gpio_mask;
800 break;
801 #endif
802 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
803 case METHOD_GPIO_24XX:
804 if (enable)
805 reg += OMAP24XX_GPIO_SETIRQENABLE1;
806 else
807 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
808 l = gpio_mask;
809 break;
810 #endif
811 default:
812 WARN_ON(1);
813 return;
814 }
815 __raw_writel(l, reg);
816 }
817
818 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
819 {
820 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
821 }
822
823 /*
824 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
825 * 1510 does not seem to have a wake-up register. If JTAG is connected
826 * to the target, system will wake up always on GPIO events. While
827 * system is running all registered GPIO interrupts need to have wake-up
828 * enabled. When system is suspended, only selected GPIO interrupts need
829 * to have wake-up enabled.
830 */
831 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
832 {
833 unsigned long flags;
834
835 switch (bank->method) {
836 #ifdef CONFIG_ARCH_OMAP16XX
837 case METHOD_MPUIO:
838 case METHOD_GPIO_1610:
839 spin_lock_irqsave(&bank->lock, flags);
840 if (enable) {
841 bank->suspend_wakeup |= (1 << gpio);
842 enable_irq_wake(bank->irq);
843 } else {
844 disable_irq_wake(bank->irq);
845 bank->suspend_wakeup &= ~(1 << gpio);
846 }
847 spin_unlock_irqrestore(&bank->lock, flags);
848 return 0;
849 #endif
850 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
851 case METHOD_GPIO_24XX:
852 if (bank->non_wakeup_gpios & (1 << gpio)) {
853 printk(KERN_ERR "Unable to modify wakeup on "
854 "non-wakeup GPIO%d\n",
855 (bank - gpio_bank) * 32 + gpio);
856 return -EINVAL;
857 }
858 spin_lock_irqsave(&bank->lock, flags);
859 if (enable) {
860 bank->suspend_wakeup |= (1 << gpio);
861 enable_irq_wake(bank->irq);
862 } else {
863 disable_irq_wake(bank->irq);
864 bank->suspend_wakeup &= ~(1 << gpio);
865 }
866 spin_unlock_irqrestore(&bank->lock, flags);
867 return 0;
868 #endif
869 default:
870 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
871 bank->method);
872 return -EINVAL;
873 }
874 }
875
876 static void _reset_gpio(struct gpio_bank *bank, int gpio)
877 {
878 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
879 _set_gpio_irqenable(bank, gpio, 0);
880 _clear_gpio_irqstatus(bank, gpio);
881 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
882 }
883
884 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
885 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
886 {
887 unsigned int gpio = irq - IH_GPIO_BASE;
888 struct gpio_bank *bank;
889 int retval;
890
891 if (check_gpio(gpio) < 0)
892 return -ENODEV;
893 bank = get_irq_chip_data(irq);
894 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
895
896 return retval;
897 }
898
899 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
900 {
901 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
902 unsigned long flags;
903
904 spin_lock_irqsave(&bank->lock, flags);
905
906 /* Set trigger to none. You need to enable the desired trigger with
907 * request_irq() or set_irq_type().
908 */
909 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
910
911 #ifdef CONFIG_ARCH_OMAP15XX
912 if (bank->method == METHOD_GPIO_1510) {
913 void __iomem *reg;
914
915 /* Claim the pin for MPU */
916 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
917 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
918 }
919 #endif
920 spin_unlock_irqrestore(&bank->lock, flags);
921
922 return 0;
923 }
924
925 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
926 {
927 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
928 unsigned long flags;
929
930 spin_lock_irqsave(&bank->lock, flags);
931 #ifdef CONFIG_ARCH_OMAP16XX
932 if (bank->method == METHOD_GPIO_1610) {
933 /* Disable wake-up during idle for dynamic tick */
934 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
935 __raw_writel(1 << offset, reg);
936 }
937 #endif
938 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
939 if (bank->method == METHOD_GPIO_24XX) {
940 /* Disable wake-up during idle for dynamic tick */
941 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
942 __raw_writel(1 << offset, reg);
943 }
944 #endif
945 _reset_gpio(bank, bank->chip.base + offset);
946 spin_unlock_irqrestore(&bank->lock, flags);
947 }
948
949 /*
950 * We need to unmask the GPIO bank interrupt as soon as possible to
951 * avoid missing GPIO interrupts for other lines in the bank.
952 * Then we need to mask-read-clear-unmask the triggered GPIO lines
953 * in the bank to avoid missing nested interrupts for a GPIO line.
954 * If we wait to unmask individual GPIO lines in the bank after the
955 * line's interrupt handler has been run, we may miss some nested
956 * interrupts.
957 */
958 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
959 {
960 void __iomem *isr_reg = NULL;
961 u32 isr;
962 unsigned int gpio_irq;
963 struct gpio_bank *bank;
964 u32 retrigger = 0;
965 int unmasked = 0;
966
967 desc->chip->ack(irq);
968
969 bank = get_irq_data(irq);
970 #ifdef CONFIG_ARCH_OMAP1
971 if (bank->method == METHOD_MPUIO)
972 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
973 #endif
974 #ifdef CONFIG_ARCH_OMAP15XX
975 if (bank->method == METHOD_GPIO_1510)
976 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
977 #endif
978 #if defined(CONFIG_ARCH_OMAP16XX)
979 if (bank->method == METHOD_GPIO_1610)
980 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
981 #endif
982 #ifdef CONFIG_ARCH_OMAP730
983 if (bank->method == METHOD_GPIO_730)
984 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
985 #endif
986 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
987 if (bank->method == METHOD_GPIO_24XX)
988 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
989 #endif
990 while(1) {
991 u32 isr_saved, level_mask = 0;
992 u32 enabled;
993
994 enabled = _get_gpio_irqbank_mask(bank);
995 isr_saved = isr = __raw_readl(isr_reg) & enabled;
996
997 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
998 isr &= 0x0000ffff;
999
1000 if (cpu_class_is_omap2()) {
1001 level_mask = bank->level_mask & enabled;
1002 }
1003
1004 /* clear edge sensitive interrupts before handler(s) are
1005 called so that we don't miss any interrupt occurred while
1006 executing them */
1007 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1008 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1009 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1010
1011 /* if there is only edge sensitive GPIO pin interrupts
1012 configured, we could unmask GPIO bank interrupt immediately */
1013 if (!level_mask && !unmasked) {
1014 unmasked = 1;
1015 desc->chip->unmask(irq);
1016 }
1017
1018 isr |= retrigger;
1019 retrigger = 0;
1020 if (!isr)
1021 break;
1022
1023 gpio_irq = bank->virtual_irq_start;
1024 for (; isr != 0; isr >>= 1, gpio_irq++) {
1025 if (!(isr & 1))
1026 continue;
1027
1028 generic_handle_irq(gpio_irq);
1029 }
1030 }
1031 /* if bank has any level sensitive GPIO pin interrupt
1032 configured, we must unmask the bank interrupt only after
1033 handler(s) are executed in order to avoid spurious bank
1034 interrupt */
1035 if (!unmasked)
1036 desc->chip->unmask(irq);
1037
1038 }
1039
1040 static void gpio_irq_shutdown(unsigned int irq)
1041 {
1042 unsigned int gpio = irq - IH_GPIO_BASE;
1043 struct gpio_bank *bank = get_irq_chip_data(irq);
1044
1045 _reset_gpio(bank, gpio);
1046 }
1047
1048 static void gpio_ack_irq(unsigned int irq)
1049 {
1050 unsigned int gpio = irq - IH_GPIO_BASE;
1051 struct gpio_bank *bank = get_irq_chip_data(irq);
1052
1053 _clear_gpio_irqstatus(bank, gpio);
1054 }
1055
1056 static void gpio_mask_irq(unsigned int irq)
1057 {
1058 unsigned int gpio = irq - IH_GPIO_BASE;
1059 struct gpio_bank *bank = get_irq_chip_data(irq);
1060
1061 _set_gpio_irqenable(bank, gpio, 0);
1062 }
1063
1064 static void gpio_unmask_irq(unsigned int irq)
1065 {
1066 unsigned int gpio = irq - IH_GPIO_BASE;
1067 struct gpio_bank *bank = get_irq_chip_data(irq);
1068 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1069
1070 /* For level-triggered GPIOs, the clearing must be done after
1071 * the HW source is cleared, thus after the handler has run */
1072 if (bank->level_mask & irq_mask) {
1073 _set_gpio_irqenable(bank, gpio, 0);
1074 _clear_gpio_irqstatus(bank, gpio);
1075 }
1076
1077 _set_gpio_irqenable(bank, gpio, 1);
1078 }
1079
1080 static struct irq_chip gpio_irq_chip = {
1081 .name = "GPIO",
1082 .shutdown = gpio_irq_shutdown,
1083 .ack = gpio_ack_irq,
1084 .mask = gpio_mask_irq,
1085 .unmask = gpio_unmask_irq,
1086 .set_type = gpio_irq_type,
1087 .set_wake = gpio_wake_enable,
1088 };
1089
1090 /*---------------------------------------------------------------------*/
1091
1092 #ifdef CONFIG_ARCH_OMAP1
1093
1094 /* MPUIO uses the always-on 32k clock */
1095
1096 static void mpuio_ack_irq(unsigned int irq)
1097 {
1098 /* The ISR is reset automatically, so do nothing here. */
1099 }
1100
1101 static void mpuio_mask_irq(unsigned int irq)
1102 {
1103 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1104 struct gpio_bank *bank = get_irq_chip_data(irq);
1105
1106 _set_gpio_irqenable(bank, gpio, 0);
1107 }
1108
1109 static void mpuio_unmask_irq(unsigned int irq)
1110 {
1111 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1112 struct gpio_bank *bank = get_irq_chip_data(irq);
1113
1114 _set_gpio_irqenable(bank, gpio, 1);
1115 }
1116
1117 static struct irq_chip mpuio_irq_chip = {
1118 .name = "MPUIO",
1119 .ack = mpuio_ack_irq,
1120 .mask = mpuio_mask_irq,
1121 .unmask = mpuio_unmask_irq,
1122 .set_type = gpio_irq_type,
1123 #ifdef CONFIG_ARCH_OMAP16XX
1124 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1125 .set_wake = gpio_wake_enable,
1126 #endif
1127 };
1128
1129
1130 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1131
1132
1133 #ifdef CONFIG_ARCH_OMAP16XX
1134
1135 #include <linux/platform_device.h>
1136
1137 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1138 {
1139 struct gpio_bank *bank = platform_get_drvdata(pdev);
1140 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1141 unsigned long flags;
1142
1143 spin_lock_irqsave(&bank->lock, flags);
1144 bank->saved_wakeup = __raw_readl(mask_reg);
1145 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1146 spin_unlock_irqrestore(&bank->lock, flags);
1147
1148 return 0;
1149 }
1150
1151 static int omap_mpuio_resume_early(struct platform_device *pdev)
1152 {
1153 struct gpio_bank *bank = platform_get_drvdata(pdev);
1154 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1155 unsigned long flags;
1156
1157 spin_lock_irqsave(&bank->lock, flags);
1158 __raw_writel(bank->saved_wakeup, mask_reg);
1159 spin_unlock_irqrestore(&bank->lock, flags);
1160
1161 return 0;
1162 }
1163
1164 /* use platform_driver for this, now that there's no longer any
1165 * point to sys_device (other than not disturbing old code).
1166 */
1167 static struct platform_driver omap_mpuio_driver = {
1168 .suspend_late = omap_mpuio_suspend_late,
1169 .resume_early = omap_mpuio_resume_early,
1170 .driver = {
1171 .name = "mpuio",
1172 },
1173 };
1174
1175 static struct platform_device omap_mpuio_device = {
1176 .name = "mpuio",
1177 .id = -1,
1178 .dev = {
1179 .driver = &omap_mpuio_driver.driver,
1180 }
1181 /* could list the /proc/iomem resources */
1182 };
1183
1184 static inline void mpuio_init(void)
1185 {
1186 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1187
1188 if (platform_driver_register(&omap_mpuio_driver) == 0)
1189 (void) platform_device_register(&omap_mpuio_device);
1190 }
1191
1192 #else
1193 static inline void mpuio_init(void) {}
1194 #endif /* 16xx */
1195
1196 #else
1197
1198 extern struct irq_chip mpuio_irq_chip;
1199
1200 #define bank_is_mpuio(bank) 0
1201 static inline void mpuio_init(void) {}
1202
1203 #endif
1204
1205 /*---------------------------------------------------------------------*/
1206
1207 /* REVISIT these are stupid implementations! replace by ones that
1208 * don't switch on METHOD_* and which mostly avoid spinlocks
1209 */
1210
1211 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1212 {
1213 struct gpio_bank *bank;
1214 unsigned long flags;
1215
1216 bank = container_of(chip, struct gpio_bank, chip);
1217 spin_lock_irqsave(&bank->lock, flags);
1218 _set_gpio_direction(bank, offset, 1);
1219 spin_unlock_irqrestore(&bank->lock, flags);
1220 return 0;
1221 }
1222
1223 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1224 {
1225 return __omap_get_gpio_datain(chip->base + offset);
1226 }
1227
1228 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1229 {
1230 struct gpio_bank *bank;
1231 unsigned long flags;
1232
1233 bank = container_of(chip, struct gpio_bank, chip);
1234 spin_lock_irqsave(&bank->lock, flags);
1235 _set_gpio_dataout(bank, offset, value);
1236 _set_gpio_direction(bank, offset, 0);
1237 spin_unlock_irqrestore(&bank->lock, flags);
1238 return 0;
1239 }
1240
1241 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1242 {
1243 struct gpio_bank *bank;
1244 unsigned long flags;
1245
1246 bank = container_of(chip, struct gpio_bank, chip);
1247 spin_lock_irqsave(&bank->lock, flags);
1248 _set_gpio_dataout(bank, offset, value);
1249 spin_unlock_irqrestore(&bank->lock, flags);
1250 }
1251
1252 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1253 {
1254 struct gpio_bank *bank;
1255
1256 bank = container_of(chip, struct gpio_bank, chip);
1257 return bank->virtual_irq_start + offset;
1258 }
1259
1260 /*---------------------------------------------------------------------*/
1261
1262 static int initialized;
1263 #if !defined(CONFIG_ARCH_OMAP3)
1264 static struct clk * gpio_ick;
1265 #endif
1266
1267 #if defined(CONFIG_ARCH_OMAP2)
1268 static struct clk * gpio_fck;
1269 #endif
1270
1271 #if defined(CONFIG_ARCH_OMAP2430)
1272 static struct clk * gpio5_ick;
1273 static struct clk * gpio5_fck;
1274 #endif
1275
1276 #if defined(CONFIG_ARCH_OMAP3)
1277 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1278 #endif
1279
1280 /* This lock class tells lockdep that GPIO irqs are in a different
1281 * category than their parents, so it won't report false recursion.
1282 */
1283 static struct lock_class_key gpio_lock_class;
1284
1285 static int __init _omap_gpio_init(void)
1286 {
1287 int i;
1288 int gpio = 0;
1289 struct gpio_bank *bank;
1290 char clk_name[11];
1291
1292 initialized = 1;
1293
1294 #if defined(CONFIG_ARCH_OMAP1)
1295 if (cpu_is_omap15xx()) {
1296 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1297 if (IS_ERR(gpio_ick))
1298 printk("Could not get arm_gpio_ck\n");
1299 else
1300 clk_enable(gpio_ick);
1301 }
1302 #endif
1303 #if defined(CONFIG_ARCH_OMAP2)
1304 if (cpu_class_is_omap2()) {
1305 gpio_ick = clk_get(NULL, "gpios_ick");
1306 if (IS_ERR(gpio_ick))
1307 printk("Could not get gpios_ick\n");
1308 else
1309 clk_enable(gpio_ick);
1310 gpio_fck = clk_get(NULL, "gpios_fck");
1311 if (IS_ERR(gpio_fck))
1312 printk("Could not get gpios_fck\n");
1313 else
1314 clk_enable(gpio_fck);
1315
1316 /*
1317 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1318 */
1319 #if defined(CONFIG_ARCH_OMAP2430)
1320 if (cpu_is_omap2430()) {
1321 gpio5_ick = clk_get(NULL, "gpio5_ick");
1322 if (IS_ERR(gpio5_ick))
1323 printk("Could not get gpio5_ick\n");
1324 else
1325 clk_enable(gpio5_ick);
1326 gpio5_fck = clk_get(NULL, "gpio5_fck");
1327 if (IS_ERR(gpio5_fck))
1328 printk("Could not get gpio5_fck\n");
1329 else
1330 clk_enable(gpio5_fck);
1331 }
1332 #endif
1333 }
1334 #endif
1335
1336 #if defined(CONFIG_ARCH_OMAP3)
1337 if (cpu_is_omap34xx()) {
1338 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1339 sprintf(clk_name, "gpio%d_ick", i + 1);
1340 gpio_iclks[i] = clk_get(NULL, clk_name);
1341 if (IS_ERR(gpio_iclks[i]))
1342 printk(KERN_ERR "Could not get %s\n", clk_name);
1343 else
1344 clk_enable(gpio_iclks[i]);
1345 }
1346 }
1347 #endif
1348
1349
1350 #ifdef CONFIG_ARCH_OMAP15XX
1351 if (cpu_is_omap15xx()) {
1352 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1353 gpio_bank_count = 2;
1354 gpio_bank = gpio_bank_1510;
1355 }
1356 #endif
1357 #if defined(CONFIG_ARCH_OMAP16XX)
1358 if (cpu_is_omap16xx()) {
1359 u32 rev;
1360
1361 gpio_bank_count = 5;
1362 gpio_bank = gpio_bank_1610;
1363 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1364 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1365 (rev >> 4) & 0x0f, rev & 0x0f);
1366 }
1367 #endif
1368 #ifdef CONFIG_ARCH_OMAP730
1369 if (cpu_is_omap730()) {
1370 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1371 gpio_bank_count = 7;
1372 gpio_bank = gpio_bank_730;
1373 }
1374 #endif
1375
1376 #ifdef CONFIG_ARCH_OMAP24XX
1377 if (cpu_is_omap242x()) {
1378 int rev;
1379
1380 gpio_bank_count = 4;
1381 gpio_bank = gpio_bank_242x;
1382 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1383 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1384 (rev >> 4) & 0x0f, rev & 0x0f);
1385 }
1386 if (cpu_is_omap243x()) {
1387 int rev;
1388
1389 gpio_bank_count = 5;
1390 gpio_bank = gpio_bank_243x;
1391 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1392 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1393 (rev >> 4) & 0x0f, rev & 0x0f);
1394 }
1395 #endif
1396 #ifdef CONFIG_ARCH_OMAP34XX
1397 if (cpu_is_omap34xx()) {
1398 int rev;
1399
1400 gpio_bank_count = OMAP34XX_NR_GPIOS;
1401 gpio_bank = gpio_bank_34xx;
1402 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1403 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1404 (rev >> 4) & 0x0f, rev & 0x0f);
1405 }
1406 #endif
1407 for (i = 0; i < gpio_bank_count; i++) {
1408 int j, gpio_count = 16;
1409
1410 bank = &gpio_bank[i];
1411 spin_lock_init(&bank->lock);
1412 if (bank_is_mpuio(bank))
1413 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1414 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1415 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1416 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1417 }
1418 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1419 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1420 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1421 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1422 }
1423 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1424 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1425 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1426
1427 gpio_count = 32; /* 730 has 32-bit GPIOs */
1428 }
1429
1430 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1431 if (bank->method == METHOD_GPIO_24XX) {
1432 static const u32 non_wakeup_gpios[] = {
1433 0xe203ffc0, 0x08700040
1434 };
1435
1436 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1437 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1438 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1439
1440 /* Initialize interface clock ungated, module enabled */
1441 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1442 if (i < ARRAY_SIZE(non_wakeup_gpios))
1443 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1444 gpio_count = 32;
1445 }
1446 #endif
1447
1448 /* REVISIT eventually switch from OMAP-specific gpio structs
1449 * over to the generic ones
1450 */
1451 bank->chip.request = omap_gpio_request;
1452 bank->chip.free = omap_gpio_free;
1453 bank->chip.direction_input = gpio_input;
1454 bank->chip.get = gpio_get;
1455 bank->chip.direction_output = gpio_output;
1456 bank->chip.set = gpio_set;
1457 bank->chip.to_irq = gpio_2irq;
1458 if (bank_is_mpuio(bank)) {
1459 bank->chip.label = "mpuio";
1460 #ifdef CONFIG_ARCH_OMAP16XX
1461 bank->chip.dev = &omap_mpuio_device.dev;
1462 #endif
1463 bank->chip.base = OMAP_MPUIO(0);
1464 } else {
1465 bank->chip.label = "gpio";
1466 bank->chip.base = gpio;
1467 gpio += gpio_count;
1468 }
1469 bank->chip.ngpio = gpio_count;
1470
1471 gpiochip_add(&bank->chip);
1472
1473 for (j = bank->virtual_irq_start;
1474 j < bank->virtual_irq_start + gpio_count; j++) {
1475 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1476 set_irq_chip_data(j, bank);
1477 if (bank_is_mpuio(bank))
1478 set_irq_chip(j, &mpuio_irq_chip);
1479 else
1480 set_irq_chip(j, &gpio_irq_chip);
1481 set_irq_handler(j, handle_simple_irq);
1482 set_irq_flags(j, IRQF_VALID);
1483 }
1484 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1485 set_irq_data(bank->irq, bank);
1486
1487 if (cpu_is_omap34xx()) {
1488 sprintf(clk_name, "gpio%d_dbck", i + 1);
1489 bank->dbck = clk_get(NULL, clk_name);
1490 if (IS_ERR(bank->dbck))
1491 printk(KERN_ERR "Could not get %s\n", clk_name);
1492 }
1493 }
1494
1495 /* Enable system clock for GPIO module.
1496 * The CAM_CLK_CTRL *is* really the right place. */
1497 if (cpu_is_omap16xx())
1498 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1499
1500 /* Enable autoidle for the OCP interface */
1501 if (cpu_is_omap24xx())
1502 omap_writel(1 << 0, 0x48019010);
1503 if (cpu_is_omap34xx())
1504 omap_writel(1 << 0, 0x48306814);
1505
1506 return 0;
1507 }
1508
1509 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1510 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1511 {
1512 int i;
1513
1514 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1515 return 0;
1516
1517 for (i = 0; i < gpio_bank_count; i++) {
1518 struct gpio_bank *bank = &gpio_bank[i];
1519 void __iomem *wake_status;
1520 void __iomem *wake_clear;
1521 void __iomem *wake_set;
1522 unsigned long flags;
1523
1524 switch (bank->method) {
1525 #ifdef CONFIG_ARCH_OMAP16XX
1526 case METHOD_GPIO_1610:
1527 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1528 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1529 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1530 break;
1531 #endif
1532 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1533 case METHOD_GPIO_24XX:
1534 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1535 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1536 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1537 break;
1538 #endif
1539 default:
1540 continue;
1541 }
1542
1543 spin_lock_irqsave(&bank->lock, flags);
1544 bank->saved_wakeup = __raw_readl(wake_status);
1545 __raw_writel(0xffffffff, wake_clear);
1546 __raw_writel(bank->suspend_wakeup, wake_set);
1547 spin_unlock_irqrestore(&bank->lock, flags);
1548 }
1549
1550 return 0;
1551 }
1552
1553 static int omap_gpio_resume(struct sys_device *dev)
1554 {
1555 int i;
1556
1557 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1558 return 0;
1559
1560 for (i = 0; i < gpio_bank_count; i++) {
1561 struct gpio_bank *bank = &gpio_bank[i];
1562 void __iomem *wake_clear;
1563 void __iomem *wake_set;
1564 unsigned long flags;
1565
1566 switch (bank->method) {
1567 #ifdef CONFIG_ARCH_OMAP16XX
1568 case METHOD_GPIO_1610:
1569 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1570 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1571 break;
1572 #endif
1573 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1574 case METHOD_GPIO_24XX:
1575 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1576 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1577 break;
1578 #endif
1579 default:
1580 continue;
1581 }
1582
1583 spin_lock_irqsave(&bank->lock, flags);
1584 __raw_writel(0xffffffff, wake_clear);
1585 __raw_writel(bank->saved_wakeup, wake_set);
1586 spin_unlock_irqrestore(&bank->lock, flags);
1587 }
1588
1589 return 0;
1590 }
1591
1592 static struct sysdev_class omap_gpio_sysclass = {
1593 .name = "gpio",
1594 .suspend = omap_gpio_suspend,
1595 .resume = omap_gpio_resume,
1596 };
1597
1598 static struct sys_device omap_gpio_device = {
1599 .id = 0,
1600 .cls = &omap_gpio_sysclass,
1601 };
1602
1603 #endif
1604
1605 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1606
1607 static int workaround_enabled;
1608
1609 void omap2_gpio_prepare_for_retention(void)
1610 {
1611 int i, c = 0;
1612
1613 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1614 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1615 for (i = 0; i < gpio_bank_count; i++) {
1616 struct gpio_bank *bank = &gpio_bank[i];
1617 u32 l1, l2;
1618
1619 if (!(bank->enabled_non_wakeup_gpios))
1620 continue;
1621 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1622 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1623 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1624 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1625 #endif
1626 bank->saved_fallingdetect = l1;
1627 bank->saved_risingdetect = l2;
1628 l1 &= ~bank->enabled_non_wakeup_gpios;
1629 l2 &= ~bank->enabled_non_wakeup_gpios;
1630 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1631 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1632 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1633 #endif
1634 c++;
1635 }
1636 if (!c) {
1637 workaround_enabled = 0;
1638 return;
1639 }
1640 workaround_enabled = 1;
1641 }
1642
1643 void omap2_gpio_resume_after_retention(void)
1644 {
1645 int i;
1646
1647 if (!workaround_enabled)
1648 return;
1649 for (i = 0; i < gpio_bank_count; i++) {
1650 struct gpio_bank *bank = &gpio_bank[i];
1651 u32 l;
1652
1653 if (!(bank->enabled_non_wakeup_gpios))
1654 continue;
1655 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1656 __raw_writel(bank->saved_fallingdetect,
1657 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1658 __raw_writel(bank->saved_risingdetect,
1659 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1660 #endif
1661 /* Check if any of the non-wakeup interrupt GPIOs have changed
1662 * state. If so, generate an IRQ by software. This is
1663 * horribly racy, but it's the best we can do to work around
1664 * this silicon bug. */
1665 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1666 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1667 #endif
1668 l ^= bank->saved_datain;
1669 l &= bank->non_wakeup_gpios;
1670 if (l) {
1671 u32 old0, old1;
1672 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1673 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1674 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1675 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1676 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1677 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1678 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1679 #endif
1680 }
1681 }
1682
1683 }
1684
1685 #endif
1686
1687 /*
1688 * This may get called early from board specific init
1689 * for boards that have interrupts routed via FPGA.
1690 */
1691 int __init omap_gpio_init(void)
1692 {
1693 if (!initialized)
1694 return _omap_gpio_init();
1695 else
1696 return 0;
1697 }
1698
1699 static int __init omap_gpio_sysinit(void)
1700 {
1701 int ret = 0;
1702
1703 if (!initialized)
1704 ret = _omap_gpio_init();
1705
1706 mpuio_init();
1707
1708 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1709 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1710 if (ret == 0) {
1711 ret = sysdev_class_register(&omap_gpio_sysclass);
1712 if (ret == 0)
1713 ret = sysdev_register(&omap_gpio_device);
1714 }
1715 }
1716 #endif
1717
1718 return ret;
1719 }
1720
1721 arch_initcall(omap_gpio_sysinit);
1722
1723
1724 #ifdef CONFIG_DEBUG_FS
1725
1726 #include <linux/debugfs.h>
1727 #include <linux/seq_file.h>
1728
1729 static int gpio_is_input(struct gpio_bank *bank, int mask)
1730 {
1731 void __iomem *reg = bank->base;
1732
1733 switch (bank->method) {
1734 case METHOD_MPUIO:
1735 reg += OMAP_MPUIO_IO_CNTL;
1736 break;
1737 case METHOD_GPIO_1510:
1738 reg += OMAP1510_GPIO_DIR_CONTROL;
1739 break;
1740 case METHOD_GPIO_1610:
1741 reg += OMAP1610_GPIO_DIRECTION;
1742 break;
1743 case METHOD_GPIO_730:
1744 reg += OMAP730_GPIO_DIR_CONTROL;
1745 break;
1746 case METHOD_GPIO_24XX:
1747 reg += OMAP24XX_GPIO_OE;
1748 break;
1749 }
1750 return __raw_readl(reg) & mask;
1751 }
1752
1753
1754 static int dbg_gpio_show(struct seq_file *s, void *unused)
1755 {
1756 unsigned i, j, gpio;
1757
1758 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1759 struct gpio_bank *bank = gpio_bank + i;
1760 unsigned bankwidth = 16;
1761 u32 mask = 1;
1762
1763 if (bank_is_mpuio(bank))
1764 gpio = OMAP_MPUIO(0);
1765 else if (cpu_class_is_omap2() || cpu_is_omap730())
1766 bankwidth = 32;
1767
1768 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1769 unsigned irq, value, is_in, irqstat;
1770 const char *label;
1771
1772 label = gpiochip_is_requested(&bank->chip, j);
1773 if (!label)
1774 continue;
1775
1776 irq = bank->virtual_irq_start + j;
1777 value = gpio_get_value(gpio);
1778 is_in = gpio_is_input(bank, mask);
1779
1780 if (bank_is_mpuio(bank))
1781 seq_printf(s, "MPUIO %2d ", j);
1782 else
1783 seq_printf(s, "GPIO %3d ", gpio);
1784 seq_printf(s, "(%-20.20s): %s %s",
1785 label,
1786 is_in ? "in " : "out",
1787 value ? "hi" : "lo");
1788
1789 /* FIXME for at least omap2, show pullup/pulldown state */
1790
1791 irqstat = irq_desc[irq].status;
1792 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1793 defined(CONFIG_ARCH_OMAP34XX)
1794 if (is_in && ((bank->suspend_wakeup & mask)
1795 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1796 char *trigger = NULL;
1797
1798 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1799 case IRQ_TYPE_EDGE_FALLING:
1800 trigger = "falling";
1801 break;
1802 case IRQ_TYPE_EDGE_RISING:
1803 trigger = "rising";
1804 break;
1805 case IRQ_TYPE_EDGE_BOTH:
1806 trigger = "bothedge";
1807 break;
1808 case IRQ_TYPE_LEVEL_LOW:
1809 trigger = "low";
1810 break;
1811 case IRQ_TYPE_LEVEL_HIGH:
1812 trigger = "high";
1813 break;
1814 case IRQ_TYPE_NONE:
1815 trigger = "(?)";
1816 break;
1817 }
1818 seq_printf(s, ", irq-%d %-8s%s",
1819 irq, trigger,
1820 (bank->suspend_wakeup & mask)
1821 ? " wakeup" : "");
1822 }
1823 #endif
1824 seq_printf(s, "\n");
1825 }
1826
1827 if (bank_is_mpuio(bank)) {
1828 seq_printf(s, "\n");
1829 gpio = 0;
1830 }
1831 }
1832 return 0;
1833 }
1834
1835 static int dbg_gpio_open(struct inode *inode, struct file *file)
1836 {
1837 return single_open(file, dbg_gpio_show, &inode->i_private);
1838 }
1839
1840 static const struct file_operations debug_fops = {
1841 .open = dbg_gpio_open,
1842 .read = seq_read,
1843 .llseek = seq_lseek,
1844 .release = single_release,
1845 };
1846
1847 static int __init omap_gpio_debuginit(void)
1848 {
1849 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1850 NULL, NULL, &debug_fops);
1851 return 0;
1852 }
1853 late_initcall(omap_gpio_debuginit);
1854 #endif
Support for the Chinese Samsung S3C2440 based development boards