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[PATCH] EDAC: amd76x pci_dev_get/pci_dev_put fixes
[linux-2.6/mini2440.git] / arch / powerpc / kernel / cputable.c
blob39e348a3ade2451cdeb01663b81eaec332c80850
1 /*
2 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
3 *
4 * Modifications for ppc64:
5 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13 #include <linux/config.h>
14 #include <linux/string.h>
15 #include <linux/sched.h>
16 #include <linux/threads.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19
20 #include <asm/oprofile_impl.h>
21 #include <asm/cputable.h>
22
23 struct cpu_spec* cur_cpu_spec = NULL;
24 EXPORT_SYMBOL(cur_cpu_spec);
25
26 /* NOTE:
27 * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
28 * the responsibility of the appropriate CPU save/restore functions to
29 * eventually copy these settings over. Those save/restore aren't yet
30 * part of the cputable though. That has to be fixed for both ppc32
31 * and ppc64
32 */
33 #ifdef CONFIG_PPC64
34 extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
35 extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
36 extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
37 #else
38 extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
39 extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
40 extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
41 extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
42 extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
43 extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
44 extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
45 extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
46 #endif /* CONFIG_PPC32 */
47 extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
48
49 /* This table only contains "desktop" CPUs, it need to be filled with embedded
50 * ones as well...
51 */
52 #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
53 PPC_FEATURE_HAS_MMU)
54 #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
55 #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
56 #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
57 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
58 #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
59 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
60 #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
61 PPC_FEATURE_BOOKE)
62
63 /* We only set the spe features if the kernel was compiled with
64 * spe support
65 */
66 #ifdef CONFIG_SPE
67 #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
68 #else
69 #define PPC_FEATURE_SPE_COMP 0
70 #endif
71
72 struct cpu_spec cpu_specs[] = {
73 #ifdef CONFIG_PPC64
74 { /* Power3 */
75 .pvr_mask = 0xffff0000,
76 .pvr_value = 0x00400000,
77 .cpu_name = "POWER3 (630)",
78 .cpu_features = CPU_FTRS_POWER3,
79 .cpu_user_features = COMMON_USER_PPC64,
80 .icache_bsize = 128,
81 .dcache_bsize = 128,
82 .num_pmcs = 8,
83 .cpu_setup = __setup_cpu_power3,
84 .oprofile_cpu_type = "ppc64/power3",
85 .oprofile_type = PPC_OPROFILE_RS64,
86 .platform = "power3",
87 },
88 { /* Power3+ */
89 .pvr_mask = 0xffff0000,
90 .pvr_value = 0x00410000,
91 .cpu_name = "POWER3 (630+)",
92 .cpu_features = CPU_FTRS_POWER3,
93 .cpu_user_features = COMMON_USER_PPC64,
94 .icache_bsize = 128,
95 .dcache_bsize = 128,
96 .num_pmcs = 8,
97 .cpu_setup = __setup_cpu_power3,
98 .oprofile_cpu_type = "ppc64/power3",
99 .oprofile_type = PPC_OPROFILE_RS64,
100 .platform = "power3",
101 },
102 { /* Northstar */
103 .pvr_mask = 0xffff0000,
104 .pvr_value = 0x00330000,
105 .cpu_name = "RS64-II (northstar)",
106 .cpu_features = CPU_FTRS_RS64,
107 .cpu_user_features = COMMON_USER_PPC64,
108 .icache_bsize = 128,
109 .dcache_bsize = 128,
110 .num_pmcs = 8,
111 .cpu_setup = __setup_cpu_power3,
112 .oprofile_cpu_type = "ppc64/rs64",
113 .oprofile_type = PPC_OPROFILE_RS64,
114 .platform = "rs64",
115 },
116 { /* Pulsar */
117 .pvr_mask = 0xffff0000,
118 .pvr_value = 0x00340000,
119 .cpu_name = "RS64-III (pulsar)",
120 .cpu_features = CPU_FTRS_RS64,
121 .cpu_user_features = COMMON_USER_PPC64,
122 .icache_bsize = 128,
123 .dcache_bsize = 128,
124 .num_pmcs = 8,
125 .cpu_setup = __setup_cpu_power3,
126 .oprofile_cpu_type = "ppc64/rs64",
127 .oprofile_type = PPC_OPROFILE_RS64,
128 .platform = "rs64",
129 },
130 { /* I-star */
131 .pvr_mask = 0xffff0000,
132 .pvr_value = 0x00360000,
133 .cpu_name = "RS64-III (icestar)",
134 .cpu_features = CPU_FTRS_RS64,
135 .cpu_user_features = COMMON_USER_PPC64,
136 .icache_bsize = 128,
137 .dcache_bsize = 128,
138 .num_pmcs = 8,
139 .cpu_setup = __setup_cpu_power3,
140 .oprofile_cpu_type = "ppc64/rs64",
141 .oprofile_type = PPC_OPROFILE_RS64,
142 .platform = "rs64",
143 },
144 { /* S-star */
145 .pvr_mask = 0xffff0000,
146 .pvr_value = 0x00370000,
147 .cpu_name = "RS64-IV (sstar)",
148 .cpu_features = CPU_FTRS_RS64,
149 .cpu_user_features = COMMON_USER_PPC64,
150 .icache_bsize = 128,
151 .dcache_bsize = 128,
152 .num_pmcs = 8,
153 .cpu_setup = __setup_cpu_power3,
154 .oprofile_cpu_type = "ppc64/rs64",
155 .oprofile_type = PPC_OPROFILE_RS64,
156 .platform = "rs64",
157 },
158 { /* Power4 */
159 .pvr_mask = 0xffff0000,
160 .pvr_value = 0x00350000,
161 .cpu_name = "POWER4 (gp)",
162 .cpu_features = CPU_FTRS_POWER4,
163 .cpu_user_features = COMMON_USER_POWER4,
164 .icache_bsize = 128,
165 .dcache_bsize = 128,
166 .num_pmcs = 8,
167 .cpu_setup = __setup_cpu_power4,
168 .oprofile_cpu_type = "ppc64/power4",
169 .oprofile_type = PPC_OPROFILE_POWER4,
170 .platform = "power4",
171 },
172 { /* Power4+ */
173 .pvr_mask = 0xffff0000,
174 .pvr_value = 0x00380000,
175 .cpu_name = "POWER4+ (gq)",
176 .cpu_features = CPU_FTRS_POWER4,
177 .cpu_user_features = COMMON_USER_POWER4,
178 .icache_bsize = 128,
179 .dcache_bsize = 128,
180 .num_pmcs = 8,
181 .cpu_setup = __setup_cpu_power4,
182 .oprofile_cpu_type = "ppc64/power4",
183 .oprofile_type = PPC_OPROFILE_POWER4,
184 .platform = "power4",
185 },
186 { /* PPC970 */
187 .pvr_mask = 0xffff0000,
188 .pvr_value = 0x00390000,
189 .cpu_name = "PPC970",
190 .cpu_features = CPU_FTRS_PPC970,
191 .cpu_user_features = COMMON_USER_POWER4 |
192 PPC_FEATURE_HAS_ALTIVEC_COMP,
193 .icache_bsize = 128,
194 .dcache_bsize = 128,
195 .num_pmcs = 8,
196 .cpu_setup = __setup_cpu_ppc970,
197 .oprofile_cpu_type = "ppc64/970",
198 .oprofile_type = PPC_OPROFILE_POWER4,
199 .platform = "ppc970",
200 },
201 #endif /* CONFIG_PPC64 */
202 #if defined(CONFIG_PPC64) || defined(CONFIG_POWER4)
203 { /* PPC970FX */
204 .pvr_mask = 0xffff0000,
205 .pvr_value = 0x003c0000,
206 .cpu_name = "PPC970FX",
207 #ifdef CONFIG_PPC32
208 .cpu_features = CPU_FTRS_970_32,
209 #else
210 .cpu_features = CPU_FTRS_PPC970,
211 #endif
212 .cpu_user_features = COMMON_USER_POWER4 |
213 PPC_FEATURE_HAS_ALTIVEC_COMP,
214 .icache_bsize = 128,
215 .dcache_bsize = 128,
216 .num_pmcs = 8,
217 .cpu_setup = __setup_cpu_ppc970,
218 .oprofile_cpu_type = "ppc64/970",
219 .oprofile_type = PPC_OPROFILE_POWER4,
220 .platform = "ppc970",
221 },
222 #endif /* defined(CONFIG_PPC64) || defined(CONFIG_POWER4) */
223 #ifdef CONFIG_PPC64
224 { /* PPC970MP */
225 .pvr_mask = 0xffff0000,
226 .pvr_value = 0x00440000,
227 .cpu_name = "PPC970MP",
228 .cpu_features = CPU_FTRS_PPC970,
229 .cpu_user_features = COMMON_USER_POWER4 |
230 PPC_FEATURE_HAS_ALTIVEC_COMP,
231 .icache_bsize = 128,
232 .dcache_bsize = 128,
233 .cpu_setup = __setup_cpu_ppc970,
234 .oprofile_cpu_type = "ppc64/970",
235 .oprofile_type = PPC_OPROFILE_POWER4,
236 .platform = "ppc970",
237 },
238 { /* Power5 GR */
239 .pvr_mask = 0xffff0000,
240 .pvr_value = 0x003a0000,
241 .cpu_name = "POWER5 (gr)",
242 .cpu_features = CPU_FTRS_POWER5,
243 .cpu_user_features = COMMON_USER_POWER5,
244 .icache_bsize = 128,
245 .dcache_bsize = 128,
246 .num_pmcs = 6,
247 .cpu_setup = __setup_cpu_power4,
248 .oprofile_cpu_type = "ppc64/power5",
249 .oprofile_type = PPC_OPROFILE_POWER4,
250 .platform = "power5",
251 },
252 { /* Power5 GS */
253 .pvr_mask = 0xffff0000,
254 .pvr_value = 0x003b0000,
255 .cpu_name = "POWER5+ (gs)",
256 .cpu_features = CPU_FTRS_POWER5,
257 .cpu_user_features = COMMON_USER_POWER5_PLUS,
258 .icache_bsize = 128,
259 .dcache_bsize = 128,
260 .num_pmcs = 6,
261 .cpu_setup = __setup_cpu_power4,
262 .oprofile_cpu_type = "ppc64/power5+",
263 .oprofile_type = PPC_OPROFILE_POWER4,
264 .platform = "power5+",
265 },
266 { /* Cell Broadband Engine */
267 .pvr_mask = 0xffff0000,
268 .pvr_value = 0x00700000,
269 .cpu_name = "Cell Broadband Engine",
270 .cpu_features = CPU_FTRS_CELL,
271 .cpu_user_features = COMMON_USER_PPC64 |
272 PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
273 PPC_FEATURE_SMT,
274 .icache_bsize = 128,
275 .dcache_bsize = 128,
276 .cpu_setup = __setup_cpu_be,
277 .platform = "ppc-cell-be",
278 },
279 { /* default match */
280 .pvr_mask = 0x00000000,
281 .pvr_value = 0x00000000,
282 .cpu_name = "POWER4 (compatible)",
283 .cpu_features = CPU_FTRS_COMPATIBLE,
284 .cpu_user_features = COMMON_USER_PPC64,
285 .icache_bsize = 128,
286 .dcache_bsize = 128,
287 .num_pmcs = 6,
288 .cpu_setup = __setup_cpu_power4,
289 .platform = "power4",
290 }
291 #endif /* CONFIG_PPC64 */
292 #ifdef CONFIG_PPC32
293 #if CLASSIC_PPC
294 { /* 601 */
295 .pvr_mask = 0xffff0000,
296 .pvr_value = 0x00010000,
297 .cpu_name = "601",
298 .cpu_features = CPU_FTRS_PPC601,
299 .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
300 PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
301 .icache_bsize = 32,
302 .dcache_bsize = 32,
303 .platform = "ppc601",
304 },
305 { /* 603 */
306 .pvr_mask = 0xffff0000,
307 .pvr_value = 0x00030000,
308 .cpu_name = "603",
309 .cpu_features = CPU_FTRS_603,
310 .cpu_user_features = COMMON_USER,
311 .icache_bsize = 32,
312 .dcache_bsize = 32,
313 .cpu_setup = __setup_cpu_603,
314 .platform = "ppc603",
315 },
316 { /* 603e */
317 .pvr_mask = 0xffff0000,
318 .pvr_value = 0x00060000,
319 .cpu_name = "603e",
320 .cpu_features = CPU_FTRS_603,
321 .cpu_user_features = COMMON_USER,
322 .icache_bsize = 32,
323 .dcache_bsize = 32,
324 .cpu_setup = __setup_cpu_603,
325 .platform = "ppc603",
326 },
327 { /* 603ev */
328 .pvr_mask = 0xffff0000,
329 .pvr_value = 0x00070000,
330 .cpu_name = "603ev",
331 .cpu_features = CPU_FTRS_603,
332 .cpu_user_features = COMMON_USER,
333 .icache_bsize = 32,
334 .dcache_bsize = 32,
335 .cpu_setup = __setup_cpu_603,
336 .platform = "ppc603",
337 },
338 { /* 604 */
339 .pvr_mask = 0xffff0000,
340 .pvr_value = 0x00040000,
341 .cpu_name = "604",
342 .cpu_features = CPU_FTRS_604,
343 .cpu_user_features = COMMON_USER,
344 .icache_bsize = 32,
345 .dcache_bsize = 32,
346 .num_pmcs = 2,
347 .cpu_setup = __setup_cpu_604,
348 .platform = "ppc604",
349 },
350 { /* 604e */
351 .pvr_mask = 0xfffff000,
352 .pvr_value = 0x00090000,
353 .cpu_name = "604e",
354 .cpu_features = CPU_FTRS_604,
355 .cpu_user_features = COMMON_USER,
356 .icache_bsize = 32,
357 .dcache_bsize = 32,
358 .num_pmcs = 4,
359 .cpu_setup = __setup_cpu_604,
360 .platform = "ppc604",
361 },
362 { /* 604r */
363 .pvr_mask = 0xffff0000,
364 .pvr_value = 0x00090000,
365 .cpu_name = "604r",
366 .cpu_features = CPU_FTRS_604,
367 .cpu_user_features = COMMON_USER,
368 .icache_bsize = 32,
369 .dcache_bsize = 32,
370 .num_pmcs = 4,
371 .cpu_setup = __setup_cpu_604,
372 .platform = "ppc604",
373 },
374 { /* 604ev */
375 .pvr_mask = 0xffff0000,
376 .pvr_value = 0x000a0000,
377 .cpu_name = "604ev",
378 .cpu_features = CPU_FTRS_604,
379 .cpu_user_features = COMMON_USER,
380 .icache_bsize = 32,
381 .dcache_bsize = 32,
382 .num_pmcs = 4,
383 .cpu_setup = __setup_cpu_604,
384 .platform = "ppc604",
385 },
386 { /* 740/750 (0x4202, don't support TAU ?) */
387 .pvr_mask = 0xffffffff,
388 .pvr_value = 0x00084202,
389 .cpu_name = "740/750",
390 .cpu_features = CPU_FTRS_740_NOTAU,
391 .cpu_user_features = COMMON_USER,
392 .icache_bsize = 32,
393 .dcache_bsize = 32,
394 .num_pmcs = 4,
395 .cpu_setup = __setup_cpu_750,
396 .platform = "ppc750",
397 },
398 { /* 750CX (80100 and 8010x?) */
399 .pvr_mask = 0xfffffff0,
400 .pvr_value = 0x00080100,
401 .cpu_name = "750CX",
402 .cpu_features = CPU_FTRS_750,
403 .cpu_user_features = COMMON_USER,
404 .icache_bsize = 32,
405 .dcache_bsize = 32,
406 .num_pmcs = 4,
407 .cpu_setup = __setup_cpu_750cx,
408 .platform = "ppc750",
409 },
410 { /* 750CX (82201 and 82202) */
411 .pvr_mask = 0xfffffff0,
412 .pvr_value = 0x00082200,
413 .cpu_name = "750CX",
414 .cpu_features = CPU_FTRS_750,
415 .cpu_user_features = COMMON_USER,
416 .icache_bsize = 32,
417 .dcache_bsize = 32,
418 .num_pmcs = 4,
419 .cpu_setup = __setup_cpu_750cx,
420 .platform = "ppc750",
421 },
422 { /* 750CXe (82214) */
423 .pvr_mask = 0xfffffff0,
424 .pvr_value = 0x00082210,
425 .cpu_name = "750CXe",
426 .cpu_features = CPU_FTRS_750,
427 .cpu_user_features = COMMON_USER,
428 .icache_bsize = 32,
429 .dcache_bsize = 32,
430 .num_pmcs = 4,
431 .cpu_setup = __setup_cpu_750cx,
432 .platform = "ppc750",
433 },
434 { /* 750CXe "Gekko" (83214) */
435 .pvr_mask = 0xffffffff,
436 .pvr_value = 0x00083214,
437 .cpu_name = "750CXe",
438 .cpu_features = CPU_FTRS_750,
439 .cpu_user_features = COMMON_USER,
440 .icache_bsize = 32,
441 .dcache_bsize = 32,
442 .num_pmcs = 4,
443 .cpu_setup = __setup_cpu_750cx,
444 .platform = "ppc750",
445 },
446 { /* 745/755 */
447 .pvr_mask = 0xfffff000,
448 .pvr_value = 0x00083000,
449 .cpu_name = "745/755",
450 .cpu_features = CPU_FTRS_750,
451 .cpu_user_features = COMMON_USER,
452 .icache_bsize = 32,
453 .dcache_bsize = 32,
454 .num_pmcs = 4,
455 .cpu_setup = __setup_cpu_750,
456 .platform = "ppc750",
457 },
458 { /* 750FX rev 1.x */
459 .pvr_mask = 0xffffff00,
460 .pvr_value = 0x70000100,
461 .cpu_name = "750FX",
462 .cpu_features = CPU_FTRS_750FX1,
463 .cpu_user_features = COMMON_USER,
464 .icache_bsize = 32,
465 .dcache_bsize = 32,
466 .num_pmcs = 4,
467 .cpu_setup = __setup_cpu_750,
468 .platform = "ppc750",
469 },
470 { /* 750FX rev 2.0 must disable HID0[DPM] */
471 .pvr_mask = 0xffffffff,
472 .pvr_value = 0x70000200,
473 .cpu_name = "750FX",
474 .cpu_features = CPU_FTRS_750FX2,
475 .cpu_user_features = COMMON_USER,
476 .icache_bsize = 32,
477 .dcache_bsize = 32,
478 .num_pmcs = 4,
479 .cpu_setup = __setup_cpu_750,
480 .platform = "ppc750",
481 },
482 { /* 750FX (All revs except 2.0) */
483 .pvr_mask = 0xffff0000,
484 .pvr_value = 0x70000000,
485 .cpu_name = "750FX",
486 .cpu_features = CPU_FTRS_750FX,
487 .cpu_user_features = COMMON_USER,
488 .icache_bsize = 32,
489 .dcache_bsize = 32,
490 .num_pmcs = 4,
491 .cpu_setup = __setup_cpu_750fx,
492 .platform = "ppc750",
493 },
494 { /* 750GX */
495 .pvr_mask = 0xffff0000,
496 .pvr_value = 0x70020000,
497 .cpu_name = "750GX",
498 .cpu_features = CPU_FTRS_750GX,
499 .cpu_user_features = COMMON_USER,
500 .icache_bsize = 32,
501 .dcache_bsize = 32,
502 .num_pmcs = 4,
503 .cpu_setup = __setup_cpu_750fx,
504 .platform = "ppc750",
505 },
506 { /* 740/750 (L2CR bit need fixup for 740) */
507 .pvr_mask = 0xffff0000,
508 .pvr_value = 0x00080000,
509 .cpu_name = "740/750",
510 .cpu_features = CPU_FTRS_740,
511 .cpu_user_features = COMMON_USER,
512 .icache_bsize = 32,
513 .dcache_bsize = 32,
514 .num_pmcs = 4,
515 .cpu_setup = __setup_cpu_750,
516 .platform = "ppc750",
517 },
518 { /* 7400 rev 1.1 ? (no TAU) */
519 .pvr_mask = 0xffffffff,
520 .pvr_value = 0x000c1101,
521 .cpu_name = "7400 (1.1)",
522 .cpu_features = CPU_FTRS_7400_NOTAU,
523 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
524 .icache_bsize = 32,
525 .dcache_bsize = 32,
526 .num_pmcs = 4,
527 .cpu_setup = __setup_cpu_7400,
528 .platform = "ppc7400",
529 },
530 { /* 7400 */
531 .pvr_mask = 0xffff0000,
532 .pvr_value = 0x000c0000,
533 .cpu_name = "7400",
534 .cpu_features = CPU_FTRS_7400,
535 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
536 .icache_bsize = 32,
537 .dcache_bsize = 32,
538 .num_pmcs = 4,
539 .cpu_setup = __setup_cpu_7400,
540 .platform = "ppc7400",
541 },
542 { /* 7410 */
543 .pvr_mask = 0xffff0000,
544 .pvr_value = 0x800c0000,
545 .cpu_name = "7410",
546 .cpu_features = CPU_FTRS_7400,
547 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
548 .icache_bsize = 32,
549 .dcache_bsize = 32,
550 .num_pmcs = 4,
551 .cpu_setup = __setup_cpu_7410,
552 .platform = "ppc7400",
553 },
554 { /* 7450 2.0 - no doze/nap */
555 .pvr_mask = 0xffffffff,
556 .pvr_value = 0x80000200,
557 .cpu_name = "7450",
558 .cpu_features = CPU_FTRS_7450_20,
559 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
560 .icache_bsize = 32,
561 .dcache_bsize = 32,
562 .num_pmcs = 6,
563 .cpu_setup = __setup_cpu_745x,
564 .oprofile_cpu_type = "ppc/7450",
565 .oprofile_type = PPC_OPROFILE_G4,
566 .platform = "ppc7450",
567 },
568 { /* 7450 2.1 */
569 .pvr_mask = 0xffffffff,
570 .pvr_value = 0x80000201,
571 .cpu_name = "7450",
572 .cpu_features = CPU_FTRS_7450_21,
573 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
574 .icache_bsize = 32,
575 .dcache_bsize = 32,
576 .num_pmcs = 6,
577 .cpu_setup = __setup_cpu_745x,
578 .oprofile_cpu_type = "ppc/7450",
579 .oprofile_type = PPC_OPROFILE_G4,
580 .platform = "ppc7450",
581 },
582 { /* 7450 2.3 and newer */
583 .pvr_mask = 0xffff0000,
584 .pvr_value = 0x80000000,
585 .cpu_name = "7450",
586 .cpu_features = CPU_FTRS_7450_23,
587 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
588 .icache_bsize = 32,
589 .dcache_bsize = 32,
590 .num_pmcs = 6,
591 .cpu_setup = __setup_cpu_745x,
592 .oprofile_cpu_type = "ppc/7450",
593 .oprofile_type = PPC_OPROFILE_G4,
594 .platform = "ppc7450",
595 },
596 { /* 7455 rev 1.x */
597 .pvr_mask = 0xffffff00,
598 .pvr_value = 0x80010100,
599 .cpu_name = "7455",
600 .cpu_features = CPU_FTRS_7455_1,
601 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
602 .icache_bsize = 32,
603 .dcache_bsize = 32,
604 .num_pmcs = 6,
605 .cpu_setup = __setup_cpu_745x,
606 .oprofile_cpu_type = "ppc/7450",
607 .oprofile_type = PPC_OPROFILE_G4,
608 .platform = "ppc7450",
609 },
610 { /* 7455 rev 2.0 */
611 .pvr_mask = 0xffffffff,
612 .pvr_value = 0x80010200,
613 .cpu_name = "7455",
614 .cpu_features = CPU_FTRS_7455_20,
615 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
616 .icache_bsize = 32,
617 .dcache_bsize = 32,
618 .num_pmcs = 6,
619 .cpu_setup = __setup_cpu_745x,
620 .oprofile_cpu_type = "ppc/7450",
621 .oprofile_type = PPC_OPROFILE_G4,
622 .platform = "ppc7450",
623 },
624 { /* 7455 others */
625 .pvr_mask = 0xffff0000,
626 .pvr_value = 0x80010000,
627 .cpu_name = "7455",
628 .cpu_features = CPU_FTRS_7455,
629 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
630 .icache_bsize = 32,
631 .dcache_bsize = 32,
632 .num_pmcs = 6,
633 .cpu_setup = __setup_cpu_745x,
634 .oprofile_cpu_type = "ppc/7450",
635 .oprofile_type = PPC_OPROFILE_G4,
636 .platform = "ppc7450",
637 },
638 { /* 7447/7457 Rev 1.0 */
639 .pvr_mask = 0xffffffff,
640 .pvr_value = 0x80020100,
641 .cpu_name = "7447/7457",
642 .cpu_features = CPU_FTRS_7447_10,
643 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
644 .icache_bsize = 32,
645 .dcache_bsize = 32,
646 .num_pmcs = 6,
647 .cpu_setup = __setup_cpu_745x,
648 .oprofile_cpu_type = "ppc/7450",
649 .oprofile_type = PPC_OPROFILE_G4,
650 .platform = "ppc7450",
651 },
652 { /* 7447/7457 Rev 1.1 */
653 .pvr_mask = 0xffffffff,
654 .pvr_value = 0x80020101,
655 .cpu_name = "7447/7457",
656 .cpu_features = CPU_FTRS_7447_10,
657 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
658 .icache_bsize = 32,
659 .dcache_bsize = 32,
660 .num_pmcs = 6,
661 .cpu_setup = __setup_cpu_745x,
662 .oprofile_cpu_type = "ppc/7450",
663 .oprofile_type = PPC_OPROFILE_G4,
664 .platform = "ppc7450",
665 },
666 { /* 7447/7457 Rev 1.2 and later */
667 .pvr_mask = 0xffff0000,
668 .pvr_value = 0x80020000,
669 .cpu_name = "7447/7457",
670 .cpu_features = CPU_FTRS_7447,
671 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
672 .icache_bsize = 32,
673 .dcache_bsize = 32,
674 .num_pmcs = 6,
675 .cpu_setup = __setup_cpu_745x,
676 .oprofile_cpu_type = "ppc/7450",
677 .oprofile_type = PPC_OPROFILE_G4,
678 .platform = "ppc7450",
679 },
680 { /* 7447A */
681 .pvr_mask = 0xffff0000,
682 .pvr_value = 0x80030000,
683 .cpu_name = "7447A",
684 .cpu_features = CPU_FTRS_7447A,
685 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
686 .icache_bsize = 32,
687 .dcache_bsize = 32,
688 .num_pmcs = 6,
689 .cpu_setup = __setup_cpu_745x,
690 .oprofile_cpu_type = "ppc/7450",
691 .oprofile_type = PPC_OPROFILE_G4,
692 .platform = "ppc7450",
693 },
694 { /* 7448 */
695 .pvr_mask = 0xffff0000,
696 .pvr_value = 0x80040000,
697 .cpu_name = "7448",
698 .cpu_features = CPU_FTRS_7447A,
699 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
700 .icache_bsize = 32,
701 .dcache_bsize = 32,
702 .num_pmcs = 6,
703 .cpu_setup = __setup_cpu_745x,
704 .oprofile_cpu_type = "ppc/7450",
705 .oprofile_type = PPC_OPROFILE_G4,
706 .platform = "ppc7450",
707 },
708 { /* 82xx (8240, 8245, 8260 are all 603e cores) */
709 .pvr_mask = 0x7fff0000,
710 .pvr_value = 0x00810000,
711 .cpu_name = "82xx",
712 .cpu_features = CPU_FTRS_82XX,
713 .cpu_user_features = COMMON_USER,
714 .icache_bsize = 32,
715 .dcache_bsize = 32,
716 .cpu_setup = __setup_cpu_603,
717 .platform = "ppc603",
718 },
719 { /* All G2_LE (603e core, plus some) have the same pvr */
720 .pvr_mask = 0x7fff0000,
721 .pvr_value = 0x00820000,
722 .cpu_name = "G2_LE",
723 .cpu_features = CPU_FTRS_G2_LE,
724 .cpu_user_features = COMMON_USER,
725 .icache_bsize = 32,
726 .dcache_bsize = 32,
727 .cpu_setup = __setup_cpu_603,
728 .platform = "ppc603",
729 },
730 { /* e300 (a 603e core, plus some) on 83xx */
731 .pvr_mask = 0x7fff0000,
732 .pvr_value = 0x00830000,
733 .cpu_name = "e300",
734 .cpu_features = CPU_FTRS_E300,
735 .cpu_user_features = COMMON_USER,
736 .icache_bsize = 32,
737 .dcache_bsize = 32,
738 .cpu_setup = __setup_cpu_603,
739 .platform = "ppc603",
740 },
741 { /* default match, we assume split I/D cache & TB (non-601)... */
742 .pvr_mask = 0x00000000,
743 .pvr_value = 0x00000000,
744 .cpu_name = "(generic PPC)",
745 .cpu_features = CPU_FTRS_CLASSIC32,
746 .cpu_user_features = COMMON_USER,
747 .icache_bsize = 32,
748 .dcache_bsize = 32,
749 .platform = "ppc603",
750 },
751 #endif /* CLASSIC_PPC */
752 #ifdef CONFIG_8xx
753 { /* 8xx */
754 .pvr_mask = 0xffff0000,
755 .pvr_value = 0x00500000,
756 .cpu_name = "8xx",
757 /* CPU_FTR_MAYBE_CAN_DOZE is possible,
758 * if the 8xx code is there.... */
759 .cpu_features = CPU_FTRS_8XX,
760 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
761 .icache_bsize = 16,
762 .dcache_bsize = 16,
763 .platform = "ppc823",
764 },
765 #endif /* CONFIG_8xx */
766 #ifdef CONFIG_40x
767 { /* 403GC */
768 .pvr_mask = 0xffffff00,
769 .pvr_value = 0x00200200,
770 .cpu_name = "403GC",
771 .cpu_features = CPU_FTRS_40X,
772 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
773 .icache_bsize = 16,
774 .dcache_bsize = 16,
775 .platform = "ppc403",
776 },
777 { /* 403GCX */
778 .pvr_mask = 0xffffff00,
779 .pvr_value = 0x00201400,
780 .cpu_name = "403GCX",
781 .cpu_features = CPU_FTRS_40X,
782 .cpu_user_features = PPC_FEATURE_32 |
783 PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
784 .icache_bsize = 16,
785 .dcache_bsize = 16,
786 .platform = "ppc403",
787 },
788 { /* 403G ?? */
789 .pvr_mask = 0xffff0000,
790 .pvr_value = 0x00200000,
791 .cpu_name = "403G ??",
792 .cpu_features = CPU_FTRS_40X,
793 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
794 .icache_bsize = 16,
795 .dcache_bsize = 16,
796 .platform = "ppc403",
797 },
798 { /* 405GP */
799 .pvr_mask = 0xffff0000,
800 .pvr_value = 0x40110000,
801 .cpu_name = "405GP",
802 .cpu_features = CPU_FTRS_40X,
803 .cpu_user_features = PPC_FEATURE_32 |
804 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
805 .icache_bsize = 32,
806 .dcache_bsize = 32,
807 .platform = "ppc405",
808 },
809 { /* STB 03xxx */
810 .pvr_mask = 0xffff0000,
811 .pvr_value = 0x40130000,
812 .cpu_name = "STB03xxx",
813 .cpu_features = CPU_FTRS_40X,
814 .cpu_user_features = PPC_FEATURE_32 |
815 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
816 .icache_bsize = 32,
817 .dcache_bsize = 32,
818 .platform = "ppc405",
819 },
820 { /* STB 04xxx */
821 .pvr_mask = 0xffff0000,
822 .pvr_value = 0x41810000,
823 .cpu_name = "STB04xxx",
824 .cpu_features = CPU_FTRS_40X,
825 .cpu_user_features = PPC_FEATURE_32 |
826 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
827 .icache_bsize = 32,
828 .dcache_bsize = 32,
829 .platform = "ppc405",
830 },
831 { /* NP405L */
832 .pvr_mask = 0xffff0000,
833 .pvr_value = 0x41610000,
834 .cpu_name = "NP405L",
835 .cpu_features = CPU_FTRS_40X,
836 .cpu_user_features = PPC_FEATURE_32 |
837 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
838 .icache_bsize = 32,
839 .dcache_bsize = 32,
840 .platform = "ppc405",
841 },
842 { /* NP4GS3 */
843 .pvr_mask = 0xffff0000,
844 .pvr_value = 0x40B10000,
845 .cpu_name = "NP4GS3",
846 .cpu_features = CPU_FTRS_40X,
847 .cpu_user_features = PPC_FEATURE_32 |
848 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
849 .icache_bsize = 32,
850 .dcache_bsize = 32,
851 .platform = "ppc405",
852 },
853 { /* NP405H */
854 .pvr_mask = 0xffff0000,
855 .pvr_value = 0x41410000,
856 .cpu_name = "NP405H",
857 .cpu_features = CPU_FTRS_40X,
858 .cpu_user_features = PPC_FEATURE_32 |
859 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
860 .icache_bsize = 32,
861 .dcache_bsize = 32,
862 .platform = "ppc405",
863 },
864 { /* 405GPr */
865 .pvr_mask = 0xffff0000,
866 .pvr_value = 0x50910000,
867 .cpu_name = "405GPr",
868 .cpu_features = CPU_FTRS_40X,
869 .cpu_user_features = PPC_FEATURE_32 |
870 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
871 .icache_bsize = 32,
872 .dcache_bsize = 32,
873 .platform = "ppc405",
874 },
875 { /* STBx25xx */
876 .pvr_mask = 0xffff0000,
877 .pvr_value = 0x51510000,
878 .cpu_name = "STBx25xx",
879 .cpu_features = CPU_FTRS_40X,
880 .cpu_user_features = PPC_FEATURE_32 |
881 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
882 .icache_bsize = 32,
883 .dcache_bsize = 32,
884 .platform = "ppc405",
885 },
886 { /* 405LP */
887 .pvr_mask = 0xffff0000,
888 .pvr_value = 0x41F10000,
889 .cpu_name = "405LP",
890 .cpu_features = CPU_FTRS_40X,
891 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
892 .icache_bsize = 32,
893 .dcache_bsize = 32,
894 .platform = "ppc405",
895 },
896 { /* Xilinx Virtex-II Pro */
897 .pvr_mask = 0xfffff000,
898 .pvr_value = 0x20010000,
899 .cpu_name = "Virtex-II Pro",
900 .cpu_features = CPU_FTRS_40X,
901 .cpu_user_features = PPC_FEATURE_32 |
902 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
903 .icache_bsize = 32,
904 .dcache_bsize = 32,
905 .platform = "ppc405",
906 },
907 { /* Xilinx Virtex-4 FX */
908 .pvr_mask = 0xfffff000,
909 .pvr_value = 0x20011000,
910 .cpu_name = "Virtex-4 FX",
911 .cpu_features = CPU_FTRS_40X,
912 .cpu_user_features = PPC_FEATURE_32 |
913 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
914 .icache_bsize = 32,
915 .dcache_bsize = 32,
916 },
917 { /* 405EP */
918 .pvr_mask = 0xffff0000,
919 .pvr_value = 0x51210000,
920 .cpu_name = "405EP",
921 .cpu_features = CPU_FTRS_40X,
922 .cpu_user_features = PPC_FEATURE_32 |
923 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
924 .icache_bsize = 32,
925 .dcache_bsize = 32,
926 .platform = "ppc405",
927 },
928
929 #endif /* CONFIG_40x */
930 #ifdef CONFIG_44x
931 {
932 .pvr_mask = 0xf0000fff,
933 .pvr_value = 0x40000850,
934 .cpu_name = "440EP Rev. A",
935 .cpu_features = CPU_FTRS_44X,
936 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
937 .icache_bsize = 32,
938 .dcache_bsize = 32,
939 .platform = "ppc440",
940 },
941 {
942 .pvr_mask = 0xf0000fff,
943 .pvr_value = 0x400008d3,
944 .cpu_name = "440EP Rev. B",
945 .cpu_features = CPU_FTRS_44X,
946 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
947 .icache_bsize = 32,
948 .dcache_bsize = 32,
949 .platform = "ppc440",
950 },
951 { /* 440GP Rev. B */
952 .pvr_mask = 0xf0000fff,
953 .pvr_value = 0x40000440,
954 .cpu_name = "440GP Rev. B",
955 .cpu_features = CPU_FTRS_44X,
956 .cpu_user_features = COMMON_USER_BOOKE,
957 .icache_bsize = 32,
958 .dcache_bsize = 32,
959 .platform = "ppc440gp",
960 },
961 { /* 440GP Rev. C */
962 .pvr_mask = 0xf0000fff,
963 .pvr_value = 0x40000481,
964 .cpu_name = "440GP Rev. C",
965 .cpu_features = CPU_FTRS_44X,
966 .cpu_user_features = COMMON_USER_BOOKE,
967 .icache_bsize = 32,
968 .dcache_bsize = 32,
969 .platform = "ppc440gp",
970 },
971 { /* 440GX Rev. A */
972 .pvr_mask = 0xf0000fff,
973 .pvr_value = 0x50000850,
974 .cpu_name = "440GX Rev. A",
975 .cpu_features = CPU_FTRS_44X,
976 .cpu_user_features = COMMON_USER_BOOKE,
977 .icache_bsize = 32,
978 .dcache_bsize = 32,
979 .platform = "ppc440",
980 },
981 { /* 440GX Rev. B */
982 .pvr_mask = 0xf0000fff,
983 .pvr_value = 0x50000851,
984 .cpu_name = "440GX Rev. B",
985 .cpu_features = CPU_FTRS_44X,
986 .cpu_user_features = COMMON_USER_BOOKE,
987 .icache_bsize = 32,
988 .dcache_bsize = 32,
989 .platform = "ppc440",
990 },
991 { /* 440GX Rev. C */
992 .pvr_mask = 0xf0000fff,
993 .pvr_value = 0x50000892,
994 .cpu_name = "440GX Rev. C",
995 .cpu_features = CPU_FTRS_44X,
996 .cpu_user_features = COMMON_USER_BOOKE,
997 .icache_bsize = 32,
998 .dcache_bsize = 32,
999 .platform = "ppc440",
1000 },
1001 { /* 440GX Rev. F */
1002 .pvr_mask = 0xf0000fff,
1003 .pvr_value = 0x50000894,
1004 .cpu_name = "440GX Rev. F",
1005 .cpu_features = CPU_FTRS_44X,
1006 .cpu_user_features = COMMON_USER_BOOKE,
1007 .icache_bsize = 32,
1008 .dcache_bsize = 32,
1009 .platform = "ppc440",
1010 },
1011 { /* 440SP Rev. A */
1012 .pvr_mask = 0xff000fff,
1013 .pvr_value = 0x53000891,
1014 .cpu_name = "440SP Rev. A",
1015 .cpu_features = CPU_FTRS_44X,
1016 .cpu_user_features = COMMON_USER_BOOKE,
1017 .icache_bsize = 32,
1018 .dcache_bsize = 32,
1019 .platform = "ppc440",
1020 },
1021 { /* 440SPe Rev. A */
1022 .pvr_mask = 0xff000fff,
1023 .pvr_value = 0x53000890,
1024 .cpu_name = "440SPe Rev. A",
1025 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
1026 CPU_FTR_USE_TB,
1027 .cpu_user_features = COMMON_USER_BOOKE,
1028 .icache_bsize = 32,
1029 .dcache_bsize = 32,
1030 .platform = "ppc440",
1031 },
1032 #endif /* CONFIG_44x */
1033 #ifdef CONFIG_FSL_BOOKE
1034 { /* e200z5 */
1035 .pvr_mask = 0xfff00000,
1036 .pvr_value = 0x81000000,
1037 .cpu_name = "e200z5",
1038 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
1039 .cpu_features = CPU_FTRS_E200,
1040 .cpu_user_features = COMMON_USER_BOOKE |
1041 PPC_FEATURE_HAS_EFP_SINGLE |
1042 PPC_FEATURE_UNIFIED_CACHE,
1043 .dcache_bsize = 32,
1044 .platform = "ppc5554",
1045 },
1046 { /* e200z6 */
1047 .pvr_mask = 0xfff00000,
1048 .pvr_value = 0x81100000,
1049 .cpu_name = "e200z6",
1050 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
1051 .cpu_features = CPU_FTRS_E200,
1052 .cpu_user_features = COMMON_USER_BOOKE |
1053 PPC_FEATURE_SPE_COMP |
1054 PPC_FEATURE_HAS_EFP_SINGLE |
1055 PPC_FEATURE_UNIFIED_CACHE,
1056 .dcache_bsize = 32,
1057 .platform = "ppc5554",
1058 },
1059 { /* e500 */
1060 .pvr_mask = 0xffff0000,
1061 .pvr_value = 0x80200000,
1062 .cpu_name = "e500",
1063 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
1064 .cpu_features = CPU_FTRS_E500,
1065 .cpu_user_features = COMMON_USER_BOOKE |
1066 PPC_FEATURE_SPE_COMP |
1067 PPC_FEATURE_HAS_EFP_SINGLE,
1068 .icache_bsize = 32,
1069 .dcache_bsize = 32,
1070 .num_pmcs = 4,
1071 .oprofile_cpu_type = "ppc/e500",
1072 .oprofile_type = PPC_OPROFILE_BOOKE,
1073 .platform = "ppc8540",
1074 },
1075 { /* e500v2 */
1076 .pvr_mask = 0xffff0000,
1077 .pvr_value = 0x80210000,
1078 .cpu_name = "e500v2",
1079 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
1080 .cpu_features = CPU_FTRS_E500_2,
1081 .cpu_user_features = COMMON_USER_BOOKE |
1082 PPC_FEATURE_SPE_COMP |
1083 PPC_FEATURE_HAS_EFP_SINGLE |
1084 PPC_FEATURE_HAS_EFP_DOUBLE,
1085 .icache_bsize = 32,
1086 .dcache_bsize = 32,
1087 .num_pmcs = 4,
1088 .oprofile_cpu_type = "ppc/e500",
1089 .oprofile_type = PPC_OPROFILE_BOOKE,
1090 .platform = "ppc8548",
1091 },
1092 #endif
1093 #if !CLASSIC_PPC
1094 { /* default match */
1095 .pvr_mask = 0x00000000,
1096 .pvr_value = 0x00000000,
1097 .cpu_name = "(generic PPC)",
1098 .cpu_features = CPU_FTRS_GENERIC_32,
1099 .cpu_user_features = PPC_FEATURE_32,
1100 .icache_bsize = 32,
1101 .dcache_bsize = 32,
1102 .platform = "powerpc",
1103 }
1104 #endif /* !CLASSIC_PPC */
1105 #endif /* CONFIG_PPC32 */
1106 };
Support for the Chinese Samsung S3C2440 based development boards