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[GFS2] Allow local DF locks when holding a cached EX glock
[linux-2.6/mini2440.git] / drivers / ata / pata_amd.c
blob57dd00f463d3367a33f24cf5f1808cc1c1f294ec
1 /*
2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based on pata-sil680. Errata information is taken from data sheets
7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
8 * claimed by sata-nv.c.
9 *
10 * TODO:
11 * Variable system clock when/if it makes sense
12 * Power management on ports
13 *
14 *
15 * Documentation publically available.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <scsi/scsi_host.h>
25 #include <linux/libata.h>
26
27 #define DRV_NAME "pata_amd"
28 #define DRV_VERSION "0.3.10"
29
30 /**
31 * timing_setup - shared timing computation and load
32 * @ap: ATA port being set up
33 * @adev: drive being configured
34 * @offset: port offset
35 * @speed: target speed
36 * @clock: clock multiplier (number of times 33MHz for this part)
37 *
38 * Perform the actual timing set up for Nvidia or AMD PATA devices.
39 * The actual devices vary so they all call into this helper function
40 * providing the clock multipler and offset (because AMD and Nvidia put
41 * the ports at different locations).
42 */
43
44 static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
45 {
46 static const unsigned char amd_cyc2udma[] = {
47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
48 };
49
50 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
51 struct ata_device *peer = ata_dev_pair(adev);
52 int dn = ap->port_no * 2 + adev->devno;
53 struct ata_timing at, apeer;
54 int T, UT;
55 const int amd_clock = 33333; /* KHz. */
56 u8 t;
57
58 T = 1000000000 / amd_clock;
59 UT = T;
60 if (clock >= 2)
61 UT = T / 2;
62
63 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
64 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
65 return;
66 }
67
68 if (peer) {
69 /* This may be over conservative */
70 if (peer->dma_mode) {
71 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
72 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
73 }
74 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
75 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
76 }
77
78 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
79 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
80
81 /*
82 * Now do the setup work
83 */
84
85 /* Configure the address set up timing */
86 pci_read_config_byte(pdev, offset + 0x0C, &t);
87 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
88 pci_write_config_byte(pdev, offset + 0x0C , t);
89
90 /* Configure the 8bit I/O timing */
91 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
92 ((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1));
93
94 /* Drive timing */
95 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
96 ((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1));
97
98 switch (clock) {
99 case 1:
100 t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03;
101 break;
102
103 case 2:
104 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03;
105 break;
106
107 case 3:
108 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03;
109 break;
110
111 case 4:
112 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03;
113 break;
114
115 default:
116 return;
117 }
118
119 /* UDMA timing */
120 if (at.udma)
121 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
122 }
123
124 /**
125 * amd_pre_reset - perform reset handling
126 * @link: ATA link
127 * @deadline: deadline jiffies for the operation
128 *
129 * Reset sequence checking enable bits to see which ports are
130 * active.
131 */
132
133 static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
134 {
135 static const struct pci_bits amd_enable_bits[] = {
136 { 0x40, 1, 0x02, 0x02 },
137 { 0x40, 1, 0x01, 0x01 }
138 };
139
140 struct ata_port *ap = link->ap;
141 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
142
143 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
144 return -ENOENT;
145
146 return ata_sff_prereset(link, deadline);
147 }
148
149 static int amd_cable_detect(struct ata_port *ap)
150 {
151 static const u32 bitmask[2] = {0x03, 0x0C};
152 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
153 u8 ata66;
154
155 pci_read_config_byte(pdev, 0x42, &ata66);
156 if (ata66 & bitmask[ap->port_no])
157 return ATA_CBL_PATA80;
158 return ATA_CBL_PATA40;
159 }
160
161 /**
162 * amd33_set_piomode - set initial PIO mode data
163 * @ap: ATA interface
164 * @adev: ATA device
165 *
166 * Program the AMD registers for PIO mode.
167 */
168
169 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
170 {
171 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
172 }
173
174 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
175 {
176 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
177 }
178
179 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
180 {
181 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
182 }
183
184 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
185 {
186 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
187 }
188
189 /**
190 * amd33_set_dmamode - set initial DMA mode data
191 * @ap: ATA interface
192 * @adev: ATA device
193 *
194 * Program the MWDMA/UDMA modes for the AMD and Nvidia
195 * chipset.
196 */
197
198 static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
199 {
200 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
201 }
202
203 static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
204 {
205 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
206 }
207
208 static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
209 {
210 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
211 }
212
213 static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
214 {
215 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
216 }
217
218 /* Both host-side and drive-side detection results are worthless on NV
219 * PATAs. Ignore them and just follow what BIOS configured. Both the
220 * current configuration in PCI config reg and ACPI GTM result are
221 * cached during driver attach and are consulted to select transfer
222 * mode.
223 */
224 static unsigned long nv_mode_filter(struct ata_device *dev,
225 unsigned long xfer_mask)
226 {
227 static const unsigned int udma_mask_map[] =
228 { ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
229 ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
230 struct ata_port *ap = dev->link->ap;
231 char acpi_str[32] = "";
232 u32 saved_udma, udma;
233 const struct ata_acpi_gtm *gtm;
234 unsigned long bios_limit = 0, acpi_limit = 0, limit;
235
236 /* find out what BIOS configured */
237 udma = saved_udma = (unsigned long)ap->host->private_data;
238
239 if (ap->port_no == 0)
240 udma >>= 16;
241 if (dev->devno == 0)
242 udma >>= 8;
243
244 if ((udma & 0xc0) == 0xc0)
245 bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);
246
247 /* consult ACPI GTM too */
248 gtm = ata_acpi_init_gtm(ap);
249 if (gtm) {
250 acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);
251
252 snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
253 gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
254 }
255
256 /* be optimistic, EH can take care of things if something goes wrong */
257 limit = bios_limit | acpi_limit;
258
259 /* If PIO or DMA isn't configured at all, don't limit. Let EH
260 * handle it.
261 */
262 if (!(limit & ATA_MASK_PIO))
263 limit |= ATA_MASK_PIO;
264 if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
265 limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;
266
267 ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
268 "BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
269 xfer_mask, limit, xfer_mask & limit, bios_limit,
270 saved_udma, acpi_limit, acpi_str);
271
272 return xfer_mask & limit;
273 }
274
275 /**
276 * nv_probe_init - cable detection
277 * @lin: ATA link
278 *
279 * Perform cable detection. The BIOS stores this in PCI config
280 * space for us.
281 */
282
283 static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
284 {
285 static const struct pci_bits nv_enable_bits[] = {
286 { 0x50, 1, 0x02, 0x02 },
287 { 0x50, 1, 0x01, 0x01 }
288 };
289
290 struct ata_port *ap = link->ap;
291 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
292
293 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
294 return -ENOENT;
295
296 return ata_sff_prereset(link, deadline);
297 }
298
299 /**
300 * nv100_set_piomode - set initial PIO mode data
301 * @ap: ATA interface
302 * @adev: ATA device
303 *
304 * Program the AMD registers for PIO mode.
305 */
306
307 static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
308 {
309 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
310 }
311
312 static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
313 {
314 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
315 }
316
317 /**
318 * nv100_set_dmamode - set initial DMA mode data
319 * @ap: ATA interface
320 * @adev: ATA device
321 *
322 * Program the MWDMA/UDMA modes for the AMD and Nvidia
323 * chipset.
324 */
325
326 static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
327 {
328 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
329 }
330
331 static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
332 {
333 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
334 }
335
336 static void nv_host_stop(struct ata_host *host)
337 {
338 u32 udma = (unsigned long)host->private_data;
339
340 /* restore PCI config register 0x60 */
341 pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
342 }
343
344 static struct scsi_host_template amd_sht = {
345 ATA_BMDMA_SHT(DRV_NAME),
346 };
347
348 static const struct ata_port_operations amd_base_port_ops = {
349 .inherits = &ata_bmdma_port_ops,
350 .prereset = amd_pre_reset,
351 };
352
353 static struct ata_port_operations amd33_port_ops = {
354 .inherits = &amd_base_port_ops,
355 .cable_detect = ata_cable_40wire,
356 .set_piomode = amd33_set_piomode,
357 .set_dmamode = amd33_set_dmamode,
358 };
359
360 static struct ata_port_operations amd66_port_ops = {
361 .inherits = &amd_base_port_ops,
362 .cable_detect = ata_cable_unknown,
363 .set_piomode = amd66_set_piomode,
364 .set_dmamode = amd66_set_dmamode,
365 };
366
367 static struct ata_port_operations amd100_port_ops = {
368 .inherits = &amd_base_port_ops,
369 .cable_detect = ata_cable_unknown,
370 .set_piomode = amd100_set_piomode,
371 .set_dmamode = amd100_set_dmamode,
372 };
373
374 static struct ata_port_operations amd133_port_ops = {
375 .inherits = &amd_base_port_ops,
376 .cable_detect = amd_cable_detect,
377 .set_piomode = amd133_set_piomode,
378 .set_dmamode = amd133_set_dmamode,
379 };
380
381 static const struct ata_port_operations nv_base_port_ops = {
382 .inherits = &ata_bmdma_port_ops,
383 .cable_detect = ata_cable_ignore,
384 .mode_filter = nv_mode_filter,
385 .prereset = nv_pre_reset,
386 .host_stop = nv_host_stop,
387 };
388
389 static struct ata_port_operations nv100_port_ops = {
390 .inherits = &nv_base_port_ops,
391 .set_piomode = nv100_set_piomode,
392 .set_dmamode = nv100_set_dmamode,
393 };
394
395 static struct ata_port_operations nv133_port_ops = {
396 .inherits = &nv_base_port_ops,
397 .set_piomode = nv133_set_piomode,
398 .set_dmamode = nv133_set_dmamode,
399 };
400
401 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
402 {
403 static const struct ata_port_info info[10] = {
404 { /* 0: AMD 7401 */
405 .flags = ATA_FLAG_SLAVE_POSS,
406 .pio_mask = 0x1f,
407 .mwdma_mask = 0x07, /* No SWDMA */
408 .udma_mask = 0x07, /* UDMA 33 */
409 .port_ops = &amd33_port_ops
410 },
411 { /* 1: Early AMD7409 - no swdma */
412 .flags = ATA_FLAG_SLAVE_POSS,
413 .pio_mask = 0x1f,
414 .mwdma_mask = 0x07,
415 .udma_mask = ATA_UDMA4, /* UDMA 66 */
416 .port_ops = &amd66_port_ops
417 },
418 { /* 2: AMD 7409, no swdma errata */
419 .flags = ATA_FLAG_SLAVE_POSS,
420 .pio_mask = 0x1f,
421 .mwdma_mask = 0x07,
422 .udma_mask = ATA_UDMA4, /* UDMA 66 */
423 .port_ops = &amd66_port_ops
424 },
425 { /* 3: AMD 7411 */
426 .flags = ATA_FLAG_SLAVE_POSS,
427 .pio_mask = 0x1f,
428 .mwdma_mask = 0x07,
429 .udma_mask = ATA_UDMA5, /* UDMA 100 */
430 .port_ops = &amd100_port_ops
431 },
432 { /* 4: AMD 7441 */
433 .flags = ATA_FLAG_SLAVE_POSS,
434 .pio_mask = 0x1f,
435 .mwdma_mask = 0x07,
436 .udma_mask = ATA_UDMA5, /* UDMA 100 */
437 .port_ops = &amd100_port_ops
438 },
439 { /* 5: AMD 8111*/
440 .flags = ATA_FLAG_SLAVE_POSS,
441 .pio_mask = 0x1f,
442 .mwdma_mask = 0x07,
443 .udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
444 .port_ops = &amd133_port_ops
445 },
446 { /* 6: AMD 8111 UDMA 100 (Serenade) */
447 .flags = ATA_FLAG_SLAVE_POSS,
448 .pio_mask = 0x1f,
449 .mwdma_mask = 0x07,
450 .udma_mask = ATA_UDMA5, /* UDMA 100, no swdma */
451 .port_ops = &amd133_port_ops
452 },
453 { /* 7: Nvidia Nforce */
454 .flags = ATA_FLAG_SLAVE_POSS,
455 .pio_mask = 0x1f,
456 .mwdma_mask = 0x07,
457 .udma_mask = ATA_UDMA5, /* UDMA 100 */
458 .port_ops = &nv100_port_ops
459 },
460 { /* 8: Nvidia Nforce2 and later */
461 .flags = ATA_FLAG_SLAVE_POSS,
462 .pio_mask = 0x1f,
463 .mwdma_mask = 0x07,
464 .udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
465 .port_ops = &nv133_port_ops
466 },
467 { /* 9: AMD CS5536 (Geode companion) */
468 .flags = ATA_FLAG_SLAVE_POSS,
469 .pio_mask = 0x1f,
470 .mwdma_mask = 0x07,
471 .udma_mask = ATA_UDMA5, /* UDMA 100 */
472 .port_ops = &amd100_port_ops
473 }
474 };
475 const struct ata_port_info *ppi[] = { NULL, NULL };
476 static int printed_version;
477 int type = id->driver_data;
478 void *hpriv = NULL;
479 u8 fifo;
480 int rc;
481
482 if (!printed_version++)
483 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
484
485 rc = pcim_enable_device(pdev);
486 if (rc)
487 return rc;
488
489 pci_read_config_byte(pdev, 0x41, &fifo);
490
491 /* Check for AMD7409 without swdma errata and if found adjust type */
492 if (type == 1 && pdev->revision > 0x7)
493 type = 2;
494
495 /* Serenade ? */
496 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
497 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
498 type = 6; /* UDMA 100 only */
499
500 /*
501 * Okay, type is determined now. Apply type-specific workarounds.
502 */
503 ppi[0] = &info[type];
504
505 if (type < 3)
506 ata_pci_bmdma_clear_simplex(pdev);
507
508 /* Check for AMD7411 */
509 if (type == 3)
510 /* FIFO is broken */
511 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
512 else
513 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
514
515 /* Cable detection on Nvidia chips doesn't work too well,
516 * cache BIOS programmed UDMA mode.
517 */
518 if (type == 7 || type == 8) {
519 u32 udma;
520
521 pci_read_config_dword(pdev, 0x60, &udma);
522 hpriv = (void *)(unsigned long)udma;
523 }
524
525 /* And fire it up */
526 return ata_pci_sff_init_one(pdev, ppi, &amd_sht, hpriv);
527 }
528
529 #ifdef CONFIG_PM
530 static int amd_reinit_one(struct pci_dev *pdev)
531 {
532 struct ata_host *host = dev_get_drvdata(&pdev->dev);
533 int rc;
534
535 rc = ata_pci_device_do_resume(pdev);
536 if (rc)
537 return rc;
538
539 if (pdev->vendor == PCI_VENDOR_ID_AMD) {
540 u8 fifo;
541 pci_read_config_byte(pdev, 0x41, &fifo);
542 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
543 /* FIFO is broken */
544 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
545 else
546 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
547 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
548 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
549 ata_pci_bmdma_clear_simplex(pdev);
550 }
551
552 ata_host_resume(host);
553 return 0;
554 }
555 #endif
556
557 static const struct pci_device_id amd[] = {
558 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
559 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
560 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
561 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
562 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
563 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
564 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
565 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
566 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
567 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
568 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
569 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
570 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
571 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
572 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
573 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
574 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
575 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
576 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
577 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
578
579 { },
580 };
581
582 static struct pci_driver amd_pci_driver = {
583 .name = DRV_NAME,
584 .id_table = amd,
585 .probe = amd_init_one,
586 .remove = ata_pci_remove_one,
587 #ifdef CONFIG_PM
588 .suspend = ata_pci_device_suspend,
589 .resume = amd_reinit_one,
590 #endif
591 };
592
593 static int __init amd_init(void)
594 {
595 return pci_register_driver(&amd_pci_driver);
596 }
597
598 static void __exit amd_exit(void)
599 {
600 pci_unregister_driver(&amd_pci_driver);
601 }
602
603 MODULE_AUTHOR("Alan Cox");
604 MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
605 MODULE_LICENSE("GPL");
606 MODULE_DEVICE_TABLE(pci, amd);
607 MODULE_VERSION(DRV_VERSION);
608
609 module_init(amd_init);
610 module_exit(amd_exit);
Support for the Chinese Samsung S3C2440 based development boards