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[GFS2] Allow local DF locks when holding a cached EX glock
[linux-2.6/mini2440.git] / drivers / ata / ata_piix.c
bloba90ae03f56b2e1f09793a8ddc63aca41a281b9f8
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
95
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
98
99 enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
103 PIIX_SIDPR_BAR = 5,
104 PIIX_SIDPR_LEN = 16,
105 PIIX_SIDPR_IDX = 0,
106 PIIX_SIDPR_DATA = 4,
107
108 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
109 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
110
111 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
112 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
113
114 PIIX_80C_PRI = (1 << 5) | (1 << 4),
115 PIIX_80C_SEC = (1 << 7) | (1 << 6),
116
117 /* constants for mapping table */
118 P0 = 0, /* port 0 */
119 P1 = 1, /* port 1 */
120 P2 = 2, /* port 2 */
121 P3 = 3, /* port 3 */
122 IDE = -1, /* IDE */
123 NA = -2, /* not avaliable */
124 RV = -3, /* reserved */
125
126 PIIX_AHCI_DEVICE = 6,
127
128 /* host->flags bits */
129 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
130 };
131
132 enum piix_controller_ids {
133 /* controller IDs */
134 piix_pata_mwdma, /* PIIX3 MWDMA only */
135 piix_pata_33, /* PIIX4 at 33Mhz */
136 ich_pata_33, /* ICH up to UDMA 33 only */
137 ich_pata_66, /* ICH up to 66 Mhz */
138 ich_pata_100, /* ICH up to UDMA 100 */
139 ich5_sata,
140 ich6_sata,
141 ich6m_sata,
142 ich8_sata,
143 ich8_2port_sata,
144 ich8m_apple_sata, /* locks up on second port enable */
145 tolapai_sata,
146 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
147 };
148
149 struct piix_map_db {
150 const u32 mask;
151 const u16 port_enable;
152 const int map[][4];
153 };
154
155 struct piix_host_priv {
156 const int *map;
157 void __iomem *sidpr;
158 };
159
160 static int piix_init_one(struct pci_dev *pdev,
161 const struct pci_device_id *ent);
162 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
163 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
164 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
165 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
166 static int ich_pata_cable_detect(struct ata_port *ap);
167 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
168 static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val);
169 static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val);
170 #ifdef CONFIG_PM
171 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
172 static int piix_pci_device_resume(struct pci_dev *pdev);
173 #endif
174
175 static unsigned int in_module_init = 1;
176
177 static const struct pci_device_id piix_pci_tbl[] = {
178 /* Intel PIIX3 for the 430HX etc */
179 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
180 /* VMware ICH4 */
181 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
182 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
183 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
184 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
185 /* Intel PIIX4 */
186 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
187 /* Intel PIIX4 */
188 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
189 /* Intel PIIX */
190 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
191 /* Intel ICH (i810, i815, i840) UDMA 66*/
192 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
193 /* Intel ICH0 : UDMA 33*/
194 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
195 /* Intel ICH2M */
196 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
198 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* Intel ICH3M */
200 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH3 (E7500/1) UDMA 100 */
202 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
204 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* Intel ICH5 */
207 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* C-ICH (i810E2) */
209 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
211 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 /* ICH6 (and 6) (i915) UDMA 100 */
213 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 /* ICH7/7-R (i945, i975) UDMA 100*/
215 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
217 /* ICH8 Mobile PATA Controller */
218 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
219
220 /* NOTE: The following PCI ids must be kept in sync with the
221 * list in drivers/pci/quirks.c.
222 */
223
224 /* 82801EB (ICH5) */
225 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
226 /* 82801EB (ICH5) */
227 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
228 /* 6300ESB (ICH5 variant with broken PCS present bits) */
229 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
230 /* 6300ESB pretending RAID */
231 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
232 /* 82801FB/FW (ICH6/ICH6W) */
233 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
234 /* 82801FR/FRW (ICH6R/ICH6RW) */
235 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
236 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
237 * Attach iff the controller is in IDE mode. */
238 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
239 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
240 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
241 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
242 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
243 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
244 /* Enterprise Southbridge 2 (631xESB/632xESB) */
245 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
246 /* SATA Controller 1 IDE (ICH8) */
247 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
248 /* SATA Controller 2 IDE (ICH8) */
249 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
250 /* Mobile SATA Controller IDE (ICH8M), Apple */
251 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
252 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
253 /* Mobile SATA Controller IDE (ICH8M) */
254 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
255 /* SATA Controller IDE (ICH9) */
256 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
257 /* SATA Controller IDE (ICH9) */
258 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
259 /* SATA Controller IDE (ICH9) */
260 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
261 /* SATA Controller IDE (ICH9M) */
262 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
263 /* SATA Controller IDE (ICH9M) */
264 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
265 /* SATA Controller IDE (ICH9M) */
266 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
267 /* SATA Controller IDE (Tolapai) */
268 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
269 /* SATA Controller IDE (ICH10) */
270 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
271 /* SATA Controller IDE (ICH10) */
272 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
273 /* SATA Controller IDE (ICH10) */
274 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
275 /* SATA Controller IDE (ICH10) */
276 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
277
278 { } /* terminate list */
279 };
280
281 static struct pci_driver piix_pci_driver = {
282 .name = DRV_NAME,
283 .id_table = piix_pci_tbl,
284 .probe = piix_init_one,
285 .remove = ata_pci_remove_one,
286 #ifdef CONFIG_PM
287 .suspend = piix_pci_device_suspend,
288 .resume = piix_pci_device_resume,
289 #endif
290 };
291
292 static struct scsi_host_template piix_sht = {
293 ATA_BMDMA_SHT(DRV_NAME),
294 };
295
296 static struct ata_port_operations piix_pata_ops = {
297 .inherits = &ata_bmdma_port_ops,
298 .cable_detect = ata_cable_40wire,
299 .set_piomode = piix_set_piomode,
300 .set_dmamode = piix_set_dmamode,
301 .prereset = piix_pata_prereset,
302 };
303
304 static struct ata_port_operations piix_vmw_ops = {
305 .inherits = &piix_pata_ops,
306 .bmdma_status = piix_vmw_bmdma_status,
307 };
308
309 static struct ata_port_operations ich_pata_ops = {
310 .inherits = &piix_pata_ops,
311 .cable_detect = ich_pata_cable_detect,
312 .set_dmamode = ich_set_dmamode,
313 };
314
315 static struct ata_port_operations piix_sata_ops = {
316 .inherits = &ata_bmdma_port_ops,
317 };
318
319 static struct ata_port_operations piix_sidpr_sata_ops = {
320 .inherits = &piix_sata_ops,
321 .hardreset = sata_std_hardreset,
322 .scr_read = piix_sidpr_scr_read,
323 .scr_write = piix_sidpr_scr_write,
324 };
325
326 static const struct piix_map_db ich5_map_db = {
327 .mask = 0x7,
328 .port_enable = 0x3,
329 .map = {
330 /* PM PS SM SS MAP */
331 { P0, NA, P1, NA }, /* 000b */
332 { P1, NA, P0, NA }, /* 001b */
333 { RV, RV, RV, RV },
334 { RV, RV, RV, RV },
335 { P0, P1, IDE, IDE }, /* 100b */
336 { P1, P0, IDE, IDE }, /* 101b */
337 { IDE, IDE, P0, P1 }, /* 110b */
338 { IDE, IDE, P1, P0 }, /* 111b */
339 },
340 };
341
342 static const struct piix_map_db ich6_map_db = {
343 .mask = 0x3,
344 .port_enable = 0xf,
345 .map = {
346 /* PM PS SM SS MAP */
347 { P0, P2, P1, P3 }, /* 00b */
348 { IDE, IDE, P1, P3 }, /* 01b */
349 { P0, P2, IDE, IDE }, /* 10b */
350 { RV, RV, RV, RV },
351 },
352 };
353
354 static const struct piix_map_db ich6m_map_db = {
355 .mask = 0x3,
356 .port_enable = 0x5,
357
358 /* Map 01b isn't specified in the doc but some notebooks use
359 * it anyway. MAP 01b have been spotted on both ICH6M and
360 * ICH7M.
361 */
362 .map = {
363 /* PM PS SM SS MAP */
364 { P0, P2, NA, NA }, /* 00b */
365 { IDE, IDE, P1, P3 }, /* 01b */
366 { P0, P2, IDE, IDE }, /* 10b */
367 { RV, RV, RV, RV },
368 },
369 };
370
371 static const struct piix_map_db ich8_map_db = {
372 .mask = 0x3,
373 .port_enable = 0xf,
374 .map = {
375 /* PM PS SM SS MAP */
376 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
377 { RV, RV, RV, RV },
378 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
379 { RV, RV, RV, RV },
380 },
381 };
382
383 static const struct piix_map_db ich8_2port_map_db = {
384 .mask = 0x3,
385 .port_enable = 0x3,
386 .map = {
387 /* PM PS SM SS MAP */
388 { P0, NA, P1, NA }, /* 00b */
389 { RV, RV, RV, RV }, /* 01b */
390 { RV, RV, RV, RV }, /* 10b */
391 { RV, RV, RV, RV },
392 },
393 };
394
395 static const struct piix_map_db ich8m_apple_map_db = {
396 .mask = 0x3,
397 .port_enable = 0x1,
398 .map = {
399 /* PM PS SM SS MAP */
400 { P0, NA, NA, NA }, /* 00b */
401 { RV, RV, RV, RV },
402 { P0, P2, IDE, IDE }, /* 10b */
403 { RV, RV, RV, RV },
404 },
405 };
406
407 static const struct piix_map_db tolapai_map_db = {
408 .mask = 0x3,
409 .port_enable = 0x3,
410 .map = {
411 /* PM PS SM SS MAP */
412 { P0, NA, P1, NA }, /* 00b */
413 { RV, RV, RV, RV }, /* 01b */
414 { RV, RV, RV, RV }, /* 10b */
415 { RV, RV, RV, RV },
416 },
417 };
418
419 static const struct piix_map_db *piix_map_db_table[] = {
420 [ich5_sata] = &ich5_map_db,
421 [ich6_sata] = &ich6_map_db,
422 [ich6m_sata] = &ich6m_map_db,
423 [ich8_sata] = &ich8_map_db,
424 [ich8_2port_sata] = &ich8_2port_map_db,
425 [ich8m_apple_sata] = &ich8m_apple_map_db,
426 [tolapai_sata] = &tolapai_map_db,
427 };
428
429 static struct ata_port_info piix_port_info[] = {
430 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
431 {
432 .flags = PIIX_PATA_FLAGS,
433 .pio_mask = 0x1f, /* pio0-4 */
434 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
435 .port_ops = &piix_pata_ops,
436 },
437
438 [piix_pata_33] = /* PIIX4 at 33MHz */
439 {
440 .flags = PIIX_PATA_FLAGS,
441 .pio_mask = 0x1f, /* pio0-4 */
442 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
443 .udma_mask = ATA_UDMA_MASK_40C,
444 .port_ops = &piix_pata_ops,
445 },
446
447 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
448 {
449 .flags = PIIX_PATA_FLAGS,
450 .pio_mask = 0x1f, /* pio 0-4 */
451 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
452 .udma_mask = ATA_UDMA2, /* UDMA33 */
453 .port_ops = &ich_pata_ops,
454 },
455
456 [ich_pata_66] = /* ICH controllers up to 66MHz */
457 {
458 .flags = PIIX_PATA_FLAGS,
459 .pio_mask = 0x1f, /* pio 0-4 */
460 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
461 .udma_mask = ATA_UDMA4,
462 .port_ops = &ich_pata_ops,
463 },
464
465 [ich_pata_100] =
466 {
467 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
468 .pio_mask = 0x1f, /* pio0-4 */
469 .mwdma_mask = 0x06, /* mwdma1-2 */
470 .udma_mask = ATA_UDMA5, /* udma0-5 */
471 .port_ops = &ich_pata_ops,
472 },
473
474 [ich5_sata] =
475 {
476 .flags = PIIX_SATA_FLAGS,
477 .pio_mask = 0x1f, /* pio0-4 */
478 .mwdma_mask = 0x07, /* mwdma0-2 */
479 .udma_mask = ATA_UDMA6,
480 .port_ops = &piix_sata_ops,
481 },
482
483 [ich6_sata] =
484 {
485 .flags = PIIX_SATA_FLAGS,
486 .pio_mask = 0x1f, /* pio0-4 */
487 .mwdma_mask = 0x07, /* mwdma0-2 */
488 .udma_mask = ATA_UDMA6,
489 .port_ops = &piix_sata_ops,
490 },
491
492 [ich6m_sata] =
493 {
494 .flags = PIIX_SATA_FLAGS,
495 .pio_mask = 0x1f, /* pio0-4 */
496 .mwdma_mask = 0x07, /* mwdma0-2 */
497 .udma_mask = ATA_UDMA6,
498 .port_ops = &piix_sata_ops,
499 },
500
501 [ich8_sata] =
502 {
503 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
504 .pio_mask = 0x1f, /* pio0-4 */
505 .mwdma_mask = 0x07, /* mwdma0-2 */
506 .udma_mask = ATA_UDMA6,
507 .port_ops = &piix_sata_ops,
508 },
509
510 [ich8_2port_sata] =
511 {
512 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
513 .pio_mask = 0x1f, /* pio0-4 */
514 .mwdma_mask = 0x07, /* mwdma0-2 */
515 .udma_mask = ATA_UDMA6,
516 .port_ops = &piix_sata_ops,
517 },
518
519 [tolapai_sata] =
520 {
521 .flags = PIIX_SATA_FLAGS,
522 .pio_mask = 0x1f, /* pio0-4 */
523 .mwdma_mask = 0x07, /* mwdma0-2 */
524 .udma_mask = ATA_UDMA6,
525 .port_ops = &piix_sata_ops,
526 },
527
528 [ich8m_apple_sata] =
529 {
530 .flags = PIIX_SATA_FLAGS,
531 .pio_mask = 0x1f, /* pio0-4 */
532 .mwdma_mask = 0x07, /* mwdma0-2 */
533 .udma_mask = ATA_UDMA6,
534 .port_ops = &piix_sata_ops,
535 },
536
537 [piix_pata_vmw] =
538 {
539 .flags = PIIX_PATA_FLAGS,
540 .pio_mask = 0x1f, /* pio0-4 */
541 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
542 .udma_mask = ATA_UDMA_MASK_40C,
543 .port_ops = &piix_vmw_ops,
544 },
545
546 };
547
548 static struct pci_bits piix_enable_bits[] = {
549 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
550 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
551 };
552
553 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
554 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
555 MODULE_LICENSE("GPL");
556 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
557 MODULE_VERSION(DRV_VERSION);
558
559 struct ich_laptop {
560 u16 device;
561 u16 subvendor;
562 u16 subdevice;
563 };
564
565 /*
566 * List of laptops that use short cables rather than 80 wire
567 */
568
569 static const struct ich_laptop ich_laptop[] = {
570 /* devid, subvendor, subdev */
571 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
572 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
573 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
574 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
575 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
576 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
577 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
578 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
579 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
580 /* end marker */
581 { 0, }
582 };
583
584 /**
585 * ich_pata_cable_detect - Probe host controller cable detect info
586 * @ap: Port for which cable detect info is desired
587 *
588 * Read 80c cable indicator from ATA PCI device's PCI config
589 * register. This register is normally set by firmware (BIOS).
590 *
591 * LOCKING:
592 * None (inherited from caller).
593 */
594
595 static int ich_pata_cable_detect(struct ata_port *ap)
596 {
597 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
598 const struct ich_laptop *lap = &ich_laptop[0];
599 u8 tmp, mask;
600
601 /* Check for specials - Acer Aspire 5602WLMi */
602 while (lap->device) {
603 if (lap->device == pdev->device &&
604 lap->subvendor == pdev->subsystem_vendor &&
605 lap->subdevice == pdev->subsystem_device)
606 return ATA_CBL_PATA40_SHORT;
607
608 lap++;
609 }
610
611 /* check BIOS cable detect results */
612 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
613 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
614 if ((tmp & mask) == 0)
615 return ATA_CBL_PATA40;
616 return ATA_CBL_PATA80;
617 }
618
619 /**
620 * piix_pata_prereset - prereset for PATA host controller
621 * @link: Target link
622 * @deadline: deadline jiffies for the operation
623 *
624 * LOCKING:
625 * None (inherited from caller).
626 */
627 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
628 {
629 struct ata_port *ap = link->ap;
630 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
631
632 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
633 return -ENOENT;
634 return ata_sff_prereset(link, deadline);
635 }
636
637 /**
638 * piix_set_piomode - Initialize host controller PATA PIO timings
639 * @ap: Port whose timings we are configuring
640 * @adev: um
641 *
642 * Set PIO mode for device, in host controller PCI config space.
643 *
644 * LOCKING:
645 * None (inherited from caller).
646 */
647
648 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
649 {
650 unsigned int pio = adev->pio_mode - XFER_PIO_0;
651 struct pci_dev *dev = to_pci_dev(ap->host->dev);
652 unsigned int is_slave = (adev->devno != 0);
653 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
654 unsigned int slave_port = 0x44;
655 u16 master_data;
656 u8 slave_data;
657 u8 udma_enable;
658 int control = 0;
659
660 /*
661 * See Intel Document 298600-004 for the timing programing rules
662 * for ICH controllers.
663 */
664
665 static const /* ISP RTC */
666 u8 timings[][2] = { { 0, 0 },
667 { 0, 0 },
668 { 1, 0 },
669 { 2, 1 },
670 { 2, 3 }, };
671
672 if (pio >= 2)
673 control |= 1; /* TIME1 enable */
674 if (ata_pio_need_iordy(adev))
675 control |= 2; /* IE enable */
676
677 /* Intel specifies that the PPE functionality is for disk only */
678 if (adev->class == ATA_DEV_ATA)
679 control |= 4; /* PPE enable */
680
681 /* PIO configuration clears DTE unconditionally. It will be
682 * programmed in set_dmamode which is guaranteed to be called
683 * after set_piomode if any DMA mode is available.
684 */
685 pci_read_config_word(dev, master_port, &master_data);
686 if (is_slave) {
687 /* clear TIME1|IE1|PPE1|DTE1 */
688 master_data &= 0xff0f;
689 /* Enable SITRE (separate slave timing register) */
690 master_data |= 0x4000;
691 /* enable PPE1, IE1 and TIME1 as needed */
692 master_data |= (control << 4);
693 pci_read_config_byte(dev, slave_port, &slave_data);
694 slave_data &= (ap->port_no ? 0x0f : 0xf0);
695 /* Load the timing nibble for this slave */
696 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
697 << (ap->port_no ? 4 : 0);
698 } else {
699 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
700 master_data &= 0xccf0;
701 /* Enable PPE, IE and TIME as appropriate */
702 master_data |= control;
703 /* load ISP and RCT */
704 master_data |=
705 (timings[pio][0] << 12) |
706 (timings[pio][1] << 8);
707 }
708 pci_write_config_word(dev, master_port, master_data);
709 if (is_slave)
710 pci_write_config_byte(dev, slave_port, slave_data);
711
712 /* Ensure the UDMA bit is off - it will be turned back on if
713 UDMA is selected */
714
715 if (ap->udma_mask) {
716 pci_read_config_byte(dev, 0x48, &udma_enable);
717 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
718 pci_write_config_byte(dev, 0x48, udma_enable);
719 }
720 }
721
722 /**
723 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
724 * @ap: Port whose timings we are configuring
725 * @adev: Drive in question
726 * @udma: udma mode, 0 - 6
727 * @isich: set if the chip is an ICH device
728 *
729 * Set UDMA mode for device, in host controller PCI config space.
730 *
731 * LOCKING:
732 * None (inherited from caller).
733 */
734
735 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
736 {
737 struct pci_dev *dev = to_pci_dev(ap->host->dev);
738 u8 master_port = ap->port_no ? 0x42 : 0x40;
739 u16 master_data;
740 u8 speed = adev->dma_mode;
741 int devid = adev->devno + 2 * ap->port_no;
742 u8 udma_enable = 0;
743
744 static const /* ISP RTC */
745 u8 timings[][2] = { { 0, 0 },
746 { 0, 0 },
747 { 1, 0 },
748 { 2, 1 },
749 { 2, 3 }, };
750
751 pci_read_config_word(dev, master_port, &master_data);
752 if (ap->udma_mask)
753 pci_read_config_byte(dev, 0x48, &udma_enable);
754
755 if (speed >= XFER_UDMA_0) {
756 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
757 u16 udma_timing;
758 u16 ideconf;
759 int u_clock, u_speed;
760
761 /*
762 * UDMA is handled by a combination of clock switching and
763 * selection of dividers
764 *
765 * Handy rule: Odd modes are UDMATIMx 01, even are 02
766 * except UDMA0 which is 00
767 */
768 u_speed = min(2 - (udma & 1), udma);
769 if (udma == 5)
770 u_clock = 0x1000; /* 100Mhz */
771 else if (udma > 2)
772 u_clock = 1; /* 66Mhz */
773 else
774 u_clock = 0; /* 33Mhz */
775
776 udma_enable |= (1 << devid);
777
778 /* Load the CT/RP selection */
779 pci_read_config_word(dev, 0x4A, &udma_timing);
780 udma_timing &= ~(3 << (4 * devid));
781 udma_timing |= u_speed << (4 * devid);
782 pci_write_config_word(dev, 0x4A, udma_timing);
783
784 if (isich) {
785 /* Select a 33/66/100Mhz clock */
786 pci_read_config_word(dev, 0x54, &ideconf);
787 ideconf &= ~(0x1001 << devid);
788 ideconf |= u_clock << devid;
789 /* For ICH or later we should set bit 10 for better
790 performance (WR_PingPong_En) */
791 pci_write_config_word(dev, 0x54, ideconf);
792 }
793 } else {
794 /*
795 * MWDMA is driven by the PIO timings. We must also enable
796 * IORDY unconditionally along with TIME1. PPE has already
797 * been set when the PIO timing was set.
798 */
799 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
800 unsigned int control;
801 u8 slave_data;
802 const unsigned int needed_pio[3] = {
803 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
804 };
805 int pio = needed_pio[mwdma] - XFER_PIO_0;
806
807 control = 3; /* IORDY|TIME1 */
808
809 /* If the drive MWDMA is faster than it can do PIO then
810 we must force PIO into PIO0 */
811
812 if (adev->pio_mode < needed_pio[mwdma])
813 /* Enable DMA timing only */
814 control |= 8; /* PIO cycles in PIO0 */
815
816 if (adev->devno) { /* Slave */
817 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
818 master_data |= control << 4;
819 pci_read_config_byte(dev, 0x44, &slave_data);
820 slave_data &= (ap->port_no ? 0x0f : 0xf0);
821 /* Load the matching timing */
822 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
823 pci_write_config_byte(dev, 0x44, slave_data);
824 } else { /* Master */
825 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
826 and master timing bits */
827 master_data |= control;
828 master_data |=
829 (timings[pio][0] << 12) |
830 (timings[pio][1] << 8);
831 }
832
833 if (ap->udma_mask) {
834 udma_enable &= ~(1 << devid);
835 pci_write_config_word(dev, master_port, master_data);
836 }
837 }
838 /* Don't scribble on 0x48 if the controller does not support UDMA */
839 if (ap->udma_mask)
840 pci_write_config_byte(dev, 0x48, udma_enable);
841 }
842
843 /**
844 * piix_set_dmamode - Initialize host controller PATA DMA timings
845 * @ap: Port whose timings we are configuring
846 * @adev: um
847 *
848 * Set MW/UDMA mode for device, in host controller PCI config space.
849 *
850 * LOCKING:
851 * None (inherited from caller).
852 */
853
854 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
855 {
856 do_pata_set_dmamode(ap, adev, 0);
857 }
858
859 /**
860 * ich_set_dmamode - Initialize host controller PATA DMA timings
861 * @ap: Port whose timings we are configuring
862 * @adev: um
863 *
864 * Set MW/UDMA mode for device, in host controller PCI config space.
865 *
866 * LOCKING:
867 * None (inherited from caller).
868 */
869
870 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
871 {
872 do_pata_set_dmamode(ap, adev, 1);
873 }
874
875 /*
876 * Serial ATA Index/Data Pair Superset Registers access
877 *
878 * Beginning from ICH8, there's a sane way to access SCRs using index
879 * and data register pair located at BAR5. This creates an
880 * interesting problem of mapping two SCRs to one port.
881 *
882 * Although they have separate SCRs, the master and slave aren't
883 * independent enough to be treated as separate links - e.g. softreset
884 * resets both. Also, there's no protocol defined for hard resetting
885 * singled device sharing the virtual port (no defined way to acquire
886 * device signature). This is worked around by merging the SCR values
887 * into one sensible value and requesting follow-up SRST after
888 * hardreset.
889 *
890 * SCR merging is perfomed in nibbles which is the unit contents in
891 * SCRs are organized. If two values are equal, the value is used.
892 * When they differ, merge table which lists precedence of possible
893 * values is consulted and the first match or the last entry when
894 * nothing matches is used. When there's no merge table for the
895 * specific nibble, value from the first port is used.
896 */
897 static const int piix_sidx_map[] = {
898 [SCR_STATUS] = 0,
899 [SCR_ERROR] = 2,
900 [SCR_CONTROL] = 1,
901 };
902
903 static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg)
904 {
905 struct ata_port *ap = dev->link->ap;
906 struct piix_host_priv *hpriv = ap->host->private_data;
907
908 iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg],
909 hpriv->sidpr + PIIX_SIDPR_IDX);
910 }
911
912 static int piix_sidpr_read(struct ata_device *dev, unsigned int reg)
913 {
914 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
915
916 piix_sidpr_sel(dev, reg);
917 return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
918 }
919
920 static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val)
921 {
922 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
923
924 piix_sidpr_sel(dev, reg);
925 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
926 }
927
928 static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl)
929 {
930 u32 val = 0;
931 int i, mi;
932
933 for (i = 0, mi = 0; i < 32 / 4; i++) {
934 u8 c0 = (val0 >> (i * 4)) & 0xf;
935 u8 c1 = (val1 >> (i * 4)) & 0xf;
936 u8 merged = c0;
937 const int *cur;
938
939 /* if no merge preference, assume the first value */
940 cur = merge_tbl[mi];
941 if (!cur)
942 goto done;
943 mi++;
944
945 /* if two values equal, use it */
946 if (c0 == c1)
947 goto done;
948
949 /* choose the first match or the last from the merge table */
950 while (*cur != -1) {
951 if (c0 == *cur || c1 == *cur)
952 break;
953 cur++;
954 }
955 if (*cur == -1)
956 cur--;
957 merged = *cur;
958 done:
959 val |= merged << (i * 4);
960 }
961
962 return val;
963 }
964
965 static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val)
966 {
967 const int * const sstatus_merge_tbl[] = {
968 /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 },
969 /* SPD */ (const int []){ 2, 1, 0, -1 },
970 /* IPM */ (const int []){ 6, 2, 1, 0, -1 },
971 NULL,
972 };
973 const int * const scontrol_merge_tbl[] = {
974 /* DET */ (const int []){ 1, 0, 4, 0, -1 },
975 /* SPD */ (const int []){ 0, 2, 1, 0, -1 },
976 /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 },
977 NULL,
978 };
979 u32 v0, v1;
980
981 if (reg >= ARRAY_SIZE(piix_sidx_map))
982 return -EINVAL;
983
984 if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) {
985 *val = piix_sidpr_read(&ap->link.device[0], reg);
986 return 0;
987 }
988
989 v0 = piix_sidpr_read(&ap->link.device[0], reg);
990 v1 = piix_sidpr_read(&ap->link.device[1], reg);
991
992 switch (reg) {
993 case SCR_STATUS:
994 *val = piix_merge_scr(v0, v1, sstatus_merge_tbl);
995 break;
996 case SCR_ERROR:
997 *val = v0 | v1;
998 break;
999 case SCR_CONTROL:
1000 *val = piix_merge_scr(v0, v1, scontrol_merge_tbl);
1001 break;
1002 }
1003
1004 return 0;
1005 }
1006
1007 static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val)
1008 {
1009 if (reg >= ARRAY_SIZE(piix_sidx_map))
1010 return -EINVAL;
1011
1012 piix_sidpr_write(&ap->link.device[0], reg, val);
1013
1014 if (ap->flags & ATA_FLAG_SLAVE_POSS)
1015 piix_sidpr_write(&ap->link.device[1], reg, val);
1016
1017 return 0;
1018 }
1019
1020 #ifdef CONFIG_PM
1021 static int piix_broken_suspend(void)
1022 {
1023 static const struct dmi_system_id sysids[] = {
1024 {
1025 .ident = "TECRA M3",
1026 .matches = {
1027 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1028 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1029 },
1030 },
1031 {
1032 .ident = "TECRA M3",
1033 .matches = {
1034 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1035 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1036 },
1037 },
1038 {
1039 .ident = "TECRA M4",
1040 .matches = {
1041 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1042 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1043 },
1044 },
1045 {
1046 .ident = "TECRA M4",
1047 .matches = {
1048 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1049 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1050 },
1051 },
1052 {
1053 .ident = "TECRA M5",
1054 .matches = {
1055 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1056 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1057 },
1058 },
1059 {
1060 .ident = "TECRA M6",
1061 .matches = {
1062 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1063 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1064 },
1065 },
1066 {
1067 .ident = "TECRA M7",
1068 .matches = {
1069 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1070 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1071 },
1072 },
1073 {
1074 .ident = "TECRA A8",
1075 .matches = {
1076 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1077 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1078 },
1079 },
1080 {
1081 .ident = "Satellite R20",
1082 .matches = {
1083 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1084 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1085 },
1086 },
1087 {
1088 .ident = "Satellite R25",
1089 .matches = {
1090 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1091 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1092 },
1093 },
1094 {
1095 .ident = "Satellite U200",
1096 .matches = {
1097 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1098 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1099 },
1100 },
1101 {
1102 .ident = "Satellite U200",
1103 .matches = {
1104 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1105 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1106 },
1107 },
1108 {
1109 .ident = "Satellite Pro U200",
1110 .matches = {
1111 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1112 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1113 },
1114 },
1115 {
1116 .ident = "Satellite U205",
1117 .matches = {
1118 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1119 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1120 },
1121 },
1122 {
1123 .ident = "SATELLITE U205",
1124 .matches = {
1125 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1126 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1127 },
1128 },
1129 {
1130 .ident = "Portege M500",
1131 .matches = {
1132 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1133 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1134 },
1135 },
1136
1137 { } /* terminate list */
1138 };
1139 static const char *oemstrs[] = {
1140 "Tecra M3,",
1141 };
1142 int i;
1143
1144 if (dmi_check_system(sysids))
1145 return 1;
1146
1147 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1148 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1149 return 1;
1150
1151 return 0;
1152 }
1153
1154 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1155 {
1156 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1157 unsigned long flags;
1158 int rc = 0;
1159
1160 rc = ata_host_suspend(host, mesg);
1161 if (rc)
1162 return rc;
1163
1164 /* Some braindamaged ACPI suspend implementations expect the
1165 * controller to be awake on entry; otherwise, it burns cpu
1166 * cycles and power trying to do something to the sleeping
1167 * beauty.
1168 */
1169 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1170 pci_save_state(pdev);
1171
1172 /* mark its power state as "unknown", since we don't
1173 * know if e.g. the BIOS will change its device state
1174 * when we suspend.
1175 */
1176 if (pdev->current_state == PCI_D0)
1177 pdev->current_state = PCI_UNKNOWN;
1178
1179 /* tell resume that it's waking up from broken suspend */
1180 spin_lock_irqsave(&host->lock, flags);
1181 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1182 spin_unlock_irqrestore(&host->lock, flags);
1183 } else
1184 ata_pci_device_do_suspend(pdev, mesg);
1185
1186 return 0;
1187 }
1188
1189 static int piix_pci_device_resume(struct pci_dev *pdev)
1190 {
1191 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1192 unsigned long flags;
1193 int rc;
1194
1195 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1196 spin_lock_irqsave(&host->lock, flags);
1197 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1198 spin_unlock_irqrestore(&host->lock, flags);
1199
1200 pci_set_power_state(pdev, PCI_D0);
1201 pci_restore_state(pdev);
1202
1203 /* PCI device wasn't disabled during suspend. Use
1204 * pci_reenable_device() to avoid affecting the enable
1205 * count.
1206 */
1207 rc = pci_reenable_device(pdev);
1208 if (rc)
1209 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1210 "device after resume (%d)\n", rc);
1211 } else
1212 rc = ata_pci_device_do_resume(pdev);
1213
1214 if (rc == 0)
1215 ata_host_resume(host);
1216
1217 return rc;
1218 }
1219 #endif
1220
1221 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1222 {
1223 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1224 }
1225
1226 #define AHCI_PCI_BAR 5
1227 #define AHCI_GLOBAL_CTL 0x04
1228 #define AHCI_ENABLE (1 << 31)
1229 static int piix_disable_ahci(struct pci_dev *pdev)
1230 {
1231 void __iomem *mmio;
1232 u32 tmp;
1233 int rc = 0;
1234
1235 /* BUG: pci_enable_device has not yet been called. This
1236 * works because this device is usually set up by BIOS.
1237 */
1238
1239 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1240 !pci_resource_len(pdev, AHCI_PCI_BAR))
1241 return 0;
1242
1243 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1244 if (!mmio)
1245 return -ENOMEM;
1246
1247 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1248 if (tmp & AHCI_ENABLE) {
1249 tmp &= ~AHCI_ENABLE;
1250 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1251
1252 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1253 if (tmp & AHCI_ENABLE)
1254 rc = -EIO;
1255 }
1256
1257 pci_iounmap(pdev, mmio);
1258 return rc;
1259 }
1260
1261 /**
1262 * piix_check_450nx_errata - Check for problem 450NX setup
1263 * @ata_dev: the PCI device to check
1264 *
1265 * Check for the present of 450NX errata #19 and errata #25. If
1266 * they are found return an error code so we can turn off DMA
1267 */
1268
1269 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1270 {
1271 struct pci_dev *pdev = NULL;
1272 u16 cfg;
1273 int no_piix_dma = 0;
1274
1275 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1276 /* Look for 450NX PXB. Check for problem configurations
1277 A PCI quirk checks bit 6 already */
1278 pci_read_config_word(pdev, 0x41, &cfg);
1279 /* Only on the original revision: IDE DMA can hang */
1280 if (pdev->revision == 0x00)
1281 no_piix_dma = 1;
1282 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1283 else if (cfg & (1<<14) && pdev->revision < 5)
1284 no_piix_dma = 2;
1285 }
1286 if (no_piix_dma)
1287 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1288 if (no_piix_dma == 2)
1289 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1290 return no_piix_dma;
1291 }
1292
1293 static void __devinit piix_init_pcs(struct ata_host *host,
1294 const struct piix_map_db *map_db)
1295 {
1296 struct pci_dev *pdev = to_pci_dev(host->dev);
1297 u16 pcs, new_pcs;
1298
1299 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1300
1301 new_pcs = pcs | map_db->port_enable;
1302
1303 if (new_pcs != pcs) {
1304 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1305 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1306 msleep(150);
1307 }
1308 }
1309
1310 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1311 struct ata_port_info *pinfo,
1312 const struct piix_map_db *map_db)
1313 {
1314 const int *map;
1315 int i, invalid_map = 0;
1316 u8 map_value;
1317
1318 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1319
1320 map = map_db->map[map_value & map_db->mask];
1321
1322 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1323 for (i = 0; i < 4; i++) {
1324 switch (map[i]) {
1325 case RV:
1326 invalid_map = 1;
1327 printk(" XX");
1328 break;
1329
1330 case NA:
1331 printk(" --");
1332 break;
1333
1334 case IDE:
1335 WARN_ON((i & 1) || map[i + 1] != IDE);
1336 pinfo[i / 2] = piix_port_info[ich_pata_100];
1337 i++;
1338 printk(" IDE IDE");
1339 break;
1340
1341 default:
1342 printk(" P%d", map[i]);
1343 if (i & 1)
1344 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1345 break;
1346 }
1347 }
1348 printk(" ]\n");
1349
1350 if (invalid_map)
1351 dev_printk(KERN_ERR, &pdev->dev,
1352 "invalid MAP value %u\n", map_value);
1353
1354 return map;
1355 }
1356
1357 static void __devinit piix_init_sidpr(struct ata_host *host)
1358 {
1359 struct pci_dev *pdev = to_pci_dev(host->dev);
1360 struct piix_host_priv *hpriv = host->private_data;
1361 struct ata_device *dev0 = &host->ports[0]->link.device[0];
1362 u32 scontrol;
1363 int i;
1364
1365 /* check for availability */
1366 for (i = 0; i < 4; i++)
1367 if (hpriv->map[i] == IDE)
1368 return;
1369
1370 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1371 return;
1372
1373 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1374 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1375 return;
1376
1377 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1378 return;
1379
1380 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1381
1382 /* SCR access via SIDPR doesn't work on some configurations.
1383 * Give it a test drive by inhibiting power save modes which
1384 * we'll do anyway.
1385 */
1386 scontrol = piix_sidpr_read(dev0, SCR_CONTROL);
1387
1388 /* if IPM is already 3, SCR access is probably working. Don't
1389 * un-inhibit power save modes as BIOS might have inhibited
1390 * them for a reason.
1391 */
1392 if ((scontrol & 0xf00) != 0x300) {
1393 scontrol |= 0x300;
1394 piix_sidpr_write(dev0, SCR_CONTROL, scontrol);
1395 scontrol = piix_sidpr_read(dev0, SCR_CONTROL);
1396
1397 if ((scontrol & 0xf00) != 0x300) {
1398 dev_printk(KERN_INFO, host->dev, "SCR access via "
1399 "SIDPR is available but doesn't work\n");
1400 return;
1401 }
1402 }
1403
1404 host->ports[0]->ops = &piix_sidpr_sata_ops;
1405 host->ports[1]->ops = &piix_sidpr_sata_ops;
1406 }
1407
1408 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1409 {
1410 static const struct dmi_system_id sysids[] = {
1411 {
1412 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1413 * isn't used to boot the system which
1414 * disables the channel.
1415 */
1416 .ident = "M570U",
1417 .matches = {
1418 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1419 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1420 },
1421 },
1422
1423 { } /* terminate list */
1424 };
1425 u32 iocfg;
1426
1427 if (!dmi_check_system(sysids))
1428 return;
1429
1430 /* The datasheet says that bit 18 is NOOP but certain systems
1431 * seem to use it to disable a channel. Clear the bit on the
1432 * affected systems.
1433 */
1434 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1435 if (iocfg & (1 << 18)) {
1436 dev_printk(KERN_INFO, &pdev->dev,
1437 "applying IOCFG bit18 quirk\n");
1438 iocfg &= ~(1 << 18);
1439 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1440 }
1441 }
1442
1443 /**
1444 * piix_init_one - Register PIIX ATA PCI device with kernel services
1445 * @pdev: PCI device to register
1446 * @ent: Entry in piix_pci_tbl matching with @pdev
1447 *
1448 * Called from kernel PCI layer. We probe for combined mode (sigh),
1449 * and then hand over control to libata, for it to do the rest.
1450 *
1451 * LOCKING:
1452 * Inherited from PCI layer (may sleep).
1453 *
1454 * RETURNS:
1455 * Zero on success, or -ERRNO value.
1456 */
1457
1458 static int __devinit piix_init_one(struct pci_dev *pdev,
1459 const struct pci_device_id *ent)
1460 {
1461 static int printed_version;
1462 struct device *dev = &pdev->dev;
1463 struct ata_port_info port_info[2];
1464 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1465 unsigned long port_flags;
1466 struct ata_host *host;
1467 struct piix_host_priv *hpriv;
1468 int rc;
1469
1470 if (!printed_version++)
1471 dev_printk(KERN_DEBUG, &pdev->dev,
1472 "version " DRV_VERSION "\n");
1473
1474 /* no hotplugging support (FIXME) */
1475 if (!in_module_init)
1476 return -ENODEV;
1477
1478 port_info[0] = piix_port_info[ent->driver_data];
1479 port_info[1] = piix_port_info[ent->driver_data];
1480
1481 port_flags = port_info[0].flags;
1482
1483 /* enable device and prepare host */
1484 rc = pcim_enable_device(pdev);
1485 if (rc)
1486 return rc;
1487
1488 /* ICH6R may be driven by either ata_piix or ahci driver
1489 * regardless of BIOS configuration. Make sure AHCI mode is
1490 * off.
1491 */
1492 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1493 int rc = piix_disable_ahci(pdev);
1494 if (rc)
1495 return rc;
1496 }
1497
1498 /* SATA map init can change port_info, do it before prepping host */
1499 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1500 if (!hpriv)
1501 return -ENOMEM;
1502
1503 if (port_flags & ATA_FLAG_SATA)
1504 hpriv->map = piix_init_sata_map(pdev, port_info,
1505 piix_map_db_table[ent->driver_data]);
1506
1507 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
1508 if (rc)
1509 return rc;
1510 host->private_data = hpriv;
1511
1512 /* initialize controller */
1513 if (port_flags & ATA_FLAG_SATA) {
1514 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1515 piix_init_sidpr(host);
1516 }
1517
1518 /* apply IOCFG bit18 quirk */
1519 piix_iocfg_bit18_quirk(pdev);
1520
1521 /* On ICH5, some BIOSen disable the interrupt using the
1522 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1523 * On ICH6, this bit has the same effect, but only when
1524 * MSI is disabled (and it is disabled, as we don't use
1525 * message-signalled interrupts currently).
1526 */
1527 if (port_flags & PIIX_FLAG_CHECKINTR)
1528 pci_intx(pdev, 1);
1529
1530 if (piix_check_450nx_errata(pdev)) {
1531 /* This writes into the master table but it does not
1532 really matter for this errata as we will apply it to
1533 all the PIIX devices on the board */
1534 host->ports[0]->mwdma_mask = 0;
1535 host->ports[0]->udma_mask = 0;
1536 host->ports[1]->mwdma_mask = 0;
1537 host->ports[1]->udma_mask = 0;
1538 }
1539
1540 pci_set_master(pdev);
1541 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht);
1542 }
1543
1544 static int __init piix_init(void)
1545 {
1546 int rc;
1547
1548 DPRINTK("pci_register_driver\n");
1549 rc = pci_register_driver(&piix_pci_driver);
1550 if (rc)
1551 return rc;
1552
1553 in_module_init = 0;
1554
1555 DPRINTK("done\n");
1556 return 0;
1557 }
1558
1559 static void __exit piix_exit(void)
1560 {
1561 pci_unregister_driver(&piix_pci_driver);
1562 }
1563
1564 module_init(piix_init);
1565 module_exit(piix_exit);
Support for the Chinese Samsung S3C2440 based development boards