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[ARM] OMAP3: move USBHOST SAR handling from clock framework to powerdomain layer
[linux-2.6/mini2440.git] / arch / arm / mach-omap2 / clock34xx.c
blob439a66918d38627231ad1873128a01b3b81f74b0
1 /*
2 * OMAP3-specific clock framework functions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17 #undef DEBUG
18
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
26 #include <linux/io.h>
27 #include <linux/limits.h>
28 #include <linux/bitops.h>
29
30 #include <mach/clock.h>
31 #include <mach/sram.h>
32 #include <asm/div64.h>
33 #include <asm/clkdev.h>
34
35 #include "memory.h"
36 #include "clock.h"
37 #include "prm.h"
38 #include "prm-regbits-34xx.h"
39 #include "cm.h"
40 #include "cm-regbits-34xx.h"
41
42 static const struct clkops clkops_noncore_dpll_ops;
43
44 #include "clock34xx.h"
45
46 struct omap_clk {
47 u32 cpu;
48 struct clk_lookup lk;
49 };
50
51 #define CLK(dev, con, ck, cp) \
52 { \
53 .cpu = cp, \
54 .lk = { \
55 .dev_id = dev, \
56 .con_id = con, \
57 .clk = ck, \
58 }, \
59 }
60
61 #define CK_343X (1 << 0)
62 #define CK_3430ES1 (1 << 1)
63 #define CK_3430ES2 (1 << 2)
64
65 static struct omap_clk omap34xx_clks[] = {
66 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
67 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
68 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
69 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
70 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
71 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
72 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
73 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
74 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
75 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
76 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
77 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
78 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
79 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
80 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
81 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
82 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
83 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
84 CLK(NULL, "core_ck", &core_ck, CK_343X),
85 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
86 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
87 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
88 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
89 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
90 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
91 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
92 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
93 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
94 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
95 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
96 CLK(NULL, "virt_omap_54m_fck", &virt_omap_54m_fck, CK_343X),
97 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
98 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
99 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
100 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
101 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
102 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
103 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
104 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
105 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
106 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
107 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
108 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
109 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
110 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
111 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
112 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
113 CLK(NULL, "omap_120m_fck", &omap_120m_fck, CK_3430ES2),
114 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
115 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
116 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
117 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
118 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
119 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
120 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
121 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
122 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
123 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
124 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
125 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
126 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
127 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
128 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
129 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
130 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
131 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
132 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
133 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
134 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
135 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
136 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
137 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
138 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
139 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
140 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
141 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
142 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
143 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
144 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
145 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
146 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
147 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
148 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
149 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
150 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
151 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
152 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
153 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
154 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
155 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
156 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
157 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
158 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
159 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
160 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
161 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
162 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
163 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
164 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
165 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
166 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
167 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
168 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
169 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
170 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
171 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
172 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
173 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
174 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
175 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
176 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
177 CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
178 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
179 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
180 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
181 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
182 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
183 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
184 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
185 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
186 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
187 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
188 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
189 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
190 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
191 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
192 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
193 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
194 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
195 CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
196 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
197 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
198 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
199 CLK("omap_rng", "ick", &rng_ick, CK_343X),
200 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
201 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
202 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
203 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
204 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
205 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
206 CLK(NULL, "dss_ick", &dss_ick, CK_343X),
207 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
208 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
209 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
210 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
211 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
212 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
213 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
214 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
215 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
216 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
217 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
218 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
219 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
220 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
221 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
222 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
223 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
224 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
225 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
226 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
227 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
228 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
229 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
230 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
231 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
232 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
233 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
234 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
235 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
236 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
237 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
238 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
239 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
240 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
241 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
242 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
243 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
244 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
245 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
246 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
247 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
248 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
249 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
250 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
251 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
252 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
253 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
254 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
255 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
256 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
257 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
258 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
259 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
260 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
261 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
262 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
263 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
264 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
265 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
266 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
267 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
268 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
269 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
270 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
271 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
272 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
273 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
274 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
275 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
276 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
277 };
278
279 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
280 #define DPLL_AUTOIDLE_DISABLE 0x0
281 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
282
283 #define MAX_DPLL_WAIT_TRIES 1000000
284
285 /**
286 * omap3_dpll_recalc - recalculate DPLL rate
287 * @clk: DPLL struct clk
288 *
289 * Recalculate and propagate the DPLL rate.
290 */
291 static void omap3_dpll_recalc(struct clk *clk)
292 {
293 clk->rate = omap2_get_dpll_rate(clk);
294 }
295
296 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
297 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
298 {
299 const struct dpll_data *dd;
300 u32 v;
301
302 dd = clk->dpll_data;
303
304 v = __raw_readl(dd->control_reg);
305 v &= ~dd->enable_mask;
306 v |= clken_bits << __ffs(dd->enable_mask);
307 __raw_writel(v, dd->control_reg);
308 }
309
310 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
311 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
312 {
313 const struct dpll_data *dd;
314 int i = 0;
315 int ret = -EINVAL;
316 u32 idlest_mask;
317
318 dd = clk->dpll_data;
319
320 state <<= dd->idlest_bit;
321 idlest_mask = 1 << dd->idlest_bit;
322
323 while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
324 i < MAX_DPLL_WAIT_TRIES) {
325 i++;
326 udelay(1);
327 }
328
329 if (i == MAX_DPLL_WAIT_TRIES) {
330 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
331 clk->name, (state) ? "locked" : "bypassed");
332 } else {
333 pr_debug("clock: %s transition to '%s' in %d loops\n",
334 clk->name, (state) ? "locked" : "bypassed", i);
335
336 ret = 0;
337 }
338
339 return ret;
340 }
341
342 /* From 3430 TRM ES2 4.7.6.2 */
343 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
344 {
345 unsigned long fint;
346 u16 f = 0;
347
348 fint = clk->parent->rate / (n + 1);
349
350 pr_debug("clock: fint is %lu\n", fint);
351
352 if (fint >= 750000 && fint <= 1000000)
353 f = 0x3;
354 else if (fint > 1000000 && fint <= 1250000)
355 f = 0x4;
356 else if (fint > 1250000 && fint <= 1500000)
357 f = 0x5;
358 else if (fint > 1500000 && fint <= 1750000)
359 f = 0x6;
360 else if (fint > 1750000 && fint <= 2100000)
361 f = 0x7;
362 else if (fint > 7500000 && fint <= 10000000)
363 f = 0xB;
364 else if (fint > 10000000 && fint <= 12500000)
365 f = 0xC;
366 else if (fint > 12500000 && fint <= 15000000)
367 f = 0xD;
368 else if (fint > 15000000 && fint <= 17500000)
369 f = 0xE;
370 else if (fint > 17500000 && fint <= 21000000)
371 f = 0xF;
372 else
373 pr_debug("clock: unknown freqsel setting for %d\n", n);
374
375 return f;
376 }
377
378 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
379
380 /*
381 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
382 * @clk: pointer to a DPLL struct clk
383 *
384 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
385 * readiness before returning. Will save and restore the DPLL's
386 * autoidle state across the enable, per the CDP code. If the DPLL
387 * locked successfully, return 0; if the DPLL did not lock in the time
388 * allotted, or DPLL3 was passed in, return -EINVAL.
389 */
390 static int _omap3_noncore_dpll_lock(struct clk *clk)
391 {
392 u8 ai;
393 int r;
394
395 if (clk == &dpll3_ck)
396 return -EINVAL;
397
398 pr_debug("clock: locking DPLL %s\n", clk->name);
399
400 ai = omap3_dpll_autoidle_read(clk);
401
402 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
403
404 if (ai) {
405 /*
406 * If no downstream clocks are enabled, CM_IDLEST bit
407 * may never become active, so don't wait for DPLL to lock.
408 */
409 r = 0;
410 omap3_dpll_allow_idle(clk);
411 } else {
412 r = _omap3_wait_dpll_status(clk, 1);
413 omap3_dpll_deny_idle(clk);
414 };
415
416 return r;
417 }
418
419 /*
420 * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
421 * @clk: pointer to a DPLL struct clk
422 *
423 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
424 * bypass mode, the DPLL's rate is set equal to its parent clock's
425 * rate. Waits for the DPLL to report readiness before returning.
426 * Will save and restore the DPLL's autoidle state across the enable,
427 * per the CDP code. If the DPLL entered bypass mode successfully,
428 * return 0; if the DPLL did not enter bypass in the time allotted, or
429 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
430 * return -EINVAL.
431 */
432 static int _omap3_noncore_dpll_bypass(struct clk *clk)
433 {
434 int r;
435 u8 ai;
436
437 if (clk == &dpll3_ck)
438 return -EINVAL;
439
440 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
441 return -EINVAL;
442
443 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
444 clk->name);
445
446 ai = omap3_dpll_autoidle_read(clk);
447
448 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
449
450 r = _omap3_wait_dpll_status(clk, 0);
451
452 if (ai)
453 omap3_dpll_allow_idle(clk);
454 else
455 omap3_dpll_deny_idle(clk);
456
457 return r;
458 }
459
460 /*
461 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
462 * @clk: pointer to a DPLL struct clk
463 *
464 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
465 * restore the DPLL's autoidle state across the stop, per the CDP
466 * code. If DPLL3 was passed in, or the DPLL does not support
467 * low-power stop, return -EINVAL; otherwise, return 0.
468 */
469 static int _omap3_noncore_dpll_stop(struct clk *clk)
470 {
471 u8 ai;
472
473 if (clk == &dpll3_ck)
474 return -EINVAL;
475
476 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
477 return -EINVAL;
478
479 pr_debug("clock: stopping DPLL %s\n", clk->name);
480
481 ai = omap3_dpll_autoidle_read(clk);
482
483 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
484
485 if (ai)
486 omap3_dpll_allow_idle(clk);
487 else
488 omap3_dpll_deny_idle(clk);
489
490 return 0;
491 }
492
493 /**
494 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
495 * @clk: pointer to a DPLL struct clk
496 *
497 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
498 * The choice of modes depends on the DPLL's programmed rate: if it is
499 * the same as the DPLL's parent clock, it will enter bypass;
500 * otherwise, it will enter lock. This code will wait for the DPLL to
501 * indicate readiness before returning, unless the DPLL takes too long
502 * to enter the target state. Intended to be used as the struct clk's
503 * enable function. If DPLL3 was passed in, or the DPLL does not
504 * support low-power stop, or if the DPLL took too long to enter
505 * bypass or lock, return -EINVAL; otherwise, return 0.
506 */
507 static int omap3_noncore_dpll_enable(struct clk *clk)
508 {
509 int r;
510
511 if (clk == &dpll3_ck)
512 return -EINVAL;
513
514 if (clk->parent->rate == omap2_get_dpll_rate(clk))
515 r = _omap3_noncore_dpll_bypass(clk);
516 else
517 r = _omap3_noncore_dpll_lock(clk);
518
519 return r;
520 }
521
522 /**
523 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
524 * @clk: pointer to a DPLL struct clk
525 *
526 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
527 * The choice of modes depends on the DPLL's programmed rate: if it is
528 * the same as the DPLL's parent clock, it will enter bypass;
529 * otherwise, it will enter lock. This code will wait for the DPLL to
530 * indicate readiness before returning, unless the DPLL takes too long
531 * to enter the target state. Intended to be used as the struct clk's
532 * enable function. If DPLL3 was passed in, or the DPLL does not
533 * support low-power stop, or if the DPLL took too long to enter
534 * bypass or lock, return -EINVAL; otherwise, return 0.
535 */
536 static void omap3_noncore_dpll_disable(struct clk *clk)
537 {
538 if (clk == &dpll3_ck)
539 return;
540
541 _omap3_noncore_dpll_stop(clk);
542 }
543
544
545 /* Non-CORE DPLL rate set code */
546
547 /*
548 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
549 * @clk: struct clk * of DPLL to set
550 * @m: DPLL multiplier to set
551 * @n: DPLL divider to set
552 * @freqsel: FREQSEL value to set
553 *
554 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
555 * lock.. Returns -EINVAL upon error, or 0 upon success.
556 */
557 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
558 {
559 struct dpll_data *dd = clk->dpll_data;
560 u32 v;
561
562 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
563 _omap3_noncore_dpll_bypass(clk);
564
565 v = __raw_readl(dd->mult_div1_reg);
566 v &= ~(dd->mult_mask | dd->div1_mask);
567
568 /* Set mult (M), div1 (N), freqsel */
569 v |= m << __ffs(dd->mult_mask);
570 v |= n << __ffs(dd->div1_mask);
571 v |= freqsel << __ffs(dd->freqsel_mask);
572
573 __raw_writel(v, dd->mult_div1_reg);
574
575 /* We let the clock framework set the other output dividers later */
576
577 /* REVISIT: Set ramp-up delay? */
578
579 _omap3_noncore_dpll_lock(clk);
580
581 return 0;
582 }
583
584 /**
585 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
586 * @clk: struct clk * of DPLL to set
587 * @rate: rounded target rate
588 *
589 * Program the DPLL with the rounded target rate. Returns -EINVAL upon
590 * error, or 0 upon success.
591 */
592 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
593 {
594 u16 freqsel;
595 struct dpll_data *dd;
596
597 if (!clk || !rate)
598 return -EINVAL;
599
600 dd = clk->dpll_data;
601 if (!dd)
602 return -EINVAL;
603
604 if (rate == omap2_get_dpll_rate(clk))
605 return 0;
606
607 if (dd->last_rounded_rate != rate)
608 omap2_dpll_round_rate(clk, rate);
609
610 if (dd->last_rounded_rate == 0)
611 return -EINVAL;
612
613 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
614 if (!freqsel)
615 WARN_ON(1);
616
617 omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n,
618 freqsel);
619
620 omap3_dpll_recalc(clk);
621
622 return 0;
623 }
624
625 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
626 {
627 /*
628 * According to the 12-5 CDP code from TI, "Limitation 2.5"
629 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
630 * on DPLL4.
631 */
632 if (omap_rev() == OMAP3430_REV_ES1_0) {
633 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
634 "silicon 'Limitation 2.5' on 3430ES1.\n");
635 return -EINVAL;
636 }
637 return omap3_noncore_dpll_set_rate(clk, rate);
638 }
639
640 static const struct clkops clkops_noncore_dpll_ops = {
641 .enable = &omap3_noncore_dpll_enable,
642 .disable = &omap3_noncore_dpll_disable,
643 };
644
645 /* DPLL autoidle read/set code */
646
647
648 /**
649 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
650 * @clk: struct clk * of the DPLL to read
651 *
652 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
653 * -EINVAL if passed a null pointer or if the struct clk does not
654 * appear to refer to a DPLL.
655 */
656 static u32 omap3_dpll_autoidle_read(struct clk *clk)
657 {
658 const struct dpll_data *dd;
659 u32 v;
660
661 if (!clk || !clk->dpll_data)
662 return -EINVAL;
663
664 dd = clk->dpll_data;
665
666 v = __raw_readl(dd->autoidle_reg);
667 v &= dd->autoidle_mask;
668 v >>= __ffs(dd->autoidle_mask);
669
670 return v;
671 }
672
673 /**
674 * omap3_dpll_allow_idle - enable DPLL autoidle bits
675 * @clk: struct clk * of the DPLL to operate on
676 *
677 * Enable DPLL automatic idle control. This automatic idle mode
678 * switching takes effect only when the DPLL is locked, at least on
679 * OMAP3430. The DPLL will enter low-power stop when its downstream
680 * clocks are gated. No return value.
681 */
682 static void omap3_dpll_allow_idle(struct clk *clk)
683 {
684 const struct dpll_data *dd;
685 u32 v;
686
687 if (!clk || !clk->dpll_data)
688 return;
689
690 dd = clk->dpll_data;
691
692 /*
693 * REVISIT: CORE DPLL can optionally enter low-power bypass
694 * by writing 0x5 instead of 0x1. Add some mechanism to
695 * optionally enter this mode.
696 */
697 v = __raw_readl(dd->autoidle_reg);
698 v &= ~dd->autoidle_mask;
699 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
700 __raw_writel(v, dd->autoidle_reg);
701 }
702
703 /**
704 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
705 * @clk: struct clk * of the DPLL to operate on
706 *
707 * Disable DPLL automatic idle control. No return value.
708 */
709 static void omap3_dpll_deny_idle(struct clk *clk)
710 {
711 const struct dpll_data *dd;
712 u32 v;
713
714 if (!clk || !clk->dpll_data)
715 return;
716
717 dd = clk->dpll_data;
718
719 v = __raw_readl(dd->autoidle_reg);
720 v &= ~dd->autoidle_mask;
721 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
722 __raw_writel(v, dd->autoidle_reg);
723 }
724
725 /* Clock control for DPLL outputs */
726
727 /**
728 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
729 * @clk: DPLL output struct clk
730 *
731 * Using parent clock DPLL data, look up DPLL state. If locked, set our
732 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
733 */
734 static void omap3_clkoutx2_recalc(struct clk *clk)
735 {
736 const struct dpll_data *dd;
737 u32 v;
738 struct clk *pclk;
739
740 /* Walk up the parents of clk, looking for a DPLL */
741 pclk = clk->parent;
742 while (pclk && !pclk->dpll_data)
743 pclk = pclk->parent;
744
745 /* clk does not have a DPLL as a parent? */
746 WARN_ON(!pclk);
747
748 dd = pclk->dpll_data;
749
750 WARN_ON(!dd->control_reg || !dd->enable_mask);
751
752 v = __raw_readl(dd->control_reg) & dd->enable_mask;
753 v >>= __ffs(dd->enable_mask);
754 if (v != DPLL_LOCKED)
755 clk->rate = clk->parent->rate;
756 else
757 clk->rate = clk->parent->rate * 2;
758 }
759
760 /* Common clock code */
761
762 /*
763 * As it is structured now, this will prevent an OMAP2/3 multiboot
764 * kernel from compiling. This will need further attention.
765 */
766 #if defined(CONFIG_ARCH_OMAP3)
767
768 static struct clk_functions omap2_clk_functions = {
769 .clk_enable = omap2_clk_enable,
770 .clk_disable = omap2_clk_disable,
771 .clk_round_rate = omap2_clk_round_rate,
772 .clk_set_rate = omap2_clk_set_rate,
773 .clk_set_parent = omap2_clk_set_parent,
774 .clk_disable_unused = omap2_clk_disable_unused,
775 };
776
777 /*
778 * Set clocks for bypass mode for reboot to work.
779 */
780 void omap2_clk_prepare_for_reboot(void)
781 {
782 /* REVISIT: Not ready for 343x */
783 #if 0
784 u32 rate;
785
786 if (vclk == NULL || sclk == NULL)
787 return;
788
789 rate = clk_get_rate(sclk);
790 clk_set_rate(vclk, rate);
791 #endif
792 }
793
794 /* REVISIT: Move this init stuff out into clock.c */
795
796 /*
797 * Switch the MPU rate if specified on cmdline.
798 * We cannot do this early until cmdline is parsed.
799 */
800 static int __init omap2_clk_arch_init(void)
801 {
802 if (!mpurate)
803 return -EINVAL;
804
805 /* REVISIT: not yet ready for 343x */
806 #if 0
807 if (omap2_select_table_rate(&virt_prcm_set, mpurate))
808 printk(KERN_ERR "Could not find matching MPU rate\n");
809 #endif
810
811 recalculate_root_clocks();
812
813 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
814 "%ld.%01ld/%ld/%ld MHz\n",
815 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
816 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
817
818 return 0;
819 }
820 arch_initcall(omap2_clk_arch_init);
821
822 int __init omap2_clk_init(void)
823 {
824 /* struct prcm_config *prcm; */
825 struct omap_clk *c;
826 /* u32 clkrate; */
827 u32 cpu_clkflg;
828
829 if (cpu_is_omap34xx()) {
830 cpu_mask = RATE_IN_343X;
831 cpu_clkflg = CK_343X;
832
833 /*
834 * Update this if there are further clock changes between ES2
835 * and production parts
836 */
837 if (omap_rev() == OMAP3430_REV_ES1_0) {
838 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
839 cpu_clkflg |= CK_3430ES1;
840 } else {
841 cpu_mask |= RATE_IN_3430ES2;
842 cpu_clkflg |= CK_3430ES2;
843 }
844 }
845
846 clk_init(&omap2_clk_functions);
847
848 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
849 if (c->cpu & cpu_clkflg) {
850 clkdev_add(&c->lk);
851 clk_register(c->lk.clk);
852 omap2_init_clk_clkdm(c->lk.clk);
853 }
854
855 /* REVISIT: Not yet ready for OMAP3 */
856 #if 0
857 /* Check the MPU rate set by bootloader */
858 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
859 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
860 if (!(prcm->flags & cpu_mask))
861 continue;
862 if (prcm->xtal_speed != sys_ck.rate)
863 continue;
864 if (prcm->dpll_speed <= clkrate)
865 break;
866 }
867 curr_prcm_set = prcm;
868 #endif
869
870 recalculate_root_clocks();
871
872 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
873 "%ld.%01ld/%ld/%ld MHz\n",
874 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
875 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
876
877 /*
878 * Only enable those clocks we will need, let the drivers
879 * enable other clocks as necessary
880 */
881 clk_enable_init_clocks();
882
883 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
884 /* REVISIT: not yet ready for 343x */
885 #if 0
886 vclk = clk_get(NULL, "virt_prcm_set");
887 sclk = clk_get(NULL, "sys_ck");
888 #endif
889 return 0;
890 }
891
892 #endif
Support for the Chinese Samsung S3C2440 based development boards