2 * MPC86XX pci setup code
4 * Recode: ZHANG WEI <wei.zhang@freescale.com>
5 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
7 * Copyright 2006 Freescale Semiconductor Inc.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #include <linux/types.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/serial.h>
21 #include <asm/system.h>
22 #include <asm/atomic.h>
25 #include <asm/pci-bridge.h>
26 #include <sysdev/fsl_soc.h>
27 #include <sysdev/fsl_pcie.h>
34 #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
36 #define DBG(fmt, args...)
39 struct pcie_outbound_window_regs
{
40 uint pexotar
; /* 0x.0 - PCI Express outbound translation address register */
41 uint pexotear
; /* 0x.4 - PCI Express outbound translation extended address register */
42 uint pexowbar
; /* 0x.8 - PCI Express outbound window base address register */
44 uint pexowar
; /* 0x.10 - PCI Express outbound window attributes register */
48 struct pcie_inbound_window_regs
{
49 uint pexitar
; /* 0x.0 - PCI Express inbound translation address register */
51 uint pexiwbar
; /* 0x.8 - PCI Express inbound window base address register */
52 uint pexiwbear
; /* 0x.c - PCI Express inbound window base extended address register */
53 uint pexiwar
; /* 0x.10 - PCI Express inbound window attributes register */
57 static void __init
setup_pcie_atmu(struct pci_controller
*hose
, struct resource
*rsrc
)
59 volatile struct ccsr_pex
*pcie
;
60 volatile struct pcie_outbound_window_regs
*pcieow
;
61 volatile struct pcie_inbound_window_regs
*pcieiw
;
64 DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc
->start
,
65 rsrc
->end
- rsrc
->start
+ 1);
66 pcie
= ioremap(rsrc
->start
, rsrc
->end
- rsrc
->start
+ 1);
68 /* Disable all windows (except pexowar0 since its ignored) */
77 pcieow
= (struct pcie_outbound_window_regs
*)&pcie
->pexotar1
;
78 pcieiw
= (struct pcie_inbound_window_regs
*)&pcie
->pexitar1
;
80 /* Setup outbound MEM window */
81 for(i
= 0; i
< 3; i
++)
82 if (hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
){
83 DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
84 hose
->mem_resources
[i
].start
,
85 hose
->mem_resources
[i
].end
86 - hose
->mem_resources
[i
].start
+ 1);
87 pcieow
->pexotar
= (hose
->mem_resources
[i
].start
) >> 12
90 pcieow
->pexowbar
= (hose
->mem_resources
[i
].start
) >> 12
93 pcieow
->pexowar
= 0x80044000 |
94 (__ilog2(hose
->mem_resources
[i
].end
95 - hose
->mem_resources
[i
].start
+ 1)
100 /* Setup outbound IO window */
101 if (hose
->io_resource
.flags
& IORESOURCE_IO
){
102 DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
103 hose
->io_resource
.start
,
104 hose
->io_resource
.end
- hose
->io_resource
.start
+ 1,
106 pcieow
->pexotar
= (hose
->io_resource
.start
) >> 12 & 0x000fffff;
107 pcieow
->pexotear
= 0;
108 pcieow
->pexowbar
= (hose
->io_base_phys
) >> 12 & 0x000fffff;
110 pcieow
->pexowar
= 0x80088000 | (__ilog2(hose
->io_resource
.end
111 - hose
->io_resource
.start
+ 1) - 1);
114 /* Setup 2G inbound Memory Window @ 0 */
115 pcieiw
->pexitar
= 0x00000000;
116 pcieiw
->pexiwbar
= 0x00000000;
117 /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
118 pcieiw
->pexiwar
= 0xa0f5501e;
122 mpc86xx_setup_pcie(struct pci_controller
*hose
, u32 pcie_offset
, u32 pcie_size
)
126 DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
127 pcie_offset
, pcie_size
);
129 early_read_config_word(hose
, 0, 0, PCI_COMMAND
, &cmd
);
130 cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
132 early_write_config_word(hose
, 0, 0, PCI_COMMAND
, cmd
);
134 early_write_config_byte(hose
, 0, 0, PCI_LATENCY_TIMER
, 0x80);
137 static void __devinit
quirk_fsl_pcie_transparent(struct pci_dev
*dev
)
139 struct resource
*res
;
140 int i
, res_idx
= PCI_BRIDGE_RESOURCES
;
141 struct pci_controller
*hose
;
144 * Make the bridge be transparent.
146 dev
->transparent
= 1;
148 hose
= pci_bus_to_hose(dev
->bus
->number
);
150 printk(KERN_ERR
"Can't find hose for bus %d\n",
155 if (hose
->io_resource
.flags
) {
156 res
= &dev
->resource
[res_idx
++];
157 res
->start
= hose
->io_resource
.start
;
158 res
->end
= hose
->io_resource
.end
;
159 res
->flags
= hose
->io_resource
.flags
;
162 for (i
= 0; i
< 3; i
++) {
163 res
= &dev
->resource
[res_idx
+ i
];
164 res
->start
= hose
->mem_resources
[i
].start
;
165 res
->end
= hose
->mem_resources
[i
].end
;
166 res
->flags
= hose
->mem_resources
[i
].flags
;
171 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent
);
172 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent
);
174 #define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
175 #define PCIE_LTSSM_L0 0x16 /* L0 state */
177 int __init
mpc86xx_add_bridge(struct device_node
*dev
)
180 struct pci_controller
*hose
;
181 struct resource rsrc
;
182 const int *bus_range
;
187 DBG("Adding PCIE host bridge %s\n", dev
->full_name
);
189 /* Fetch host bridge registers address */
190 has_address
= (of_address_to_resource(dev
, 0, &rsrc
) == 0);
192 /* Get bus range if any */
193 bus_range
= of_get_property(dev
, "bus-range", &len
);
194 if (bus_range
== NULL
|| len
< 2 * sizeof(int))
195 printk(KERN_WARNING
"Can't get bus-range for %s, assume"
196 " bus 0\n", dev
->full_name
);
198 pci_assign_all_buses
= 1;
199 hose
= pcibios_alloc_controller();
202 hose
->arch_data
= dev
;
203 hose
->indirect_type
= PPC_INDIRECT_TYPE_EXT_REG
|
204 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS
;
206 hose
->first_busno
= bus_range
? bus_range
[0] : 0x0;
207 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
209 setup_indirect_pci(hose
, rsrc
.start
, rsrc
.start
+ 0x4);
211 /* Probe the hose link training status */
212 early_read_config_word(hose
, 0, 0, PCIE_LTSSM
, &val
);
213 if (val
< PCIE_LTSSM_L0
)
216 /* Setup the PCIE host controller. */
217 mpc86xx_setup_pcie(hose
, rsrc
.start
, rsrc
.end
- rsrc
.start
+ 1);
219 if ((rsrc
.start
& 0xfffff) == 0x8000)
222 printk(KERN_INFO
"Found MPC86xx PCIE host bridge at 0x%08lx. "
223 "Firmware bus number: %d->%d\n",
224 (unsigned long) rsrc
.start
,
225 hose
->first_busno
, hose
->last_busno
);
227 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
228 hose
, hose
->cfg_addr
, hose
->cfg_data
);
230 /* Interpret the "ranges" property */
231 /* This also maps the I/O region and sets isa_io/mem_base */
232 pci_process_bridge_OF_ranges(hose
, dev
, primary
);
234 /* Setup PEX window registers */
235 setup_pcie_atmu(hose
, &rsrc
);