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x86: remove mach_apicdef.h
[linux-2.6/mini2440.git] / arch / x86 / kernel / io_apic.c
blobabae81989c2fb6789e011fcdb0aa1c03a41e45dd
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #ifdef CONFIG_ACPI
40 #include <acpi/acpi_bus.h>
41 #endif
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
45
46 #include <asm/idle.h>
47 #include <asm/io.h>
48 #include <asm/smp.h>
49 #include <asm/cpu.h>
50 #include <asm/desc.h>
51 #include <asm/proto.h>
52 #include <asm/acpi.h>
53 #include <asm/dma.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
56 #include <asm/nmi.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
61 #include <asm/hpet.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
64
65 #include <mach_ipi.h>
66 #include <mach_apic.h>
67
68 #define __apicdebuginit(type) static type __init
69
70 /*
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
73 */
74 int sis_apic_bug = -1;
75
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
78
79 /*
80 * # of IRQ routing registers
81 */
82 int nr_ioapic_registers[MAX_IO_APICS];
83
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
86 int nr_ioapics;
87
88 /* MP IRQ source entries */
89 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
90
91 /* # of MP IRQ source entries */
92 int mp_irq_entries;
93
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
96 #endif
97
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99
100 int skip_ioapic_setup;
101
102 static int __init parse_noapic(char *str)
103 {
104 /* disable IO-APIC */
105 disable_ioapic_setup();
106 return 0;
107 }
108 early_param("noapic", parse_noapic);
109
110 struct irq_pin_list;
111
112 /*
113 * This is performance-critical, we want to do it O(1)
114 *
115 * the indexing order of this array favors 1:1 mappings
116 * between pins and IRQs.
117 */
118
119 struct irq_pin_list {
120 int apic, pin;
121 struct irq_pin_list *next;
122 };
123
124 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
125 {
126 struct irq_pin_list *pin;
127 int node;
128
129 node = cpu_to_node(cpu);
130
131 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
132
133 return pin;
134 }
135
136 struct irq_cfg {
137 struct irq_pin_list *irq_2_pin;
138 cpumask_var_t domain;
139 cpumask_var_t old_domain;
140 unsigned move_cleanup_count;
141 u8 vector;
142 u8 move_in_progress : 1;
143 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
144 u8 move_desc_pending : 1;
145 #endif
146 };
147
148 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
149 #ifdef CONFIG_SPARSE_IRQ
150 static struct irq_cfg irq_cfgx[] = {
151 #else
152 static struct irq_cfg irq_cfgx[NR_IRQS] = {
153 #endif
154 [0] = { .vector = IRQ0_VECTOR, },
155 [1] = { .vector = IRQ1_VECTOR, },
156 [2] = { .vector = IRQ2_VECTOR, },
157 [3] = { .vector = IRQ3_VECTOR, },
158 [4] = { .vector = IRQ4_VECTOR, },
159 [5] = { .vector = IRQ5_VECTOR, },
160 [6] = { .vector = IRQ6_VECTOR, },
161 [7] = { .vector = IRQ7_VECTOR, },
162 [8] = { .vector = IRQ8_VECTOR, },
163 [9] = { .vector = IRQ9_VECTOR, },
164 [10] = { .vector = IRQ10_VECTOR, },
165 [11] = { .vector = IRQ11_VECTOR, },
166 [12] = { .vector = IRQ12_VECTOR, },
167 [13] = { .vector = IRQ13_VECTOR, },
168 [14] = { .vector = IRQ14_VECTOR, },
169 [15] = { .vector = IRQ15_VECTOR, },
170 };
171
172 int __init arch_early_irq_init(void)
173 {
174 struct irq_cfg *cfg;
175 struct irq_desc *desc;
176 int count;
177 int i;
178
179 cfg = irq_cfgx;
180 count = ARRAY_SIZE(irq_cfgx);
181
182 for (i = 0; i < count; i++) {
183 desc = irq_to_desc(i);
184 desc->chip_data = &cfg[i];
185 alloc_bootmem_cpumask_var(&cfg[i].domain);
186 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
187 if (i < NR_IRQS_LEGACY)
188 cpumask_setall(cfg[i].domain);
189 }
190
191 return 0;
192 }
193
194 #ifdef CONFIG_SPARSE_IRQ
195 static struct irq_cfg *irq_cfg(unsigned int irq)
196 {
197 struct irq_cfg *cfg = NULL;
198 struct irq_desc *desc;
199
200 desc = irq_to_desc(irq);
201 if (desc)
202 cfg = desc->chip_data;
203
204 return cfg;
205 }
206
207 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
208 {
209 struct irq_cfg *cfg;
210 int node;
211
212 node = cpu_to_node(cpu);
213
214 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
215 if (cfg) {
216 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
217 kfree(cfg);
218 cfg = NULL;
219 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
220 GFP_ATOMIC, node)) {
221 free_cpumask_var(cfg->domain);
222 kfree(cfg);
223 cfg = NULL;
224 } else {
225 cpumask_clear(cfg->domain);
226 cpumask_clear(cfg->old_domain);
227 }
228 }
229
230 return cfg;
231 }
232
233 int arch_init_chip_data(struct irq_desc *desc, int cpu)
234 {
235 struct irq_cfg *cfg;
236
237 cfg = desc->chip_data;
238 if (!cfg) {
239 desc->chip_data = get_one_free_irq_cfg(cpu);
240 if (!desc->chip_data) {
241 printk(KERN_ERR "can not alloc irq_cfg\n");
242 BUG_ON(1);
243 }
244 }
245
246 return 0;
247 }
248
249 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
250
251 static void
252 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
253 {
254 struct irq_pin_list *old_entry, *head, *tail, *entry;
255
256 cfg->irq_2_pin = NULL;
257 old_entry = old_cfg->irq_2_pin;
258 if (!old_entry)
259 return;
260
261 entry = get_one_free_irq_2_pin(cpu);
262 if (!entry)
263 return;
264
265 entry->apic = old_entry->apic;
266 entry->pin = old_entry->pin;
267 head = entry;
268 tail = entry;
269 old_entry = old_entry->next;
270 while (old_entry) {
271 entry = get_one_free_irq_2_pin(cpu);
272 if (!entry) {
273 entry = head;
274 while (entry) {
275 head = entry->next;
276 kfree(entry);
277 entry = head;
278 }
279 /* still use the old one */
280 return;
281 }
282 entry->apic = old_entry->apic;
283 entry->pin = old_entry->pin;
284 tail->next = entry;
285 tail = entry;
286 old_entry = old_entry->next;
287 }
288
289 tail->next = NULL;
290 cfg->irq_2_pin = head;
291 }
292
293 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
294 {
295 struct irq_pin_list *entry, *next;
296
297 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
298 return;
299
300 entry = old_cfg->irq_2_pin;
301
302 while (entry) {
303 next = entry->next;
304 kfree(entry);
305 entry = next;
306 }
307 old_cfg->irq_2_pin = NULL;
308 }
309
310 void arch_init_copy_chip_data(struct irq_desc *old_desc,
311 struct irq_desc *desc, int cpu)
312 {
313 struct irq_cfg *cfg;
314 struct irq_cfg *old_cfg;
315
316 cfg = get_one_free_irq_cfg(cpu);
317
318 if (!cfg)
319 return;
320
321 desc->chip_data = cfg;
322
323 old_cfg = old_desc->chip_data;
324
325 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
326
327 init_copy_irq_2_pin(old_cfg, cfg, cpu);
328 }
329
330 static void free_irq_cfg(struct irq_cfg *old_cfg)
331 {
332 kfree(old_cfg);
333 }
334
335 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
336 {
337 struct irq_cfg *old_cfg, *cfg;
338
339 old_cfg = old_desc->chip_data;
340 cfg = desc->chip_data;
341
342 if (old_cfg == cfg)
343 return;
344
345 if (old_cfg) {
346 free_irq_2_pin(old_cfg, cfg);
347 free_irq_cfg(old_cfg);
348 old_desc->chip_data = NULL;
349 }
350 }
351
352 static void
353 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
354 {
355 struct irq_cfg *cfg = desc->chip_data;
356
357 if (!cfg->move_in_progress) {
358 /* it means that domain is not changed */
359 if (!cpumask_intersects(desc->affinity, mask))
360 cfg->move_desc_pending = 1;
361 }
362 }
363 #endif
364
365 #else
366 static struct irq_cfg *irq_cfg(unsigned int irq)
367 {
368 return irq < nr_irqs ? irq_cfgx + irq : NULL;
369 }
370
371 #endif
372
373 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
374 static inline void
375 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
376 {
377 }
378 #endif
379
380 struct io_apic {
381 unsigned int index;
382 unsigned int unused[3];
383 unsigned int data;
384 };
385
386 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
387 {
388 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
389 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
390 }
391
392 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
393 {
394 struct io_apic __iomem *io_apic = io_apic_base(apic);
395 writel(reg, &io_apic->index);
396 return readl(&io_apic->data);
397 }
398
399 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
400 {
401 struct io_apic __iomem *io_apic = io_apic_base(apic);
402 writel(reg, &io_apic->index);
403 writel(value, &io_apic->data);
404 }
405
406 /*
407 * Re-write a value: to be used for read-modify-write
408 * cycles where the read already set up the index register.
409 *
410 * Older SiS APIC requires we rewrite the index register
411 */
412 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
413 {
414 struct io_apic __iomem *io_apic = io_apic_base(apic);
415
416 if (sis_apic_bug)
417 writel(reg, &io_apic->index);
418 writel(value, &io_apic->data);
419 }
420
421 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
422 {
423 struct irq_pin_list *entry;
424 unsigned long flags;
425
426 spin_lock_irqsave(&ioapic_lock, flags);
427 entry = cfg->irq_2_pin;
428 for (;;) {
429 unsigned int reg;
430 int pin;
431
432 if (!entry)
433 break;
434 pin = entry->pin;
435 reg = io_apic_read(entry->apic, 0x10 + pin*2);
436 /* Is the remote IRR bit set? */
437 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
438 spin_unlock_irqrestore(&ioapic_lock, flags);
439 return true;
440 }
441 if (!entry->next)
442 break;
443 entry = entry->next;
444 }
445 spin_unlock_irqrestore(&ioapic_lock, flags);
446
447 return false;
448 }
449
450 union entry_union {
451 struct { u32 w1, w2; };
452 struct IO_APIC_route_entry entry;
453 };
454
455 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
456 {
457 union entry_union eu;
458 unsigned long flags;
459 spin_lock_irqsave(&ioapic_lock, flags);
460 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
461 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
462 spin_unlock_irqrestore(&ioapic_lock, flags);
463 return eu.entry;
464 }
465
466 /*
467 * When we write a new IO APIC routing entry, we need to write the high
468 * word first! If the mask bit in the low word is clear, we will enable
469 * the interrupt, and we need to make sure the entry is fully populated
470 * before that happens.
471 */
472 static void
473 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
474 {
475 union entry_union eu;
476 eu.entry = e;
477 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
478 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
479 }
480
481 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
482 {
483 unsigned long flags;
484 spin_lock_irqsave(&ioapic_lock, flags);
485 __ioapic_write_entry(apic, pin, e);
486 spin_unlock_irqrestore(&ioapic_lock, flags);
487 }
488
489 /*
490 * When we mask an IO APIC routing entry, we need to write the low
491 * word first, in order to set the mask bit before we change the
492 * high bits!
493 */
494 static void ioapic_mask_entry(int apic, int pin)
495 {
496 unsigned long flags;
497 union entry_union eu = { .entry.mask = 1 };
498
499 spin_lock_irqsave(&ioapic_lock, flags);
500 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
501 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
502 spin_unlock_irqrestore(&ioapic_lock, flags);
503 }
504
505 #ifdef CONFIG_SMP
506 static void send_cleanup_vector(struct irq_cfg *cfg)
507 {
508 cpumask_var_t cleanup_mask;
509
510 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
511 unsigned int i;
512 cfg->move_cleanup_count = 0;
513 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
514 cfg->move_cleanup_count++;
515 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
516 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
517 } else {
518 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
519 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
520 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
521 free_cpumask_var(cleanup_mask);
522 }
523 cfg->move_in_progress = 0;
524 }
525
526 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
527 {
528 int apic, pin;
529 struct irq_pin_list *entry;
530 u8 vector = cfg->vector;
531
532 entry = cfg->irq_2_pin;
533 for (;;) {
534 unsigned int reg;
535
536 if (!entry)
537 break;
538
539 apic = entry->apic;
540 pin = entry->pin;
541 #ifdef CONFIG_INTR_REMAP
542 /*
543 * With interrupt-remapping, destination information comes
544 * from interrupt-remapping table entry.
545 */
546 if (!irq_remapped(irq))
547 io_apic_write(apic, 0x11 + pin*2, dest);
548 #else
549 io_apic_write(apic, 0x11 + pin*2, dest);
550 #endif
551 reg = io_apic_read(apic, 0x10 + pin*2);
552 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
553 reg |= vector;
554 io_apic_modify(apic, 0x10 + pin*2, reg);
555 if (!entry->next)
556 break;
557 entry = entry->next;
558 }
559 }
560
561 static int
562 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
563
564 /*
565 * Either sets desc->affinity to a valid value, and returns
566 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
567 * leaves desc->affinity untouched.
568 */
569 static unsigned int
570 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
571 {
572 struct irq_cfg *cfg;
573 unsigned int irq;
574
575 if (!cpumask_intersects(mask, cpu_online_mask))
576 return BAD_APICID;
577
578 irq = desc->irq;
579 cfg = desc->chip_data;
580 if (assign_irq_vector(irq, cfg, mask))
581 return BAD_APICID;
582
583 cpumask_and(desc->affinity, cfg->domain, mask);
584 set_extra_move_desc(desc, mask);
585
586 return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
587 }
588
589 static void
590 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
591 {
592 struct irq_cfg *cfg;
593 unsigned long flags;
594 unsigned int dest;
595 unsigned int irq;
596
597 irq = desc->irq;
598 cfg = desc->chip_data;
599
600 spin_lock_irqsave(&ioapic_lock, flags);
601 dest = set_desc_affinity(desc, mask);
602 if (dest != BAD_APICID) {
603 /* Only the high 8 bits are valid. */
604 dest = SET_APIC_LOGICAL_ID(dest);
605 __target_IO_APIC_irq(irq, dest, cfg);
606 }
607 spin_unlock_irqrestore(&ioapic_lock, flags);
608 }
609
610 static void
611 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
612 {
613 struct irq_desc *desc;
614
615 desc = irq_to_desc(irq);
616
617 set_ioapic_affinity_irq_desc(desc, mask);
618 }
619 #endif /* CONFIG_SMP */
620
621 /*
622 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
623 * shared ISA-space IRQs, so we have to support them. We are super
624 * fast in the common case, and fast for shared ISA-space IRQs.
625 */
626 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
627 {
628 struct irq_pin_list *entry;
629
630 entry = cfg->irq_2_pin;
631 if (!entry) {
632 entry = get_one_free_irq_2_pin(cpu);
633 if (!entry) {
634 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
635 apic, pin);
636 return;
637 }
638 cfg->irq_2_pin = entry;
639 entry->apic = apic;
640 entry->pin = pin;
641 return;
642 }
643
644 while (entry->next) {
645 /* not again, please */
646 if (entry->apic == apic && entry->pin == pin)
647 return;
648
649 entry = entry->next;
650 }
651
652 entry->next = get_one_free_irq_2_pin(cpu);
653 entry = entry->next;
654 entry->apic = apic;
655 entry->pin = pin;
656 }
657
658 /*
659 * Reroute an IRQ to a different pin.
660 */
661 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
662 int oldapic, int oldpin,
663 int newapic, int newpin)
664 {
665 struct irq_pin_list *entry = cfg->irq_2_pin;
666 int replaced = 0;
667
668 while (entry) {
669 if (entry->apic == oldapic && entry->pin == oldpin) {
670 entry->apic = newapic;
671 entry->pin = newpin;
672 replaced = 1;
673 /* every one is different, right? */
674 break;
675 }
676 entry = entry->next;
677 }
678
679 /* why? call replace before add? */
680 if (!replaced)
681 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
682 }
683
684 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
685 int mask_and, int mask_or,
686 void (*final)(struct irq_pin_list *entry))
687 {
688 int pin;
689 struct irq_pin_list *entry;
690
691 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
692 unsigned int reg;
693 pin = entry->pin;
694 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
695 reg &= mask_and;
696 reg |= mask_or;
697 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
698 if (final)
699 final(entry);
700 }
701 }
702
703 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
704 {
705 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
706 }
707
708 #ifdef CONFIG_X86_64
709 static void io_apic_sync(struct irq_pin_list *entry)
710 {
711 /*
712 * Synchronize the IO-APIC and the CPU by doing
713 * a dummy read from the IO-APIC
714 */
715 struct io_apic __iomem *io_apic;
716 io_apic = io_apic_base(entry->apic);
717 readl(&io_apic->data);
718 }
719
720 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
721 {
722 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
723 }
724 #else /* CONFIG_X86_32 */
725 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
726 {
727 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
728 }
729
730 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
731 {
732 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
733 IO_APIC_REDIR_MASKED, NULL);
734 }
735
736 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
737 {
738 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
739 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
740 }
741 #endif /* CONFIG_X86_32 */
742
743 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
744 {
745 struct irq_cfg *cfg = desc->chip_data;
746 unsigned long flags;
747
748 BUG_ON(!cfg);
749
750 spin_lock_irqsave(&ioapic_lock, flags);
751 __mask_IO_APIC_irq(cfg);
752 spin_unlock_irqrestore(&ioapic_lock, flags);
753 }
754
755 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
756 {
757 struct irq_cfg *cfg = desc->chip_data;
758 unsigned long flags;
759
760 spin_lock_irqsave(&ioapic_lock, flags);
761 __unmask_IO_APIC_irq(cfg);
762 spin_unlock_irqrestore(&ioapic_lock, flags);
763 }
764
765 static void mask_IO_APIC_irq(unsigned int irq)
766 {
767 struct irq_desc *desc = irq_to_desc(irq);
768
769 mask_IO_APIC_irq_desc(desc);
770 }
771 static void unmask_IO_APIC_irq(unsigned int irq)
772 {
773 struct irq_desc *desc = irq_to_desc(irq);
774
775 unmask_IO_APIC_irq_desc(desc);
776 }
777
778 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
779 {
780 struct IO_APIC_route_entry entry;
781
782 /* Check delivery_mode to be sure we're not clearing an SMI pin */
783 entry = ioapic_read_entry(apic, pin);
784 if (entry.delivery_mode == dest_SMI)
785 return;
786 /*
787 * Disable it in the IO-APIC irq-routing table:
788 */
789 ioapic_mask_entry(apic, pin);
790 }
791
792 static void clear_IO_APIC (void)
793 {
794 int apic, pin;
795
796 for (apic = 0; apic < nr_ioapics; apic++)
797 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
798 clear_IO_APIC_pin(apic, pin);
799 }
800
801 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
802 void default_send_IPI_self(int vector)
803 {
804 unsigned int cfg;
805
806 /*
807 * Wait for idle.
808 */
809 apic_wait_icr_idle();
810 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | apic->dest_logical;
811 /*
812 * Send the IPI. The write to APIC_ICR fires this off.
813 */
814 apic_write(APIC_ICR, cfg);
815 }
816 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
817
818 #ifdef CONFIG_X86_32
819 /*
820 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
821 * specific CPU-side IRQs.
822 */
823
824 #define MAX_PIRQS 8
825 static int pirq_entries [MAX_PIRQS];
826 static int pirqs_enabled;
827
828 static int __init ioapic_pirq_setup(char *str)
829 {
830 int i, max;
831 int ints[MAX_PIRQS+1];
832
833 get_options(str, ARRAY_SIZE(ints), ints);
834
835 for (i = 0; i < MAX_PIRQS; i++)
836 pirq_entries[i] = -1;
837
838 pirqs_enabled = 1;
839 apic_printk(APIC_VERBOSE, KERN_INFO
840 "PIRQ redirection, working around broken MP-BIOS.\n");
841 max = MAX_PIRQS;
842 if (ints[0] < MAX_PIRQS)
843 max = ints[0];
844
845 for (i = 0; i < max; i++) {
846 apic_printk(APIC_VERBOSE, KERN_DEBUG
847 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
848 /*
849 * PIRQs are mapped upside down, usually.
850 */
851 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
852 }
853 return 1;
854 }
855
856 __setup("pirq=", ioapic_pirq_setup);
857 #endif /* CONFIG_X86_32 */
858
859 #ifdef CONFIG_INTR_REMAP
860 /* I/O APIC RTE contents at the OS boot up */
861 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
862
863 /*
864 * Saves and masks all the unmasked IO-APIC RTE's
865 */
866 int save_mask_IO_APIC_setup(void)
867 {
868 union IO_APIC_reg_01 reg_01;
869 unsigned long flags;
870 int apic, pin;
871
872 /*
873 * The number of IO-APIC IRQ registers (== #pins):
874 */
875 for (apic = 0; apic < nr_ioapics; apic++) {
876 spin_lock_irqsave(&ioapic_lock, flags);
877 reg_01.raw = io_apic_read(apic, 1);
878 spin_unlock_irqrestore(&ioapic_lock, flags);
879 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
880 }
881
882 for (apic = 0; apic < nr_ioapics; apic++) {
883 early_ioapic_entries[apic] =
884 kzalloc(sizeof(struct IO_APIC_route_entry) *
885 nr_ioapic_registers[apic], GFP_KERNEL);
886 if (!early_ioapic_entries[apic])
887 goto nomem;
888 }
889
890 for (apic = 0; apic < nr_ioapics; apic++)
891 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
892 struct IO_APIC_route_entry entry;
893
894 entry = early_ioapic_entries[apic][pin] =
895 ioapic_read_entry(apic, pin);
896 if (!entry.mask) {
897 entry.mask = 1;
898 ioapic_write_entry(apic, pin, entry);
899 }
900 }
901
902 return 0;
903
904 nomem:
905 while (apic >= 0)
906 kfree(early_ioapic_entries[apic--]);
907 memset(early_ioapic_entries, 0,
908 ARRAY_SIZE(early_ioapic_entries));
909
910 return -ENOMEM;
911 }
912
913 void restore_IO_APIC_setup(void)
914 {
915 int apic, pin;
916
917 for (apic = 0; apic < nr_ioapics; apic++) {
918 if (!early_ioapic_entries[apic])
919 break;
920 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
921 ioapic_write_entry(apic, pin,
922 early_ioapic_entries[apic][pin]);
923 kfree(early_ioapic_entries[apic]);
924 early_ioapic_entries[apic] = NULL;
925 }
926 }
927
928 void reinit_intr_remapped_IO_APIC(int intr_remapping)
929 {
930 /*
931 * for now plain restore of previous settings.
932 * TBD: In the case of OS enabling interrupt-remapping,
933 * IO-APIC RTE's need to be setup to point to interrupt-remapping
934 * table entries. for now, do a plain restore, and wait for
935 * the setup_IO_APIC_irqs() to do proper initialization.
936 */
937 restore_IO_APIC_setup();
938 }
939 #endif
940
941 /*
942 * Find the IRQ entry number of a certain pin.
943 */
944 static int find_irq_entry(int apic, int pin, int type)
945 {
946 int i;
947
948 for (i = 0; i < mp_irq_entries; i++)
949 if (mp_irqs[i].irqtype == type &&
950 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
951 mp_irqs[i].dstapic == MP_APIC_ALL) &&
952 mp_irqs[i].dstirq == pin)
953 return i;
954
955 return -1;
956 }
957
958 /*
959 * Find the pin to which IRQ[irq] (ISA) is connected
960 */
961 static int __init find_isa_irq_pin(int irq, int type)
962 {
963 int i;
964
965 for (i = 0; i < mp_irq_entries; i++) {
966 int lbus = mp_irqs[i].srcbus;
967
968 if (test_bit(lbus, mp_bus_not_pci) &&
969 (mp_irqs[i].irqtype == type) &&
970 (mp_irqs[i].srcbusirq == irq))
971
972 return mp_irqs[i].dstirq;
973 }
974 return -1;
975 }
976
977 static int __init find_isa_irq_apic(int irq, int type)
978 {
979 int i;
980
981 for (i = 0; i < mp_irq_entries; i++) {
982 int lbus = mp_irqs[i].srcbus;
983
984 if (test_bit(lbus, mp_bus_not_pci) &&
985 (mp_irqs[i].irqtype == type) &&
986 (mp_irqs[i].srcbusirq == irq))
987 break;
988 }
989 if (i < mp_irq_entries) {
990 int apic;
991 for(apic = 0; apic < nr_ioapics; apic++) {
992 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
993 return apic;
994 }
995 }
996
997 return -1;
998 }
999
1000 /*
1001 * Find a specific PCI IRQ entry.
1002 * Not an __init, possibly needed by modules
1003 */
1004 static int pin_2_irq(int idx, int apic, int pin);
1005
1006 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1007 {
1008 int apic, i, best_guess = -1;
1009
1010 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1011 bus, slot, pin);
1012 if (test_bit(bus, mp_bus_not_pci)) {
1013 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1014 return -1;
1015 }
1016 for (i = 0; i < mp_irq_entries; i++) {
1017 int lbus = mp_irqs[i].srcbus;
1018
1019 for (apic = 0; apic < nr_ioapics; apic++)
1020 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1021 mp_irqs[i].dstapic == MP_APIC_ALL)
1022 break;
1023
1024 if (!test_bit(lbus, mp_bus_not_pci) &&
1025 !mp_irqs[i].irqtype &&
1026 (bus == lbus) &&
1027 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1028 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1029
1030 if (!(apic || IO_APIC_IRQ(irq)))
1031 continue;
1032
1033 if (pin == (mp_irqs[i].srcbusirq & 3))
1034 return irq;
1035 /*
1036 * Use the first all-but-pin matching entry as a
1037 * best-guess fuzzy result for broken mptables.
1038 */
1039 if (best_guess < 0)
1040 best_guess = irq;
1041 }
1042 }
1043 return best_guess;
1044 }
1045
1046 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1047
1048 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1049 /*
1050 * EISA Edge/Level control register, ELCR
1051 */
1052 static int EISA_ELCR(unsigned int irq)
1053 {
1054 if (irq < NR_IRQS_LEGACY) {
1055 unsigned int port = 0x4d0 + (irq >> 3);
1056 return (inb(port) >> (irq & 7)) & 1;
1057 }
1058 apic_printk(APIC_VERBOSE, KERN_INFO
1059 "Broken MPtable reports ISA irq %d\n", irq);
1060 return 0;
1061 }
1062
1063 #endif
1064
1065 /* ISA interrupts are always polarity zero edge triggered,
1066 * when listed as conforming in the MP table. */
1067
1068 #define default_ISA_trigger(idx) (0)
1069 #define default_ISA_polarity(idx) (0)
1070
1071 /* EISA interrupts are always polarity zero and can be edge or level
1072 * trigger depending on the ELCR value. If an interrupt is listed as
1073 * EISA conforming in the MP table, that means its trigger type must
1074 * be read in from the ELCR */
1075
1076 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
1077 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1078
1079 /* PCI interrupts are always polarity one level triggered,
1080 * when listed as conforming in the MP table. */
1081
1082 #define default_PCI_trigger(idx) (1)
1083 #define default_PCI_polarity(idx) (1)
1084
1085 /* MCA interrupts are always polarity zero level triggered,
1086 * when listed as conforming in the MP table. */
1087
1088 #define default_MCA_trigger(idx) (1)
1089 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1090
1091 static int MPBIOS_polarity(int idx)
1092 {
1093 int bus = mp_irqs[idx].srcbus;
1094 int polarity;
1095
1096 /*
1097 * Determine IRQ line polarity (high active or low active):
1098 */
1099 switch (mp_irqs[idx].irqflag & 3)
1100 {
1101 case 0: /* conforms, ie. bus-type dependent polarity */
1102 if (test_bit(bus, mp_bus_not_pci))
1103 polarity = default_ISA_polarity(idx);
1104 else
1105 polarity = default_PCI_polarity(idx);
1106 break;
1107 case 1: /* high active */
1108 {
1109 polarity = 0;
1110 break;
1111 }
1112 case 2: /* reserved */
1113 {
1114 printk(KERN_WARNING "broken BIOS!!\n");
1115 polarity = 1;
1116 break;
1117 }
1118 case 3: /* low active */
1119 {
1120 polarity = 1;
1121 break;
1122 }
1123 default: /* invalid */
1124 {
1125 printk(KERN_WARNING "broken BIOS!!\n");
1126 polarity = 1;
1127 break;
1128 }
1129 }
1130 return polarity;
1131 }
1132
1133 static int MPBIOS_trigger(int idx)
1134 {
1135 int bus = mp_irqs[idx].srcbus;
1136 int trigger;
1137
1138 /*
1139 * Determine IRQ trigger mode (edge or level sensitive):
1140 */
1141 switch ((mp_irqs[idx].irqflag>>2) & 3)
1142 {
1143 case 0: /* conforms, ie. bus-type dependent */
1144 if (test_bit(bus, mp_bus_not_pci))
1145 trigger = default_ISA_trigger(idx);
1146 else
1147 trigger = default_PCI_trigger(idx);
1148 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1149 switch (mp_bus_id_to_type[bus]) {
1150 case MP_BUS_ISA: /* ISA pin */
1151 {
1152 /* set before the switch */
1153 break;
1154 }
1155 case MP_BUS_EISA: /* EISA pin */
1156 {
1157 trigger = default_EISA_trigger(idx);
1158 break;
1159 }
1160 case MP_BUS_PCI: /* PCI pin */
1161 {
1162 /* set before the switch */
1163 break;
1164 }
1165 case MP_BUS_MCA: /* MCA pin */
1166 {
1167 trigger = default_MCA_trigger(idx);
1168 break;
1169 }
1170 default:
1171 {
1172 printk(KERN_WARNING "broken BIOS!!\n");
1173 trigger = 1;
1174 break;
1175 }
1176 }
1177 #endif
1178 break;
1179 case 1: /* edge */
1180 {
1181 trigger = 0;
1182 break;
1183 }
1184 case 2: /* reserved */
1185 {
1186 printk(KERN_WARNING "broken BIOS!!\n");
1187 trigger = 1;
1188 break;
1189 }
1190 case 3: /* level */
1191 {
1192 trigger = 1;
1193 break;
1194 }
1195 default: /* invalid */
1196 {
1197 printk(KERN_WARNING "broken BIOS!!\n");
1198 trigger = 0;
1199 break;
1200 }
1201 }
1202 return trigger;
1203 }
1204
1205 static inline int irq_polarity(int idx)
1206 {
1207 return MPBIOS_polarity(idx);
1208 }
1209
1210 static inline int irq_trigger(int idx)
1211 {
1212 return MPBIOS_trigger(idx);
1213 }
1214
1215 int (*ioapic_renumber_irq)(int ioapic, int irq);
1216 static int pin_2_irq(int idx, int apic, int pin)
1217 {
1218 int irq, i;
1219 int bus = mp_irqs[idx].srcbus;
1220
1221 /*
1222 * Debugging check, we are in big trouble if this message pops up!
1223 */
1224 if (mp_irqs[idx].dstirq != pin)
1225 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1226
1227 if (test_bit(bus, mp_bus_not_pci)) {
1228 irq = mp_irqs[idx].srcbusirq;
1229 } else {
1230 /*
1231 * PCI IRQs are mapped in order
1232 */
1233 i = irq = 0;
1234 while (i < apic)
1235 irq += nr_ioapic_registers[i++];
1236 irq += pin;
1237 /*
1238 * For MPS mode, so far only needed by ES7000 platform
1239 */
1240 if (ioapic_renumber_irq)
1241 irq = ioapic_renumber_irq(apic, irq);
1242 }
1243
1244 #ifdef CONFIG_X86_32
1245 /*
1246 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1247 */
1248 if ((pin >= 16) && (pin <= 23)) {
1249 if (pirq_entries[pin-16] != -1) {
1250 if (!pirq_entries[pin-16]) {
1251 apic_printk(APIC_VERBOSE, KERN_DEBUG
1252 "disabling PIRQ%d\n", pin-16);
1253 } else {
1254 irq = pirq_entries[pin-16];
1255 apic_printk(APIC_VERBOSE, KERN_DEBUG
1256 "using PIRQ%d -> IRQ %d\n",
1257 pin-16, irq);
1258 }
1259 }
1260 }
1261 #endif
1262
1263 return irq;
1264 }
1265
1266 void lock_vector_lock(void)
1267 {
1268 /* Used to the online set of cpus does not change
1269 * during assign_irq_vector.
1270 */
1271 spin_lock(&vector_lock);
1272 }
1273
1274 void unlock_vector_lock(void)
1275 {
1276 spin_unlock(&vector_lock);
1277 }
1278
1279 static int
1280 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1281 {
1282 /*
1283 * NOTE! The local APIC isn't very good at handling
1284 * multiple interrupts at the same interrupt level.
1285 * As the interrupt level is determined by taking the
1286 * vector number and shifting that right by 4, we
1287 * want to spread these out a bit so that they don't
1288 * all fall in the same interrupt level.
1289 *
1290 * Also, we've got to be careful not to trash gate
1291 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1292 */
1293 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1294 unsigned int old_vector;
1295 int cpu, err;
1296 cpumask_var_t tmp_mask;
1297
1298 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1299 return -EBUSY;
1300
1301 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1302 return -ENOMEM;
1303
1304 old_vector = cfg->vector;
1305 if (old_vector) {
1306 cpumask_and(tmp_mask, mask, cpu_online_mask);
1307 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1308 if (!cpumask_empty(tmp_mask)) {
1309 free_cpumask_var(tmp_mask);
1310 return 0;
1311 }
1312 }
1313
1314 /* Only try and allocate irqs on cpus that are present */
1315 err = -ENOSPC;
1316 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1317 int new_cpu;
1318 int vector, offset;
1319
1320 apic->vector_allocation_domain(cpu, tmp_mask);
1321
1322 vector = current_vector;
1323 offset = current_offset;
1324 next:
1325 vector += 8;
1326 if (vector >= first_system_vector) {
1327 /* If out of vectors on large boxen, must share them. */
1328 offset = (offset + 1) % 8;
1329 vector = FIRST_DEVICE_VECTOR + offset;
1330 }
1331 if (unlikely(current_vector == vector))
1332 continue;
1333
1334 if (test_bit(vector, used_vectors))
1335 goto next;
1336
1337 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1338 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1339 goto next;
1340 /* Found one! */
1341 current_vector = vector;
1342 current_offset = offset;
1343 if (old_vector) {
1344 cfg->move_in_progress = 1;
1345 cpumask_copy(cfg->old_domain, cfg->domain);
1346 }
1347 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1348 per_cpu(vector_irq, new_cpu)[vector] = irq;
1349 cfg->vector = vector;
1350 cpumask_copy(cfg->domain, tmp_mask);
1351 err = 0;
1352 break;
1353 }
1354 free_cpumask_var(tmp_mask);
1355 return err;
1356 }
1357
1358 static int
1359 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1360 {
1361 int err;
1362 unsigned long flags;
1363
1364 spin_lock_irqsave(&vector_lock, flags);
1365 err = __assign_irq_vector(irq, cfg, mask);
1366 spin_unlock_irqrestore(&vector_lock, flags);
1367 return err;
1368 }
1369
1370 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1371 {
1372 int cpu, vector;
1373
1374 BUG_ON(!cfg->vector);
1375
1376 vector = cfg->vector;
1377 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1378 per_cpu(vector_irq, cpu)[vector] = -1;
1379
1380 cfg->vector = 0;
1381 cpumask_clear(cfg->domain);
1382
1383 if (likely(!cfg->move_in_progress))
1384 return;
1385 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1386 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1387 vector++) {
1388 if (per_cpu(vector_irq, cpu)[vector] != irq)
1389 continue;
1390 per_cpu(vector_irq, cpu)[vector] = -1;
1391 break;
1392 }
1393 }
1394 cfg->move_in_progress = 0;
1395 }
1396
1397 void __setup_vector_irq(int cpu)
1398 {
1399 /* Initialize vector_irq on a new cpu */
1400 /* This function must be called with vector_lock held */
1401 int irq, vector;
1402 struct irq_cfg *cfg;
1403 struct irq_desc *desc;
1404
1405 /* Mark the inuse vectors */
1406 for_each_irq_desc(irq, desc) {
1407 cfg = desc->chip_data;
1408 if (!cpumask_test_cpu(cpu, cfg->domain))
1409 continue;
1410 vector = cfg->vector;
1411 per_cpu(vector_irq, cpu)[vector] = irq;
1412 }
1413 /* Mark the free vectors */
1414 for (vector = 0; vector < NR_VECTORS; ++vector) {
1415 irq = per_cpu(vector_irq, cpu)[vector];
1416 if (irq < 0)
1417 continue;
1418
1419 cfg = irq_cfg(irq);
1420 if (!cpumask_test_cpu(cpu, cfg->domain))
1421 per_cpu(vector_irq, cpu)[vector] = -1;
1422 }
1423 }
1424
1425 static struct irq_chip ioapic_chip;
1426 #ifdef CONFIG_INTR_REMAP
1427 static struct irq_chip ir_ioapic_chip;
1428 #endif
1429
1430 #define IOAPIC_AUTO -1
1431 #define IOAPIC_EDGE 0
1432 #define IOAPIC_LEVEL 1
1433
1434 #ifdef CONFIG_X86_32
1435 static inline int IO_APIC_irq_trigger(int irq)
1436 {
1437 int apic, idx, pin;
1438
1439 for (apic = 0; apic < nr_ioapics; apic++) {
1440 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1441 idx = find_irq_entry(apic, pin, mp_INT);
1442 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1443 return irq_trigger(idx);
1444 }
1445 }
1446 /*
1447 * nonexistent IRQs are edge default
1448 */
1449 return 0;
1450 }
1451 #else
1452 static inline int IO_APIC_irq_trigger(int irq)
1453 {
1454 return 1;
1455 }
1456 #endif
1457
1458 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1459 {
1460
1461 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1462 trigger == IOAPIC_LEVEL)
1463 desc->status |= IRQ_LEVEL;
1464 else
1465 desc->status &= ~IRQ_LEVEL;
1466
1467 #ifdef CONFIG_INTR_REMAP
1468 if (irq_remapped(irq)) {
1469 desc->status |= IRQ_MOVE_PCNTXT;
1470 if (trigger)
1471 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1472 handle_fasteoi_irq,
1473 "fasteoi");
1474 else
1475 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1476 handle_edge_irq, "edge");
1477 return;
1478 }
1479 #endif
1480 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1481 trigger == IOAPIC_LEVEL)
1482 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1483 handle_fasteoi_irq,
1484 "fasteoi");
1485 else
1486 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1487 handle_edge_irq, "edge");
1488 }
1489
1490 static int setup_ioapic_entry(int apic_id, int irq,
1491 struct IO_APIC_route_entry *entry,
1492 unsigned int destination, int trigger,
1493 int polarity, int vector)
1494 {
1495 /*
1496 * add it to the IO-APIC irq-routing table:
1497 */
1498 memset(entry,0,sizeof(*entry));
1499
1500 #ifdef CONFIG_INTR_REMAP
1501 if (intr_remapping_enabled) {
1502 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1503 struct irte irte;
1504 struct IR_IO_APIC_route_entry *ir_entry =
1505 (struct IR_IO_APIC_route_entry *) entry;
1506 int index;
1507
1508 if (!iommu)
1509 panic("No mapping iommu for ioapic %d\n", apic_id);
1510
1511 index = alloc_irte(iommu, irq, 1);
1512 if (index < 0)
1513 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1514
1515 memset(&irte, 0, sizeof(irte));
1516
1517 irte.present = 1;
1518 irte.dst_mode = apic->irq_dest_mode;
1519 irte.trigger_mode = trigger;
1520 irte.dlvry_mode = apic->irq_delivery_mode;
1521 irte.vector = vector;
1522 irte.dest_id = IRTE_DEST(destination);
1523
1524 modify_irte(irq, &irte);
1525
1526 ir_entry->index2 = (index >> 15) & 0x1;
1527 ir_entry->zero = 0;
1528 ir_entry->format = 1;
1529 ir_entry->index = (index & 0x7fff);
1530 } else
1531 #endif
1532 {
1533 entry->delivery_mode = apic->irq_delivery_mode;
1534 entry->dest_mode = apic->irq_dest_mode;
1535 entry->dest = destination;
1536 }
1537
1538 entry->mask = 0; /* enable IRQ */
1539 entry->trigger = trigger;
1540 entry->polarity = polarity;
1541 entry->vector = vector;
1542
1543 /* Mask level triggered irqs.
1544 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1545 */
1546 if (trigger)
1547 entry->mask = 1;
1548 return 0;
1549 }
1550
1551 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1552 int trigger, int polarity)
1553 {
1554 struct irq_cfg *cfg;
1555 struct IO_APIC_route_entry entry;
1556 unsigned int dest;
1557
1558 if (!IO_APIC_IRQ(irq))
1559 return;
1560
1561 cfg = desc->chip_data;
1562
1563 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1564 return;
1565
1566 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1567
1568 apic_printk(APIC_VERBOSE,KERN_DEBUG
1569 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1570 "IRQ %d Mode:%i Active:%i)\n",
1571 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1572 irq, trigger, polarity);
1573
1574
1575 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1576 dest, trigger, polarity, cfg->vector)) {
1577 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1578 mp_ioapics[apic_id].apicid, pin);
1579 __clear_irq_vector(irq, cfg);
1580 return;
1581 }
1582
1583 ioapic_register_intr(irq, desc, trigger);
1584 if (irq < NR_IRQS_LEGACY)
1585 disable_8259A_irq(irq);
1586
1587 ioapic_write_entry(apic_id, pin, entry);
1588 }
1589
1590 static void __init setup_IO_APIC_irqs(void)
1591 {
1592 int apic_id, pin, idx, irq;
1593 int notcon = 0;
1594 struct irq_desc *desc;
1595 struct irq_cfg *cfg;
1596 int cpu = boot_cpu_id;
1597
1598 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1599
1600 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1601 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1602
1603 idx = find_irq_entry(apic_id, pin, mp_INT);
1604 if (idx == -1) {
1605 if (!notcon) {
1606 notcon = 1;
1607 apic_printk(APIC_VERBOSE,
1608 KERN_DEBUG " %d-%d",
1609 mp_ioapics[apic_id].apicid, pin);
1610 } else
1611 apic_printk(APIC_VERBOSE, " %d-%d",
1612 mp_ioapics[apic_id].apicid, pin);
1613 continue;
1614 }
1615 if (notcon) {
1616 apic_printk(APIC_VERBOSE,
1617 " (apicid-pin) not connected\n");
1618 notcon = 0;
1619 }
1620
1621 irq = pin_2_irq(idx, apic_id, pin);
1622
1623 /*
1624 * Skip the timer IRQ if there's a quirk handler
1625 * installed and if it returns 1:
1626 */
1627 if (apic->multi_timer_check &&
1628 apic->multi_timer_check(apic_id, irq))
1629 continue;
1630
1631 desc = irq_to_desc_alloc_cpu(irq, cpu);
1632 if (!desc) {
1633 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1634 continue;
1635 }
1636 cfg = desc->chip_data;
1637 add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1638
1639 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1640 irq_trigger(idx), irq_polarity(idx));
1641 }
1642 }
1643
1644 if (notcon)
1645 apic_printk(APIC_VERBOSE,
1646 " (apicid-pin) not connected\n");
1647 }
1648
1649 /*
1650 * Set up the timer pin, possibly with the 8259A-master behind.
1651 */
1652 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1653 int vector)
1654 {
1655 struct IO_APIC_route_entry entry;
1656
1657 #ifdef CONFIG_INTR_REMAP
1658 if (intr_remapping_enabled)
1659 return;
1660 #endif
1661
1662 memset(&entry, 0, sizeof(entry));
1663
1664 /*
1665 * We use logical delivery to get the timer IRQ
1666 * to the first CPU.
1667 */
1668 entry.dest_mode = apic->irq_dest_mode;
1669 entry.mask = 1; /* mask IRQ now */
1670 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1671 entry.delivery_mode = apic->irq_delivery_mode;
1672 entry.polarity = 0;
1673 entry.trigger = 0;
1674 entry.vector = vector;
1675
1676 /*
1677 * The timer IRQ doesn't have to know that behind the
1678 * scene we may have a 8259A-master in AEOI mode ...
1679 */
1680 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1681
1682 /*
1683 * Add it to the IO-APIC irq-routing table:
1684 */
1685 ioapic_write_entry(apic_id, pin, entry);
1686 }
1687
1688
1689 __apicdebuginit(void) print_IO_APIC(void)
1690 {
1691 int apic, i;
1692 union IO_APIC_reg_00 reg_00;
1693 union IO_APIC_reg_01 reg_01;
1694 union IO_APIC_reg_02 reg_02;
1695 union IO_APIC_reg_03 reg_03;
1696 unsigned long flags;
1697 struct irq_cfg *cfg;
1698 struct irq_desc *desc;
1699 unsigned int irq;
1700
1701 if (apic_verbosity == APIC_QUIET)
1702 return;
1703
1704 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1705 for (i = 0; i < nr_ioapics; i++)
1706 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1707 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1708
1709 /*
1710 * We are a bit conservative about what we expect. We have to
1711 * know about every hardware change ASAP.
1712 */
1713 printk(KERN_INFO "testing the IO APIC.......................\n");
1714
1715 for (apic = 0; apic < nr_ioapics; apic++) {
1716
1717 spin_lock_irqsave(&ioapic_lock, flags);
1718 reg_00.raw = io_apic_read(apic, 0);
1719 reg_01.raw = io_apic_read(apic, 1);
1720 if (reg_01.bits.version >= 0x10)
1721 reg_02.raw = io_apic_read(apic, 2);
1722 if (reg_01.bits.version >= 0x20)
1723 reg_03.raw = io_apic_read(apic, 3);
1724 spin_unlock_irqrestore(&ioapic_lock, flags);
1725
1726 printk("\n");
1727 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1728 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1729 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1730 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1731 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1732
1733 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1734 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1735
1736 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1737 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1738
1739 /*
1740 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1741 * but the value of reg_02 is read as the previous read register
1742 * value, so ignore it if reg_02 == reg_01.
1743 */
1744 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1745 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1746 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1747 }
1748
1749 /*
1750 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1751 * or reg_03, but the value of reg_0[23] is read as the previous read
1752 * register value, so ignore it if reg_03 == reg_0[12].
1753 */
1754 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1755 reg_03.raw != reg_01.raw) {
1756 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1757 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1758 }
1759
1760 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1761
1762 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1763 " Stat Dmod Deli Vect: \n");
1764
1765 for (i = 0; i <= reg_01.bits.entries; i++) {
1766 struct IO_APIC_route_entry entry;
1767
1768 entry = ioapic_read_entry(apic, i);
1769
1770 printk(KERN_DEBUG " %02x %03X ",
1771 i,
1772 entry.dest
1773 );
1774
1775 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1776 entry.mask,
1777 entry.trigger,
1778 entry.irr,
1779 entry.polarity,
1780 entry.delivery_status,
1781 entry.dest_mode,
1782 entry.delivery_mode,
1783 entry.vector
1784 );
1785 }
1786 }
1787 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1788 for_each_irq_desc(irq, desc) {
1789 struct irq_pin_list *entry;
1790
1791 cfg = desc->chip_data;
1792 entry = cfg->irq_2_pin;
1793 if (!entry)
1794 continue;
1795 printk(KERN_DEBUG "IRQ%d ", irq);
1796 for (;;) {
1797 printk("-> %d:%d", entry->apic, entry->pin);
1798 if (!entry->next)
1799 break;
1800 entry = entry->next;
1801 }
1802 printk("\n");
1803 }
1804
1805 printk(KERN_INFO ".................................... done.\n");
1806
1807 return;
1808 }
1809
1810 __apicdebuginit(void) print_APIC_bitfield(int base)
1811 {
1812 unsigned int v;
1813 int i, j;
1814
1815 if (apic_verbosity == APIC_QUIET)
1816 return;
1817
1818 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1819 for (i = 0; i < 8; i++) {
1820 v = apic_read(base + i*0x10);
1821 for (j = 0; j < 32; j++) {
1822 if (v & (1<<j))
1823 printk("1");
1824 else
1825 printk("0");
1826 }
1827 printk("\n");
1828 }
1829 }
1830
1831 __apicdebuginit(void) print_local_APIC(void *dummy)
1832 {
1833 unsigned int v, ver, maxlvt;
1834 u64 icr;
1835
1836 if (apic_verbosity == APIC_QUIET)
1837 return;
1838
1839 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1840 smp_processor_id(), hard_smp_processor_id());
1841 v = apic_read(APIC_ID);
1842 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1843 v = apic_read(APIC_LVR);
1844 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1845 ver = GET_APIC_VERSION(v);
1846 maxlvt = lapic_get_maxlvt();
1847
1848 v = apic_read(APIC_TASKPRI);
1849 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1850
1851 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1852 if (!APIC_XAPIC(ver)) {
1853 v = apic_read(APIC_ARBPRI);
1854 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1855 v & APIC_ARBPRI_MASK);
1856 }
1857 v = apic_read(APIC_PROCPRI);
1858 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1859 }
1860
1861 /*
1862 * Remote read supported only in the 82489DX and local APIC for
1863 * Pentium processors.
1864 */
1865 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1866 v = apic_read(APIC_RRR);
1867 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1868 }
1869
1870 v = apic_read(APIC_LDR);
1871 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1872 if (!x2apic_enabled()) {
1873 v = apic_read(APIC_DFR);
1874 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1875 }
1876 v = apic_read(APIC_SPIV);
1877 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1878
1879 printk(KERN_DEBUG "... APIC ISR field:\n");
1880 print_APIC_bitfield(APIC_ISR);
1881 printk(KERN_DEBUG "... APIC TMR field:\n");
1882 print_APIC_bitfield(APIC_TMR);
1883 printk(KERN_DEBUG "... APIC IRR field:\n");
1884 print_APIC_bitfield(APIC_IRR);
1885
1886 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1887 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1888 apic_write(APIC_ESR, 0);
1889
1890 v = apic_read(APIC_ESR);
1891 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1892 }
1893
1894 icr = apic_icr_read();
1895 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1896 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1897
1898 v = apic_read(APIC_LVTT);
1899 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1900
1901 if (maxlvt > 3) { /* PC is LVT#4. */
1902 v = apic_read(APIC_LVTPC);
1903 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1904 }
1905 v = apic_read(APIC_LVT0);
1906 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1907 v = apic_read(APIC_LVT1);
1908 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1909
1910 if (maxlvt > 2) { /* ERR is LVT#3. */
1911 v = apic_read(APIC_LVTERR);
1912 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1913 }
1914
1915 v = apic_read(APIC_TMICT);
1916 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1917 v = apic_read(APIC_TMCCT);
1918 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1919 v = apic_read(APIC_TDCR);
1920 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1921 printk("\n");
1922 }
1923
1924 __apicdebuginit(void) print_all_local_APICs(void)
1925 {
1926 int cpu;
1927
1928 preempt_disable();
1929 for_each_online_cpu(cpu)
1930 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1931 preempt_enable();
1932 }
1933
1934 __apicdebuginit(void) print_PIC(void)
1935 {
1936 unsigned int v;
1937 unsigned long flags;
1938
1939 if (apic_verbosity == APIC_QUIET)
1940 return;
1941
1942 printk(KERN_DEBUG "\nprinting PIC contents\n");
1943
1944 spin_lock_irqsave(&i8259A_lock, flags);
1945
1946 v = inb(0xa1) << 8 | inb(0x21);
1947 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1948
1949 v = inb(0xa0) << 8 | inb(0x20);
1950 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1951
1952 outb(0x0b,0xa0);
1953 outb(0x0b,0x20);
1954 v = inb(0xa0) << 8 | inb(0x20);
1955 outb(0x0a,0xa0);
1956 outb(0x0a,0x20);
1957
1958 spin_unlock_irqrestore(&i8259A_lock, flags);
1959
1960 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1961
1962 v = inb(0x4d1) << 8 | inb(0x4d0);
1963 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1964 }
1965
1966 __apicdebuginit(int) print_all_ICs(void)
1967 {
1968 print_PIC();
1969 print_all_local_APICs();
1970 print_IO_APIC();
1971
1972 return 0;
1973 }
1974
1975 fs_initcall(print_all_ICs);
1976
1977
1978 /* Where if anywhere is the i8259 connect in external int mode */
1979 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1980
1981 void __init enable_IO_APIC(void)
1982 {
1983 union IO_APIC_reg_01 reg_01;
1984 int i8259_apic, i8259_pin;
1985 int apic;
1986 unsigned long flags;
1987
1988 #ifdef CONFIG_X86_32
1989 int i;
1990 if (!pirqs_enabled)
1991 for (i = 0; i < MAX_PIRQS; i++)
1992 pirq_entries[i] = -1;
1993 #endif
1994
1995 /*
1996 * The number of IO-APIC IRQ registers (== #pins):
1997 */
1998 for (apic = 0; apic < nr_ioapics; apic++) {
1999 spin_lock_irqsave(&ioapic_lock, flags);
2000 reg_01.raw = io_apic_read(apic, 1);
2001 spin_unlock_irqrestore(&ioapic_lock, flags);
2002 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2003 }
2004 for(apic = 0; apic < nr_ioapics; apic++) {
2005 int pin;
2006 /* See if any of the pins is in ExtINT mode */
2007 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2008 struct IO_APIC_route_entry entry;
2009 entry = ioapic_read_entry(apic, pin);
2010
2011 /* If the interrupt line is enabled and in ExtInt mode
2012 * I have found the pin where the i8259 is connected.
2013 */
2014 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2015 ioapic_i8259.apic = apic;
2016 ioapic_i8259.pin = pin;
2017 goto found_i8259;
2018 }
2019 }
2020 }
2021 found_i8259:
2022 /* Look to see what if the MP table has reported the ExtINT */
2023 /* If we could not find the appropriate pin by looking at the ioapic
2024 * the i8259 probably is not connected the ioapic but give the
2025 * mptable a chance anyway.
2026 */
2027 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2028 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2029 /* Trust the MP table if nothing is setup in the hardware */
2030 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2031 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2032 ioapic_i8259.pin = i8259_pin;
2033 ioapic_i8259.apic = i8259_apic;
2034 }
2035 /* Complain if the MP table and the hardware disagree */
2036 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2037 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2038 {
2039 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2040 }
2041
2042 /*
2043 * Do not trust the IO-APIC being empty at bootup
2044 */
2045 clear_IO_APIC();
2046 }
2047
2048 /*
2049 * Not an __init, needed by the reboot code
2050 */
2051 void disable_IO_APIC(void)
2052 {
2053 /*
2054 * Clear the IO-APIC before rebooting:
2055 */
2056 clear_IO_APIC();
2057
2058 /*
2059 * If the i8259 is routed through an IOAPIC
2060 * Put that IOAPIC in virtual wire mode
2061 * so legacy interrupts can be delivered.
2062 */
2063 if (ioapic_i8259.pin != -1) {
2064 struct IO_APIC_route_entry entry;
2065
2066 memset(&entry, 0, sizeof(entry));
2067 entry.mask = 0; /* Enabled */
2068 entry.trigger = 0; /* Edge */
2069 entry.irr = 0;
2070 entry.polarity = 0; /* High */
2071 entry.delivery_status = 0;
2072 entry.dest_mode = 0; /* Physical */
2073 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2074 entry.vector = 0;
2075 entry.dest = read_apic_id();
2076
2077 /*
2078 * Add it to the IO-APIC irq-routing table:
2079 */
2080 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2081 }
2082
2083 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2084 }
2085
2086 #ifdef CONFIG_X86_32
2087 /*
2088 * function to set the IO-APIC physical IDs based on the
2089 * values stored in the MPC table.
2090 *
2091 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2092 */
2093
2094 static void __init setup_ioapic_ids_from_mpc(void)
2095 {
2096 union IO_APIC_reg_00 reg_00;
2097 physid_mask_t phys_id_present_map;
2098 int apic_id;
2099 int i;
2100 unsigned char old_id;
2101 unsigned long flags;
2102
2103 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2104 return;
2105
2106 /*
2107 * Don't check I/O APIC IDs for xAPIC systems. They have
2108 * no meaning without the serial APIC bus.
2109 */
2110 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2111 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2112 return;
2113 /*
2114 * This is broken; anything with a real cpu count has to
2115 * circumvent this idiocy regardless.
2116 */
2117 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2118
2119 /*
2120 * Set the IOAPIC ID to the value stored in the MPC table.
2121 */
2122 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2123
2124 /* Read the register 0 value */
2125 spin_lock_irqsave(&ioapic_lock, flags);
2126 reg_00.raw = io_apic_read(apic_id, 0);
2127 spin_unlock_irqrestore(&ioapic_lock, flags);
2128
2129 old_id = mp_ioapics[apic_id].apicid;
2130
2131 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2132 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2133 apic_id, mp_ioapics[apic_id].apicid);
2134 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2135 reg_00.bits.ID);
2136 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2137 }
2138
2139 /*
2140 * Sanity check, is the ID really free? Every APIC in a
2141 * system must have a unique ID or we get lots of nice
2142 * 'stuck on smp_invalidate_needed IPI wait' messages.
2143 */
2144 if (apic->check_apicid_used(phys_id_present_map,
2145 mp_ioapics[apic_id].apicid)) {
2146 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2147 apic_id, mp_ioapics[apic_id].apicid);
2148 for (i = 0; i < get_physical_broadcast(); i++)
2149 if (!physid_isset(i, phys_id_present_map))
2150 break;
2151 if (i >= get_physical_broadcast())
2152 panic("Max APIC ID exceeded!\n");
2153 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2154 i);
2155 physid_set(i, phys_id_present_map);
2156 mp_ioapics[apic_id].apicid = i;
2157 } else {
2158 physid_mask_t tmp;
2159 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2160 apic_printk(APIC_VERBOSE, "Setting %d in the "
2161 "phys_id_present_map\n",
2162 mp_ioapics[apic_id].apicid);
2163 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2164 }
2165
2166
2167 /*
2168 * We need to adjust the IRQ routing table
2169 * if the ID changed.
2170 */
2171 if (old_id != mp_ioapics[apic_id].apicid)
2172 for (i = 0; i < mp_irq_entries; i++)
2173 if (mp_irqs[i].dstapic == old_id)
2174 mp_irqs[i].dstapic
2175 = mp_ioapics[apic_id].apicid;
2176
2177 /*
2178 * Read the right value from the MPC table and
2179 * write it into the ID register.
2180 */
2181 apic_printk(APIC_VERBOSE, KERN_INFO
2182 "...changing IO-APIC physical APIC ID to %d ...",
2183 mp_ioapics[apic_id].apicid);
2184
2185 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2186 spin_lock_irqsave(&ioapic_lock, flags);
2187 io_apic_write(apic_id, 0, reg_00.raw);
2188 spin_unlock_irqrestore(&ioapic_lock, flags);
2189
2190 /*
2191 * Sanity check
2192 */
2193 spin_lock_irqsave(&ioapic_lock, flags);
2194 reg_00.raw = io_apic_read(apic_id, 0);
2195 spin_unlock_irqrestore(&ioapic_lock, flags);
2196 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2197 printk("could not set ID!\n");
2198 else
2199 apic_printk(APIC_VERBOSE, " ok.\n");
2200 }
2201 }
2202 #endif
2203
2204 int no_timer_check __initdata;
2205
2206 static int __init notimercheck(char *s)
2207 {
2208 no_timer_check = 1;
2209 return 1;
2210 }
2211 __setup("no_timer_check", notimercheck);
2212
2213 /*
2214 * There is a nasty bug in some older SMP boards, their mptable lies
2215 * about the timer IRQ. We do the following to work around the situation:
2216 *
2217 * - timer IRQ defaults to IO-APIC IRQ
2218 * - if this function detects that timer IRQs are defunct, then we fall
2219 * back to ISA timer IRQs
2220 */
2221 static int __init timer_irq_works(void)
2222 {
2223 unsigned long t1 = jiffies;
2224 unsigned long flags;
2225
2226 if (no_timer_check)
2227 return 1;
2228
2229 local_save_flags(flags);
2230 local_irq_enable();
2231 /* Let ten ticks pass... */
2232 mdelay((10 * 1000) / HZ);
2233 local_irq_restore(flags);
2234
2235 /*
2236 * Expect a few ticks at least, to be sure some possible
2237 * glue logic does not lock up after one or two first
2238 * ticks in a non-ExtINT mode. Also the local APIC
2239 * might have cached one ExtINT interrupt. Finally, at
2240 * least one tick may be lost due to delays.
2241 */
2242
2243 /* jiffies wrap? */
2244 if (time_after(jiffies, t1 + 4))
2245 return 1;
2246 return 0;
2247 }
2248
2249 /*
2250 * In the SMP+IOAPIC case it might happen that there are an unspecified
2251 * number of pending IRQ events unhandled. These cases are very rare,
2252 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2253 * better to do it this way as thus we do not have to be aware of
2254 * 'pending' interrupts in the IRQ path, except at this point.
2255 */
2256 /*
2257 * Edge triggered needs to resend any interrupt
2258 * that was delayed but this is now handled in the device
2259 * independent code.
2260 */
2261
2262 /*
2263 * Starting up a edge-triggered IO-APIC interrupt is
2264 * nasty - we need to make sure that we get the edge.
2265 * If it is already asserted for some reason, we need
2266 * return 1 to indicate that is was pending.
2267 *
2268 * This is not complete - we should be able to fake
2269 * an edge even if it isn't on the 8259A...
2270 */
2271
2272 static unsigned int startup_ioapic_irq(unsigned int irq)
2273 {
2274 int was_pending = 0;
2275 unsigned long flags;
2276 struct irq_cfg *cfg;
2277
2278 spin_lock_irqsave(&ioapic_lock, flags);
2279 if (irq < NR_IRQS_LEGACY) {
2280 disable_8259A_irq(irq);
2281 if (i8259A_irq_pending(irq))
2282 was_pending = 1;
2283 }
2284 cfg = irq_cfg(irq);
2285 __unmask_IO_APIC_irq(cfg);
2286 spin_unlock_irqrestore(&ioapic_lock, flags);
2287
2288 return was_pending;
2289 }
2290
2291 #ifdef CONFIG_X86_64
2292 static int ioapic_retrigger_irq(unsigned int irq)
2293 {
2294
2295 struct irq_cfg *cfg = irq_cfg(irq);
2296 unsigned long flags;
2297
2298 spin_lock_irqsave(&vector_lock, flags);
2299 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2300 spin_unlock_irqrestore(&vector_lock, flags);
2301
2302 return 1;
2303 }
2304 #else
2305 static int ioapic_retrigger_irq(unsigned int irq)
2306 {
2307 apic->send_IPI_self(irq_cfg(irq)->vector);
2308
2309 return 1;
2310 }
2311 #endif
2312
2313 /*
2314 * Level and edge triggered IO-APIC interrupts need different handling,
2315 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2316 * handled with the level-triggered descriptor, but that one has slightly
2317 * more overhead. Level-triggered interrupts cannot be handled with the
2318 * edge-triggered handler, without risking IRQ storms and other ugly
2319 * races.
2320 */
2321
2322 #ifdef CONFIG_SMP
2323
2324 #ifdef CONFIG_INTR_REMAP
2325 static void ir_irq_migration(struct work_struct *work);
2326
2327 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2328
2329 /*
2330 * Migrate the IO-APIC irq in the presence of intr-remapping.
2331 *
2332 * For edge triggered, irq migration is a simple atomic update(of vector
2333 * and cpu destination) of IRTE and flush the hardware cache.
2334 *
2335 * For level triggered, we need to modify the io-apic RTE aswell with the update
2336 * vector information, along with modifying IRTE with vector and destination.
2337 * So irq migration for level triggered is little bit more complex compared to
2338 * edge triggered migration. But the good news is, we use the same algorithm
2339 * for level triggered migration as we have today, only difference being,
2340 * we now initiate the irq migration from process context instead of the
2341 * interrupt context.
2342 *
2343 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2344 * suppression) to the IO-APIC, level triggered irq migration will also be
2345 * as simple as edge triggered migration and we can do the irq migration
2346 * with a simple atomic update to IO-APIC RTE.
2347 */
2348 static void
2349 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2350 {
2351 struct irq_cfg *cfg;
2352 struct irte irte;
2353 int modify_ioapic_rte;
2354 unsigned int dest;
2355 unsigned long flags;
2356 unsigned int irq;
2357
2358 if (!cpumask_intersects(mask, cpu_online_mask))
2359 return;
2360
2361 irq = desc->irq;
2362 if (get_irte(irq, &irte))
2363 return;
2364
2365 cfg = desc->chip_data;
2366 if (assign_irq_vector(irq, cfg, mask))
2367 return;
2368
2369 set_extra_move_desc(desc, mask);
2370
2371 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2372
2373 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2374 if (modify_ioapic_rte) {
2375 spin_lock_irqsave(&ioapic_lock, flags);
2376 __target_IO_APIC_irq(irq, dest, cfg);
2377 spin_unlock_irqrestore(&ioapic_lock, flags);
2378 }
2379
2380 irte.vector = cfg->vector;
2381 irte.dest_id = IRTE_DEST(dest);
2382
2383 /*
2384 * Modified the IRTE and flushes the Interrupt entry cache.
2385 */
2386 modify_irte(irq, &irte);
2387
2388 if (cfg->move_in_progress)
2389 send_cleanup_vector(cfg);
2390
2391 cpumask_copy(desc->affinity, mask);
2392 }
2393
2394 static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2395 {
2396 int ret = -1;
2397 struct irq_cfg *cfg = desc->chip_data;
2398
2399 mask_IO_APIC_irq_desc(desc);
2400
2401 if (io_apic_level_ack_pending(cfg)) {
2402 /*
2403 * Interrupt in progress. Migrating irq now will change the
2404 * vector information in the IO-APIC RTE and that will confuse
2405 * the EOI broadcast performed by cpu.
2406 * So, delay the irq migration to the next instance.
2407 */
2408 schedule_delayed_work(&ir_migration_work, 1);
2409 goto unmask;
2410 }
2411
2412 /* everthing is clear. we have right of way */
2413 migrate_ioapic_irq_desc(desc, desc->pending_mask);
2414
2415 ret = 0;
2416 desc->status &= ~IRQ_MOVE_PENDING;
2417 cpumask_clear(desc->pending_mask);
2418
2419 unmask:
2420 unmask_IO_APIC_irq_desc(desc);
2421
2422 return ret;
2423 }
2424
2425 static void ir_irq_migration(struct work_struct *work)
2426 {
2427 unsigned int irq;
2428 struct irq_desc *desc;
2429
2430 for_each_irq_desc(irq, desc) {
2431 if (desc->status & IRQ_MOVE_PENDING) {
2432 unsigned long flags;
2433
2434 spin_lock_irqsave(&desc->lock, flags);
2435 if (!desc->chip->set_affinity ||
2436 !(desc->status & IRQ_MOVE_PENDING)) {
2437 desc->status &= ~IRQ_MOVE_PENDING;
2438 spin_unlock_irqrestore(&desc->lock, flags);
2439 continue;
2440 }
2441
2442 desc->chip->set_affinity(irq, desc->pending_mask);
2443 spin_unlock_irqrestore(&desc->lock, flags);
2444 }
2445 }
2446 }
2447
2448 /*
2449 * Migrates the IRQ destination in the process context.
2450 */
2451 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2452 const struct cpumask *mask)
2453 {
2454 if (desc->status & IRQ_LEVEL) {
2455 desc->status |= IRQ_MOVE_PENDING;
2456 cpumask_copy(desc->pending_mask, mask);
2457 migrate_irq_remapped_level_desc(desc);
2458 return;
2459 }
2460
2461 migrate_ioapic_irq_desc(desc, mask);
2462 }
2463 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2464 const struct cpumask *mask)
2465 {
2466 struct irq_desc *desc = irq_to_desc(irq);
2467
2468 set_ir_ioapic_affinity_irq_desc(desc, mask);
2469 }
2470 #endif
2471
2472 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2473 {
2474 unsigned vector, me;
2475
2476 ack_APIC_irq();
2477 exit_idle();
2478 irq_enter();
2479
2480 me = smp_processor_id();
2481 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2482 unsigned int irq;
2483 struct irq_desc *desc;
2484 struct irq_cfg *cfg;
2485 irq = __get_cpu_var(vector_irq)[vector];
2486
2487 if (irq == -1)
2488 continue;
2489
2490 desc = irq_to_desc(irq);
2491 if (!desc)
2492 continue;
2493
2494 cfg = irq_cfg(irq);
2495 spin_lock(&desc->lock);
2496 if (!cfg->move_cleanup_count)
2497 goto unlock;
2498
2499 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2500 goto unlock;
2501
2502 __get_cpu_var(vector_irq)[vector] = -1;
2503 cfg->move_cleanup_count--;
2504 unlock:
2505 spin_unlock(&desc->lock);
2506 }
2507
2508 irq_exit();
2509 }
2510
2511 static void irq_complete_move(struct irq_desc **descp)
2512 {
2513 struct irq_desc *desc = *descp;
2514 struct irq_cfg *cfg = desc->chip_data;
2515 unsigned vector, me;
2516
2517 if (likely(!cfg->move_in_progress)) {
2518 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2519 if (likely(!cfg->move_desc_pending))
2520 return;
2521
2522 /* domain has not changed, but affinity did */
2523 me = smp_processor_id();
2524 if (cpumask_test_cpu(me, desc->affinity)) {
2525 *descp = desc = move_irq_desc(desc, me);
2526 /* get the new one */
2527 cfg = desc->chip_data;
2528 cfg->move_desc_pending = 0;
2529 }
2530 #endif
2531 return;
2532 }
2533
2534 vector = ~get_irq_regs()->orig_ax;
2535 me = smp_processor_id();
2536 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2537 *descp = desc = move_irq_desc(desc, me);
2538 /* get the new one */
2539 cfg = desc->chip_data;
2540 #endif
2541
2542 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2543 send_cleanup_vector(cfg);
2544 }
2545 #else
2546 static inline void irq_complete_move(struct irq_desc **descp) {}
2547 #endif
2548
2549 #ifdef CONFIG_INTR_REMAP
2550 static void ack_x2apic_level(unsigned int irq)
2551 {
2552 ack_x2APIC_irq();
2553 }
2554
2555 static void ack_x2apic_edge(unsigned int irq)
2556 {
2557 ack_x2APIC_irq();
2558 }
2559
2560 #endif
2561
2562 static void ack_apic_edge(unsigned int irq)
2563 {
2564 struct irq_desc *desc = irq_to_desc(irq);
2565
2566 irq_complete_move(&desc);
2567 move_native_irq(irq);
2568 ack_APIC_irq();
2569 }
2570
2571 atomic_t irq_mis_count;
2572
2573 static void ack_apic_level(unsigned int irq)
2574 {
2575 struct irq_desc *desc = irq_to_desc(irq);
2576
2577 #ifdef CONFIG_X86_32
2578 unsigned long v;
2579 int i;
2580 #endif
2581 struct irq_cfg *cfg;
2582 int do_unmask_irq = 0;
2583
2584 irq_complete_move(&desc);
2585 #ifdef CONFIG_GENERIC_PENDING_IRQ
2586 /* If we are moving the irq we need to mask it */
2587 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2588 do_unmask_irq = 1;
2589 mask_IO_APIC_irq_desc(desc);
2590 }
2591 #endif
2592
2593 #ifdef CONFIG_X86_32
2594 /*
2595 * It appears there is an erratum which affects at least version 0x11
2596 * of I/O APIC (that's the 82093AA and cores integrated into various
2597 * chipsets). Under certain conditions a level-triggered interrupt is
2598 * erroneously delivered as edge-triggered one but the respective IRR
2599 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2600 * message but it will never arrive and further interrupts are blocked
2601 * from the source. The exact reason is so far unknown, but the
2602 * phenomenon was observed when two consecutive interrupt requests
2603 * from a given source get delivered to the same CPU and the source is
2604 * temporarily disabled in between.
2605 *
2606 * A workaround is to simulate an EOI message manually. We achieve it
2607 * by setting the trigger mode to edge and then to level when the edge
2608 * trigger mode gets detected in the TMR of a local APIC for a
2609 * level-triggered interrupt. We mask the source for the time of the
2610 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2611 * The idea is from Manfred Spraul. --macro
2612 */
2613 cfg = desc->chip_data;
2614 i = cfg->vector;
2615
2616 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2617 #endif
2618
2619 /*
2620 * We must acknowledge the irq before we move it or the acknowledge will
2621 * not propagate properly.
2622 */
2623 ack_APIC_irq();
2624
2625 /* Now we can move and renable the irq */
2626 if (unlikely(do_unmask_irq)) {
2627 /* Only migrate the irq if the ack has been received.
2628 *
2629 * On rare occasions the broadcast level triggered ack gets
2630 * delayed going to ioapics, and if we reprogram the
2631 * vector while Remote IRR is still set the irq will never
2632 * fire again.
2633 *
2634 * To prevent this scenario we read the Remote IRR bit
2635 * of the ioapic. This has two effects.
2636 * - On any sane system the read of the ioapic will
2637 * flush writes (and acks) going to the ioapic from
2638 * this cpu.
2639 * - We get to see if the ACK has actually been delivered.
2640 *
2641 * Based on failed experiments of reprogramming the
2642 * ioapic entry from outside of irq context starting
2643 * with masking the ioapic entry and then polling until
2644 * Remote IRR was clear before reprogramming the
2645 * ioapic I don't trust the Remote IRR bit to be
2646 * completey accurate.
2647 *
2648 * However there appears to be no other way to plug
2649 * this race, so if the Remote IRR bit is not
2650 * accurate and is causing problems then it is a hardware bug
2651 * and you can go talk to the chipset vendor about it.
2652 */
2653 cfg = desc->chip_data;
2654 if (!io_apic_level_ack_pending(cfg))
2655 move_masked_irq(irq);
2656 unmask_IO_APIC_irq_desc(desc);
2657 }
2658
2659 #ifdef CONFIG_X86_32
2660 if (!(v & (1 << (i & 0x1f)))) {
2661 atomic_inc(&irq_mis_count);
2662 spin_lock(&ioapic_lock);
2663 __mask_and_edge_IO_APIC_irq(cfg);
2664 __unmask_and_level_IO_APIC_irq(cfg);
2665 spin_unlock(&ioapic_lock);
2666 }
2667 #endif
2668 }
2669
2670 static struct irq_chip ioapic_chip __read_mostly = {
2671 .name = "IO-APIC",
2672 .startup = startup_ioapic_irq,
2673 .mask = mask_IO_APIC_irq,
2674 .unmask = unmask_IO_APIC_irq,
2675 .ack = ack_apic_edge,
2676 .eoi = ack_apic_level,
2677 #ifdef CONFIG_SMP
2678 .set_affinity = set_ioapic_affinity_irq,
2679 #endif
2680 .retrigger = ioapic_retrigger_irq,
2681 };
2682
2683 #ifdef CONFIG_INTR_REMAP
2684 static struct irq_chip ir_ioapic_chip __read_mostly = {
2685 .name = "IR-IO-APIC",
2686 .startup = startup_ioapic_irq,
2687 .mask = mask_IO_APIC_irq,
2688 .unmask = unmask_IO_APIC_irq,
2689 .ack = ack_x2apic_edge,
2690 .eoi = ack_x2apic_level,
2691 #ifdef CONFIG_SMP
2692 .set_affinity = set_ir_ioapic_affinity_irq,
2693 #endif
2694 .retrigger = ioapic_retrigger_irq,
2695 };
2696 #endif
2697
2698 static inline void init_IO_APIC_traps(void)
2699 {
2700 int irq;
2701 struct irq_desc *desc;
2702 struct irq_cfg *cfg;
2703
2704 /*
2705 * NOTE! The local APIC isn't very good at handling
2706 * multiple interrupts at the same interrupt level.
2707 * As the interrupt level is determined by taking the
2708 * vector number and shifting that right by 4, we
2709 * want to spread these out a bit so that they don't
2710 * all fall in the same interrupt level.
2711 *
2712 * Also, we've got to be careful not to trash gate
2713 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2714 */
2715 for_each_irq_desc(irq, desc) {
2716 cfg = desc->chip_data;
2717 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2718 /*
2719 * Hmm.. We don't have an entry for this,
2720 * so default to an old-fashioned 8259
2721 * interrupt if we can..
2722 */
2723 if (irq < NR_IRQS_LEGACY)
2724 make_8259A_irq(irq);
2725 else
2726 /* Strange. Oh, well.. */
2727 desc->chip = &no_irq_chip;
2728 }
2729 }
2730 }
2731
2732 /*
2733 * The local APIC irq-chip implementation:
2734 */
2735
2736 static void mask_lapic_irq(unsigned int irq)
2737 {
2738 unsigned long v;
2739
2740 v = apic_read(APIC_LVT0);
2741 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2742 }
2743
2744 static void unmask_lapic_irq(unsigned int irq)
2745 {
2746 unsigned long v;
2747
2748 v = apic_read(APIC_LVT0);
2749 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2750 }
2751
2752 static void ack_lapic_irq(unsigned int irq)
2753 {
2754 ack_APIC_irq();
2755 }
2756
2757 static struct irq_chip lapic_chip __read_mostly = {
2758 .name = "local-APIC",
2759 .mask = mask_lapic_irq,
2760 .unmask = unmask_lapic_irq,
2761 .ack = ack_lapic_irq,
2762 };
2763
2764 static void lapic_register_intr(int irq, struct irq_desc *desc)
2765 {
2766 desc->status &= ~IRQ_LEVEL;
2767 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2768 "edge");
2769 }
2770
2771 static void __init setup_nmi(void)
2772 {
2773 /*
2774 * Dirty trick to enable the NMI watchdog ...
2775 * We put the 8259A master into AEOI mode and
2776 * unmask on all local APICs LVT0 as NMI.
2777 *
2778 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2779 * is from Maciej W. Rozycki - so we do not have to EOI from
2780 * the NMI handler or the timer interrupt.
2781 */
2782 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2783
2784 enable_NMI_through_LVT0();
2785
2786 apic_printk(APIC_VERBOSE, " done.\n");
2787 }
2788
2789 /*
2790 * This looks a bit hackish but it's about the only one way of sending
2791 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2792 * not support the ExtINT mode, unfortunately. We need to send these
2793 * cycles as some i82489DX-based boards have glue logic that keeps the
2794 * 8259A interrupt line asserted until INTA. --macro
2795 */
2796 static inline void __init unlock_ExtINT_logic(void)
2797 {
2798 int apic, pin, i;
2799 struct IO_APIC_route_entry entry0, entry1;
2800 unsigned char save_control, save_freq_select;
2801
2802 pin = find_isa_irq_pin(8, mp_INT);
2803 if (pin == -1) {
2804 WARN_ON_ONCE(1);
2805 return;
2806 }
2807 apic = find_isa_irq_apic(8, mp_INT);
2808 if (apic == -1) {
2809 WARN_ON_ONCE(1);
2810 return;
2811 }
2812
2813 entry0 = ioapic_read_entry(apic, pin);
2814 clear_IO_APIC_pin(apic, pin);
2815
2816 memset(&entry1, 0, sizeof(entry1));
2817
2818 entry1.dest_mode = 0; /* physical delivery */
2819 entry1.mask = 0; /* unmask IRQ now */
2820 entry1.dest = hard_smp_processor_id();
2821 entry1.delivery_mode = dest_ExtINT;
2822 entry1.polarity = entry0.polarity;
2823 entry1.trigger = 0;
2824 entry1.vector = 0;
2825
2826 ioapic_write_entry(apic, pin, entry1);
2827
2828 save_control = CMOS_READ(RTC_CONTROL);
2829 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2830 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2831 RTC_FREQ_SELECT);
2832 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2833
2834 i = 100;
2835 while (i-- > 0) {
2836 mdelay(10);
2837 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2838 i -= 10;
2839 }
2840
2841 CMOS_WRITE(save_control, RTC_CONTROL);
2842 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2843 clear_IO_APIC_pin(apic, pin);
2844
2845 ioapic_write_entry(apic, pin, entry0);
2846 }
2847
2848 static int disable_timer_pin_1 __initdata;
2849 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2850 static int __init disable_timer_pin_setup(char *arg)
2851 {
2852 disable_timer_pin_1 = 1;
2853 return 0;
2854 }
2855 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2856
2857 int timer_through_8259 __initdata;
2858
2859 /*
2860 * This code may look a bit paranoid, but it's supposed to cooperate with
2861 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2862 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2863 * fanatically on his truly buggy board.
2864 *
2865 * FIXME: really need to revamp this for all platforms.
2866 */
2867 static inline void __init check_timer(void)
2868 {
2869 struct irq_desc *desc = irq_to_desc(0);
2870 struct irq_cfg *cfg = desc->chip_data;
2871 int cpu = boot_cpu_id;
2872 int apic1, pin1, apic2, pin2;
2873 unsigned long flags;
2874 unsigned int ver;
2875 int no_pin1 = 0;
2876
2877 local_irq_save(flags);
2878
2879 ver = apic_read(APIC_LVR);
2880 ver = GET_APIC_VERSION(ver);
2881
2882 /*
2883 * get/set the timer IRQ vector:
2884 */
2885 disable_8259A_irq(0);
2886 assign_irq_vector(0, cfg, apic->target_cpus());
2887
2888 /*
2889 * As IRQ0 is to be enabled in the 8259A, the virtual
2890 * wire has to be disabled in the local APIC. Also
2891 * timer interrupts need to be acknowledged manually in
2892 * the 8259A for the i82489DX when using the NMI
2893 * watchdog as that APIC treats NMIs as level-triggered.
2894 * The AEOI mode will finish them in the 8259A
2895 * automatically.
2896 */
2897 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2898 init_8259A(1);
2899 #ifdef CONFIG_X86_32
2900 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2901 #endif
2902
2903 pin1 = find_isa_irq_pin(0, mp_INT);
2904 apic1 = find_isa_irq_apic(0, mp_INT);
2905 pin2 = ioapic_i8259.pin;
2906 apic2 = ioapic_i8259.apic;
2907
2908 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2909 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2910 cfg->vector, apic1, pin1, apic2, pin2);
2911
2912 /*
2913 * Some BIOS writers are clueless and report the ExtINTA
2914 * I/O APIC input from the cascaded 8259A as the timer
2915 * interrupt input. So just in case, if only one pin
2916 * was found above, try it both directly and through the
2917 * 8259A.
2918 */
2919 if (pin1 == -1) {
2920 #ifdef CONFIG_INTR_REMAP
2921 if (intr_remapping_enabled)
2922 panic("BIOS bug: timer not connected to IO-APIC");
2923 #endif
2924 pin1 = pin2;
2925 apic1 = apic2;
2926 no_pin1 = 1;
2927 } else if (pin2 == -1) {
2928 pin2 = pin1;
2929 apic2 = apic1;
2930 }
2931
2932 if (pin1 != -1) {
2933 /*
2934 * Ok, does IRQ0 through the IOAPIC work?
2935 */
2936 if (no_pin1) {
2937 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2938 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2939 }
2940 unmask_IO_APIC_irq_desc(desc);
2941 if (timer_irq_works()) {
2942 if (nmi_watchdog == NMI_IO_APIC) {
2943 setup_nmi();
2944 enable_8259A_irq(0);
2945 }
2946 if (disable_timer_pin_1 > 0)
2947 clear_IO_APIC_pin(0, pin1);
2948 goto out;
2949 }
2950 #ifdef CONFIG_INTR_REMAP
2951 if (intr_remapping_enabled)
2952 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2953 #endif
2954 clear_IO_APIC_pin(apic1, pin1);
2955 if (!no_pin1)
2956 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2957 "8254 timer not connected to IO-APIC\n");
2958
2959 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2960 "(IRQ0) through the 8259A ...\n");
2961 apic_printk(APIC_QUIET, KERN_INFO
2962 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2963 /*
2964 * legacy devices should be connected to IO APIC #0
2965 */
2966 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2967 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2968 unmask_IO_APIC_irq_desc(desc);
2969 enable_8259A_irq(0);
2970 if (timer_irq_works()) {
2971 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2972 timer_through_8259 = 1;
2973 if (nmi_watchdog == NMI_IO_APIC) {
2974 disable_8259A_irq(0);
2975 setup_nmi();
2976 enable_8259A_irq(0);
2977 }
2978 goto out;
2979 }
2980 /*
2981 * Cleanup, just in case ...
2982 */
2983 disable_8259A_irq(0);
2984 clear_IO_APIC_pin(apic2, pin2);
2985 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2986 }
2987
2988 if (nmi_watchdog == NMI_IO_APIC) {
2989 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2990 "through the IO-APIC - disabling NMI Watchdog!\n");
2991 nmi_watchdog = NMI_NONE;
2992 }
2993 #ifdef CONFIG_X86_32
2994 timer_ack = 0;
2995 #endif
2996
2997 apic_printk(APIC_QUIET, KERN_INFO
2998 "...trying to set up timer as Virtual Wire IRQ...\n");
2999
3000 lapic_register_intr(0, desc);
3001 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3002 enable_8259A_irq(0);
3003
3004 if (timer_irq_works()) {
3005 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3006 goto out;
3007 }
3008 disable_8259A_irq(0);
3009 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3010 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3011
3012 apic_printk(APIC_QUIET, KERN_INFO
3013 "...trying to set up timer as ExtINT IRQ...\n");
3014
3015 init_8259A(0);
3016 make_8259A_irq(0);
3017 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3018
3019 unlock_ExtINT_logic();
3020
3021 if (timer_irq_works()) {
3022 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3023 goto out;
3024 }
3025 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3026 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3027 "report. Then try booting with the 'noapic' option.\n");
3028 out:
3029 local_irq_restore(flags);
3030 }
3031
3032 /*
3033 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3034 * to devices. However there may be an I/O APIC pin available for
3035 * this interrupt regardless. The pin may be left unconnected, but
3036 * typically it will be reused as an ExtINT cascade interrupt for
3037 * the master 8259A. In the MPS case such a pin will normally be
3038 * reported as an ExtINT interrupt in the MP table. With ACPI
3039 * there is no provision for ExtINT interrupts, and in the absence
3040 * of an override it would be treated as an ordinary ISA I/O APIC
3041 * interrupt, that is edge-triggered and unmasked by default. We
3042 * used to do this, but it caused problems on some systems because
3043 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3044 * the same ExtINT cascade interrupt to drive the local APIC of the
3045 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3046 * the I/O APIC in all cases now. No actual device should request
3047 * it anyway. --macro
3048 */
3049 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3050
3051 void __init setup_IO_APIC(void)
3052 {
3053
3054 #ifdef CONFIG_X86_32
3055 enable_IO_APIC();
3056 #else
3057 /*
3058 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3059 */
3060 #endif
3061
3062 io_apic_irqs = ~PIC_IRQS;
3063
3064 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3065 /*
3066 * Set up IO-APIC IRQ routing.
3067 */
3068 #ifdef CONFIG_X86_32
3069 if (!acpi_ioapic)
3070 setup_ioapic_ids_from_mpc();
3071 #endif
3072 sync_Arb_IDs();
3073 setup_IO_APIC_irqs();
3074 init_IO_APIC_traps();
3075 check_timer();
3076 }
3077
3078 /*
3079 * Called after all the initialization is done. If we didnt find any
3080 * APIC bugs then we can allow the modify fast path
3081 */
3082
3083 static int __init io_apic_bug_finalize(void)
3084 {
3085 if (sis_apic_bug == -1)
3086 sis_apic_bug = 0;
3087 return 0;
3088 }
3089
3090 late_initcall(io_apic_bug_finalize);
3091
3092 struct sysfs_ioapic_data {
3093 struct sys_device dev;
3094 struct IO_APIC_route_entry entry[0];
3095 };
3096 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3097
3098 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3099 {
3100 struct IO_APIC_route_entry *entry;
3101 struct sysfs_ioapic_data *data;
3102 int i;
3103
3104 data = container_of(dev, struct sysfs_ioapic_data, dev);
3105 entry = data->entry;
3106 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3107 *entry = ioapic_read_entry(dev->id, i);
3108
3109 return 0;
3110 }
3111
3112 static int ioapic_resume(struct sys_device *dev)
3113 {
3114 struct IO_APIC_route_entry *entry;
3115 struct sysfs_ioapic_data *data;
3116 unsigned long flags;
3117 union IO_APIC_reg_00 reg_00;
3118 int i;
3119
3120 data = container_of(dev, struct sysfs_ioapic_data, dev);
3121 entry = data->entry;
3122
3123 spin_lock_irqsave(&ioapic_lock, flags);
3124 reg_00.raw = io_apic_read(dev->id, 0);
3125 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3126 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3127 io_apic_write(dev->id, 0, reg_00.raw);
3128 }
3129 spin_unlock_irqrestore(&ioapic_lock, flags);
3130 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3131 ioapic_write_entry(dev->id, i, entry[i]);
3132
3133 return 0;
3134 }
3135
3136 static struct sysdev_class ioapic_sysdev_class = {
3137 .name = "ioapic",
3138 .suspend = ioapic_suspend,
3139 .resume = ioapic_resume,
3140 };
3141
3142 static int __init ioapic_init_sysfs(void)
3143 {
3144 struct sys_device * dev;
3145 int i, size, error;
3146
3147 error = sysdev_class_register(&ioapic_sysdev_class);
3148 if (error)
3149 return error;
3150
3151 for (i = 0; i < nr_ioapics; i++ ) {
3152 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3153 * sizeof(struct IO_APIC_route_entry);
3154 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3155 if (!mp_ioapic_data[i]) {
3156 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3157 continue;
3158 }
3159 dev = &mp_ioapic_data[i]->dev;
3160 dev->id = i;
3161 dev->cls = &ioapic_sysdev_class;
3162 error = sysdev_register(dev);
3163 if (error) {
3164 kfree(mp_ioapic_data[i]);
3165 mp_ioapic_data[i] = NULL;
3166 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3167 continue;
3168 }
3169 }
3170
3171 return 0;
3172 }
3173
3174 device_initcall(ioapic_init_sysfs);
3175
3176 /*
3177 * Dynamic irq allocate and deallocation
3178 */
3179 unsigned int create_irq_nr(unsigned int irq_want)
3180 {
3181 /* Allocate an unused irq */
3182 unsigned int irq;
3183 unsigned int new;
3184 unsigned long flags;
3185 struct irq_cfg *cfg_new = NULL;
3186 int cpu = boot_cpu_id;
3187 struct irq_desc *desc_new = NULL;
3188
3189 irq = 0;
3190 spin_lock_irqsave(&vector_lock, flags);
3191 for (new = irq_want; new < nr_irqs; new++) {
3192 if (platform_legacy_irq(new))
3193 continue;
3194
3195 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3196 if (!desc_new) {
3197 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3198 continue;
3199 }
3200 cfg_new = desc_new->chip_data;
3201
3202 if (cfg_new->vector != 0)
3203 continue;
3204 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3205 irq = new;
3206 break;
3207 }
3208 spin_unlock_irqrestore(&vector_lock, flags);
3209
3210 if (irq > 0) {
3211 dynamic_irq_init(irq);
3212 /* restore it, in case dynamic_irq_init clear it */
3213 if (desc_new)
3214 desc_new->chip_data = cfg_new;
3215 }
3216 return irq;
3217 }
3218
3219 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3220 int create_irq(void)
3221 {
3222 unsigned int irq_want;
3223 int irq;
3224
3225 irq_want = nr_irqs_gsi;
3226 irq = create_irq_nr(irq_want);
3227
3228 if (irq == 0)
3229 irq = -1;
3230
3231 return irq;
3232 }
3233
3234 void destroy_irq(unsigned int irq)
3235 {
3236 unsigned long flags;
3237 struct irq_cfg *cfg;
3238 struct irq_desc *desc;
3239
3240 /* store it, in case dynamic_irq_cleanup clear it */
3241 desc = irq_to_desc(irq);
3242 cfg = desc->chip_data;
3243 dynamic_irq_cleanup(irq);
3244 /* connect back irq_cfg */
3245 if (desc)
3246 desc->chip_data = cfg;
3247
3248 #ifdef CONFIG_INTR_REMAP
3249 free_irte(irq);
3250 #endif
3251 spin_lock_irqsave(&vector_lock, flags);
3252 __clear_irq_vector(irq, cfg);
3253 spin_unlock_irqrestore(&vector_lock, flags);
3254 }
3255
3256 /*
3257 * MSI message composition
3258 */
3259 #ifdef CONFIG_PCI_MSI
3260 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3261 {
3262 struct irq_cfg *cfg;
3263 int err;
3264 unsigned dest;
3265
3266 if (disable_apic)
3267 return -ENXIO;
3268
3269 cfg = irq_cfg(irq);
3270 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3271 if (err)
3272 return err;
3273
3274 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3275
3276 #ifdef CONFIG_INTR_REMAP
3277 if (irq_remapped(irq)) {
3278 struct irte irte;
3279 int ir_index;
3280 u16 sub_handle;
3281
3282 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3283 BUG_ON(ir_index == -1);
3284
3285 memset (&irte, 0, sizeof(irte));
3286
3287 irte.present = 1;
3288 irte.dst_mode = apic->irq_dest_mode;
3289 irte.trigger_mode = 0; /* edge */
3290 irte.dlvry_mode = apic->irq_delivery_mode;
3291 irte.vector = cfg->vector;
3292 irte.dest_id = IRTE_DEST(dest);
3293
3294 modify_irte(irq, &irte);
3295
3296 msg->address_hi = MSI_ADDR_BASE_HI;
3297 msg->data = sub_handle;
3298 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3299 MSI_ADDR_IR_SHV |
3300 MSI_ADDR_IR_INDEX1(ir_index) |
3301 MSI_ADDR_IR_INDEX2(ir_index);
3302 } else
3303 #endif
3304 {
3305 msg->address_hi = MSI_ADDR_BASE_HI;
3306 msg->address_lo =
3307 MSI_ADDR_BASE_LO |
3308 ((apic->irq_dest_mode == 0) ?
3309 MSI_ADDR_DEST_MODE_PHYSICAL:
3310 MSI_ADDR_DEST_MODE_LOGICAL) |
3311 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3312 MSI_ADDR_REDIRECTION_CPU:
3313 MSI_ADDR_REDIRECTION_LOWPRI) |
3314 MSI_ADDR_DEST_ID(dest);
3315
3316 msg->data =
3317 MSI_DATA_TRIGGER_EDGE |
3318 MSI_DATA_LEVEL_ASSERT |
3319 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3320 MSI_DATA_DELIVERY_FIXED:
3321 MSI_DATA_DELIVERY_LOWPRI) |
3322 MSI_DATA_VECTOR(cfg->vector);
3323 }
3324 return err;
3325 }
3326
3327 #ifdef CONFIG_SMP
3328 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3329 {
3330 struct irq_desc *desc = irq_to_desc(irq);
3331 struct irq_cfg *cfg;
3332 struct msi_msg msg;
3333 unsigned int dest;
3334
3335 dest = set_desc_affinity(desc, mask);
3336 if (dest == BAD_APICID)
3337 return;
3338
3339 cfg = desc->chip_data;
3340
3341 read_msi_msg_desc(desc, &msg);
3342
3343 msg.data &= ~MSI_DATA_VECTOR_MASK;
3344 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3345 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3346 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3347
3348 write_msi_msg_desc(desc, &msg);
3349 }
3350 #ifdef CONFIG_INTR_REMAP
3351 /*
3352 * Migrate the MSI irq to another cpumask. This migration is
3353 * done in the process context using interrupt-remapping hardware.
3354 */
3355 static void
3356 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3357 {
3358 struct irq_desc *desc = irq_to_desc(irq);
3359 struct irq_cfg *cfg = desc->chip_data;
3360 unsigned int dest;
3361 struct irte irte;
3362
3363 if (get_irte(irq, &irte))
3364 return;
3365
3366 dest = set_desc_affinity(desc, mask);
3367 if (dest == BAD_APICID)
3368 return;
3369
3370 irte.vector = cfg->vector;
3371 irte.dest_id = IRTE_DEST(dest);
3372
3373 /*
3374 * atomically update the IRTE with the new destination and vector.
3375 */
3376 modify_irte(irq, &irte);
3377
3378 /*
3379 * After this point, all the interrupts will start arriving
3380 * at the new destination. So, time to cleanup the previous
3381 * vector allocation.
3382 */
3383 if (cfg->move_in_progress)
3384 send_cleanup_vector(cfg);
3385 }
3386
3387 #endif
3388 #endif /* CONFIG_SMP */
3389
3390 /*
3391 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3392 * which implement the MSI or MSI-X Capability Structure.
3393 */
3394 static struct irq_chip msi_chip = {
3395 .name = "PCI-MSI",
3396 .unmask = unmask_msi_irq,
3397 .mask = mask_msi_irq,
3398 .ack = ack_apic_edge,
3399 #ifdef CONFIG_SMP
3400 .set_affinity = set_msi_irq_affinity,
3401 #endif
3402 .retrigger = ioapic_retrigger_irq,
3403 };
3404
3405 #ifdef CONFIG_INTR_REMAP
3406 static struct irq_chip msi_ir_chip = {
3407 .name = "IR-PCI-MSI",
3408 .unmask = unmask_msi_irq,
3409 .mask = mask_msi_irq,
3410 .ack = ack_x2apic_edge,
3411 #ifdef CONFIG_SMP
3412 .set_affinity = ir_set_msi_irq_affinity,
3413 #endif
3414 .retrigger = ioapic_retrigger_irq,
3415 };
3416
3417 /*
3418 * Map the PCI dev to the corresponding remapping hardware unit
3419 * and allocate 'nvec' consecutive interrupt-remapping table entries
3420 * in it.
3421 */
3422 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3423 {
3424 struct intel_iommu *iommu;
3425 int index;
3426
3427 iommu = map_dev_to_ir(dev);
3428 if (!iommu) {
3429 printk(KERN_ERR
3430 "Unable to map PCI %s to iommu\n", pci_name(dev));
3431 return -ENOENT;
3432 }
3433
3434 index = alloc_irte(iommu, irq, nvec);
3435 if (index < 0) {
3436 printk(KERN_ERR
3437 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3438 pci_name(dev));
3439 return -ENOSPC;
3440 }
3441 return index;
3442 }
3443 #endif
3444
3445 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3446 {
3447 int ret;
3448 struct msi_msg msg;
3449
3450 ret = msi_compose_msg(dev, irq, &msg);
3451 if (ret < 0)
3452 return ret;
3453
3454 set_irq_msi(irq, msidesc);
3455 write_msi_msg(irq, &msg);
3456
3457 #ifdef CONFIG_INTR_REMAP
3458 if (irq_remapped(irq)) {
3459 struct irq_desc *desc = irq_to_desc(irq);
3460 /*
3461 * irq migration in process context
3462 */
3463 desc->status |= IRQ_MOVE_PCNTXT;
3464 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3465 } else
3466 #endif
3467 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3468
3469 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3470
3471 return 0;
3472 }
3473
3474 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3475 {
3476 unsigned int irq;
3477 int ret, sub_handle;
3478 struct msi_desc *msidesc;
3479 unsigned int irq_want;
3480
3481 #ifdef CONFIG_INTR_REMAP
3482 struct intel_iommu *iommu = 0;
3483 int index = 0;
3484 #endif
3485
3486 irq_want = nr_irqs_gsi;
3487 sub_handle = 0;
3488 list_for_each_entry(msidesc, &dev->msi_list, list) {
3489 irq = create_irq_nr(irq_want);
3490 irq_want++;
3491 if (irq == 0)
3492 return -1;
3493 #ifdef CONFIG_INTR_REMAP
3494 if (!intr_remapping_enabled)
3495 goto no_ir;
3496
3497 if (!sub_handle) {
3498 /*
3499 * allocate the consecutive block of IRTE's
3500 * for 'nvec'
3501 */
3502 index = msi_alloc_irte(dev, irq, nvec);
3503 if (index < 0) {
3504 ret = index;
3505 goto error;
3506 }
3507 } else {
3508 iommu = map_dev_to_ir(dev);
3509 if (!iommu) {
3510 ret = -ENOENT;
3511 goto error;
3512 }
3513 /*
3514 * setup the mapping between the irq and the IRTE
3515 * base index, the sub_handle pointing to the
3516 * appropriate interrupt remap table entry.
3517 */
3518 set_irte_irq(irq, iommu, index, sub_handle);
3519 }
3520 no_ir:
3521 #endif
3522 ret = setup_msi_irq(dev, msidesc, irq);
3523 if (ret < 0)
3524 goto error;
3525 sub_handle++;
3526 }
3527 return 0;
3528
3529 error:
3530 destroy_irq(irq);
3531 return ret;
3532 }
3533
3534 void arch_teardown_msi_irq(unsigned int irq)
3535 {
3536 destroy_irq(irq);
3537 }
3538
3539 #ifdef CONFIG_DMAR
3540 #ifdef CONFIG_SMP
3541 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3542 {
3543 struct irq_desc *desc = irq_to_desc(irq);
3544 struct irq_cfg *cfg;
3545 struct msi_msg msg;
3546 unsigned int dest;
3547
3548 dest = set_desc_affinity(desc, mask);
3549 if (dest == BAD_APICID)
3550 return;
3551
3552 cfg = desc->chip_data;
3553
3554 dmar_msi_read(irq, &msg);
3555
3556 msg.data &= ~MSI_DATA_VECTOR_MASK;
3557 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3558 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3559 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3560
3561 dmar_msi_write(irq, &msg);
3562 }
3563
3564 #endif /* CONFIG_SMP */
3565
3566 struct irq_chip dmar_msi_type = {
3567 .name = "DMAR_MSI",
3568 .unmask = dmar_msi_unmask,
3569 .mask = dmar_msi_mask,
3570 .ack = ack_apic_edge,
3571 #ifdef CONFIG_SMP
3572 .set_affinity = dmar_msi_set_affinity,
3573 #endif
3574 .retrigger = ioapic_retrigger_irq,
3575 };
3576
3577 int arch_setup_dmar_msi(unsigned int irq)
3578 {
3579 int ret;
3580 struct msi_msg msg;
3581
3582 ret = msi_compose_msg(NULL, irq, &msg);
3583 if (ret < 0)
3584 return ret;
3585 dmar_msi_write(irq, &msg);
3586 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3587 "edge");
3588 return 0;
3589 }
3590 #endif
3591
3592 #ifdef CONFIG_HPET_TIMER
3593
3594 #ifdef CONFIG_SMP
3595 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3596 {
3597 struct irq_desc *desc = irq_to_desc(irq);
3598 struct irq_cfg *cfg;
3599 struct msi_msg msg;
3600 unsigned int dest;
3601
3602 dest = set_desc_affinity(desc, mask);
3603 if (dest == BAD_APICID)
3604 return;
3605
3606 cfg = desc->chip_data;
3607
3608 hpet_msi_read(irq, &msg);
3609
3610 msg.data &= ~MSI_DATA_VECTOR_MASK;
3611 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3612 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3613 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3614
3615 hpet_msi_write(irq, &msg);
3616 }
3617
3618 #endif /* CONFIG_SMP */
3619
3620 struct irq_chip hpet_msi_type = {
3621 .name = "HPET_MSI",
3622 .unmask = hpet_msi_unmask,
3623 .mask = hpet_msi_mask,
3624 .ack = ack_apic_edge,
3625 #ifdef CONFIG_SMP
3626 .set_affinity = hpet_msi_set_affinity,
3627 #endif
3628 .retrigger = ioapic_retrigger_irq,
3629 };
3630
3631 int arch_setup_hpet_msi(unsigned int irq)
3632 {
3633 int ret;
3634 struct msi_msg msg;
3635
3636 ret = msi_compose_msg(NULL, irq, &msg);
3637 if (ret < 0)
3638 return ret;
3639
3640 hpet_msi_write(irq, &msg);
3641 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3642 "edge");
3643
3644 return 0;
3645 }
3646 #endif
3647
3648 #endif /* CONFIG_PCI_MSI */
3649 /*
3650 * Hypertransport interrupt support
3651 */
3652 #ifdef CONFIG_HT_IRQ
3653
3654 #ifdef CONFIG_SMP
3655
3656 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3657 {
3658 struct ht_irq_msg msg;
3659 fetch_ht_irq_msg(irq, &msg);
3660
3661 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3662 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3663
3664 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3665 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3666
3667 write_ht_irq_msg(irq, &msg);
3668 }
3669
3670 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3671 {
3672 struct irq_desc *desc = irq_to_desc(irq);
3673 struct irq_cfg *cfg;
3674 unsigned int dest;
3675
3676 dest = set_desc_affinity(desc, mask);
3677 if (dest == BAD_APICID)
3678 return;
3679
3680 cfg = desc->chip_data;
3681
3682 target_ht_irq(irq, dest, cfg->vector);
3683 }
3684
3685 #endif
3686
3687 static struct irq_chip ht_irq_chip = {
3688 .name = "PCI-HT",
3689 .mask = mask_ht_irq,
3690 .unmask = unmask_ht_irq,
3691 .ack = ack_apic_edge,
3692 #ifdef CONFIG_SMP
3693 .set_affinity = set_ht_irq_affinity,
3694 #endif
3695 .retrigger = ioapic_retrigger_irq,
3696 };
3697
3698 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3699 {
3700 struct irq_cfg *cfg;
3701 int err;
3702
3703 if (disable_apic)
3704 return -ENXIO;
3705
3706 cfg = irq_cfg(irq);
3707 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3708 if (!err) {
3709 struct ht_irq_msg msg;
3710 unsigned dest;
3711
3712 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3713 apic->target_cpus());
3714
3715 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3716
3717 msg.address_lo =
3718 HT_IRQ_LOW_BASE |
3719 HT_IRQ_LOW_DEST_ID(dest) |
3720 HT_IRQ_LOW_VECTOR(cfg->vector) |
3721 ((apic->irq_dest_mode == 0) ?
3722 HT_IRQ_LOW_DM_PHYSICAL :
3723 HT_IRQ_LOW_DM_LOGICAL) |
3724 HT_IRQ_LOW_RQEOI_EDGE |
3725 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3726 HT_IRQ_LOW_MT_FIXED :
3727 HT_IRQ_LOW_MT_ARBITRATED) |
3728 HT_IRQ_LOW_IRQ_MASKED;
3729
3730 write_ht_irq_msg(irq, &msg);
3731
3732 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3733 handle_edge_irq, "edge");
3734
3735 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3736 }
3737 return err;
3738 }
3739 #endif /* CONFIG_HT_IRQ */
3740
3741 #ifdef CONFIG_X86_UV
3742 /*
3743 * Re-target the irq to the specified CPU and enable the specified MMR located
3744 * on the specified blade to allow the sending of MSIs to the specified CPU.
3745 */
3746 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3747 unsigned long mmr_offset)
3748 {
3749 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3750 struct irq_cfg *cfg;
3751 int mmr_pnode;
3752 unsigned long mmr_value;
3753 struct uv_IO_APIC_route_entry *entry;
3754 unsigned long flags;
3755 int err;
3756
3757 cfg = irq_cfg(irq);
3758
3759 err = assign_irq_vector(irq, cfg, eligible_cpu);
3760 if (err != 0)
3761 return err;
3762
3763 spin_lock_irqsave(&vector_lock, flags);
3764 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3765 irq_name);
3766 spin_unlock_irqrestore(&vector_lock, flags);
3767
3768 mmr_value = 0;
3769 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3770 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3771
3772 entry->vector = cfg->vector;
3773 entry->delivery_mode = apic->irq_delivery_mode;
3774 entry->dest_mode = apic->irq_dest_mode;
3775 entry->polarity = 0;
3776 entry->trigger = 0;
3777 entry->mask = 0;
3778 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3779
3780 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3781 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3782
3783 return irq;
3784 }
3785
3786 /*
3787 * Disable the specified MMR located on the specified blade so that MSIs are
3788 * longer allowed to be sent.
3789 */
3790 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3791 {
3792 unsigned long mmr_value;
3793 struct uv_IO_APIC_route_entry *entry;
3794 int mmr_pnode;
3795
3796 mmr_value = 0;
3797 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3798 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3799
3800 entry->mask = 1;
3801
3802 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3803 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3804 }
3805 #endif /* CONFIG_X86_64 */
3806
3807 int __init io_apic_get_redir_entries (int ioapic)
3808 {
3809 union IO_APIC_reg_01 reg_01;
3810 unsigned long flags;
3811
3812 spin_lock_irqsave(&ioapic_lock, flags);
3813 reg_01.raw = io_apic_read(ioapic, 1);
3814 spin_unlock_irqrestore(&ioapic_lock, flags);
3815
3816 return reg_01.bits.entries;
3817 }
3818
3819 void __init probe_nr_irqs_gsi(void)
3820 {
3821 int idx;
3822 int nr = 0;
3823
3824 for (idx = 0; idx < nr_ioapics; idx++)
3825 nr += io_apic_get_redir_entries(idx) + 1;
3826
3827 if (nr > nr_irqs_gsi)
3828 nr_irqs_gsi = nr;
3829 }
3830
3831 #ifdef CONFIG_SPARSE_IRQ
3832 int __init arch_probe_nr_irqs(void)
3833 {
3834 int nr;
3835
3836 nr = ((8 * nr_cpu_ids) > (32 * nr_ioapics) ?
3837 (NR_VECTORS + (8 * nr_cpu_ids)) :
3838 (NR_VECTORS + (32 * nr_ioapics)));
3839
3840 if (nr < nr_irqs && nr > nr_irqs_gsi)
3841 nr_irqs = nr;
3842
3843 return 0;
3844 }
3845 #endif
3846
3847 /* --------------------------------------------------------------------------
3848 ACPI-based IOAPIC Configuration
3849 -------------------------------------------------------------------------- */
3850
3851 #ifdef CONFIG_ACPI
3852
3853 #ifdef CONFIG_X86_32
3854 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3855 {
3856 union IO_APIC_reg_00 reg_00;
3857 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3858 physid_mask_t tmp;
3859 unsigned long flags;
3860 int i = 0;
3861
3862 /*
3863 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3864 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3865 * supports up to 16 on one shared APIC bus.
3866 *
3867 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3868 * advantage of new APIC bus architecture.
3869 */
3870
3871 if (physids_empty(apic_id_map))
3872 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3873
3874 spin_lock_irqsave(&ioapic_lock, flags);
3875 reg_00.raw = io_apic_read(ioapic, 0);
3876 spin_unlock_irqrestore(&ioapic_lock, flags);
3877
3878 if (apic_id >= get_physical_broadcast()) {
3879 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3880 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3881 apic_id = reg_00.bits.ID;
3882 }
3883
3884 /*
3885 * Every APIC in a system must have a unique ID or we get lots of nice
3886 * 'stuck on smp_invalidate_needed IPI wait' messages.
3887 */
3888 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3889
3890 for (i = 0; i < get_physical_broadcast(); i++) {
3891 if (!apic->check_apicid_used(apic_id_map, i))
3892 break;
3893 }
3894
3895 if (i == get_physical_broadcast())
3896 panic("Max apic_id exceeded!\n");
3897
3898 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3899 "trying %d\n", ioapic, apic_id, i);
3900
3901 apic_id = i;
3902 }
3903
3904 tmp = apic->apicid_to_cpu_present(apic_id);
3905 physids_or(apic_id_map, apic_id_map, tmp);
3906
3907 if (reg_00.bits.ID != apic_id) {
3908 reg_00.bits.ID = apic_id;
3909
3910 spin_lock_irqsave(&ioapic_lock, flags);
3911 io_apic_write(ioapic, 0, reg_00.raw);
3912 reg_00.raw = io_apic_read(ioapic, 0);
3913 spin_unlock_irqrestore(&ioapic_lock, flags);
3914
3915 /* Sanity check */
3916 if (reg_00.bits.ID != apic_id) {
3917 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3918 return -1;
3919 }
3920 }
3921
3922 apic_printk(APIC_VERBOSE, KERN_INFO
3923 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3924
3925 return apic_id;
3926 }
3927
3928 int __init io_apic_get_version(int ioapic)
3929 {
3930 union IO_APIC_reg_01 reg_01;
3931 unsigned long flags;
3932
3933 spin_lock_irqsave(&ioapic_lock, flags);
3934 reg_01.raw = io_apic_read(ioapic, 1);
3935 spin_unlock_irqrestore(&ioapic_lock, flags);
3936
3937 return reg_01.bits.version;
3938 }
3939 #endif
3940
3941 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3942 {
3943 struct irq_desc *desc;
3944 struct irq_cfg *cfg;
3945 int cpu = boot_cpu_id;
3946
3947 if (!IO_APIC_IRQ(irq)) {
3948 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3949 ioapic);
3950 return -EINVAL;
3951 }
3952
3953 desc = irq_to_desc_alloc_cpu(irq, cpu);
3954 if (!desc) {
3955 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3956 return 0;
3957 }
3958
3959 /*
3960 * IRQs < 16 are already in the irq_2_pin[] map
3961 */
3962 if (irq >= NR_IRQS_LEGACY) {
3963 cfg = desc->chip_data;
3964 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3965 }
3966
3967 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3968
3969 return 0;
3970 }
3971
3972
3973 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3974 {
3975 int i;
3976
3977 if (skip_ioapic_setup)
3978 return -1;
3979
3980 for (i = 0; i < mp_irq_entries; i++)
3981 if (mp_irqs[i].irqtype == mp_INT &&
3982 mp_irqs[i].srcbusirq == bus_irq)
3983 break;
3984 if (i >= mp_irq_entries)
3985 return -1;
3986
3987 *trigger = irq_trigger(i);
3988 *polarity = irq_polarity(i);
3989 return 0;
3990 }
3991
3992 #endif /* CONFIG_ACPI */
3993
3994 /*
3995 * This function currently is only a helper for the i386 smp boot process where
3996 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3997 * so mask in all cases should simply be apic->target_cpus()
3998 */
3999 #ifdef CONFIG_SMP
4000 void __init setup_ioapic_dest(void)
4001 {
4002 int pin, ioapic, irq, irq_entry;
4003 struct irq_desc *desc;
4004 struct irq_cfg *cfg;
4005 const struct cpumask *mask;
4006
4007 if (skip_ioapic_setup == 1)
4008 return;
4009
4010 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4011 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4012 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4013 if (irq_entry == -1)
4014 continue;
4015 irq = pin_2_irq(irq_entry, ioapic, pin);
4016
4017 /* setup_IO_APIC_irqs could fail to get vector for some device
4018 * when you have too many devices, because at that time only boot
4019 * cpu is online.
4020 */
4021 desc = irq_to_desc(irq);
4022 cfg = desc->chip_data;
4023 if (!cfg->vector) {
4024 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4025 irq_trigger(irq_entry),
4026 irq_polarity(irq_entry));
4027 continue;
4028
4029 }
4030
4031 /*
4032 * Honour affinities which have been set in early boot
4033 */
4034 if (desc->status &
4035 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4036 mask = desc->affinity;
4037 else
4038 mask = apic->target_cpus();
4039
4040 #ifdef CONFIG_INTR_REMAP
4041 if (intr_remapping_enabled)
4042 set_ir_ioapic_affinity_irq_desc(desc, mask);
4043 else
4044 #endif
4045 set_ioapic_affinity_irq_desc(desc, mask);
4046 }
4047
4048 }
4049 }
4050 #endif
4051
4052 #define IOAPIC_RESOURCE_NAME_SIZE 11
4053
4054 static struct resource *ioapic_resources;
4055
4056 static struct resource * __init ioapic_setup_resources(void)
4057 {
4058 unsigned long n;
4059 struct resource *res;
4060 char *mem;
4061 int i;
4062
4063 if (nr_ioapics <= 0)
4064 return NULL;
4065
4066 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4067 n *= nr_ioapics;
4068
4069 mem = alloc_bootmem(n);
4070 res = (void *)mem;
4071
4072 if (mem != NULL) {
4073 mem += sizeof(struct resource) * nr_ioapics;
4074
4075 for (i = 0; i < nr_ioapics; i++) {
4076 res[i].name = mem;
4077 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4078 sprintf(mem, "IOAPIC %u", i);
4079 mem += IOAPIC_RESOURCE_NAME_SIZE;
4080 }
4081 }
4082
4083 ioapic_resources = res;
4084
4085 return res;
4086 }
4087
4088 void __init ioapic_init_mappings(void)
4089 {
4090 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4091 struct resource *ioapic_res;
4092 int i;
4093
4094 ioapic_res = ioapic_setup_resources();
4095 for (i = 0; i < nr_ioapics; i++) {
4096 if (smp_found_config) {
4097 ioapic_phys = mp_ioapics[i].apicaddr;
4098 #ifdef CONFIG_X86_32
4099 if (!ioapic_phys) {
4100 printk(KERN_ERR
4101 "WARNING: bogus zero IO-APIC "
4102 "address found in MPTABLE, "
4103 "disabling IO/APIC support!\n");
4104 smp_found_config = 0;
4105 skip_ioapic_setup = 1;
4106 goto fake_ioapic_page;
4107 }
4108 #endif
4109 } else {
4110 #ifdef CONFIG_X86_32
4111 fake_ioapic_page:
4112 #endif
4113 ioapic_phys = (unsigned long)
4114 alloc_bootmem_pages(PAGE_SIZE);
4115 ioapic_phys = __pa(ioapic_phys);
4116 }
4117 set_fixmap_nocache(idx, ioapic_phys);
4118 apic_printk(APIC_VERBOSE,
4119 "mapped IOAPIC to %08lx (%08lx)\n",
4120 __fix_to_virt(idx), ioapic_phys);
4121 idx++;
4122
4123 if (ioapic_res != NULL) {
4124 ioapic_res->start = ioapic_phys;
4125 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4126 ioapic_res++;
4127 }
4128 }
4129 }
4130
4131 static int __init ioapic_insert_resources(void)
4132 {
4133 int i;
4134 struct resource *r = ioapic_resources;
4135
4136 if (!r) {
4137 printk(KERN_ERR
4138 "IO APIC resources could be not be allocated.\n");
4139 return -1;
4140 }
4141
4142 for (i = 0; i < nr_ioapics; i++) {
4143 insert_resource(&iomem_resource, r);
4144 r++;
4145 }
4146
4147 return 0;
4148 }
4149
4150 /* Insert the IO APIC resources after PCI initialization has occured to handle
4151 * IO APICS that are mapped in on a BAR in PCI space. */
4152 late_initcall(ioapic_insert_resources);
Support for the Chinese Samsung S3C2440 based development boards