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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux...
[linux-2.6/mini2440.git] / drivers / ata / sata_promise.c
blob5a10dc5048ad3f8e88f748775f220b209e584056
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Mikael Pettersson <mikpe@it.uu.se>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware information only available under NDA.
31 *
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "2.12"
50
51 enum {
52 PDC_MAX_PORTS = 4,
53 PDC_MMIO_BAR = 3,
54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
55
56 /* register offsets */
57 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
58 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
59 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
60 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
61 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
62 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
63 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
64 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
65 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
66 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
67 PDC_FLASH_CTL = 0x44, /* Flash control register */
68 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
69 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
70 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
71 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
72 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
73 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
74
75 /* PDC_GLOBAL_CTL bit definitions */
76 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
77 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
78 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
79 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
80 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
81 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
82 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
83 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
84 PDC_DRIVE_ERR = (1 << 21), /* drive error */
85 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
86 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
87 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
88 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
89 PDC2_ATA_DMA_CNT_ERR,
90 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
91 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
92 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
93 PDC1_ERR_MASK | PDC2_ERR_MASK,
94
95 board_2037x = 0, /* FastTrak S150 TX2plus */
96 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
97 board_20319 = 2, /* FastTrak S150 TX4 */
98 board_20619 = 3, /* FastTrak TX4000 */
99 board_2057x = 4, /* SATAII150 Tx2plus */
100 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
101 board_40518 = 6, /* SATAII150 Tx4 */
102
103 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
104
105 /* Sequence counter control registers bit definitions */
106 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
107
108 /* Feature register values */
109 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
110 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
111
112 /* Device/Head register values */
113 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
114
115 /* PDC_CTLSTAT bit definitions */
116 PDC_DMA_ENABLE = (1 << 7),
117 PDC_IRQ_DISABLE = (1 << 10),
118 PDC_RESET = (1 << 11), /* HDMA reset */
119
120 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
121 ATA_FLAG_MMIO |
122 ATA_FLAG_PIO_POLLING,
123
124 /* ap->flags bits */
125 PDC_FLAG_GEN_II = (1 << 24),
126 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
127 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
128 };
129
130 struct pdc_port_priv {
131 u8 *pkt;
132 dma_addr_t pkt_dma;
133 };
134
135 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
136 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
137 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
138 static int pdc_common_port_start(struct ata_port *ap);
139 static int pdc_sata_port_start(struct ata_port *ap);
140 static void pdc_qc_prep(struct ata_queued_cmd *qc);
141 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
142 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
143 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
144 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
145 static void pdc_irq_clear(struct ata_port *ap);
146 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
147 static void pdc_freeze(struct ata_port *ap);
148 static void pdc_sata_freeze(struct ata_port *ap);
149 static void pdc_thaw(struct ata_port *ap);
150 static void pdc_sata_thaw(struct ata_port *ap);
151 static void pdc_error_handler(struct ata_port *ap);
152 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
153 static int pdc_pata_cable_detect(struct ata_port *ap);
154 static int pdc_sata_cable_detect(struct ata_port *ap);
155
156 static struct scsi_host_template pdc_ata_sht = {
157 ATA_BASE_SHT(DRV_NAME),
158 .sg_tablesize = PDC_MAX_PRD,
159 .dma_boundary = ATA_DMA_BOUNDARY,
160 };
161
162 static const struct ata_port_operations pdc_common_ops = {
163 .inherits = &ata_sff_port_ops,
164
165 .sff_tf_load = pdc_tf_load_mmio,
166 .sff_exec_command = pdc_exec_command_mmio,
167 .check_atapi_dma = pdc_check_atapi_dma,
168 .qc_prep = pdc_qc_prep,
169 .qc_issue = pdc_qc_issue,
170 .sff_irq_clear = pdc_irq_clear,
171
172 .post_internal_cmd = pdc_post_internal_cmd,
173 .error_handler = pdc_error_handler,
174 };
175
176 static struct ata_port_operations pdc_sata_ops = {
177 .inherits = &pdc_common_ops,
178 .cable_detect = pdc_sata_cable_detect,
179 .freeze = pdc_sata_freeze,
180 .thaw = pdc_sata_thaw,
181 .scr_read = pdc_sata_scr_read,
182 .scr_write = pdc_sata_scr_write,
183 .port_start = pdc_sata_port_start,
184 };
185
186 /* First-generation chips need a more restrictive ->check_atapi_dma op */
187 static struct ata_port_operations pdc_old_sata_ops = {
188 .inherits = &pdc_sata_ops,
189 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
190 };
191
192 static struct ata_port_operations pdc_pata_ops = {
193 .inherits = &pdc_common_ops,
194 .cable_detect = pdc_pata_cable_detect,
195 .freeze = pdc_freeze,
196 .thaw = pdc_thaw,
197 .port_start = pdc_common_port_start,
198 };
199
200 static const struct ata_port_info pdc_port_info[] = {
201 [board_2037x] =
202 {
203 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
204 PDC_FLAG_SATA_PATA,
205 .pio_mask = 0x1f, /* pio0-4 */
206 .mwdma_mask = 0x07, /* mwdma0-2 */
207 .udma_mask = ATA_UDMA6,
208 .port_ops = &pdc_old_sata_ops,
209 },
210
211 [board_2037x_pata] =
212 {
213 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
214 .pio_mask = 0x1f, /* pio0-4 */
215 .mwdma_mask = 0x07, /* mwdma0-2 */
216 .udma_mask = ATA_UDMA6,
217 .port_ops = &pdc_pata_ops,
218 },
219
220 [board_20319] =
221 {
222 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
223 PDC_FLAG_4_PORTS,
224 .pio_mask = 0x1f, /* pio0-4 */
225 .mwdma_mask = 0x07, /* mwdma0-2 */
226 .udma_mask = ATA_UDMA6,
227 .port_ops = &pdc_old_sata_ops,
228 },
229
230 [board_20619] =
231 {
232 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
233 PDC_FLAG_4_PORTS,
234 .pio_mask = 0x1f, /* pio0-4 */
235 .mwdma_mask = 0x07, /* mwdma0-2 */
236 .udma_mask = ATA_UDMA6,
237 .port_ops = &pdc_pata_ops,
238 },
239
240 [board_2057x] =
241 {
242 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
243 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
244 .pio_mask = 0x1f, /* pio0-4 */
245 .mwdma_mask = 0x07, /* mwdma0-2 */
246 .udma_mask = ATA_UDMA6,
247 .port_ops = &pdc_sata_ops,
248 },
249
250 [board_2057x_pata] =
251 {
252 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
253 PDC_FLAG_GEN_II,
254 .pio_mask = 0x1f, /* pio0-4 */
255 .mwdma_mask = 0x07, /* mwdma0-2 */
256 .udma_mask = ATA_UDMA6,
257 .port_ops = &pdc_pata_ops,
258 },
259
260 [board_40518] =
261 {
262 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
263 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
264 .pio_mask = 0x1f, /* pio0-4 */
265 .mwdma_mask = 0x07, /* mwdma0-2 */
266 .udma_mask = ATA_UDMA6,
267 .port_ops = &pdc_sata_ops,
268 },
269 };
270
271 static const struct pci_device_id pdc_ata_pci_tbl[] = {
272 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
273 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
274 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
275 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
276 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
277 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
278 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
279 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
280 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
281 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
282
283 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
284 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
285 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
286 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
287 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
288 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
289
290 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
291
292 { } /* terminate list */
293 };
294
295 static struct pci_driver pdc_ata_pci_driver = {
296 .name = DRV_NAME,
297 .id_table = pdc_ata_pci_tbl,
298 .probe = pdc_ata_init_one,
299 .remove = ata_pci_remove_one,
300 };
301
302 static int pdc_common_port_start(struct ata_port *ap)
303 {
304 struct device *dev = ap->host->dev;
305 struct pdc_port_priv *pp;
306 int rc;
307
308 rc = ata_port_start(ap);
309 if (rc)
310 return rc;
311
312 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
313 if (!pp)
314 return -ENOMEM;
315
316 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
317 if (!pp->pkt)
318 return -ENOMEM;
319
320 ap->private_data = pp;
321
322 return 0;
323 }
324
325 static int pdc_sata_port_start(struct ata_port *ap)
326 {
327 int rc;
328
329 rc = pdc_common_port_start(ap);
330 if (rc)
331 return rc;
332
333 /* fix up PHYMODE4 align timing */
334 if (ap->flags & PDC_FLAG_GEN_II) {
335 void __iomem *mmio = ap->ioaddr.scr_addr;
336 unsigned int tmp;
337
338 tmp = readl(mmio + 0x014);
339 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
340 writel(tmp, mmio + 0x014);
341 }
342
343 return 0;
344 }
345
346 static void pdc_reset_port(struct ata_port *ap)
347 {
348 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
349 unsigned int i;
350 u32 tmp;
351
352 for (i = 11; i > 0; i--) {
353 tmp = readl(mmio);
354 if (tmp & PDC_RESET)
355 break;
356
357 udelay(100);
358
359 tmp |= PDC_RESET;
360 writel(tmp, mmio);
361 }
362
363 tmp &= ~PDC_RESET;
364 writel(tmp, mmio);
365 readl(mmio); /* flush */
366 }
367
368 static int pdc_pata_cable_detect(struct ata_port *ap)
369 {
370 u8 tmp;
371 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
372
373 tmp = readb(mmio);
374 if (tmp & 0x01)
375 return ATA_CBL_PATA40;
376 return ATA_CBL_PATA80;
377 }
378
379 static int pdc_sata_cable_detect(struct ata_port *ap)
380 {
381 return ATA_CBL_SATA;
382 }
383
384 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
385 {
386 if (sc_reg > SCR_CONTROL)
387 return -EINVAL;
388 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
389 return 0;
390 }
391
392 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
393 {
394 if (sc_reg > SCR_CONTROL)
395 return -EINVAL;
396 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
397 return 0;
398 }
399
400 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
401 {
402 struct ata_port *ap = qc->ap;
403 dma_addr_t sg_table = ap->prd_dma;
404 unsigned int cdb_len = qc->dev->cdb_len;
405 u8 *cdb = qc->cdb;
406 struct pdc_port_priv *pp = ap->private_data;
407 u8 *buf = pp->pkt;
408 __le32 *buf32 = (__le32 *) buf;
409 unsigned int dev_sel, feature;
410
411 /* set control bits (byte 0), zero delay seq id (byte 3),
412 * and seq id (byte 2)
413 */
414 switch (qc->tf.protocol) {
415 case ATAPI_PROT_DMA:
416 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
417 buf32[0] = cpu_to_le32(PDC_PKT_READ);
418 else
419 buf32[0] = 0;
420 break;
421 case ATAPI_PROT_NODATA:
422 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
423 break;
424 default:
425 BUG();
426 break;
427 }
428 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
429 buf32[2] = 0; /* no next-packet */
430
431 /* select drive */
432 if (sata_scr_valid(&ap->link))
433 dev_sel = PDC_DEVICE_SATA;
434 else
435 dev_sel = qc->tf.device;
436
437 buf[12] = (1 << 5) | ATA_REG_DEVICE;
438 buf[13] = dev_sel;
439 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
440 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
441
442 buf[16] = (1 << 5) | ATA_REG_NSECT;
443 buf[17] = qc->tf.nsect;
444 buf[18] = (1 << 5) | ATA_REG_LBAL;
445 buf[19] = qc->tf.lbal;
446
447 /* set feature and byte counter registers */
448 if (qc->tf.protocol != ATAPI_PROT_DMA)
449 feature = PDC_FEATURE_ATAPI_PIO;
450 else
451 feature = PDC_FEATURE_ATAPI_DMA;
452
453 buf[20] = (1 << 5) | ATA_REG_FEATURE;
454 buf[21] = feature;
455 buf[22] = (1 << 5) | ATA_REG_BYTEL;
456 buf[23] = qc->tf.lbam;
457 buf[24] = (1 << 5) | ATA_REG_BYTEH;
458 buf[25] = qc->tf.lbah;
459
460 /* send ATAPI packet command 0xA0 */
461 buf[26] = (1 << 5) | ATA_REG_CMD;
462 buf[27] = qc->tf.command;
463
464 /* select drive and check DRQ */
465 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
466 buf[29] = dev_sel;
467
468 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
469 BUG_ON(cdb_len & ~0x1E);
470
471 /* append the CDB as the final part */
472 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
473 memcpy(buf+31, cdb, cdb_len);
474 }
475
476 /**
477 * pdc_fill_sg - Fill PCI IDE PRD table
478 * @qc: Metadata associated with taskfile to be transferred
479 *
480 * Fill PCI IDE PRD (scatter-gather) table with segments
481 * associated with the current disk command.
482 * Make sure hardware does not choke on it.
483 *
484 * LOCKING:
485 * spin_lock_irqsave(host lock)
486 *
487 */
488 static void pdc_fill_sg(struct ata_queued_cmd *qc)
489 {
490 struct ata_port *ap = qc->ap;
491 struct scatterlist *sg;
492 const u32 SG_COUNT_ASIC_BUG = 41*4;
493 unsigned int si, idx;
494 u32 len;
495
496 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
497 return;
498
499 idx = 0;
500 for_each_sg(qc->sg, sg, qc->n_elem, si) {
501 u32 addr, offset;
502 u32 sg_len;
503
504 /* determine if physical DMA addr spans 64K boundary.
505 * Note h/w doesn't support 64-bit, so we unconditionally
506 * truncate dma_addr_t to u32.
507 */
508 addr = (u32) sg_dma_address(sg);
509 sg_len = sg_dma_len(sg);
510
511 while (sg_len) {
512 offset = addr & 0xffff;
513 len = sg_len;
514 if ((offset + sg_len) > 0x10000)
515 len = 0x10000 - offset;
516
517 ap->prd[idx].addr = cpu_to_le32(addr);
518 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
519 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
520
521 idx++;
522 sg_len -= len;
523 addr += len;
524 }
525 }
526
527 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
528
529 if (len > SG_COUNT_ASIC_BUG) {
530 u32 addr;
531
532 VPRINTK("Splitting last PRD.\n");
533
534 addr = le32_to_cpu(ap->prd[idx - 1].addr);
535 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
536 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
537
538 addr = addr + len - SG_COUNT_ASIC_BUG;
539 len = SG_COUNT_ASIC_BUG;
540 ap->prd[idx].addr = cpu_to_le32(addr);
541 ap->prd[idx].flags_len = cpu_to_le32(len);
542 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
543
544 idx++;
545 }
546
547 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
548 }
549
550 static void pdc_qc_prep(struct ata_queued_cmd *qc)
551 {
552 struct pdc_port_priv *pp = qc->ap->private_data;
553 unsigned int i;
554
555 VPRINTK("ENTER\n");
556
557 switch (qc->tf.protocol) {
558 case ATA_PROT_DMA:
559 pdc_fill_sg(qc);
560 /* fall through */
561
562 case ATA_PROT_NODATA:
563 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
564 qc->dev->devno, pp->pkt);
565
566 if (qc->tf.flags & ATA_TFLAG_LBA48)
567 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
568 else
569 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
570
571 pdc_pkt_footer(&qc->tf, pp->pkt, i);
572 break;
573
574 case ATAPI_PROT_PIO:
575 pdc_fill_sg(qc);
576 break;
577
578 case ATAPI_PROT_DMA:
579 pdc_fill_sg(qc);
580 /*FALLTHROUGH*/
581 case ATAPI_PROT_NODATA:
582 pdc_atapi_pkt(qc);
583 break;
584
585 default:
586 break;
587 }
588 }
589
590 static int pdc_is_sataii_tx4(unsigned long flags)
591 {
592 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
593 return (flags & mask) == mask;
594 }
595
596 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
597 int is_sataii_tx4)
598 {
599 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
600 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
601 }
602
603 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
604 {
605 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
606 }
607
608 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
609 {
610 const struct ata_host *host = ap->host;
611 unsigned int nr_ports = pdc_sata_nr_ports(ap);
612 unsigned int i;
613
614 for(i = 0; i < nr_ports && host->ports[i] != ap; ++i)
615 ;
616 BUG_ON(i >= nr_ports);
617 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
618 }
619
620 static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap)
621 {
622 return (ap->flags & PDC_FLAG_GEN_II) ? PDC2_SATA_PLUG_CSR : PDC_SATA_PLUG_CSR;
623 }
624
625 static void pdc_freeze(struct ata_port *ap)
626 {
627 void __iomem *mmio = ap->ioaddr.cmd_addr;
628 u32 tmp;
629
630 tmp = readl(mmio + PDC_CTLSTAT);
631 tmp |= PDC_IRQ_DISABLE;
632 tmp &= ~PDC_DMA_ENABLE;
633 writel(tmp, mmio + PDC_CTLSTAT);
634 readl(mmio + PDC_CTLSTAT); /* flush */
635 }
636
637 static void pdc_sata_freeze(struct ata_port *ap)
638 {
639 struct ata_host *host = ap->host;
640 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
641 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
642 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
643 u32 hotplug_status;
644
645 /* Disable hotplug events on this port.
646 *
647 * Locking:
648 * 1) hotplug register accesses must be serialised via host->lock
649 * 2) ap->lock == &ap->host->lock
650 * 3) ->freeze() and ->thaw() are called with ap->lock held
651 */
652 hotplug_status = readl(host_mmio + hotplug_offset);
653 hotplug_status |= 0x11 << (ata_no + 16);
654 writel(hotplug_status, host_mmio + hotplug_offset);
655 readl(host_mmio + hotplug_offset); /* flush */
656
657 pdc_freeze(ap);
658 }
659
660 static void pdc_thaw(struct ata_port *ap)
661 {
662 void __iomem *mmio = ap->ioaddr.cmd_addr;
663 u32 tmp;
664
665 /* clear IRQ */
666 readl(mmio + PDC_INT_SEQMASK);
667
668 /* turn IRQ back on */
669 tmp = readl(mmio + PDC_CTLSTAT);
670 tmp &= ~PDC_IRQ_DISABLE;
671 writel(tmp, mmio + PDC_CTLSTAT);
672 readl(mmio + PDC_CTLSTAT); /* flush */
673 }
674
675 static void pdc_sata_thaw(struct ata_port *ap)
676 {
677 struct ata_host *host = ap->host;
678 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
679 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
680 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
681 u32 hotplug_status;
682
683 pdc_thaw(ap);
684
685 /* Enable hotplug events on this port.
686 * Locking: see pdc_sata_freeze().
687 */
688 hotplug_status = readl(host_mmio + hotplug_offset);
689 hotplug_status |= 0x11 << ata_no;
690 hotplug_status &= ~(0x11 << (ata_no + 16));
691 writel(hotplug_status, host_mmio + hotplug_offset);
692 readl(host_mmio + hotplug_offset); /* flush */
693 }
694
695 static void pdc_error_handler(struct ata_port *ap)
696 {
697 if (!(ap->pflags & ATA_PFLAG_FROZEN))
698 pdc_reset_port(ap);
699
700 ata_std_error_handler(ap);
701 }
702
703 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
704 {
705 struct ata_port *ap = qc->ap;
706
707 /* make DMA engine forget about the failed command */
708 if (qc->flags & ATA_QCFLAG_FAILED)
709 pdc_reset_port(ap);
710 }
711
712 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
713 u32 port_status, u32 err_mask)
714 {
715 struct ata_eh_info *ehi = &ap->link.eh_info;
716 unsigned int ac_err_mask = 0;
717
718 ata_ehi_clear_desc(ehi);
719 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
720 port_status &= err_mask;
721
722 if (port_status & PDC_DRIVE_ERR)
723 ac_err_mask |= AC_ERR_DEV;
724 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
725 ac_err_mask |= AC_ERR_HSM;
726 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
727 ac_err_mask |= AC_ERR_ATA_BUS;
728 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
729 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
730 ac_err_mask |= AC_ERR_HOST_BUS;
731
732 if (sata_scr_valid(&ap->link)) {
733 u32 serror;
734
735 pdc_sata_scr_read(ap, SCR_ERROR, &serror);
736 ehi->serror |= serror;
737 }
738
739 qc->err_mask |= ac_err_mask;
740
741 pdc_reset_port(ap);
742
743 ata_port_abort(ap);
744 }
745
746 static inline unsigned int pdc_host_intr(struct ata_port *ap,
747 struct ata_queued_cmd *qc)
748 {
749 unsigned int handled = 0;
750 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
751 u32 port_status, err_mask;
752
753 err_mask = PDC_ERR_MASK;
754 if (ap->flags & PDC_FLAG_GEN_II)
755 err_mask &= ~PDC1_ERR_MASK;
756 else
757 err_mask &= ~PDC2_ERR_MASK;
758 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
759 if (unlikely(port_status & err_mask)) {
760 pdc_error_intr(ap, qc, port_status, err_mask);
761 return 1;
762 }
763
764 switch (qc->tf.protocol) {
765 case ATA_PROT_DMA:
766 case ATA_PROT_NODATA:
767 case ATAPI_PROT_DMA:
768 case ATAPI_PROT_NODATA:
769 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
770 ata_qc_complete(qc);
771 handled = 1;
772 break;
773
774 default:
775 ap->stats.idle_irq++;
776 break;
777 }
778
779 return handled;
780 }
781
782 static void pdc_irq_clear(struct ata_port *ap)
783 {
784 struct ata_host *host = ap->host;
785 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
786
787 readl(mmio + PDC_INT_SEQMASK);
788 }
789
790 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
791 {
792 struct ata_host *host = dev_instance;
793 struct ata_port *ap;
794 u32 mask = 0;
795 unsigned int i, tmp;
796 unsigned int handled = 0;
797 void __iomem *mmio_base;
798 unsigned int hotplug_offset, ata_no;
799 u32 hotplug_status;
800 int is_sataii_tx4;
801
802 VPRINTK("ENTER\n");
803
804 if (!host || !host->iomap[PDC_MMIO_BAR]) {
805 VPRINTK("QUICK EXIT\n");
806 return IRQ_NONE;
807 }
808
809 mmio_base = host->iomap[PDC_MMIO_BAR];
810
811 spin_lock(&host->lock);
812
813 /* read and clear hotplug flags for all ports */
814 if (host->ports[0]->flags & PDC_FLAG_GEN_II)
815 hotplug_offset = PDC2_SATA_PLUG_CSR;
816 else
817 hotplug_offset = PDC_SATA_PLUG_CSR;
818 hotplug_status = readl(mmio_base + hotplug_offset);
819 if (hotplug_status & 0xff)
820 writel(hotplug_status | 0xff, mmio_base + hotplug_offset);
821 hotplug_status &= 0xff; /* clear uninteresting bits */
822
823 /* reading should also clear interrupts */
824 mask = readl(mmio_base + PDC_INT_SEQMASK);
825
826 if (mask == 0xffffffff && hotplug_status == 0) {
827 VPRINTK("QUICK EXIT 2\n");
828 goto done_irq;
829 }
830
831 mask &= 0xffff; /* only 16 tags possible */
832 if (mask == 0 && hotplug_status == 0) {
833 VPRINTK("QUICK EXIT 3\n");
834 goto done_irq;
835 }
836
837 writel(mask, mmio_base + PDC_INT_SEQMASK);
838
839 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
840
841 for (i = 0; i < host->n_ports; i++) {
842 VPRINTK("port %u\n", i);
843 ap = host->ports[i];
844
845 /* check for a plug or unplug event */
846 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
847 tmp = hotplug_status & (0x11 << ata_no);
848 if (tmp && ap &&
849 !(ap->flags & ATA_FLAG_DISABLED)) {
850 struct ata_eh_info *ehi = &ap->link.eh_info;
851 ata_ehi_clear_desc(ehi);
852 ata_ehi_hotplugged(ehi);
853 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
854 ata_port_freeze(ap);
855 ++handled;
856 continue;
857 }
858
859 /* check for a packet interrupt */
860 tmp = mask & (1 << (i + 1));
861 if (tmp && ap &&
862 !(ap->flags & ATA_FLAG_DISABLED)) {
863 struct ata_queued_cmd *qc;
864
865 qc = ata_qc_from_tag(ap, ap->link.active_tag);
866 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
867 handled += pdc_host_intr(ap, qc);
868 }
869 }
870
871 VPRINTK("EXIT\n");
872
873 done_irq:
874 spin_unlock(&host->lock);
875 return IRQ_RETVAL(handled);
876 }
877
878 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
879 {
880 struct ata_port *ap = qc->ap;
881 struct pdc_port_priv *pp = ap->private_data;
882 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
883 unsigned int port_no = ap->port_no;
884 u8 seq = (u8) (port_no + 1);
885
886 VPRINTK("ENTER, ap %p\n", ap);
887
888 writel(0x00000001, mmio + (seq * 4));
889 readl(mmio + (seq * 4)); /* flush */
890
891 pp->pkt[2] = seq;
892 wmb(); /* flush PRD, pkt writes */
893 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
894 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
895 }
896
897 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
898 {
899 switch (qc->tf.protocol) {
900 case ATAPI_PROT_NODATA:
901 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
902 break;
903 /*FALLTHROUGH*/
904 case ATA_PROT_NODATA:
905 if (qc->tf.flags & ATA_TFLAG_POLLING)
906 break;
907 /*FALLTHROUGH*/
908 case ATAPI_PROT_DMA:
909 case ATA_PROT_DMA:
910 pdc_packet_start(qc);
911 return 0;
912
913 default:
914 break;
915 }
916
917 return ata_sff_qc_issue(qc);
918 }
919
920 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
921 {
922 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
923 ata_sff_tf_load(ap, tf);
924 }
925
926 static void pdc_exec_command_mmio(struct ata_port *ap,
927 const struct ata_taskfile *tf)
928 {
929 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
930 ata_sff_exec_command(ap, tf);
931 }
932
933 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
934 {
935 u8 *scsicmd = qc->scsicmd->cmnd;
936 int pio = 1; /* atapi dma off by default */
937
938 /* Whitelist commands that may use DMA. */
939 switch (scsicmd[0]) {
940 case WRITE_12:
941 case WRITE_10:
942 case WRITE_6:
943 case READ_12:
944 case READ_10:
945 case READ_6:
946 case 0xad: /* READ_DVD_STRUCTURE */
947 case 0xbe: /* READ_CD */
948 pio = 0;
949 }
950 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
951 if (scsicmd[0] == WRITE_10) {
952 unsigned int lba =
953 (scsicmd[2] << 24) |
954 (scsicmd[3] << 16) |
955 (scsicmd[4] << 8) |
956 scsicmd[5];
957 if (lba >= 0xFFFF4FA2)
958 pio = 1;
959 }
960 return pio;
961 }
962
963 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
964 {
965 /* First generation chips cannot use ATAPI DMA on SATA ports */
966 return 1;
967 }
968
969 static void pdc_ata_setup_port(struct ata_port *ap,
970 void __iomem *base, void __iomem *scr_addr)
971 {
972 ap->ioaddr.cmd_addr = base;
973 ap->ioaddr.data_addr = base;
974 ap->ioaddr.feature_addr =
975 ap->ioaddr.error_addr = base + 0x4;
976 ap->ioaddr.nsect_addr = base + 0x8;
977 ap->ioaddr.lbal_addr = base + 0xc;
978 ap->ioaddr.lbam_addr = base + 0x10;
979 ap->ioaddr.lbah_addr = base + 0x14;
980 ap->ioaddr.device_addr = base + 0x18;
981 ap->ioaddr.command_addr =
982 ap->ioaddr.status_addr = base + 0x1c;
983 ap->ioaddr.altstatus_addr =
984 ap->ioaddr.ctl_addr = base + 0x38;
985 ap->ioaddr.scr_addr = scr_addr;
986 }
987
988 static void pdc_host_init(struct ata_host *host)
989 {
990 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
991 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
992 int hotplug_offset;
993 u32 tmp;
994
995 if (is_gen2)
996 hotplug_offset = PDC2_SATA_PLUG_CSR;
997 else
998 hotplug_offset = PDC_SATA_PLUG_CSR;
999
1000 /*
1001 * Except for the hotplug stuff, this is voodoo from the
1002 * Promise driver. Label this entire section
1003 * "TODO: figure out why we do this"
1004 */
1005
1006 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1007 tmp = readl(mmio + PDC_FLASH_CTL);
1008 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1009 if (!is_gen2)
1010 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1011 writel(tmp, mmio + PDC_FLASH_CTL);
1012
1013 /* clear plug/unplug flags for all ports */
1014 tmp = readl(mmio + hotplug_offset);
1015 writel(tmp | 0xff, mmio + hotplug_offset);
1016
1017 /* unmask plug/unplug ints */
1018 tmp = readl(mmio + hotplug_offset);
1019 writel(tmp & ~0xff0000, mmio + hotplug_offset);
1020
1021 /* don't initialise TBG or SLEW on 2nd generation chips */
1022 if (is_gen2)
1023 return;
1024
1025 /* reduce TBG clock to 133 Mhz. */
1026 tmp = readl(mmio + PDC_TBG_MODE);
1027 tmp &= ~0x30000; /* clear bit 17, 16*/
1028 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1029 writel(tmp, mmio + PDC_TBG_MODE);
1030
1031 readl(mmio + PDC_TBG_MODE); /* flush */
1032 msleep(10);
1033
1034 /* adjust slew rate control register. */
1035 tmp = readl(mmio + PDC_SLEW_CTL);
1036 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1037 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1038 writel(tmp, mmio + PDC_SLEW_CTL);
1039 }
1040
1041 static int pdc_ata_init_one(struct pci_dev *pdev,
1042 const struct pci_device_id *ent)
1043 {
1044 static int printed_version;
1045 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1046 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1047 struct ata_host *host;
1048 void __iomem *base;
1049 int n_ports, i, rc;
1050 int is_sataii_tx4;
1051
1052 if (!printed_version++)
1053 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1054
1055 /* enable and acquire resources */
1056 rc = pcim_enable_device(pdev);
1057 if (rc)
1058 return rc;
1059
1060 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1061 if (rc == -EBUSY)
1062 pcim_pin_device(pdev);
1063 if (rc)
1064 return rc;
1065 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1066
1067 /* determine port configuration and setup host */
1068 n_ports = 2;
1069 if (pi->flags & PDC_FLAG_4_PORTS)
1070 n_ports = 4;
1071 for (i = 0; i < n_ports; i++)
1072 ppi[i] = pi;
1073
1074 if (pi->flags & PDC_FLAG_SATA_PATA) {
1075 u8 tmp = readb(base + PDC_FLASH_CTL+1);
1076 if (!(tmp & 0x80))
1077 ppi[n_ports++] = pi + 1;
1078 }
1079
1080 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1081 if (!host) {
1082 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1083 return -ENOMEM;
1084 }
1085 host->iomap = pcim_iomap_table(pdev);
1086
1087 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1088 for (i = 0; i < host->n_ports; i++) {
1089 struct ata_port *ap = host->ports[i];
1090 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1091 unsigned int port_offset = 0x200 + ata_no * 0x80;
1092 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1093
1094 pdc_ata_setup_port(ap, base + port_offset, base + scr_offset);
1095
1096 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1097 ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port");
1098 }
1099
1100 /* initialize adapter */
1101 pdc_host_init(host);
1102
1103 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1104 if (rc)
1105 return rc;
1106 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1107 if (rc)
1108 return rc;
1109
1110 /* start host, request IRQ and attach */
1111 pci_set_master(pdev);
1112 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1113 &pdc_ata_sht);
1114 }
1115
1116 static int __init pdc_ata_init(void)
1117 {
1118 return pci_register_driver(&pdc_ata_pci_driver);
1119 }
1120
1121 static void __exit pdc_ata_exit(void)
1122 {
1123 pci_unregister_driver(&pdc_ata_pci_driver);
1124 }
1125
1126 MODULE_AUTHOR("Jeff Garzik");
1127 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1128 MODULE_LICENSE("GPL");
1129 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1130 MODULE_VERSION(DRV_VERSION);
1131
1132 module_init(pdc_ata_init);
1133 module_exit(pdc_ata_exit);
Support for the Chinese Samsung S3C2440 based development boards