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HID: move ezkey quirks
[linux-2.6/mini2440.git] / drivers / serial / netx-serial.c
blob3f489329e8d3b45f11a453330bdf65e663ed2dbd
1 /*
2 * drivers/serial/netx-serial.c
3 *
4 * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #include <linux/device.h>
25 #include <linux/module.h>
26 #include <linux/ioport.h>
27 #include <linux/init.h>
28 #include <linux/console.h>
29 #include <linux/sysrq.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial_core.h>
34 #include <linux/serial.h>
35
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 #include <mach/hardware.h>
39 #include <mach/netx-regs.h>
40
41 /* We've been assigned a range on the "Low-density serial ports" major */
42 #define SERIAL_NX_MAJOR 204
43 #define MINOR_START 170
44
45 #ifdef CONFIG_SERIAL_NETX_CONSOLE
46
47 enum uart_regs {
48 UART_DR = 0x00,
49 UART_SR = 0x04,
50 UART_LINE_CR = 0x08,
51 UART_BAUDDIV_MSB = 0x0c,
52 UART_BAUDDIV_LSB = 0x10,
53 UART_CR = 0x14,
54 UART_FR = 0x18,
55 UART_IIR = 0x1c,
56 UART_ILPR = 0x20,
57 UART_RTS_CR = 0x24,
58 UART_RTS_LEAD = 0x28,
59 UART_RTS_TRAIL = 0x2c,
60 UART_DRV_ENABLE = 0x30,
61 UART_BRM_CR = 0x34,
62 UART_RXFIFO_IRQLEVEL = 0x38,
63 UART_TXFIFO_IRQLEVEL = 0x3c,
64 };
65
66 #define SR_FE (1<<0)
67 #define SR_PE (1<<1)
68 #define SR_BE (1<<2)
69 #define SR_OE (1<<3)
70
71 #define LINE_CR_BRK (1<<0)
72 #define LINE_CR_PEN (1<<1)
73 #define LINE_CR_EPS (1<<2)
74 #define LINE_CR_STP2 (1<<3)
75 #define LINE_CR_FEN (1<<4)
76 #define LINE_CR_5BIT (0<<5)
77 #define LINE_CR_6BIT (1<<5)
78 #define LINE_CR_7BIT (2<<5)
79 #define LINE_CR_8BIT (3<<5)
80 #define LINE_CR_BITS_MASK (3<<5)
81
82 #define CR_UART_EN (1<<0)
83 #define CR_SIREN (1<<1)
84 #define CR_SIRLP (1<<2)
85 #define CR_MSIE (1<<3)
86 #define CR_RIE (1<<4)
87 #define CR_TIE (1<<5)
88 #define CR_RTIE (1<<6)
89 #define CR_LBE (1<<7)
90
91 #define FR_CTS (1<<0)
92 #define FR_DSR (1<<1)
93 #define FR_DCD (1<<2)
94 #define FR_BUSY (1<<3)
95 #define FR_RXFE (1<<4)
96 #define FR_TXFF (1<<5)
97 #define FR_RXFF (1<<6)
98 #define FR_TXFE (1<<7)
99
100 #define IIR_MIS (1<<0)
101 #define IIR_RIS (1<<1)
102 #define IIR_TIS (1<<2)
103 #define IIR_RTIS (1<<3)
104 #define IIR_MASK 0xf
105
106 #define RTS_CR_AUTO (1<<0)
107 #define RTS_CR_RTS (1<<1)
108 #define RTS_CR_COUNT (1<<2)
109 #define RTS_CR_MOD2 (1<<3)
110 #define RTS_CR_RTS_POL (1<<4)
111 #define RTS_CR_CTS_CTR (1<<5)
112 #define RTS_CR_CTS_POL (1<<6)
113 #define RTS_CR_STICK (1<<7)
114
115 #define UART_PORT_SIZE 0x40
116 #define DRIVER_NAME "netx-uart"
117
118 struct netx_port {
119 struct uart_port port;
120 };
121
122 static void netx_stop_tx(struct uart_port *port)
123 {
124 unsigned int val;
125 val = readl(port->membase + UART_CR);
126 writel(val & ~CR_TIE, port->membase + UART_CR);
127 }
128
129 static void netx_stop_rx(struct uart_port *port)
130 {
131 unsigned int val;
132 val = readl(port->membase + UART_CR);
133 writel(val & ~CR_RIE, port->membase + UART_CR);
134 }
135
136 static void netx_enable_ms(struct uart_port *port)
137 {
138 unsigned int val;
139 val = readl(port->membase + UART_CR);
140 writel(val | CR_MSIE, port->membase + UART_CR);
141 }
142
143 static inline void netx_transmit_buffer(struct uart_port *port)
144 {
145 struct circ_buf *xmit = &port->info->xmit;
146
147 if (port->x_char) {
148 writel(port->x_char, port->membase + UART_DR);
149 port->icount.tx++;
150 port->x_char = 0;
151 return;
152 }
153
154 if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
155 netx_stop_tx(port);
156 return;
157 }
158
159 do {
160 /* send xmit->buf[xmit->tail]
161 * out the port here */
162 writel(xmit->buf[xmit->tail], port->membase + UART_DR);
163 xmit->tail = (xmit->tail + 1) &
164 (UART_XMIT_SIZE - 1);
165 port->icount.tx++;
166 if (uart_circ_empty(xmit))
167 break;
168 } while (!(readl(port->membase + UART_FR) & FR_TXFF));
169
170 if (uart_circ_empty(xmit))
171 netx_stop_tx(port);
172 }
173
174 static void netx_start_tx(struct uart_port *port)
175 {
176 writel(
177 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);
178
179 if (!(readl(port->membase + UART_FR) & FR_TXFF))
180 netx_transmit_buffer(port);
181 }
182
183 static unsigned int netx_tx_empty(struct uart_port *port)
184 {
185 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
186 }
187
188 static void netx_txint(struct uart_port *port)
189 {
190 struct circ_buf *xmit = &port->info->xmit;
191
192 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
193 netx_stop_tx(port);
194 return;
195 }
196
197 netx_transmit_buffer(port);
198
199 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
200 uart_write_wakeup(port);
201 }
202
203 static void netx_rxint(struct uart_port *port)
204 {
205 unsigned char rx, flg, status;
206 struct tty_struct *tty = port->info->port.tty;
207
208 while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
209 rx = readl(port->membase + UART_DR);
210 flg = TTY_NORMAL;
211 port->icount.rx++;
212 status = readl(port->membase + UART_SR);
213 if (status & SR_BE) {
214 writel(0, port->membase + UART_SR);
215 if (uart_handle_break(port))
216 continue;
217 }
218
219 if (unlikely(status & (SR_FE | SR_PE | SR_OE))) {
220
221 if (status & SR_PE)
222 port->icount.parity++;
223 else if (status & SR_FE)
224 port->icount.frame++;
225 if (status & SR_OE)
226 port->icount.overrun++;
227
228 status &= port->read_status_mask;
229
230 if (status & SR_BE)
231 flg = TTY_BREAK;
232 else if (status & SR_PE)
233 flg = TTY_PARITY;
234 else if (status & SR_FE)
235 flg = TTY_FRAME;
236 }
237
238 if (uart_handle_sysrq_char(port, rx))
239 continue;
240
241 uart_insert_char(port, status, SR_OE, rx, flg);
242 }
243
244 tty_flip_buffer_push(tty);
245 return;
246 }
247
248 static irqreturn_t netx_int(int irq, void *dev_id)
249 {
250 struct uart_port *port = dev_id;
251 unsigned long flags;
252 unsigned char status;
253
254 spin_lock_irqsave(&port->lock,flags);
255
256 status = readl(port->membase + UART_IIR) & IIR_MASK;
257 while (status) {
258 if (status & IIR_RIS)
259 netx_rxint(port);
260 if (status & IIR_TIS)
261 netx_txint(port);
262 if (status & IIR_MIS) {
263 if (readl(port->membase + UART_FR) & FR_CTS)
264 uart_handle_cts_change(port, 1);
265 else
266 uart_handle_cts_change(port, 0);
267 }
268 writel(0, port->membase + UART_IIR);
269 status = readl(port->membase + UART_IIR) & IIR_MASK;
270 }
271
272 spin_unlock_irqrestore(&port->lock,flags);
273 return IRQ_HANDLED;
274 }
275
276 static unsigned int netx_get_mctrl(struct uart_port *port)
277 {
278 unsigned int ret = TIOCM_DSR | TIOCM_CAR;
279
280 if (readl(port->membase + UART_FR) & FR_CTS)
281 ret |= TIOCM_CTS;
282
283 return ret;
284 }
285
286 static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
287 {
288 unsigned int val;
289
290 /* FIXME: Locking needed ? */
291 if (mctrl & TIOCM_RTS) {
292 val = readl(port->membase + UART_RTS_CR);
293 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
294 }
295 }
296
297 static void netx_break_ctl(struct uart_port *port, int break_state)
298 {
299 unsigned int line_cr;
300 spin_lock_irq(&port->lock);
301
302 line_cr = readl(port->membase + UART_LINE_CR);
303 if (break_state != 0)
304 line_cr |= LINE_CR_BRK;
305 else
306 line_cr &= ~LINE_CR_BRK;
307 writel(line_cr, port->membase + UART_LINE_CR);
308
309 spin_unlock_irq(&port->lock);
310 }
311
312 static int netx_startup(struct uart_port *port)
313 {
314 int ret;
315
316 ret = request_irq(port->irq, netx_int, 0,
317 DRIVER_NAME, port);
318 if (ret) {
319 dev_err(port->dev, "unable to grab irq%d\n",port->irq);
320 goto exit;
321 }
322
323 writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
324 port->membase + UART_LINE_CR);
325
326 writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,
327 port->membase + UART_CR);
328
329 exit:
330 return ret;
331 }
332
333 static void netx_shutdown(struct uart_port *port)
334 {
335 writel(0, port->membase + UART_CR) ;
336
337 free_irq(port->irq, port);
338 }
339
340 static void
341 netx_set_termios(struct uart_port *port, struct ktermios *termios,
342 struct ktermios *old)
343 {
344 unsigned int baud, quot;
345 unsigned char old_cr;
346 unsigned char line_cr = LINE_CR_FEN;
347 unsigned char rts_cr = 0;
348
349 switch (termios->c_cflag & CSIZE) {
350 case CS5:
351 line_cr |= LINE_CR_5BIT;
352 break;
353 case CS6:
354 line_cr |= LINE_CR_6BIT;
355 break;
356 case CS7:
357 line_cr |= LINE_CR_7BIT;
358 break;
359 case CS8:
360 line_cr |= LINE_CR_8BIT;
361 break;
362 }
363
364 if (termios->c_cflag & CSTOPB)
365 line_cr |= LINE_CR_STP2;
366
367 if (termios->c_cflag & PARENB) {
368 line_cr |= LINE_CR_PEN;
369 if (!(termios->c_cflag & PARODD))
370 line_cr |= LINE_CR_EPS;
371 }
372
373 if (termios->c_cflag & CRTSCTS)
374 rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL;
375
376 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
377 quot = baud * 4096;
378 quot /= 1000;
379 quot *= 256;
380 quot /= 100000;
381
382 spin_lock_irq(&port->lock);
383
384 uart_update_timeout(port, termios->c_cflag, baud);
385
386 old_cr = readl(port->membase + UART_CR);
387
388 /* disable interrupts */
389 writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),
390 port->membase + UART_CR);
391
392 /* drain transmitter */
393 while (readl(port->membase + UART_FR) & FR_BUSY);
394
395 /* disable UART */
396 writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
397
398 /* modem status interrupts */
399 old_cr &= ~CR_MSIE;
400 if (UART_ENABLE_MS(port, termios->c_cflag))
401 old_cr |= CR_MSIE;
402
403 writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
404 writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
405 writel(line_cr, port->membase + UART_LINE_CR);
406
407 writel(rts_cr, port->membase + UART_RTS_CR);
408
409 /*
410 * Characters to ignore
411 */
412 port->ignore_status_mask = 0;
413 if (termios->c_iflag & IGNPAR)
414 port->ignore_status_mask |= SR_PE;
415 if (termios->c_iflag & IGNBRK) {
416 port->ignore_status_mask |= SR_BE;
417 /*
418 * If we're ignoring parity and break indicators,
419 * ignore overruns too (for real raw support).
420 */
421 if (termios->c_iflag & IGNPAR)
422 port->ignore_status_mask |= SR_PE;
423 }
424
425 port->read_status_mask = 0;
426 if (termios->c_iflag & (BRKINT | PARMRK))
427 port->read_status_mask |= SR_BE;
428 if (termios->c_iflag & INPCK)
429 port->read_status_mask |= SR_PE | SR_FE;
430
431 writel(old_cr, port->membase + UART_CR);
432
433 spin_unlock_irq(&port->lock);
434 }
435
436 static const char *netx_type(struct uart_port *port)
437 {
438 return port->type == PORT_NETX ? "NETX" : NULL;
439 }
440
441 static void netx_release_port(struct uart_port *port)
442 {
443 release_mem_region(port->mapbase, UART_PORT_SIZE);
444 }
445
446 static int netx_request_port(struct uart_port *port)
447 {
448 return request_mem_region(port->mapbase, UART_PORT_SIZE,
449 DRIVER_NAME) != NULL ? 0 : -EBUSY;
450 }
451
452 static void netx_config_port(struct uart_port *port, int flags)
453 {
454 if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
455 port->type = PORT_NETX;
456 }
457
458 static int
459 netx_verify_port(struct uart_port *port, struct serial_struct *ser)
460 {
461 int ret = 0;
462
463 if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
464 ret = -EINVAL;
465
466 return ret;
467 }
468
469 static struct uart_ops netx_pops = {
470 .tx_empty = netx_tx_empty,
471 .set_mctrl = netx_set_mctrl,
472 .get_mctrl = netx_get_mctrl,
473 .stop_tx = netx_stop_tx,
474 .start_tx = netx_start_tx,
475 .stop_rx = netx_stop_rx,
476 .enable_ms = netx_enable_ms,
477 .break_ctl = netx_break_ctl,
478 .startup = netx_startup,
479 .shutdown = netx_shutdown,
480 .set_termios = netx_set_termios,
481 .type = netx_type,
482 .release_port = netx_release_port,
483 .request_port = netx_request_port,
484 .config_port = netx_config_port,
485 .verify_port = netx_verify_port,
486 };
487
488 static struct netx_port netx_ports[] = {
489 {
490 .port = {
491 .type = PORT_NETX,
492 .iotype = UPIO_MEM,
493 .membase = (char __iomem *)io_p2v(NETX_PA_UART0),
494 .mapbase = NETX_PA_UART0,
495 .irq = NETX_IRQ_UART0,
496 .uartclk = 100000000,
497 .fifosize = 16,
498 .flags = UPF_BOOT_AUTOCONF,
499 .ops = &netx_pops,
500 .line = 0,
501 },
502 }, {
503 .port = {
504 .type = PORT_NETX,
505 .iotype = UPIO_MEM,
506 .membase = (char __iomem *)io_p2v(NETX_PA_UART1),
507 .mapbase = NETX_PA_UART1,
508 .irq = NETX_IRQ_UART1,
509 .uartclk = 100000000,
510 .fifosize = 16,
511 .flags = UPF_BOOT_AUTOCONF,
512 .ops = &netx_pops,
513 .line = 1,
514 },
515 }, {
516 .port = {
517 .type = PORT_NETX,
518 .iotype = UPIO_MEM,
519 .membase = (char __iomem *)io_p2v(NETX_PA_UART2),
520 .mapbase = NETX_PA_UART2,
521 .irq = NETX_IRQ_UART2,
522 .uartclk = 100000000,
523 .fifosize = 16,
524 .flags = UPF_BOOT_AUTOCONF,
525 .ops = &netx_pops,
526 .line = 2,
527 },
528 }
529 };
530
531 static void netx_console_putchar(struct uart_port *port, int ch)
532 {
533 while (readl(port->membase + UART_FR) & FR_BUSY);
534 writel(ch, port->membase + UART_DR);
535 }
536
537 static void
538 netx_console_write(struct console *co, const char *s, unsigned int count)
539 {
540 struct uart_port *port = &netx_ports[co->index].port;
541 unsigned char cr_save;
542
543 cr_save = readl(port->membase + UART_CR);
544 writel(cr_save | CR_UART_EN, port->membase + UART_CR);
545
546 uart_console_write(port, s, count, netx_console_putchar);
547
548 while (readl(port->membase + UART_FR) & FR_BUSY);
549 writel(cr_save, port->membase + UART_CR);
550 }
551
552 static void __init
553 netx_console_get_options(struct uart_port *port, int *baud,
554 int *parity, int *bits, int *flow)
555 {
556 unsigned char line_cr;
557
558 *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
559 readl(port->membase + UART_BAUDDIV_LSB);
560 *baud *= 1000;
561 *baud /= 4096;
562 *baud *= 1000;
563 *baud /= 256;
564 *baud *= 100;
565
566 line_cr = readl(port->membase + UART_LINE_CR);
567 *parity = 'n';
568 if (line_cr & LINE_CR_PEN) {
569 if (line_cr & LINE_CR_EPS)
570 *parity = 'e';
571 else
572 *parity = 'o';
573 }
574
575 switch (line_cr & LINE_CR_BITS_MASK) {
576 case LINE_CR_8BIT:
577 *bits = 8;
578 break;
579 case LINE_CR_7BIT:
580 *bits = 7;
581 break;
582 case LINE_CR_6BIT:
583 *bits = 6;
584 break;
585 case LINE_CR_5BIT:
586 *bits = 5;
587 break;
588 }
589
590 if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
591 *flow = 'r';
592 }
593
594 static int __init
595 netx_console_setup(struct console *co, char *options)
596 {
597 struct netx_port *sport;
598 int baud = 9600;
599 int bits = 8;
600 int parity = 'n';
601 int flow = 'n';
602
603 /*
604 * Check whether an invalid uart number has been specified, and
605 * if so, search for the first available port that does have
606 * console support.
607 */
608 if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports))
609 co->index = 0;
610 sport = &netx_ports[co->index];
611
612 if (options) {
613 uart_parse_options(options, &baud, &parity, &bits, &flow);
614 } else {
615 /* if the UART is enabled, assume it has been correctly setup
616 * by the bootloader and get the options
617 */
618 if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
619 netx_console_get_options(&sport->port, &baud,
620 &parity, &bits, &flow);
621 }
622
623 }
624
625 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
626 }
627
628 static struct uart_driver netx_reg;
629 static struct console netx_console = {
630 .name = "ttyNX",
631 .write = netx_console_write,
632 .device = uart_console_device,
633 .setup = netx_console_setup,
634 .flags = CON_PRINTBUFFER,
635 .index = -1,
636 .data = &netx_reg,
637 };
638
639 static int __init netx_console_init(void)
640 {
641 register_console(&netx_console);
642 return 0;
643 }
644 console_initcall(netx_console_init);
645
646 #define NETX_CONSOLE &netx_console
647 #else
648 #define NETX_CONSOLE NULL
649 #endif
650
651 static struct uart_driver netx_reg = {
652 .owner = THIS_MODULE,
653 .driver_name = DRIVER_NAME,
654 .dev_name = "ttyNX",
655 .major = SERIAL_NX_MAJOR,
656 .minor = MINOR_START,
657 .nr = ARRAY_SIZE(netx_ports),
658 .cons = NETX_CONSOLE,
659 };
660
661 static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
662 {
663 struct netx_port *sport = platform_get_drvdata(pdev);
664
665 if (sport)
666 uart_suspend_port(&netx_reg, &sport->port);
667
668 return 0;
669 }
670
671 static int serial_netx_resume(struct platform_device *pdev)
672 {
673 struct netx_port *sport = platform_get_drvdata(pdev);
674
675 if (sport)
676 uart_resume_port(&netx_reg, &sport->port);
677
678 return 0;
679 }
680
681 static int serial_netx_probe(struct platform_device *pdev)
682 {
683 struct uart_port *port = &netx_ports[pdev->id].port;
684
685 dev_info(&pdev->dev, "initialising\n");
686
687 port->dev = &pdev->dev;
688
689 writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
690 uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
691 platform_set_drvdata(pdev, &netx_ports[pdev->id]);
692
693 return 0;
694 }
695
696 static int serial_netx_remove(struct platform_device *pdev)
697 {
698 struct netx_port *sport = platform_get_drvdata(pdev);
699
700 platform_set_drvdata(pdev, NULL);
701
702 if (sport)
703 uart_remove_one_port(&netx_reg, &sport->port);
704
705 return 0;
706 }
707
708 static struct platform_driver serial_netx_driver = {
709 .probe = serial_netx_probe,
710 .remove = serial_netx_remove,
711
712 .suspend = serial_netx_suspend,
713 .resume = serial_netx_resume,
714
715 .driver = {
716 .name = DRIVER_NAME,
717 .owner = THIS_MODULE,
718 },
719 };
720
721 static int __init netx_serial_init(void)
722 {
723 int ret;
724
725 printk(KERN_INFO "Serial: NetX driver\n");
726
727 ret = uart_register_driver(&netx_reg);
728 if (ret)
729 return ret;
730
731 ret = platform_driver_register(&serial_netx_driver);
732 if (ret != 0)
733 uart_unregister_driver(&netx_reg);
734
735 return 0;
736 }
737
738 static void __exit netx_serial_exit(void)
739 {
740 platform_driver_unregister(&serial_netx_driver);
741 uart_unregister_driver(&netx_reg);
742 }
743
744 module_init(netx_serial_init);
745 module_exit(netx_serial_exit);
746
747 MODULE_AUTHOR("Sascha Hauer");
748 MODULE_DESCRIPTION("NetX serial port driver");
749 MODULE_LICENSE("GPL");
750 MODULE_ALIAS("platform:" DRIVER_NAME);
Support for the Chinese Samsung S3C2440 based development boards