?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ASoC: DaVinci: i2s, only start sample generator if needed
[linux-2.6/mini2440.git] / sound / soc / davinci / davinci-i2s.c
blob42609654b5e3a4c3ae49c45dc098d579b897374a
1 /*
2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <linux/delay.h>
16 #include <linux/io.h>
17 #include <linux/clk.h>
18
19 #include <sound/core.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/initval.h>
23 #include <sound/soc.h>
24
25 #include "davinci-pcm.h"
26
27
28 /*
29 * NOTE: terminology here is confusing.
30 *
31 * - This driver supports the "Audio Serial Port" (ASP),
32 * found on dm6446, dm355, and other DaVinci chips.
33 *
34 * - But it labels it a "Multi-channel Buffered Serial Port"
35 * (McBSP) as on older chips like the dm642 ... which was
36 * backward-compatible, possibly explaining that confusion.
37 *
38 * - OMAP chips have a controller called McBSP, which is
39 * incompatible with the DaVinci flavor of McBSP.
40 *
41 * - Newer DaVinci chips have a controller called McASP,
42 * incompatible with ASP and with either McBSP.
43 *
44 * In short: this uses ASP to implement I2S, not McBSP.
45 * And it won't be the only DaVinci implemention of I2S.
46 */
47 #define DAVINCI_MCBSP_DRR_REG 0x00
48 #define DAVINCI_MCBSP_DXR_REG 0x04
49 #define DAVINCI_MCBSP_SPCR_REG 0x08
50 #define DAVINCI_MCBSP_RCR_REG 0x0c
51 #define DAVINCI_MCBSP_XCR_REG 0x10
52 #define DAVINCI_MCBSP_SRGR_REG 0x14
53 #define DAVINCI_MCBSP_PCR_REG 0x24
54
55 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
56 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
57 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
58 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
59 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
60 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
61 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
62
63 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
64 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
65 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
66 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
67
68 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
69 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
70 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
71 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
72 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
73
74 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
75 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
76 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
77
78 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
79 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
80 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
81 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
82 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
83 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
84 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
85 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
86 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
87
88 enum {
89 DAVINCI_MCBSP_WORD_8 = 0,
90 DAVINCI_MCBSP_WORD_12,
91 DAVINCI_MCBSP_WORD_16,
92 DAVINCI_MCBSP_WORD_20,
93 DAVINCI_MCBSP_WORD_24,
94 DAVINCI_MCBSP_WORD_32,
95 };
96
97 static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
98 .name = "I2S PCM Stereo out",
99 };
100
101 static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
102 .name = "I2S PCM Stereo in",
103 };
104
105 struct davinci_mcbsp_dev {
106 void __iomem *base;
107 u32 pcr;
108 struct clk *clk;
109 struct davinci_pcm_dma_params *dma_params[2];
110 };
111
112 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
113 int reg, u32 val)
114 {
115 __raw_writel(val, dev->base + reg);
116 }
117
118 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
119 {
120 return __raw_readl(dev->base + reg);
121 }
122
123 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
124 {
125 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
126 /* The clock needs to toggle to complete reset.
127 * So, fake it by toggling the clk polarity.
128 */
129 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
130 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
131 }
132
133 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
134 struct snd_pcm_substream *substream)
135 {
136 struct snd_soc_pcm_runtime *rtd = substream->private_data;
137 struct snd_soc_device *socdev = rtd->socdev;
138 struct snd_soc_platform *platform = socdev->card->platform;
139 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
140 u32 spcr;
141 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
142 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
143 if (spcr & mask) {
144 /* start off disabled */
145 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
146 spcr & ~mask);
147 toggle_clock(dev, playback);
148 }
149 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
150 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
151 /* Start the sample generator */
152 spcr |= DAVINCI_MCBSP_SPCR_GRST;
153 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
154 }
155
156 if (playback) {
157 /* Stop the DMA to avoid data loss */
158 /* while the transmitter is out of reset to handle XSYNCERR */
159 if (platform->pcm_ops->trigger) {
160 int ret = platform->pcm_ops->trigger(substream,
161 SNDRV_PCM_TRIGGER_STOP);
162 if (ret < 0)
163 printk(KERN_DEBUG "Playback DMA stop failed\n");
164 }
165
166 /* Enable the transmitter */
167 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
168 spcr |= DAVINCI_MCBSP_SPCR_XRST;
169 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
170
171 /* wait for any unexpected frame sync error to occur */
172 udelay(100);
173
174 /* Disable the transmitter to clear any outstanding XSYNCERR */
175 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
176 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
177 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
178 toggle_clock(dev, playback);
179
180 /* Restart the DMA */
181 if (platform->pcm_ops->trigger) {
182 int ret = platform->pcm_ops->trigger(substream,
183 SNDRV_PCM_TRIGGER_START);
184 if (ret < 0)
185 printk(KERN_DEBUG "Playback DMA start failed\n");
186 }
187 }
188
189 /* Enable transmitter or receiver */
190 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
191 spcr |= mask;
192
193 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
194 /* Start frame sync */
195 spcr |= DAVINCI_MCBSP_SPCR_FRST;
196 }
197 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
198 }
199
200 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
201 {
202 u32 spcr;
203
204 /* Reset transmitter/receiver and sample rate/frame sync generators */
205 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
206 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
207 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
208 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
209 toggle_clock(dev, playback);
210 }
211
212 static int davinci_i2s_startup(struct snd_pcm_substream *substream,
213 struct snd_soc_dai *dai)
214 {
215 struct snd_soc_pcm_runtime *rtd = substream->private_data;
216 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
217 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
218
219 cpu_dai->dma_data = dev->dma_params[substream->stream];
220
221 return 0;
222 }
223
224 #define DEFAULT_BITPERSAMPLE 16
225
226 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
227 unsigned int fmt)
228 {
229 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
230 unsigned int pcr;
231 unsigned int srgr;
232 unsigned int rcr;
233 unsigned int xcr;
234 srgr = DAVINCI_MCBSP_SRGR_FSGM |
235 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
236 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
237
238 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
239 case SND_SOC_DAIFMT_CBS_CFS:
240 /* cpu is master */
241 pcr = DAVINCI_MCBSP_PCR_FSXM |
242 DAVINCI_MCBSP_PCR_FSRM |
243 DAVINCI_MCBSP_PCR_CLKXM |
244 DAVINCI_MCBSP_PCR_CLKRM;
245 break;
246 case SND_SOC_DAIFMT_CBM_CFS:
247 /* McBSP CLKR pin is the input for the Sample Rate Generator.
248 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
249 pcr = DAVINCI_MCBSP_PCR_SCLKME |
250 DAVINCI_MCBSP_PCR_FSXM |
251 DAVINCI_MCBSP_PCR_FSRM;
252 break;
253 case SND_SOC_DAIFMT_CBM_CFM:
254 /* codec is master */
255 pcr = 0;
256 break;
257 default:
258 printk(KERN_ERR "%s:bad master\n", __func__);
259 return -EINVAL;
260 }
261
262 rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
263 xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1);
264 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
265 case SND_SOC_DAIFMT_DSP_B:
266 break;
267 case SND_SOC_DAIFMT_I2S:
268 /* Davinci doesn't support TRUE I2S, but some codecs will have
269 * the left and right channels contiguous. This allows
270 * dsp_a mode to be used with an inverted normal frame clk.
271 * If your codec is master and does not have contiguous
272 * channels, then you will have sound on only one channel.
273 * Try using a different mode, or codec as slave.
274 *
275 * The TLV320AIC33 is an example of a codec where this works.
276 * It has a variable bit clock frequency allowing it to have
277 * valid data on every bit clock.
278 *
279 * The TLV320AIC23 is an example of a codec where this does not
280 * work. It has a fixed bit clock frequency with progressively
281 * more empty bit clock slots between channels as the sample
282 * rate is lowered.
283 */
284 fmt ^= SND_SOC_DAIFMT_NB_IF;
285 case SND_SOC_DAIFMT_DSP_A:
286 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
287 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
288 break;
289 default:
290 printk(KERN_ERR "%s:bad format\n", __func__);
291 return -EINVAL;
292 }
293
294 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
295 case SND_SOC_DAIFMT_NB_NF:
296 /* CLKRP Receive clock polarity,
297 * 1 - sampled on rising edge of CLKR
298 * valid on rising edge
299 * CLKXP Transmit clock polarity,
300 * 1 - clocked on falling edge of CLKX
301 * valid on rising edge
302 * FSRP Receive frame sync pol, 0 - active high
303 * FSXP Transmit frame sync pol, 0 - active high
304 */
305 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
306 break;
307 case SND_SOC_DAIFMT_IB_IF:
308 /* CLKRP Receive clock polarity,
309 * 0 - sampled on falling edge of CLKR
310 * valid on falling edge
311 * CLKXP Transmit clock polarity,
312 * 0 - clocked on rising edge of CLKX
313 * valid on falling edge
314 * FSRP Receive frame sync pol, 1 - active low
315 * FSXP Transmit frame sync pol, 1 - active low
316 */
317 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
318 break;
319 case SND_SOC_DAIFMT_NB_IF:
320 /* CLKRP Receive clock polarity,
321 * 1 - sampled on rising edge of CLKR
322 * valid on rising edge
323 * CLKXP Transmit clock polarity,
324 * 1 - clocked on falling edge of CLKX
325 * valid on rising edge
326 * FSRP Receive frame sync pol, 1 - active low
327 * FSXP Transmit frame sync pol, 1 - active low
328 */
329 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
330 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
331 break;
332 case SND_SOC_DAIFMT_IB_NF:
333 /* CLKRP Receive clock polarity,
334 * 0 - sampled on falling edge of CLKR
335 * valid on falling edge
336 * CLKXP Transmit clock polarity,
337 * 0 - clocked on rising edge of CLKX
338 * valid on falling edge
339 * FSRP Receive frame sync pol, 0 - active high
340 * FSXP Transmit frame sync pol, 0 - active high
341 */
342 break;
343 default:
344 return -EINVAL;
345 }
346 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
347 dev->pcr = pcr;
348 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
349 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
350 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
351 return 0;
352 }
353
354 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
355 struct snd_pcm_hw_params *params,
356 struct snd_soc_dai *dai)
357 {
358 struct snd_soc_pcm_runtime *rtd = substream->private_data;
359 struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
360 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
361 struct snd_interval *i = NULL;
362 int mcbsp_word_length;
363 unsigned int rcr, xcr, srgr;
364 u32 spcr;
365
366 /* general line settings */
367 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
368 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
369 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
370 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
371 } else {
372 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
373 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
374 }
375
376 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
377 srgr = DAVINCI_MCBSP_SRGR_FSGM;
378 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
379
380 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
381 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
382 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
383
384 /* Determine xfer data type */
385 switch (params_format(params)) {
386 case SNDRV_PCM_FORMAT_S8:
387 dma_params->data_type = 1;
388 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
389 break;
390 case SNDRV_PCM_FORMAT_S16_LE:
391 dma_params->data_type = 2;
392 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
393 break;
394 case SNDRV_PCM_FORMAT_S32_LE:
395 dma_params->data_type = 4;
396 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
397 break;
398 default:
399 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
400 return -EINVAL;
401 }
402
403 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
404 rcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
405 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
406 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
407 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
408
409 } else {
410 xcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
411 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
412 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
413 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
414
415 }
416 return 0;
417 }
418
419 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
420 struct snd_soc_dai *dai)
421 {
422 struct snd_soc_pcm_runtime *rtd = substream->private_data;
423 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
424 int ret = 0;
425 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
426
427 switch (cmd) {
428 case SNDRV_PCM_TRIGGER_START:
429 case SNDRV_PCM_TRIGGER_RESUME:
430 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
431 davinci_mcbsp_start(dev, substream);
432 break;
433 case SNDRV_PCM_TRIGGER_STOP:
434 case SNDRV_PCM_TRIGGER_SUSPEND:
435 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
436 davinci_mcbsp_stop(dev, playback);
437 break;
438 default:
439 ret = -EINVAL;
440 }
441
442 return ret;
443 }
444
445 static int davinci_i2s_probe(struct platform_device *pdev,
446 struct snd_soc_dai *dai)
447 {
448 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
449 struct snd_soc_card *card = socdev->card;
450 struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
451 struct davinci_mcbsp_dev *dev;
452 struct resource *mem, *ioarea;
453 struct evm_snd_platform_data *pdata;
454 int ret;
455
456 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
457 if (!mem) {
458 dev_err(&pdev->dev, "no mem resource?\n");
459 return -ENODEV;
460 }
461
462 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
463 pdev->name);
464 if (!ioarea) {
465 dev_err(&pdev->dev, "McBSP region already claimed\n");
466 return -EBUSY;
467 }
468
469 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
470 if (!dev) {
471 ret = -ENOMEM;
472 goto err_release_region;
473 }
474
475 cpu_dai->private_data = dev;
476
477 dev->clk = clk_get(&pdev->dev, NULL);
478 if (IS_ERR(dev->clk)) {
479 ret = -ENODEV;
480 goto err_free_mem;
481 }
482 clk_enable(dev->clk);
483
484 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
485 pdata = pdev->dev.platform_data;
486
487 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
488 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
489 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
490 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
491
492 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
493 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
494 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
495 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
496
497 return 0;
498
499 err_free_mem:
500 kfree(dev);
501 err_release_region:
502 release_mem_region(mem->start, (mem->end - mem->start) + 1);
503
504 return ret;
505 }
506
507 static void davinci_i2s_remove(struct platform_device *pdev,
508 struct snd_soc_dai *dai)
509 {
510 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
511 struct snd_soc_card *card = socdev->card;
512 struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
513 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
514 struct resource *mem;
515
516 clk_disable(dev->clk);
517 clk_put(dev->clk);
518 dev->clk = NULL;
519
520 kfree(dev);
521
522 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
523 release_mem_region(mem->start, (mem->end - mem->start) + 1);
524 }
525
526 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
527
528 static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
529 .startup = davinci_i2s_startup,
530 .trigger = davinci_i2s_trigger,
531 .hw_params = davinci_i2s_hw_params,
532 .set_fmt = davinci_i2s_set_dai_fmt,
533 };
534
535 struct snd_soc_dai davinci_i2s_dai = {
536 .name = "davinci-i2s",
537 .id = 0,
538 .probe = davinci_i2s_probe,
539 .remove = davinci_i2s_remove,
540 .playback = {
541 .channels_min = 2,
542 .channels_max = 2,
543 .rates = DAVINCI_I2S_RATES,
544 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
545 .capture = {
546 .channels_min = 2,
547 .channels_max = 2,
548 .rates = DAVINCI_I2S_RATES,
549 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
550 .ops = &davinci_i2s_dai_ops,
551 };
552 EXPORT_SYMBOL_GPL(davinci_i2s_dai);
553
554 static int __init davinci_i2s_init(void)
555 {
556 return snd_soc_register_dai(&davinci_i2s_dai);
557 }
558 module_init(davinci_i2s_init);
559
560 static void __exit davinci_i2s_exit(void)
561 {
562 snd_soc_unregister_dai(&davinci_i2s_dai);
563 }
564 module_exit(davinci_i2s_exit);
565
566 MODULE_AUTHOR("Vladimir Barinov");
567 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
568 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards