1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
26 #include <mach_apic.h>
27 #include <asm/genapic.h>
30 #include <asm/pgtable.h>
31 #include <asm/processor.h>
33 #include <asm/atomic.h>
34 #include <asm/proto.h>
35 #include <asm/sections.h>
36 #include <asm/setup.h>
40 static struct cpu_dev
*this_cpu __cpuinitdata
;
43 /* We need valid kernel segments for data and code in long mode too
44 * IRET will check the segment types kkeil 2000/10/28
45 * Also sysret mandates a special GDT layout
47 /* The TLS descriptors are currently at a different place compared to i386.
48 Hopefully nobody expects them at a fixed place (Wine?) */
49 DEFINE_PER_CPU(struct gdt_page
, gdt_page
) = { .gdt
= {
50 [GDT_ENTRY_KERNEL32_CS
] = { { { 0x0000ffff, 0x00cf9b00 } } },
51 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00af9b00 } } },
52 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9300 } } },
53 [GDT_ENTRY_DEFAULT_USER32_CS
] = { { { 0x0000ffff, 0x00cffb00 } } },
54 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff300 } } },
55 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00affb00 } } },
58 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
59 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00cf9a00 } } },
60 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9200 } } },
61 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00cffa00 } } },
62 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff200 } } },
64 * Segments used for calling PnP BIOS have byte granularity.
65 * They code segments and data segments have fixed 64k limits,
66 * the transfer segment sizes are set at run time.
69 [GDT_ENTRY_PNPBIOS_CS32
] = { { { 0x0000ffff, 0x00409a00 } } },
71 [GDT_ENTRY_PNPBIOS_CS16
] = { { { 0x0000ffff, 0x00009a00 } } },
73 [GDT_ENTRY_PNPBIOS_DS
] = { { { 0x0000ffff, 0x00009200 } } },
75 [GDT_ENTRY_PNPBIOS_TS1
] = { { { 0x00000000, 0x00009200 } } },
77 [GDT_ENTRY_PNPBIOS_TS2
] = { { { 0x00000000, 0x00009200 } } },
79 * The APM segments have byte granularity and their bases
80 * are set at run time. All have 64k limits.
83 [GDT_ENTRY_APMBIOS_BASE
] = { { { 0x0000ffff, 0x00409a00 } } },
85 [GDT_ENTRY_APMBIOS_BASE
+1] = { { { 0x0000ffff, 0x00009a00 } } },
87 [GDT_ENTRY_APMBIOS_BASE
+2] = { { { 0x0000ffff, 0x00409200 } } },
89 [GDT_ENTRY_ESPFIX_SS
] = { { { 0x00000000, 0x00c09200 } } },
90 [GDT_ENTRY_PERCPU
] = { { { 0x00000000, 0x00000000 } } },
93 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
96 static int cachesize_override __cpuinitdata
= -1;
97 static int disable_x86_serial_nr __cpuinitdata
= 1;
99 static int __init
cachesize_setup(char *str
)
101 get_option(&str
, &cachesize_override
);
104 __setup("cachesize=", cachesize_setup
);
107 * Naming convention should be: <Name> [(<Codename>)]
108 * This table only is used unless init_<vendor>() below doesn't set it;
109 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
113 /* Look up CPU names by table lookup. */
114 static char __cpuinit
*table_lookup_model(struct cpuinfo_x86
*c
)
116 struct cpu_model_info
*info
;
118 if (c
->x86_model
>= 16)
119 return NULL
; /* Range check */
124 info
= this_cpu
->c_models
;
126 while (info
&& info
->family
) {
127 if (info
->family
== c
->x86
)
128 return info
->model_names
[c
->x86_model
];
131 return NULL
; /* Not found */
134 static int __init
x86_fxsr_setup(char *s
)
136 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
137 setup_clear_cpu_cap(X86_FEATURE_XMM
);
140 __setup("nofxsr", x86_fxsr_setup
);
142 static int __init
x86_sep_setup(char *s
)
144 setup_clear_cpu_cap(X86_FEATURE_SEP
);
147 __setup("nosep", x86_sep_setup
);
149 /* Standard macro to see if a specific flag is changeable */
150 static inline int flag_is_changeable_p(u32 flag
)
164 : "=&r" (f1
), "=&r" (f2
)
167 return ((f1
^f2
) & flag
) != 0;
170 /* Probe for the CPUID instruction */
171 static int __cpuinit
have_cpuid_p(void)
173 return flag_is_changeable_p(X86_EFLAGS_ID
);
176 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
178 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
179 /* Disable processor serial number */
180 unsigned long lo
, hi
;
181 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
183 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
184 printk(KERN_NOTICE
"CPU serial number disabled.\n");
185 clear_cpu_cap(c
, X86_FEATURE_PN
);
187 /* Disabling the serial number may affect the cpuid level */
188 c
->cpuid_level
= cpuid_eax(0);
192 static int __init
x86_serial_nr_setup(char *s
)
194 disable_x86_serial_nr
= 0;
197 __setup("serialnumber", x86_serial_nr_setup
);
199 /* Probe for the CPUID instruction */
200 static inline int have_cpuid_p(void)
206 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
208 /* Current gdt points %fs at the "master" per-cpu area: after this,
209 * it's on the real one. */
210 void switch_to_new_gdt(void)
212 struct desc_ptr gdt_descr
;
214 gdt_descr
.address
= (long)get_cpu_gdt_table(smp_processor_id());
215 gdt_descr
.size
= GDT_SIZE
- 1;
216 load_gdt(&gdt_descr
);
219 static struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
221 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
223 display_cacheinfo(c
);
226 static struct cpu_dev __cpuinitdata default_cpu
= {
227 .c_init
= default_init
,
228 .c_vendor
= "Unknown",
229 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
232 int __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
237 if (c
->extended_cpuid_level
< 0x80000004)
240 v
= (unsigned int *) c
->x86_model_id
;
241 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
242 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
243 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
244 c
->x86_model_id
[48] = 0;
246 /* Intel chips right-justify this string for some dumb reason;
247 undo that brain damage */
248 p
= q
= &c
->x86_model_id
[0];
254 while (q
<= &c
->x86_model_id
[48])
255 *q
++ = '\0'; /* Zero-pad the rest */
262 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
264 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
266 n
= c
->extended_cpuid_level
;
268 if (n
>= 0x80000005) {
269 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
270 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
271 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
272 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
273 /* On K8 L1 TLB is inclusive, so don't count it */
277 if (n
< 0x80000006) /* Some chips just has a large L1. */
280 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
282 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
284 c
->x86_cache_size
= l2size
;
286 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
290 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
293 u32 eax
, ebx
, ecx
, edx
;
294 int index_msb
, core_bits
;
296 if (!cpu_has(c
, X86_FEATURE_HT
))
298 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
301 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
304 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
306 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
308 if (smp_num_siblings
== 1) {
309 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
310 } else if (smp_num_siblings
> 1) {
312 if (smp_num_siblings
> NR_CPUS
) {
313 printk(KERN_WARNING
"CPU: Unsupported number of siblings %d",
315 smp_num_siblings
= 1;
319 index_msb
= get_count_order(smp_num_siblings
);
320 c
->phys_proc_id
= phys_pkg_id(index_msb
);
322 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
324 index_msb
= get_count_order(smp_num_siblings
);
326 core_bits
= get_count_order(c
->x86_max_cores
);
328 c
->cpu_core_id
= phys_pkg_id(index_msb
) &
329 ((1 << core_bits
) - 1);
333 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
334 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
336 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
342 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
344 char *v
= c
->x86_vendor_id
;
348 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
352 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
353 (cpu_devs
[i
]->c_ident
[1] &&
354 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
355 this_cpu
= cpu_devs
[i
];
356 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
363 printk(KERN_ERR
"CPU: Vendor unknown, using generic init.\n");
364 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
367 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
368 this_cpu
= &default_cpu
;
371 void __cpuinit
cpu_detect(struct cpuinfo_x86
*c
)
373 /* Get vendor name */
374 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
375 (unsigned int *)&c
->x86_vendor_id
[0],
376 (unsigned int *)&c
->x86_vendor_id
[8],
377 (unsigned int *)&c
->x86_vendor_id
[4]);
380 /* Intel-defined flags: level 0x00000001 */
381 if (c
->cpuid_level
>= 0x00000001) {
382 u32 junk
, tfms
, cap0
, misc
;
383 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
384 c
->x86
= (tfms
>> 8) & 0xf;
385 c
->x86_model
= (tfms
>> 4) & 0xf;
386 c
->x86_mask
= tfms
& 0xf;
388 c
->x86
+= (tfms
>> 20) & 0xff;
390 c
->x86_model
+= ((tfms
>> 16) & 0xf) << 4;
391 if (cap0
& (1<<19)) {
392 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
393 c
->x86_cache_alignment
= c
->x86_clflush_size
;
399 static void __cpuinit
get_cpu_cap(struct cpuinfo_x86
*c
)
404 /* Intel-defined flags: level 0x00000001 */
405 if (c
->cpuid_level
>= 0x00000001) {
406 u32 capability
, excap
;
408 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
409 c
->x86_capability
[0] = capability
;
410 c
->x86_capability
[4] = excap
;
413 /* AMD-defined flags: level 0x80000001 */
414 xlvl
= cpuid_eax(0x80000000);
415 c
->extended_cpuid_level
= xlvl
;
416 if ((xlvl
& 0xffff0000) == 0x80000000) {
417 if (xlvl
>= 0x80000001) {
418 c
->x86_capability
[1] = cpuid_edx(0x80000001);
419 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
423 /* Transmeta-defined flags: level 0x80860001 */
424 xlvl
= cpuid_eax(0x80860000);
425 if ((xlvl
& 0xffff0000) == 0x80860000) {
426 /* Don't set x86_cpuid_level here for now to not confuse. */
427 if (xlvl
>= 0x80860001)
428 c
->x86_capability
[2] = cpuid_edx(0x80860001);
431 if (c
->extended_cpuid_level
>= 0x80000007)
432 c
->x86_power
= cpuid_edx(0x80000007);
434 if (c
->extended_cpuid_level
>= 0x80000008) {
435 u32 eax
= cpuid_eax(0x80000008);
437 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
438 c
->x86_phys_bits
= eax
& 0xff;
442 /* Do some early cpuid on the boot CPU to get some parameter that are
443 needed before check_bugs. Everything advanced is in identify_cpu
445 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
448 c
->x86_clflush_size
= 64;
449 c
->x86_cache_alignment
= c
->x86_clflush_size
;
451 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
453 c
->extended_cpuid_level
= 0;
461 if (this_cpu
->c_early_init
)
462 this_cpu
->c_early_init(c
);
464 validate_pat_support(c
);
467 void __init
early_cpu_init(void)
469 struct cpu_dev
**cdev
;
472 printk("KERNEL supported cpus:\n");
473 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
474 struct cpu_dev
*cpudev
= *cdev
;
477 if (count
>= X86_VENDOR_NUM
)
479 cpu_devs
[count
] = cpudev
;
482 for (j
= 0; j
< 2; j
++) {
483 if (!cpudev
->c_ident
[j
])
485 printk(" %s %s\n", cpudev
->c_vendor
,
490 early_identify_cpu(&boot_cpu_data
);
494 * The NOPL instruction is supposed to exist on all CPUs with
495 * family >= 6, unfortunately, that's not true in practice because
496 * of early VIA chips and (more importantly) broken virtualizers that
497 * are not easy to detect. Hence, probe for it based on first
500 * Note: no 64-bit chip is known to lack these, but put the code here
501 * for consistency with 32 bits, and to make it utterly trivial to
502 * diagnose the problem should it ever surface.
504 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
506 const u32 nopl_signature
= 0x888c53b1; /* Random number */
507 u32 has_nopl
= nopl_signature
;
509 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
512 "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
514 " .section .fixup,\"ax\"\n"
521 if (has_nopl
== nopl_signature
)
522 set_cpu_cap(c
, X86_FEATURE_NOPL
);
526 static void __cpuinit
generic_identify(struct cpuinfo_x86
*c
)
528 c
->extended_cpuid_level
= 0;
536 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xff;
538 c
->phys_proc_id
= c
->initial_apicid
;
541 if (c
->extended_cpuid_level
>= 0x80000004)
542 get_model_name(c
); /* Default name */
544 init_scattered_cpuid_features(c
);
549 * This does the hard work of actually picking apart the CPU stuff...
551 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
555 c
->loops_per_jiffy
= loops_per_jiffy
;
556 c
->x86_cache_size
= -1;
557 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
558 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
559 c
->x86_vendor_id
[0] = '\0'; /* Unset */
560 c
->x86_model_id
[0] = '\0'; /* Unset */
561 c
->x86_max_cores
= 1;
562 c
->x86_coreid_bits
= 0;
563 c
->x86_clflush_size
= 64;
564 c
->x86_cache_alignment
= c
->x86_clflush_size
;
565 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
569 c
->apicid
= phys_pkg_id(0);
572 * Vendor-specific initialization. In this section we
573 * canonicalize the feature flags, meaning if there are
574 * features a certain CPU supports which CPUID doesn't
575 * tell us, CPUID claiming incorrect flags, or other bugs,
576 * we handle them here.
578 * At the end of this section, c->x86_capability better
579 * indicate the features this CPU genuinely supports!
581 if (this_cpu
->c_init
)
587 * On SMP, boot_cpu_data holds the common feature set between
588 * all CPUs; so make sure that we indicate which features are
589 * common between the CPUs. The first time this routine gets
590 * executed, c == &boot_cpu_data.
592 if (c
!= &boot_cpu_data
) {
593 /* AND the already accumulated flags with these */
594 for (i
= 0; i
< NCAPINTS
; i
++)
595 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
598 /* Clear all flags overriden by options */
599 for (i
= 0; i
< NCAPINTS
; i
++)
600 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
602 #ifdef CONFIG_X86_MCE
605 select_idle_routine(c
);
608 numa_add_cpu(smp_processor_id());
613 void __init
identify_boot_cpu(void)
615 identify_cpu(&boot_cpu_data
);
618 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
620 BUG_ON(c
== &boot_cpu_data
);
630 static struct msr_range msr_range_array
[] __cpuinitdata
= {
631 { 0x00000000, 0x00000418},
632 { 0xc0000000, 0xc000040b},
633 { 0xc0010000, 0xc0010142},
634 { 0xc0011000, 0xc001103b},
637 static void __cpuinit
print_cpu_msr(void)
642 unsigned index_min
, index_max
;
644 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
645 index_min
= msr_range_array
[i
].min
;
646 index_max
= msr_range_array
[i
].max
;
647 for (index
= index_min
; index
< index_max
; index
++) {
648 if (rdmsrl_amd_safe(index
, &val
))
650 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
655 static int show_msr __cpuinitdata
;
656 static __init
int setup_show_msr(char *arg
)
660 get_option(&arg
, &num
);
666 __setup("show_msr=", setup_show_msr
);
668 static __init
int setup_noclflush(char *arg
)
670 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
673 __setup("noclflush", setup_noclflush
);
675 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
677 if (c
->x86_model_id
[0])
678 printk(KERN_CONT
"%s", c
->x86_model_id
);
680 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
681 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
683 printk(KERN_CONT
"\n");
686 if (c
->cpu_index
< show_msr
)
694 static __init
int setup_disablecpuid(char *arg
)
697 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
698 setup_clear_cpu_cap(bit
);
703 __setup("clearcpuid=", setup_disablecpuid
);
705 cpumask_t cpu_initialized __cpuinitdata
= CPU_MASK_NONE
;
708 struct x8664_pda
**_cpu_pda __read_mostly
;
709 EXPORT_SYMBOL(_cpu_pda
);
711 struct desc_ptr idt_descr
= { 256 * 16 - 1, (unsigned long) idt_table
};
713 char boot_cpu_stack
[IRQSTACKSIZE
] __page_aligned_bss
;
715 unsigned long __supported_pte_mask __read_mostly
= ~0UL;
716 EXPORT_SYMBOL_GPL(__supported_pte_mask
);
718 static int do_not_nx __cpuinitdata
;
721 Control non executable mappings for 64bit processes.
726 static int __init
nonx_setup(char *str
)
730 if (!strncmp(str
, "on", 2)) {
731 __supported_pte_mask
|= _PAGE_NX
;
733 } else if (!strncmp(str
, "off", 3)) {
735 __supported_pte_mask
&= ~_PAGE_NX
;
739 early_param("noexec", nonx_setup
);
741 int force_personality32
;
744 Control non executable heap for 32bit processes.
745 To control the stack too use noexec=off
747 on PROT_READ does not imply PROT_EXEC for 32bit processes (default)
748 off PROT_READ implies PROT_EXEC
750 static int __init
nonx32_setup(char *str
)
752 if (!strcmp(str
, "on"))
753 force_personality32
&= ~READ_IMPLIES_EXEC
;
754 else if (!strcmp(str
, "off"))
755 force_personality32
|= READ_IMPLIES_EXEC
;
758 __setup("noexec32=", nonx32_setup
);
760 void pda_init(int cpu
)
762 struct x8664_pda
*pda
= cpu_pda(cpu
);
764 /* Setup up data that may be needed in __get_free_pages early */
767 /* Memory clobbers used to order PDA accessed */
769 wrmsrl(MSR_GS_BASE
, pda
);
772 pda
->cpunumber
= cpu
;
774 pda
->kernelstack
= (unsigned long)stack_thread_info() -
775 PDA_STACKOFFSET
+ THREAD_SIZE
;
776 pda
->active_mm
= &init_mm
;
780 /* others are initialized in smpboot.c */
781 pda
->pcurrent
= &init_task
;
782 pda
->irqstackptr
= boot_cpu_stack
;
783 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
785 if (!pda
->irqstackptr
) {
786 pda
->irqstackptr
= (char *)
787 __get_free_pages(GFP_ATOMIC
, IRQSTACK_ORDER
);
788 if (!pda
->irqstackptr
)
789 panic("cannot allocate irqstack for cpu %d",
791 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
794 if (pda
->nodenumber
== 0 && cpu_to_node(cpu
) != NUMA_NO_NODE
)
795 pda
->nodenumber
= cpu_to_node(cpu
);
799 char boot_exception_stacks
[(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+
800 DEBUG_STKSZ
] __page_aligned_bss
;
802 extern asmlinkage
void ignore_sysret(void);
804 /* May not be marked __init: used by software suspend */
805 void syscall_init(void)
808 * LSTAR and STAR live in a bit strange symbiosis.
809 * They both write to the same internal register. STAR allows to
810 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
812 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
813 wrmsrl(MSR_LSTAR
, system_call
);
814 wrmsrl(MSR_CSTAR
, ignore_sysret
);
816 #ifdef CONFIG_IA32_EMULATION
817 syscall32_cpu_init();
820 /* Flags to clear on syscall */
821 wrmsrl(MSR_SYSCALL_MASK
,
822 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|X86_EFLAGS_IOPL
);
825 void __cpuinit
check_efer(void)
829 rdmsrl(MSR_EFER
, efer
);
830 if (!(efer
& EFER_NX
) || do_not_nx
)
831 __supported_pte_mask
&= ~_PAGE_NX
;
834 unsigned long kernel_eflags
;
837 * Copies of the original ist values from the tss are only accessed during
838 * debugging, no special alignment required.
840 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
844 /* Make sure %fs is initialized properly in idle threads */
845 struct pt_regs
* __cpuinit
idle_regs(struct pt_regs
*regs
)
847 memset(regs
, 0, sizeof(struct pt_regs
));
848 regs
->fs
= __KERNEL_PERCPU
;
854 * cpu_init() initializes state that is per-CPU. Some data is already
855 * initialized (naturally) in the bootstrap process, such as the GDT
856 * and IDT. We reload them nevertheless, this function acts as a
857 * 'CPU state barrier', nothing should get across.
858 * A lot of state is already set up in PDA init for 64 bit
861 void __cpuinit
cpu_init(void)
863 int cpu
= stack_smp_processor_id();
864 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
865 struct orig_ist
*orig_ist
= &per_cpu(orig_ist
, cpu
);
867 char *estacks
= NULL
;
868 struct task_struct
*me
;
871 /* CPU 0 is initialised in head64.c */
875 estacks
= boot_exception_stacks
;
879 if (cpu_test_and_set(cpu
, cpu_initialized
))
880 panic("CPU#%d already initialized!\n", cpu
);
882 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
884 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
887 * Initialize the per-CPU GDT with the boot GDT,
888 * and set up the GDT descriptor:
892 load_idt((const struct desc_ptr
*)&idt_descr
);
894 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
897 wrmsrl(MSR_FS_BASE
, 0);
898 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
902 if (cpu
!= 0 && x2apic
)
906 * set up and load the per-CPU TSS
908 if (!orig_ist
->ist
[0]) {
909 static const unsigned int order
[N_EXCEPTION_STACKS
] = {
910 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STACK_ORDER
,
911 [DEBUG_STACK
- 1] = DEBUG_STACK_ORDER
913 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
915 estacks
= (char *)__get_free_pages(GFP_ATOMIC
, order
[v
]);
917 panic("Cannot allocate exception "
918 "stack %ld %d\n", v
, cpu
);
920 estacks
+= PAGE_SIZE
<< order
[v
];
921 orig_ist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
922 (unsigned long)estacks
;
926 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
928 * <= is required because the CPU will access up to
929 * 8 bits beyond the end of the IO permission bitmap.
931 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
932 t
->io_bitmap
[i
] = ~0UL;
934 atomic_inc(&init_mm
.mm_count
);
935 me
->active_mm
= &init_mm
;
938 enter_lazy_tlb(&init_mm
, me
);
940 load_sp0(t
, ¤t
->thread
);
941 set_tss_desc(cpu
, t
);
943 load_LDT(&init_mm
.context
);
947 * If the kgdb is connected no debug regs should be altered. This
948 * is only applicable when KGDB and a KGDB I/O module are built
949 * into the kernel and you are using early debugging with
950 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
952 if (kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
)
953 arch_kgdb_ops
.correct_hw_break();
957 * Clear all 6 debug registers:
960 set_debugreg(0UL, 0);
961 set_debugreg(0UL, 1);
962 set_debugreg(0UL, 2);
963 set_debugreg(0UL, 3);
964 set_debugreg(0UL, 6);
965 set_debugreg(0UL, 7);
967 /* If the kgdb is connected no debug regs should be altered. */
973 raw_local_save_flags(kernel_eflags
);
981 void __cpuinit
cpu_init(void)
983 int cpu
= smp_processor_id();
984 struct task_struct
*curr
= current
;
985 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
986 struct thread_struct
*thread
= &curr
->thread
;
988 if (cpu_test_and_set(cpu
, cpu_initialized
)) {
989 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
990 for (;;) local_irq_enable();
993 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
995 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
996 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
998 load_idt(&idt_descr
);
1002 * Set up and load the per-CPU TSS and LDT
1004 atomic_inc(&init_mm
.mm_count
);
1005 curr
->active_mm
= &init_mm
;
1008 enter_lazy_tlb(&init_mm
, curr
);
1010 load_sp0(t
, thread
);
1011 set_tss_desc(cpu
, t
);
1013 load_LDT(&init_mm
.context
);
1015 #ifdef CONFIG_DOUBLEFAULT
1016 /* Set up doublefault TSS pointer in the GDT */
1017 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1021 asm volatile ("mov %0, %%gs" : : "r" (0));
1023 /* Clear all 6 debug registers: */
1032 * Force FPU initialization:
1035 current_thread_info()->status
= TS_XSAVE
;
1037 current_thread_info()->status
= 0;
1039 mxcsr_feature_mask_init();
1042 * Boot processor to setup the FP and extended state context info.
1044 if (!smp_processor_id())
1045 init_thread_xstate();
1050 #ifdef CONFIG_HOTPLUG_CPU
1051 void __cpuinit
cpu_uninit(void)
1053 int cpu
= raw_smp_processor_id();
1054 cpu_clear(cpu
, cpu_initialized
);
1056 /* lazy TLB state */
1057 per_cpu(cpu_tlbstate
, cpu
).state
= 0;
1058 per_cpu(cpu_tlbstate
, cpu
).active_mm
= &init_mm
;