1 /* AM33v2 on-board timer module registers
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
12 #ifndef _ASM_TIMER_REGS_H
13 #define _ASM_TIMER_REGS_H
15 #include <asm/cpu-regs.h>
16 #include <asm/intctl-regs.h>
20 /* timer prescalar control */
21 #define TMPSCNT __SYSREG(0xd4003071, u8) /* timer prescaler control */
22 #define TMPSCNT_ENABLE 0x80 /* timer prescaler enable */
23 #define TMPSCNT_DISABLE 0x00 /* timer prescaler disable */
26 #define TM0MD __SYSREG(0xd4003000, u8) /* timer 0 mode register */
27 #define TM0MD_SRC 0x07 /* timer source */
28 #define TM0MD_SRC_IOCLK 0x00 /* - IOCLK */
29 #define TM0MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
30 #define TM0MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
31 #define TM0MD_SRC_TM2IO 0x03 /* - TM2IO pin input */
32 #define TM0MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
33 #define TM0MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
34 #define TM0MD_SRC_TM0IO 0x07 /* - TM0IO pin input */
35 #define TM0MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
36 #define TM0MD_COUNT_ENABLE 0x80 /* timer count enable */
38 #define TM1MD __SYSREG(0xd4003001, u8) /* timer 1 mode register */
39 #define TM1MD_SRC 0x07 /* timer source */
40 #define TM1MD_SRC_IOCLK 0x00 /* - IOCLK */
41 #define TM1MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
42 #define TM1MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
43 #define TM1MD_SRC_TM0CASCADE 0x03 /* - cascade with timer 0 */
44 #define TM1MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
45 #define TM1MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
46 #define TM1MD_SRC_TM1IO 0x07 /* - TM1IO pin input */
47 #define TM1MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
48 #define TM1MD_COUNT_ENABLE 0x80 /* timer count enable */
50 #define TM2MD __SYSREG(0xd4003002, u8) /* timer 2 mode register */
51 #define TM2MD_SRC 0x07 /* timer source */
52 #define TM2MD_SRC_IOCLK 0x00 /* - IOCLK */
53 #define TM2MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
54 #define TM2MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
55 #define TM2MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 1 */
56 #define TM2MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
57 #define TM2MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
58 #define TM2MD_SRC_TM2IO 0x07 /* - TM2IO pin input */
59 #define TM2MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
60 #define TM2MD_COUNT_ENABLE 0x80 /* timer count enable */
62 #define TM3MD __SYSREG(0xd4003003, u8) /* timer 3 mode register */
63 #define TM3MD_SRC 0x07 /* timer source */
64 #define TM3MD_SRC_IOCLK 0x00 /* - IOCLK */
65 #define TM3MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
66 #define TM3MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
67 #define TM3MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 2 */
68 #define TM3MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
69 #define TM3MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
70 #define TM3MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
71 #define TM3MD_SRC_TM3IO 0x07 /* - TM3IO pin input */
72 #define TM3MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
73 #define TM3MD_COUNT_ENABLE 0x80 /* timer count enable */
75 #define TM01MD __SYSREG(0xd4003000, u16) /* timer 0:1 mode register */
77 #define TM0BR __SYSREG(0xd4003010, u8) /* timer 0 base register */
78 #define TM1BR __SYSREG(0xd4003011, u8) /* timer 1 base register */
79 #define TM2BR __SYSREG(0xd4003012, u8) /* timer 2 base register */
80 #define TM3BR __SYSREG(0xd4003013, u8) /* timer 3 base register */
81 #define TM01BR __SYSREG(0xd4003010, u16) /* timer 0:1 base register */
83 #define TM0BC __SYSREGC(0xd4003020, u8) /* timer 0 binary counter */
84 #define TM1BC __SYSREGC(0xd4003021, u8) /* timer 1 binary counter */
85 #define TM2BC __SYSREGC(0xd4003022, u8) /* timer 2 binary counter */
86 #define TM3BC __SYSREGC(0xd4003023, u8) /* timer 3 binary counter */
87 #define TM01BC __SYSREGC(0xd4003020, u16) /* timer 0:1 binary counter */
89 #define TM0IRQ 2 /* timer 0 IRQ */
90 #define TM1IRQ 3 /* timer 1 IRQ */
91 #define TM2IRQ 4 /* timer 2 IRQ */
92 #define TM3IRQ 5 /* timer 3 IRQ */
94 #define TM0ICR GxICR(TM0IRQ) /* timer 0 uflow intr ctrl reg */
95 #define TM1ICR GxICR(TM1IRQ) /* timer 1 uflow intr ctrl reg */
96 #define TM2ICR GxICR(TM2IRQ) /* timer 2 uflow intr ctrl reg */
97 #define TM3ICR GxICR(TM3IRQ) /* timer 3 uflow intr ctrl reg */
99 /* 16-bit timers 4,5 & 7-11 */
100 #define TM4MD __SYSREG(0xd4003080, u8) /* timer 4 mode register */
101 #define TM4MD_SRC 0x07 /* timer source */
102 #define TM4MD_SRC_IOCLK 0x00 /* - IOCLK */
103 #define TM4MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
104 #define TM4MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
105 #define TM4MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
106 #define TM4MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
107 #define TM4MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
108 #define TM4MD_SRC_TM4IO 0x07 /* - TM4IO pin input */
109 #define TM4MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
110 #define TM4MD_COUNT_ENABLE 0x80 /* timer count enable */
112 #define TM5MD __SYSREG(0xd4003082, u8) /* timer 5 mode register */
113 #define TM5MD_SRC 0x07 /* timer source */
114 #define TM5MD_SRC_IOCLK 0x00 /* - IOCLK */
115 #define TM5MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
116 #define TM5MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
117 #define TM5MD_SRC_TM4CASCADE 0x03 /* - cascade with timer 4 */
118 #define TM5MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
119 #define TM5MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
120 #define TM5MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
121 #define TM5MD_SRC_TM5IO 0x07 /* - TM5IO pin input */
122 #define TM5MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
123 #define TM5MD_COUNT_ENABLE 0x80 /* timer count enable */
125 #define TM7MD __SYSREG(0xd4003086, u8) /* timer 7 mode register */
126 #define TM7MD_SRC 0x07 /* timer source */
127 #define TM7MD_SRC_IOCLK 0x00 /* - IOCLK */
128 #define TM7MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
129 #define TM7MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
130 #define TM7MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
131 #define TM7MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
132 #define TM7MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
133 #define TM7MD_SRC_TM7IO 0x07 /* - TM7IO pin input */
134 #define TM7MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
135 #define TM7MD_COUNT_ENABLE 0x80 /* timer count enable */
137 #define TM8MD __SYSREG(0xd4003088, u8) /* timer 8 mode register */
138 #define TM8MD_SRC 0x07 /* timer source */
139 #define TM8MD_SRC_IOCLK 0x00 /* - IOCLK */
140 #define TM8MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
141 #define TM8MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
142 #define TM8MD_SRC_TM7CASCADE 0x03 /* - cascade with timer 7 */
143 #define TM8MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
144 #define TM8MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
145 #define TM8MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
146 #define TM8MD_SRC_TM8IO 0x07 /* - TM8IO pin input */
147 #define TM8MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
148 #define TM8MD_COUNT_ENABLE 0x80 /* timer count enable */
150 #define TM9MD __SYSREG(0xd400308a, u8) /* timer 9 mode register */
151 #define TM9MD_SRC 0x07 /* timer source */
152 #define TM9MD_SRC_IOCLK 0x00 /* - IOCLK */
153 #define TM9MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
154 #define TM9MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
155 #define TM9MD_SRC_TM8CASCADE 0x03 /* - cascade with timer 8 */
156 #define TM9MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
157 #define TM9MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
158 #define TM9MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
159 #define TM9MD_SRC_TM9IO 0x07 /* - TM9IO pin input */
160 #define TM9MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
161 #define TM9MD_COUNT_ENABLE 0x80 /* timer count enable */
163 #define TM10MD __SYSREG(0xd400308c, u8) /* timer 10 mode register */
164 #define TM10MD_SRC 0x07 /* timer source */
165 #define TM10MD_SRC_IOCLK 0x00 /* - IOCLK */
166 #define TM10MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
167 #define TM10MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
168 #define TM10MD_SRC_TM9CASCADE 0x03 /* - cascade with timer 9 */
169 #define TM10MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
170 #define TM10MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
171 #define TM10MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
172 #define TM10MD_SRC_TM10IO 0x07 /* - TM10IO pin input */
173 #define TM10MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
174 #define TM10MD_COUNT_ENABLE 0x80 /* timer count enable */
176 #define TM11MD __SYSREG(0xd400308e, u8) /* timer 11 mode register */
177 #define TM11MD_SRC 0x07 /* timer source */
178 #define TM11MD_SRC_IOCLK 0x00 /* - IOCLK */
179 #define TM11MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
180 #define TM11MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
181 #define TM11MD_SRC_TM7CASCADE 0x03 /* - cascade with timer 7 */
182 #define TM11MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
183 #define TM11MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
184 #define TM11MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
185 #define TM11MD_SRC_TM11IO 0x07 /* - TM11IO pin input */
186 #define TM11MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
187 #define TM11MD_COUNT_ENABLE 0x80 /* timer count enable */
189 #define TM4BR __SYSREG(0xd4003090, u16) /* timer 4 base register */
190 #define TM5BR __SYSREG(0xd4003092, u16) /* timer 5 base register */
191 #define TM7BR __SYSREG(0xd4003096, u16) /* timer 7 base register */
192 #define TM8BR __SYSREG(0xd4003098, u16) /* timer 8 base register */
193 #define TM9BR __SYSREG(0xd400309a, u16) /* timer 9 base register */
194 #define TM10BR __SYSREG(0xd400309c, u16) /* timer 10 base register */
195 #define TM11BR __SYSREG(0xd400309e, u16) /* timer 11 base register */
196 #define TM45BR __SYSREG(0xd4003090, u32) /* timer 4:5 base register */
198 #define TM4BC __SYSREG(0xd40030a0, u16) /* timer 4 binary counter */
199 #define TM5BC __SYSREG(0xd40030a2, u16) /* timer 5 binary counter */
200 #define TM45BC __SYSREG(0xd40030a0, u32) /* timer 4:5 binary counter */
202 #define TM7BC __SYSREG(0xd40030a6, u16) /* timer 7 binary counter */
203 #define TM8BC __SYSREG(0xd40030a8, u16) /* timer 8 binary counter */
204 #define TM9BC __SYSREG(0xd40030aa, u16) /* timer 9 binary counter */
205 #define TM10BC __SYSREG(0xd40030ac, u16) /* timer 10 binary counter */
206 #define TM11BC __SYSREG(0xd40030ae, u16) /* timer 11 binary counter */
208 #define TM4IRQ 6 /* timer 4 IRQ */
209 #define TM5IRQ 7 /* timer 5 IRQ */
210 #define TM7IRQ 11 /* timer 7 IRQ */
211 #define TM8IRQ 12 /* timer 8 IRQ */
212 #define TM9IRQ 13 /* timer 9 IRQ */
213 #define TM10IRQ 14 /* timer 10 IRQ */
214 #define TM11IRQ 15 /* timer 11 IRQ */
216 #define TM4ICR GxICR(TM4IRQ) /* timer 4 uflow intr ctrl reg */
217 #define TM5ICR GxICR(TM5IRQ) /* timer 5 uflow intr ctrl reg */
218 #define TM7ICR GxICR(TM7IRQ) /* timer 7 uflow intr ctrl reg */
219 #define TM8ICR GxICR(TM8IRQ) /* timer 8 uflow intr ctrl reg */
220 #define TM9ICR GxICR(TM9IRQ) /* timer 9 uflow intr ctrl reg */
221 #define TM10ICR GxICR(TM10IRQ) /* timer 10 uflow intr ctrl reg */
222 #define TM11ICR GxICR(TM11IRQ) /* timer 11 uflow intr ctrl reg */
225 #define TM6MD __SYSREG(0xd4003084, u16) /* timer6 mode register */
226 #define TM6MD_SRC 0x0007 /* timer source */
227 #define TM6MD_SRC_IOCLK 0x0000 /* - IOCLK */
228 #define TM6MD_SRC_IOCLK_8 0x0001 /* - 1/8 IOCLK */
229 #define TM6MD_SRC_IOCLK_32 0x0002 /* - 1/32 IOCLK */
230 #define TM6MD_SRC_TM0UFLOW 0x0004 /* - timer 0 underflow */
231 #define TM6MD_SRC_TM1UFLOW 0x0005 /* - timer 1 underflow */
232 #define TM6MD_SRC_TM6IOB_BOTH 0x0006 /* - TM6IOB pin input (both edges) */
233 #define TM6MD_SRC_TM6IOB_SINGLE 0x0007 /* - TM6IOB pin input (single edge) */
234 #define TM6MD_CLR_ENABLE 0x0010 /* clear count enable */
235 #define TM6MD_ONESHOT_ENABLE 0x0040 /* oneshot count */
236 #define TM6MD_TRIG_ENABLE 0x0080 /* TM6IOB pin trigger enable */
237 #define TM6MD_PWM 0x3800 /* PWM output mode */
238 #define TM6MD_PWM_DIS 0x0000 /* - disabled */
239 #define TM6MD_PWM_10BIT 0x1000 /* - 10 bits mode */
240 #define TM6MD_PWM_11BIT 0x1800 /* - 11 bits mode */
241 #define TM6MD_PWM_12BIT 0x3000 /* - 12 bits mode */
242 #define TM6MD_PWM_14BIT 0x3800 /* - 14 bits mode */
243 #define TM6MD_INIT_COUNTER 0x4000 /* initialize TMnBC to zero */
244 #define TM6MD_COUNT_ENABLE 0x8000 /* timer count enable */
246 #define TM6MDA __SYSREG(0xd40030b4, u8) /* timer6 cmp/cap A mode reg */
247 #define TM6MDA_OUT 0x07 /* output select */
248 #define TM6MDA_OUT_SETA_RESETB 0x00 /* - set at match A, reset at match B */
249 #define TM6MDA_OUT_SETA_RESETOV 0x01 /* - set at match A, reset at overflow */
250 #define TM6MDA_OUT_SETA 0x02 /* - set at match A */
251 #define TM6MDA_OUT_RESETA 0x03 /* - reset at match A */
252 #define TM6MDA_OUT_TOGGLE 0x04 /* - toggle on match A */
253 #define TM6MDA_MODE 0xc0 /* compare A register mode */
254 #define TM6MDA_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */
255 #define TM6MDA_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */
256 #define TM6MDA_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */
257 #define TM6MDA_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */
258 #define TM6MDA_EDGE 0x20 /* compare A edge select */
259 #define TM6MDA_EDGE_FALLING 0x00 /* capture on falling edge */
260 #define TM6MDA_EDGE_RISING 0x20 /* capture on rising edge */
261 #define TM6MDA_CAPTURE_ENABLE 0x10 /* capture enable */
263 #define TM6MDB __SYSREG(0xd40030b5, u8) /* timer6 cmp/cap B mode reg */
264 #define TM6MDB_OUT 0x07 /* output select */
265 #define TM6MDB_OUT_SETB_RESETA 0x00 /* - set at match B, reset at match A */
266 #define TM6MDB_OUT_SETB_RESETOV 0x01 /* - set at match B */
267 #define TM6MDB_OUT_RESETB 0x03 /* - reset at match B */
268 #define TM6MDB_OUT_TOGGLE 0x04 /* - toggle on match B */
269 #define TM6MDB_MODE 0xc0 /* compare B register mode */
270 #define TM6MDB_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */
271 #define TM6MDB_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */
272 #define TM6MDB_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */
273 #define TM6MDB_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */
274 #define TM6MDB_EDGE 0x20 /* compare B edge select */
275 #define TM6MDB_EDGE_FALLING 0x00 /* capture on falling edge */
276 #define TM6MDB_EDGE_RISING 0x20 /* capture on rising edge */
277 #define TM6MDB_CAPTURE_ENABLE 0x10 /* capture enable */
279 #define TM6CA __SYSREG(0xd40030c4, u16) /* timer6 cmp/capture reg A */
280 #define TM6CB __SYSREG(0xd40030d4, u16) /* timer6 cmp/capture reg B */
281 #define TM6BC __SYSREG(0xd40030a4, u16) /* timer6 binary counter */
283 #define TM6IRQ 6 /* timer 6 IRQ */
284 #define TM6AIRQ 9 /* timer 6A IRQ */
285 #define TM6BIRQ 10 /* timer 6B IRQ */
287 #define TM6ICR GxICR(TM6IRQ) /* timer 6 uflow intr ctrl reg */
288 #define TM6AICR GxICR(TM6AIRQ) /* timer 6A intr control reg */
289 #define TM6BICR GxICR(TM6BIRQ) /* timer 6B intr control reg */
291 #endif /* __KERNEL__ */
293 #endif /* _ASM_TIMER_REGS_H */
