include/asm-x86/spinlock.h

   1 #ifndef _X86_SPINLOCK_H_
   2 #define _X86_SPINLOCK_H_
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7 #include <asm/processor.h>
   8 #include <linux/compiler.h>
   9
  10 /*
  11  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  12  *
  13  * Simple spin lock operations.  There are two variants, one clears IRQ's
  14  * on the local processor, one does not.
  15  *
  16  * These are fair FIFO ticket locks, which are currently limited to 256
  17  * CPUs.
  18  *
  19  * (the type definitions are in asm/spinlock_types.h)
  20  */
  21
  22 #ifdef CONFIG_X86_32
  23 # define LOCK_PTR_REG "a"
  24 #else
  25 # define LOCK_PTR_REG "D"
  26 #endif
  27
  28 #if defined(CONFIG_X86_32) && \
  29         (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
  30 /*
  31  * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
  32  * (PPro errata 66, 92)
  33  */
  34 # define UNLOCK_LOCK_PREFIX LOCK_PREFIX
  35 #else
  36 # define UNLOCK_LOCK_PREFIX
  37 #endif
  38
  39 /*
  40  * Ticket locks are conceptually two parts, one indicating the current head of
  41  * the queue, and the other indicating the current tail. The lock is acquired
  42  * by atomically noting the tail and incrementing it by one (thus adding
  43  * ourself to the queue and noting our position), then waiting until the head
  44  * becomes equal to the the initial value of the tail.
  45  *
  46  * We use an xadd covering *both* parts of the lock, to increment the tail and
  47  * also load the position of the head, which takes care of memory ordering
  48  * issues and should be optimal for the uncontended case. Note the tail must be
  49  * in the high part, because a wide xadd increment of the low part would carry
  50  * up and contaminate the high part.
  51  *
  52  * With fewer than 2^8 possible CPUs, we can use x86's partial registers to
  53  * save some instructions and make the code more elegant. There really isn't
  54  * much between them in performance though, especially as locks are out of line.
  55  */
  56 #if (NR_CPUS < 256)
  57 static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
  58 {
  59         int tmp = ACCESS_ONCE(lock->slock);
  60
  61         return (((tmp >> 8) & 0xff) != (tmp & 0xff));
  62 }
  63
  64 static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
  65 {
  66         int tmp = ACCESS_ONCE(lock->slock);
  67
  68         return (((tmp >> 8) & 0xff) - (tmp & 0xff)) > 1;
  69 }
  70
  71 static __always_inline void __raw_spin_lock(raw_spinlock_t *lock)
  72 {
  73         short inc = 0x0100;
  74
  75         asm volatile (
  76                 LOCK_PREFIX "xaddw %w0, %1\n"
  77                 "1:\t"
  78                 "cmpb %h0, %b0\n\t"
  79                 "je 2f\n\t"
  80                 "rep ; nop\n\t"
  81                 "movb %1, %b0\n\t"
  82                 /* don't need lfence here, because loads are in-order */
  83                 "jmp 1b\n"
  84                 "2:"
  85                 : "+Q" (inc), "+m" (lock->slock)
  86                 :
  87                 : "memory", "cc");
  88 }
  89
  90 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
  91
  92 static __always_inline int __raw_spin_trylock(raw_spinlock_t *lock)
  93 {
  94         int tmp;
  95         short new;
  96
  97         asm volatile("movw %2,%w0\n\t"
  98                      "cmpb %h0,%b0\n\t"
  99                      "jne 1f\n\t"
 100                      "movw %w0,%w1\n\t"
 101                      "incb %h1\n\t"
 102                      "lock ; cmpxchgw %w1,%2\n\t"
 103                      "1:"
 104                      "sete %b1\n\t"
 105                      "movzbl %b1,%0\n\t"
 106                      : "=&a" (tmp), "=Q" (new), "+m" (lock->slock)
 107                      :
 108                      : "memory", "cc");
 109
 110         return tmp;
 111 }
 112
 113 static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
 114 {
 115         asm volatile(UNLOCK_LOCK_PREFIX "incb %0"
 116                      : "+m" (lock->slock)
 117                      :
 118                      : "memory", "cc");
 119 }
 120 #else
 121 static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
 122 {
 123         int tmp = ACCESS_ONCE(lock->slock);
 124
 125         return (((tmp >> 16) & 0xffff) != (tmp & 0xffff));
 126 }
 127
 128 static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
 129 {
 130         int tmp = ACCESS_ONCE(lock->slock);
 131
 132         return (((tmp >> 16) & 0xffff) - (tmp & 0xffff)) > 1;
 133 }
 134
 135 static __always_inline void __raw_spin_lock(raw_spinlock_t *lock)
 136 {
 137         int inc = 0x00010000;
 138         int tmp;
 139
 140         asm volatile("lock ; xaddl %0, %1\n"
 141                      "movzwl %w0, %2\n\t"
 142                      "shrl $16, %0\n\t"
 143                      "1:\t"
 144                      "cmpl %0, %2\n\t"
 145                      "je 2f\n\t"
 146                      "rep ; nop\n\t"
 147                      "movzwl %1, %2\n\t"
 148                      /* don't need lfence here, because loads are in-order */
 149                      "jmp 1b\n"
 150                      "2:"
 151                      : "+Q" (inc), "+m" (lock->slock), "=r" (tmp)
 152                      :
 153                      : "memory", "cc");
 154 }
 155
 156 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
 157
 158 static __always_inline int __raw_spin_trylock(raw_spinlock_t *lock)
 159 {
 160         int tmp;
 161         int new;
 162
 163         asm volatile("movl %2,%0\n\t"
 164                      "movl %0,%1\n\t"
 165                      "roll $16, %0\n\t"
 166                      "cmpl %0,%1\n\t"
 167                      "jne 1f\n\t"
 168                      "addl $0x00010000, %1\n\t"
 169                      "lock ; cmpxchgl %1,%2\n\t"
 170                      "1:"
 171                      "sete %b1\n\t"
 172                      "movzbl %b1,%0\n\t"
 173                      : "=&a" (tmp), "=r" (new), "+m" (lock->slock)
 174                      :
 175                      : "memory", "cc");
 176
 177         return tmp;
 178 }
 179
 180 static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
 181 {
 182         asm volatile(UNLOCK_LOCK_PREFIX "incw %0"
 183                      : "+m" (lock->slock)
 184                      :
 185                      : "memory", "cc");
 186 }
 187 #endif
 188
 189 static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
 190 {
 191         while (__raw_spin_is_locked(lock))
 192                 cpu_relax();
 193 }
 194
 195 /*
 196  * Read-write spinlocks, allowing multiple readers
 197  * but only one writer.
 198  *
 199  * NOTE! it is quite common to have readers in interrupts
 200  * but no interrupt writers. For those circumstances we
 201  * can "mix" irq-safe locks - any writer needs to get a
 202  * irq-safe write-lock, but readers can get non-irqsafe
 203  * read-locks.
 204  *
 205  * On x86, we implement read-write locks as a 32-bit counter
 206  * with the high bit (sign) being the "contended" bit.
 207  */
 208
 209 /**
 210  * read_can_lock - would read_trylock() succeed?
 211  * @lock: the rwlock in question.
 212  */
 213 static inline int __raw_read_can_lock(raw_rwlock_t *lock)
 214 {
 215         return (int)(lock)->lock > 0;
 216 }
 217
 218 /**
 219  * write_can_lock - would write_trylock() succeed?
 220  * @lock: the rwlock in question.
 221  */
 222 static inline int __raw_write_can_lock(raw_rwlock_t *lock)
 223 {
 224         return (lock)->lock == RW_LOCK_BIAS;
 225 }
 226
 227 static inline void __raw_read_lock(raw_rwlock_t *rw)
 228 {
 229         asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
 230                      "jns 1f\n"
 231                      "call __read_lock_failed\n\t"
 232                      "1:\n"
 233                      ::LOCK_PTR_REG (rw) : "memory");
 234 }
 235
 236 static inline void __raw_write_lock(raw_rwlock_t *rw)
 237 {
 238         asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t"
 239                      "jz 1f\n"
 240                      "call __write_lock_failed\n\t"
 241                      "1:\n"
 242                      ::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory");
 243 }
 244
 245 static inline int __raw_read_trylock(raw_rwlock_t *lock)
 246 {
 247         atomic_t *count = (atomic_t *)lock;
 248
 249         atomic_dec(count);
 250         if (atomic_read(count) >= 0)
 251                 return 1;
 252         atomic_inc(count);
 253         return 0;
 254 }
 255
 256 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 257 {
 258         atomic_t *count = (atomic_t *)lock;
 259
 260         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 261                 return 1;
 262         atomic_add(RW_LOCK_BIAS, count);
 263         return 0;
 264 }
 265
 266 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 267 {
 268         asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
 269 }
 270
 271 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 272 {
 273         asm volatile(LOCK_PREFIX "addl %1, %0"
 274                      : "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory");
 275 }
 276
 277 #define _raw_spin_relax(lock)   cpu_relax()
 278 #define _raw_read_relax(lock)   cpu_relax()
 279 #define _raw_write_relax(lock)  cpu_relax()
 280
 281 #endif