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percpu_counter: FBC_BATCH should be a variable
[linux-2.6/mini2440.git] / drivers / dma / iop-adma.c
blob6be3172622009ff67ec502b049f167d6ccebe1cd
1 /*
2 * offload engine driver for the Intel Xscale series of i/o processors
3 * Copyright © 2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20 /*
21 * This driver supports the asynchrounous DMA copy and RAID engines available
22 * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/async_tx.h>
28 #include <linux/delay.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/spinlock.h>
31 #include <linux/interrupt.h>
32 #include <linux/platform_device.h>
33 #include <linux/memory.h>
34 #include <linux/ioport.h>
35
36 #include <mach/adma.h>
37
38 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
39 #define to_iop_adma_device(dev) \
40 container_of(dev, struct iop_adma_device, common)
41 #define tx_to_iop_adma_slot(tx) \
42 container_of(tx, struct iop_adma_desc_slot, async_tx)
43
44 /**
45 * iop_adma_free_slots - flags descriptor slots for reuse
46 * @slot: Slot to free
47 * Caller must hold &iop_chan->lock while calling this function
48 */
49 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
50 {
51 int stride = slot->slots_per_op;
52
53 while (stride--) {
54 slot->slots_per_op = 0;
55 slot = list_entry(slot->slot_node.next,
56 struct iop_adma_desc_slot,
57 slot_node);
58 }
59 }
60
61 static dma_cookie_t
62 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
63 struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
64 {
65 BUG_ON(desc->async_tx.cookie < 0);
66 if (desc->async_tx.cookie > 0) {
67 cookie = desc->async_tx.cookie;
68 desc->async_tx.cookie = 0;
69
70 /* call the callback (must not sleep or submit new
71 * operations to this channel)
72 */
73 if (desc->async_tx.callback)
74 desc->async_tx.callback(
75 desc->async_tx.callback_param);
76
77 /* unmap dma addresses
78 * (unmap_single vs unmap_page?)
79 */
80 if (desc->group_head && desc->unmap_len) {
81 struct iop_adma_desc_slot *unmap = desc->group_head;
82 struct device *dev =
83 &iop_chan->device->pdev->dev;
84 u32 len = unmap->unmap_len;
85 enum dma_ctrl_flags flags = desc->async_tx.flags;
86 u32 src_cnt;
87 dma_addr_t addr;
88 dma_addr_t dest;
89
90 src_cnt = unmap->unmap_src_cnt;
91 dest = iop_desc_get_dest_addr(unmap, iop_chan);
92 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
93 enum dma_data_direction dir;
94
95 if (src_cnt > 1) /* is xor? */
96 dir = DMA_BIDIRECTIONAL;
97 else
98 dir = DMA_FROM_DEVICE;
99
100 dma_unmap_page(dev, dest, len, dir);
101 }
102
103 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
104 while (src_cnt--) {
105 addr = iop_desc_get_src_addr(unmap,
106 iop_chan,
107 src_cnt);
108 if (addr == dest)
109 continue;
110 dma_unmap_page(dev, addr, len,
111 DMA_TO_DEVICE);
112 }
113 }
114 desc->group_head = NULL;
115 }
116 }
117
118 /* run dependent operations */
119 async_tx_run_dependencies(&desc->async_tx);
120
121 return cookie;
122 }
123
124 static int
125 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
126 struct iop_adma_chan *iop_chan)
127 {
128 /* the client is allowed to attach dependent operations
129 * until 'ack' is set
130 */
131 if (!async_tx_test_ack(&desc->async_tx))
132 return 0;
133
134 /* leave the last descriptor in the chain
135 * so we can append to it
136 */
137 if (desc->chain_node.next == &iop_chan->chain)
138 return 1;
139
140 dev_dbg(iop_chan->device->common.dev,
141 "\tfree slot: %d slots_per_op: %d\n",
142 desc->idx, desc->slots_per_op);
143
144 list_del(&desc->chain_node);
145 iop_adma_free_slots(desc);
146
147 return 0;
148 }
149
150 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
151 {
152 struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
153 dma_cookie_t cookie = 0;
154 u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
155 int busy = iop_chan_is_busy(iop_chan);
156 int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
157
158 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
159 /* free completed slots from the chain starting with
160 * the oldest descriptor
161 */
162 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
163 chain_node) {
164 pr_debug("\tcookie: %d slot: %d busy: %d "
165 "this_desc: %#x next_desc: %#x ack: %d\n",
166 iter->async_tx.cookie, iter->idx, busy,
167 iter->async_tx.phys, iop_desc_get_next_desc(iter),
168 async_tx_test_ack(&iter->async_tx));
169 prefetch(_iter);
170 prefetch(&_iter->async_tx);
171
172 /* do not advance past the current descriptor loaded into the
173 * hardware channel, subsequent descriptors are either in
174 * process or have not been submitted
175 */
176 if (seen_current)
177 break;
178
179 /* stop the search if we reach the current descriptor and the
180 * channel is busy, or if it appears that the current descriptor
181 * needs to be re-read (i.e. has been appended to)
182 */
183 if (iter->async_tx.phys == current_desc) {
184 BUG_ON(seen_current++);
185 if (busy || iop_desc_get_next_desc(iter))
186 break;
187 }
188
189 /* detect the start of a group transaction */
190 if (!slot_cnt && !slots_per_op) {
191 slot_cnt = iter->slot_cnt;
192 slots_per_op = iter->slots_per_op;
193 if (slot_cnt <= slots_per_op) {
194 slot_cnt = 0;
195 slots_per_op = 0;
196 }
197 }
198
199 if (slot_cnt) {
200 pr_debug("\tgroup++\n");
201 if (!grp_start)
202 grp_start = iter;
203 slot_cnt -= slots_per_op;
204 }
205
206 /* all the members of a group are complete */
207 if (slots_per_op != 0 && slot_cnt == 0) {
208 struct iop_adma_desc_slot *grp_iter, *_grp_iter;
209 int end_of_chain = 0;
210 pr_debug("\tgroup end\n");
211
212 /* collect the total results */
213 if (grp_start->xor_check_result) {
214 u32 zero_sum_result = 0;
215 slot_cnt = grp_start->slot_cnt;
216 grp_iter = grp_start;
217
218 list_for_each_entry_from(grp_iter,
219 &iop_chan->chain, chain_node) {
220 zero_sum_result |=
221 iop_desc_get_zero_result(grp_iter);
222 pr_debug("\titer%d result: %d\n",
223 grp_iter->idx, zero_sum_result);
224 slot_cnt -= slots_per_op;
225 if (slot_cnt == 0)
226 break;
227 }
228 pr_debug("\tgrp_start->xor_check_result: %p\n",
229 grp_start->xor_check_result);
230 *grp_start->xor_check_result = zero_sum_result;
231 }
232
233 /* clean up the group */
234 slot_cnt = grp_start->slot_cnt;
235 grp_iter = grp_start;
236 list_for_each_entry_safe_from(grp_iter, _grp_iter,
237 &iop_chan->chain, chain_node) {
238 cookie = iop_adma_run_tx_complete_actions(
239 grp_iter, iop_chan, cookie);
240
241 slot_cnt -= slots_per_op;
242 end_of_chain = iop_adma_clean_slot(grp_iter,
243 iop_chan);
244
245 if (slot_cnt == 0 || end_of_chain)
246 break;
247 }
248
249 /* the group should be complete at this point */
250 BUG_ON(slot_cnt);
251
252 slots_per_op = 0;
253 grp_start = NULL;
254 if (end_of_chain)
255 break;
256 else
257 continue;
258 } else if (slots_per_op) /* wait for group completion */
259 continue;
260
261 /* write back zero sum results (single descriptor case) */
262 if (iter->xor_check_result && iter->async_tx.cookie)
263 *iter->xor_check_result =
264 iop_desc_get_zero_result(iter);
265
266 cookie = iop_adma_run_tx_complete_actions(
267 iter, iop_chan, cookie);
268
269 if (iop_adma_clean_slot(iter, iop_chan))
270 break;
271 }
272
273 BUG_ON(!seen_current);
274
275 if (cookie > 0) {
276 iop_chan->completed_cookie = cookie;
277 pr_debug("\tcompleted cookie %d\n", cookie);
278 }
279 }
280
281 static void
282 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
283 {
284 spin_lock_bh(&iop_chan->lock);
285 __iop_adma_slot_cleanup(iop_chan);
286 spin_unlock_bh(&iop_chan->lock);
287 }
288
289 static void iop_adma_tasklet(unsigned long data)
290 {
291 struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
292
293 spin_lock(&iop_chan->lock);
294 __iop_adma_slot_cleanup(iop_chan);
295 spin_unlock(&iop_chan->lock);
296 }
297
298 static struct iop_adma_desc_slot *
299 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
300 int slots_per_op)
301 {
302 struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
303 LIST_HEAD(chain);
304 int slots_found, retry = 0;
305
306 /* start search from the last allocated descrtiptor
307 * if a contiguous allocation can not be found start searching
308 * from the beginning of the list
309 */
310 retry:
311 slots_found = 0;
312 if (retry == 0)
313 iter = iop_chan->last_used;
314 else
315 iter = list_entry(&iop_chan->all_slots,
316 struct iop_adma_desc_slot,
317 slot_node);
318
319 list_for_each_entry_safe_continue(
320 iter, _iter, &iop_chan->all_slots, slot_node) {
321 prefetch(_iter);
322 prefetch(&_iter->async_tx);
323 if (iter->slots_per_op) {
324 /* give up after finding the first busy slot
325 * on the second pass through the list
326 */
327 if (retry)
328 break;
329
330 slots_found = 0;
331 continue;
332 }
333
334 /* start the allocation if the slot is correctly aligned */
335 if (!slots_found++) {
336 if (iop_desc_is_aligned(iter, slots_per_op))
337 alloc_start = iter;
338 else {
339 slots_found = 0;
340 continue;
341 }
342 }
343
344 if (slots_found == num_slots) {
345 struct iop_adma_desc_slot *alloc_tail = NULL;
346 struct iop_adma_desc_slot *last_used = NULL;
347 iter = alloc_start;
348 while (num_slots) {
349 int i;
350 dev_dbg(iop_chan->device->common.dev,
351 "allocated slot: %d "
352 "(desc %p phys: %#x) slots_per_op %d\n",
353 iter->idx, iter->hw_desc,
354 iter->async_tx.phys, slots_per_op);
355
356 /* pre-ack all but the last descriptor */
357 if (num_slots != slots_per_op)
358 async_tx_ack(&iter->async_tx);
359
360 list_add_tail(&iter->chain_node, &chain);
361 alloc_tail = iter;
362 iter->async_tx.cookie = 0;
363 iter->slot_cnt = num_slots;
364 iter->xor_check_result = NULL;
365 for (i = 0; i < slots_per_op; i++) {
366 iter->slots_per_op = slots_per_op - i;
367 last_used = iter;
368 iter = list_entry(iter->slot_node.next,
369 struct iop_adma_desc_slot,
370 slot_node);
371 }
372 num_slots -= slots_per_op;
373 }
374 alloc_tail->group_head = alloc_start;
375 alloc_tail->async_tx.cookie = -EBUSY;
376 list_splice(&chain, &alloc_tail->async_tx.tx_list);
377 iop_chan->last_used = last_used;
378 iop_desc_clear_next_desc(alloc_start);
379 iop_desc_clear_next_desc(alloc_tail);
380 return alloc_tail;
381 }
382 }
383 if (!retry++)
384 goto retry;
385
386 /* perform direct reclaim if the allocation fails */
387 __iop_adma_slot_cleanup(iop_chan);
388
389 return NULL;
390 }
391
392 static dma_cookie_t
393 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
394 struct iop_adma_desc_slot *desc)
395 {
396 dma_cookie_t cookie = iop_chan->common.cookie;
397 cookie++;
398 if (cookie < 0)
399 cookie = 1;
400 iop_chan->common.cookie = desc->async_tx.cookie = cookie;
401 return cookie;
402 }
403
404 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
405 {
406 dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
407 iop_chan->pending);
408
409 if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
410 iop_chan->pending = 0;
411 iop_chan_append(iop_chan);
412 }
413 }
414
415 static dma_cookie_t
416 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
417 {
418 struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
419 struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
420 struct iop_adma_desc_slot *grp_start, *old_chain_tail;
421 int slot_cnt;
422 int slots_per_op;
423 dma_cookie_t cookie;
424 dma_addr_t next_dma;
425
426 grp_start = sw_desc->group_head;
427 slot_cnt = grp_start->slot_cnt;
428 slots_per_op = grp_start->slots_per_op;
429
430 spin_lock_bh(&iop_chan->lock);
431 cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
432
433 old_chain_tail = list_entry(iop_chan->chain.prev,
434 struct iop_adma_desc_slot, chain_node);
435 list_splice_init(&sw_desc->async_tx.tx_list,
436 &old_chain_tail->chain_node);
437
438 /* fix up the hardware chain */
439 next_dma = grp_start->async_tx.phys;
440 iop_desc_set_next_desc(old_chain_tail, next_dma);
441 BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */
442
443 /* check for pre-chained descriptors */
444 iop_paranoia(iop_desc_get_next_desc(sw_desc));
445
446 /* increment the pending count by the number of slots
447 * memcpy operations have a 1:1 (slot:operation) relation
448 * other operations are heavier and will pop the threshold
449 * more often.
450 */
451 iop_chan->pending += slot_cnt;
452 iop_adma_check_threshold(iop_chan);
453 spin_unlock_bh(&iop_chan->lock);
454
455 dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
456 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
457
458 return cookie;
459 }
460
461 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
462 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
463
464 /**
465 * iop_adma_alloc_chan_resources - returns the number of allocated descriptors
466 * @chan - allocate descriptor resources for this channel
467 * @client - current client requesting the channel be ready for requests
468 *
469 * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To
470 * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be
471 * greater than 2x the number slots needed to satisfy a device->max_xor
472 * request.
473 * */
474 static int iop_adma_alloc_chan_resources(struct dma_chan *chan,
475 struct dma_client *client)
476 {
477 char *hw_desc;
478 int idx;
479 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
480 struct iop_adma_desc_slot *slot = NULL;
481 int init = iop_chan->slots_allocated ? 0 : 1;
482 struct iop_adma_platform_data *plat_data =
483 iop_chan->device->pdev->dev.platform_data;
484 int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
485
486 /* Allocate descriptor slots */
487 do {
488 idx = iop_chan->slots_allocated;
489 if (idx == num_descs_in_pool)
490 break;
491
492 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
493 if (!slot) {
494 printk(KERN_INFO "IOP ADMA Channel only initialized"
495 " %d descriptor slots", idx);
496 break;
497 }
498 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
499 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
500
501 dma_async_tx_descriptor_init(&slot->async_tx, chan);
502 slot->async_tx.tx_submit = iop_adma_tx_submit;
503 INIT_LIST_HEAD(&slot->chain_node);
504 INIT_LIST_HEAD(&slot->slot_node);
505 INIT_LIST_HEAD(&slot->async_tx.tx_list);
506 hw_desc = (char *) iop_chan->device->dma_desc_pool;
507 slot->async_tx.phys =
508 (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
509 slot->idx = idx;
510
511 spin_lock_bh(&iop_chan->lock);
512 iop_chan->slots_allocated++;
513 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
514 spin_unlock_bh(&iop_chan->lock);
515 } while (iop_chan->slots_allocated < num_descs_in_pool);
516
517 if (idx && !iop_chan->last_used)
518 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
519 struct iop_adma_desc_slot,
520 slot_node);
521
522 dev_dbg(iop_chan->device->common.dev,
523 "allocated %d descriptor slots last_used: %p\n",
524 iop_chan->slots_allocated, iop_chan->last_used);
525
526 /* initialize the channel and the chain with a null operation */
527 if (init) {
528 if (dma_has_cap(DMA_MEMCPY,
529 iop_chan->device->common.cap_mask))
530 iop_chan_start_null_memcpy(iop_chan);
531 else if (dma_has_cap(DMA_XOR,
532 iop_chan->device->common.cap_mask))
533 iop_chan_start_null_xor(iop_chan);
534 else
535 BUG();
536 }
537
538 return (idx > 0) ? idx : -ENOMEM;
539 }
540
541 static struct dma_async_tx_descriptor *
542 iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
543 {
544 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
545 struct iop_adma_desc_slot *sw_desc, *grp_start;
546 int slot_cnt, slots_per_op;
547
548 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
549
550 spin_lock_bh(&iop_chan->lock);
551 slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
552 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
553 if (sw_desc) {
554 grp_start = sw_desc->group_head;
555 iop_desc_init_interrupt(grp_start, iop_chan);
556 grp_start->unmap_len = 0;
557 sw_desc->async_tx.flags = flags;
558 }
559 spin_unlock_bh(&iop_chan->lock);
560
561 return sw_desc ? &sw_desc->async_tx : NULL;
562 }
563
564 static struct dma_async_tx_descriptor *
565 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
566 dma_addr_t dma_src, size_t len, unsigned long flags)
567 {
568 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
569 struct iop_adma_desc_slot *sw_desc, *grp_start;
570 int slot_cnt, slots_per_op;
571
572 if (unlikely(!len))
573 return NULL;
574 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
575
576 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
577 __func__, len);
578
579 spin_lock_bh(&iop_chan->lock);
580 slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
581 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
582 if (sw_desc) {
583 grp_start = sw_desc->group_head;
584 iop_desc_init_memcpy(grp_start, flags);
585 iop_desc_set_byte_count(grp_start, iop_chan, len);
586 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
587 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
588 sw_desc->unmap_src_cnt = 1;
589 sw_desc->unmap_len = len;
590 sw_desc->async_tx.flags = flags;
591 }
592 spin_unlock_bh(&iop_chan->lock);
593
594 return sw_desc ? &sw_desc->async_tx : NULL;
595 }
596
597 static struct dma_async_tx_descriptor *
598 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
599 int value, size_t len, unsigned long flags)
600 {
601 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
602 struct iop_adma_desc_slot *sw_desc, *grp_start;
603 int slot_cnt, slots_per_op;
604
605 if (unlikely(!len))
606 return NULL;
607 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
608
609 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
610 __func__, len);
611
612 spin_lock_bh(&iop_chan->lock);
613 slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
614 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
615 if (sw_desc) {
616 grp_start = sw_desc->group_head;
617 iop_desc_init_memset(grp_start, flags);
618 iop_desc_set_byte_count(grp_start, iop_chan, len);
619 iop_desc_set_block_fill_val(grp_start, value);
620 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
621 sw_desc->unmap_src_cnt = 1;
622 sw_desc->unmap_len = len;
623 sw_desc->async_tx.flags = flags;
624 }
625 spin_unlock_bh(&iop_chan->lock);
626
627 return sw_desc ? &sw_desc->async_tx : NULL;
628 }
629
630 static struct dma_async_tx_descriptor *
631 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
632 dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
633 unsigned long flags)
634 {
635 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
636 struct iop_adma_desc_slot *sw_desc, *grp_start;
637 int slot_cnt, slots_per_op;
638
639 if (unlikely(!len))
640 return NULL;
641 BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
642
643 dev_dbg(iop_chan->device->common.dev,
644 "%s src_cnt: %d len: %u flags: %lx\n",
645 __func__, src_cnt, len, flags);
646
647 spin_lock_bh(&iop_chan->lock);
648 slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
649 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
650 if (sw_desc) {
651 grp_start = sw_desc->group_head;
652 iop_desc_init_xor(grp_start, src_cnt, flags);
653 iop_desc_set_byte_count(grp_start, iop_chan, len);
654 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
655 sw_desc->unmap_src_cnt = src_cnt;
656 sw_desc->unmap_len = len;
657 sw_desc->async_tx.flags = flags;
658 while (src_cnt--)
659 iop_desc_set_xor_src_addr(grp_start, src_cnt,
660 dma_src[src_cnt]);
661 }
662 spin_unlock_bh(&iop_chan->lock);
663
664 return sw_desc ? &sw_desc->async_tx : NULL;
665 }
666
667 static struct dma_async_tx_descriptor *
668 iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src,
669 unsigned int src_cnt, size_t len, u32 *result,
670 unsigned long flags)
671 {
672 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
673 struct iop_adma_desc_slot *sw_desc, *grp_start;
674 int slot_cnt, slots_per_op;
675
676 if (unlikely(!len))
677 return NULL;
678
679 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
680 __func__, src_cnt, len);
681
682 spin_lock_bh(&iop_chan->lock);
683 slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
684 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
685 if (sw_desc) {
686 grp_start = sw_desc->group_head;
687 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
688 iop_desc_set_zero_sum_byte_count(grp_start, len);
689 grp_start->xor_check_result = result;
690 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
691 __func__, grp_start->xor_check_result);
692 sw_desc->unmap_src_cnt = src_cnt;
693 sw_desc->unmap_len = len;
694 sw_desc->async_tx.flags = flags;
695 while (src_cnt--)
696 iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
697 dma_src[src_cnt]);
698 }
699 spin_unlock_bh(&iop_chan->lock);
700
701 return sw_desc ? &sw_desc->async_tx : NULL;
702 }
703
704 static void iop_adma_free_chan_resources(struct dma_chan *chan)
705 {
706 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
707 struct iop_adma_desc_slot *iter, *_iter;
708 int in_use_descs = 0;
709
710 iop_adma_slot_cleanup(iop_chan);
711
712 spin_lock_bh(&iop_chan->lock);
713 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
714 chain_node) {
715 in_use_descs++;
716 list_del(&iter->chain_node);
717 }
718 list_for_each_entry_safe_reverse(
719 iter, _iter, &iop_chan->all_slots, slot_node) {
720 list_del(&iter->slot_node);
721 kfree(iter);
722 iop_chan->slots_allocated--;
723 }
724 iop_chan->last_used = NULL;
725
726 dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
727 __func__, iop_chan->slots_allocated);
728 spin_unlock_bh(&iop_chan->lock);
729
730 /* one is ok since we left it on there on purpose */
731 if (in_use_descs > 1)
732 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
733 in_use_descs - 1);
734 }
735
736 /**
737 * iop_adma_is_complete - poll the status of an ADMA transaction
738 * @chan: ADMA channel handle
739 * @cookie: ADMA transaction identifier
740 */
741 static enum dma_status iop_adma_is_complete(struct dma_chan *chan,
742 dma_cookie_t cookie,
743 dma_cookie_t *done,
744 dma_cookie_t *used)
745 {
746 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
747 dma_cookie_t last_used;
748 dma_cookie_t last_complete;
749 enum dma_status ret;
750
751 last_used = chan->cookie;
752 last_complete = iop_chan->completed_cookie;
753
754 if (done)
755 *done = last_complete;
756 if (used)
757 *used = last_used;
758
759 ret = dma_async_is_complete(cookie, last_complete, last_used);
760 if (ret == DMA_SUCCESS)
761 return ret;
762
763 iop_adma_slot_cleanup(iop_chan);
764
765 last_used = chan->cookie;
766 last_complete = iop_chan->completed_cookie;
767
768 if (done)
769 *done = last_complete;
770 if (used)
771 *used = last_used;
772
773 return dma_async_is_complete(cookie, last_complete, last_used);
774 }
775
776 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
777 {
778 struct iop_adma_chan *chan = data;
779
780 dev_dbg(chan->device->common.dev, "%s\n", __func__);
781
782 tasklet_schedule(&chan->irq_tasklet);
783
784 iop_adma_device_clear_eot_status(chan);
785
786 return IRQ_HANDLED;
787 }
788
789 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
790 {
791 struct iop_adma_chan *chan = data;
792
793 dev_dbg(chan->device->common.dev, "%s\n", __func__);
794
795 tasklet_schedule(&chan->irq_tasklet);
796
797 iop_adma_device_clear_eoc_status(chan);
798
799 return IRQ_HANDLED;
800 }
801
802 static irqreturn_t iop_adma_err_handler(int irq, void *data)
803 {
804 struct iop_adma_chan *chan = data;
805 unsigned long status = iop_chan_get_status(chan);
806
807 dev_printk(KERN_ERR, chan->device->common.dev,
808 "error ( %s%s%s%s%s%s%s)\n",
809 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
810 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
811 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
812 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
813 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
814 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
815 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
816
817 iop_adma_device_clear_err_status(chan);
818
819 BUG();
820
821 return IRQ_HANDLED;
822 }
823
824 static void iop_adma_issue_pending(struct dma_chan *chan)
825 {
826 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
827
828 if (iop_chan->pending) {
829 iop_chan->pending = 0;
830 iop_chan_append(iop_chan);
831 }
832 }
833
834 /*
835 * Perform a transaction to verify the HW works.
836 */
837 #define IOP_ADMA_TEST_SIZE 2000
838
839 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
840 {
841 int i;
842 void *src, *dest;
843 dma_addr_t src_dma, dest_dma;
844 struct dma_chan *dma_chan;
845 dma_cookie_t cookie;
846 struct dma_async_tx_descriptor *tx;
847 int err = 0;
848 struct iop_adma_chan *iop_chan;
849
850 dev_dbg(device->common.dev, "%s\n", __func__);
851
852 src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
853 if (!src)
854 return -ENOMEM;
855 dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
856 if (!dest) {
857 kfree(src);
858 return -ENOMEM;
859 }
860
861 /* Fill in src buffer */
862 for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
863 ((u8 *) src)[i] = (u8)i;
864
865 /* Start copy, using first DMA channel */
866 dma_chan = container_of(device->common.channels.next,
867 struct dma_chan,
868 device_node);
869 if (iop_adma_alloc_chan_resources(dma_chan, NULL) < 1) {
870 err = -ENODEV;
871 goto out;
872 }
873
874 dest_dma = dma_map_single(dma_chan->device->dev, dest,
875 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
876 src_dma = dma_map_single(dma_chan->device->dev, src,
877 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
878 tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
879 IOP_ADMA_TEST_SIZE,
880 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
881
882 cookie = iop_adma_tx_submit(tx);
883 iop_adma_issue_pending(dma_chan);
884 msleep(1);
885
886 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
887 DMA_SUCCESS) {
888 dev_printk(KERN_ERR, dma_chan->device->dev,
889 "Self-test copy timed out, disabling\n");
890 err = -ENODEV;
891 goto free_resources;
892 }
893
894 iop_chan = to_iop_adma_chan(dma_chan);
895 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
896 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
897 if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
898 dev_printk(KERN_ERR, dma_chan->device->dev,
899 "Self-test copy failed compare, disabling\n");
900 err = -ENODEV;
901 goto free_resources;
902 }
903
904 free_resources:
905 iop_adma_free_chan_resources(dma_chan);
906 out:
907 kfree(src);
908 kfree(dest);
909 return err;
910 }
911
912 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
913 static int __devinit
914 iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device)
915 {
916 int i, src_idx;
917 struct page *dest;
918 struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
919 struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
920 dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
921 dma_addr_t dma_addr, dest_dma;
922 struct dma_async_tx_descriptor *tx;
923 struct dma_chan *dma_chan;
924 dma_cookie_t cookie;
925 u8 cmp_byte = 0;
926 u32 cmp_word;
927 u32 zero_sum_result;
928 int err = 0;
929 struct iop_adma_chan *iop_chan;
930
931 dev_dbg(device->common.dev, "%s\n", __func__);
932
933 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
934 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
935 if (!xor_srcs[src_idx])
936 while (src_idx--) {
937 __free_page(xor_srcs[src_idx]);
938 return -ENOMEM;
939 }
940 }
941
942 dest = alloc_page(GFP_KERNEL);
943 if (!dest)
944 while (src_idx--) {
945 __free_page(xor_srcs[src_idx]);
946 return -ENOMEM;
947 }
948
949 /* Fill in src buffers */
950 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
951 u8 *ptr = page_address(xor_srcs[src_idx]);
952 for (i = 0; i < PAGE_SIZE; i++)
953 ptr[i] = (1 << src_idx);
954 }
955
956 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
957 cmp_byte ^= (u8) (1 << src_idx);
958
959 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
960 (cmp_byte << 8) | cmp_byte;
961
962 memset(page_address(dest), 0, PAGE_SIZE);
963
964 dma_chan = container_of(device->common.channels.next,
965 struct dma_chan,
966 device_node);
967 if (iop_adma_alloc_chan_resources(dma_chan, NULL) < 1) {
968 err = -ENODEV;
969 goto out;
970 }
971
972 /* test xor */
973 dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
974 PAGE_SIZE, DMA_FROM_DEVICE);
975 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
976 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
977 0, PAGE_SIZE, DMA_TO_DEVICE);
978 tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
979 IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
980 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
981
982 cookie = iop_adma_tx_submit(tx);
983 iop_adma_issue_pending(dma_chan);
984 msleep(8);
985
986 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
987 DMA_SUCCESS) {
988 dev_printk(KERN_ERR, dma_chan->device->dev,
989 "Self-test xor timed out, disabling\n");
990 err = -ENODEV;
991 goto free_resources;
992 }
993
994 iop_chan = to_iop_adma_chan(dma_chan);
995 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
996 PAGE_SIZE, DMA_FROM_DEVICE);
997 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
998 u32 *ptr = page_address(dest);
999 if (ptr[i] != cmp_word) {
1000 dev_printk(KERN_ERR, dma_chan->device->dev,
1001 "Self-test xor failed compare, disabling\n");
1002 err = -ENODEV;
1003 goto free_resources;
1004 }
1005 }
1006 dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
1007 PAGE_SIZE, DMA_TO_DEVICE);
1008
1009 /* skip zero sum if the capability is not present */
1010 if (!dma_has_cap(DMA_ZERO_SUM, dma_chan->device->cap_mask))
1011 goto free_resources;
1012
1013 /* zero sum the sources with the destintation page */
1014 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1015 zero_sum_srcs[i] = xor_srcs[i];
1016 zero_sum_srcs[i] = dest;
1017
1018 zero_sum_result = 1;
1019
1020 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1021 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1022 zero_sum_srcs[i], 0, PAGE_SIZE,
1023 DMA_TO_DEVICE);
1024 tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1025 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1026 &zero_sum_result,
1027 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1028
1029 cookie = iop_adma_tx_submit(tx);
1030 iop_adma_issue_pending(dma_chan);
1031 msleep(8);
1032
1033 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1034 dev_printk(KERN_ERR, dma_chan->device->dev,
1035 "Self-test zero sum timed out, disabling\n");
1036 err = -ENODEV;
1037 goto free_resources;
1038 }
1039
1040 if (zero_sum_result != 0) {
1041 dev_printk(KERN_ERR, dma_chan->device->dev,
1042 "Self-test zero sum failed compare, disabling\n");
1043 err = -ENODEV;
1044 goto free_resources;
1045 }
1046
1047 /* test memset */
1048 dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1049 PAGE_SIZE, DMA_FROM_DEVICE);
1050 tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1051 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1052
1053 cookie = iop_adma_tx_submit(tx);
1054 iop_adma_issue_pending(dma_chan);
1055 msleep(8);
1056
1057 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1058 dev_printk(KERN_ERR, dma_chan->device->dev,
1059 "Self-test memset timed out, disabling\n");
1060 err = -ENODEV;
1061 goto free_resources;
1062 }
1063
1064 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1065 u32 *ptr = page_address(dest);
1066 if (ptr[i]) {
1067 dev_printk(KERN_ERR, dma_chan->device->dev,
1068 "Self-test memset failed compare, disabling\n");
1069 err = -ENODEV;
1070 goto free_resources;
1071 }
1072 }
1073
1074 /* test for non-zero parity sum */
1075 zero_sum_result = 0;
1076 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1077 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1078 zero_sum_srcs[i], 0, PAGE_SIZE,
1079 DMA_TO_DEVICE);
1080 tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1081 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1082 &zero_sum_result,
1083 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1084
1085 cookie = iop_adma_tx_submit(tx);
1086 iop_adma_issue_pending(dma_chan);
1087 msleep(8);
1088
1089 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1090 dev_printk(KERN_ERR, dma_chan->device->dev,
1091 "Self-test non-zero sum timed out, disabling\n");
1092 err = -ENODEV;
1093 goto free_resources;
1094 }
1095
1096 if (zero_sum_result != 1) {
1097 dev_printk(KERN_ERR, dma_chan->device->dev,
1098 "Self-test non-zero sum failed compare, disabling\n");
1099 err = -ENODEV;
1100 goto free_resources;
1101 }
1102
1103 free_resources:
1104 iop_adma_free_chan_resources(dma_chan);
1105 out:
1106 src_idx = IOP_ADMA_NUM_SRC_TEST;
1107 while (src_idx--)
1108 __free_page(xor_srcs[src_idx]);
1109 __free_page(dest);
1110 return err;
1111 }
1112
1113 static int __devexit iop_adma_remove(struct platform_device *dev)
1114 {
1115 struct iop_adma_device *device = platform_get_drvdata(dev);
1116 struct dma_chan *chan, *_chan;
1117 struct iop_adma_chan *iop_chan;
1118 int i;
1119 struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1120
1121 dma_async_device_unregister(&device->common);
1122
1123 for (i = 0; i < 3; i++) {
1124 unsigned int irq;
1125 irq = platform_get_irq(dev, i);
1126 free_irq(irq, device);
1127 }
1128
1129 dma_free_coherent(&dev->dev, plat_data->pool_size,
1130 device->dma_desc_pool_virt, device->dma_desc_pool);
1131
1132 do {
1133 struct resource *res;
1134 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1135 release_mem_region(res->start, res->end - res->start);
1136 } while (0);
1137
1138 list_for_each_entry_safe(chan, _chan, &device->common.channels,
1139 device_node) {
1140 iop_chan = to_iop_adma_chan(chan);
1141 list_del(&chan->device_node);
1142 kfree(iop_chan);
1143 }
1144 kfree(device);
1145
1146 return 0;
1147 }
1148
1149 static int __devinit iop_adma_probe(struct platform_device *pdev)
1150 {
1151 struct resource *res;
1152 int ret = 0, i;
1153 struct iop_adma_device *adev;
1154 struct iop_adma_chan *iop_chan;
1155 struct dma_device *dma_dev;
1156 struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1157
1158 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1159 if (!res)
1160 return -ENODEV;
1161
1162 if (!devm_request_mem_region(&pdev->dev, res->start,
1163 res->end - res->start, pdev->name))
1164 return -EBUSY;
1165
1166 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1167 if (!adev)
1168 return -ENOMEM;
1169 dma_dev = &adev->common;
1170
1171 /* allocate coherent memory for hardware descriptors
1172 * note: writecombine gives slightly better performance, but
1173 * requires that we explicitly flush the writes
1174 */
1175 if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1176 plat_data->pool_size,
1177 &adev->dma_desc_pool,
1178 GFP_KERNEL)) == NULL) {
1179 ret = -ENOMEM;
1180 goto err_free_adev;
1181 }
1182
1183 dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1184 __func__, adev->dma_desc_pool_virt,
1185 (void *) adev->dma_desc_pool);
1186
1187 adev->id = plat_data->hw_id;
1188
1189 /* discover transaction capabilites from the platform data */
1190 dma_dev->cap_mask = plat_data->cap_mask;
1191
1192 adev->pdev = pdev;
1193 platform_set_drvdata(pdev, adev);
1194
1195 INIT_LIST_HEAD(&dma_dev->channels);
1196
1197 /* set base routines */
1198 dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1199 dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1200 dma_dev->device_is_tx_complete = iop_adma_is_complete;
1201 dma_dev->device_issue_pending = iop_adma_issue_pending;
1202 dma_dev->dev = &pdev->dev;
1203
1204 /* set prep routines based on capability */
1205 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1206 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1207 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1208 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1209 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1210 dma_dev->max_xor = iop_adma_get_max_xor();
1211 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1212 }
1213 if (dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask))
1214 dma_dev->device_prep_dma_zero_sum =
1215 iop_adma_prep_dma_zero_sum;
1216 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1217 dma_dev->device_prep_dma_interrupt =
1218 iop_adma_prep_dma_interrupt;
1219
1220 iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1221 if (!iop_chan) {
1222 ret = -ENOMEM;
1223 goto err_free_dma;
1224 }
1225 iop_chan->device = adev;
1226
1227 iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1228 res->end - res->start);
1229 if (!iop_chan->mmr_base) {
1230 ret = -ENOMEM;
1231 goto err_free_iop_chan;
1232 }
1233 tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1234 iop_chan);
1235
1236 /* clear errors before enabling interrupts */
1237 iop_adma_device_clear_err_status(iop_chan);
1238
1239 for (i = 0; i < 3; i++) {
1240 irq_handler_t handler[] = { iop_adma_eot_handler,
1241 iop_adma_eoc_handler,
1242 iop_adma_err_handler };
1243 int irq = platform_get_irq(pdev, i);
1244 if (irq < 0) {
1245 ret = -ENXIO;
1246 goto err_free_iop_chan;
1247 } else {
1248 ret = devm_request_irq(&pdev->dev, irq,
1249 handler[i], 0, pdev->name, iop_chan);
1250 if (ret)
1251 goto err_free_iop_chan;
1252 }
1253 }
1254
1255 spin_lock_init(&iop_chan->lock);
1256 INIT_LIST_HEAD(&iop_chan->chain);
1257 INIT_LIST_HEAD(&iop_chan->all_slots);
1258 INIT_RCU_HEAD(&iop_chan->common.rcu);
1259 iop_chan->common.device = dma_dev;
1260 list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1261
1262 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1263 ret = iop_adma_memcpy_self_test(adev);
1264 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1265 if (ret)
1266 goto err_free_iop_chan;
1267 }
1268
1269 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1270 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1271 ret = iop_adma_xor_zero_sum_self_test(adev);
1272 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1273 if (ret)
1274 goto err_free_iop_chan;
1275 }
1276
1277 dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1278 "( %s%s%s%s%s%s%s%s%s%s)\n",
1279 dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "",
1280 dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "",
1281 dma_has_cap(DMA_PQ_ZERO_SUM, dma_dev->cap_mask) ? "pq_zero_sum " : "",
1282 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1283 dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "",
1284 dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask) ? "xor_zero_sum " : "",
1285 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "",
1286 dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "",
1287 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1288 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1289
1290 dma_async_device_register(dma_dev);
1291 goto out;
1292
1293 err_free_iop_chan:
1294 kfree(iop_chan);
1295 err_free_dma:
1296 dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1297 adev->dma_desc_pool_virt, adev->dma_desc_pool);
1298 err_free_adev:
1299 kfree(adev);
1300 out:
1301 return ret;
1302 }
1303
1304 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1305 {
1306 struct iop_adma_desc_slot *sw_desc, *grp_start;
1307 dma_cookie_t cookie;
1308 int slot_cnt, slots_per_op;
1309
1310 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1311
1312 spin_lock_bh(&iop_chan->lock);
1313 slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1314 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1315 if (sw_desc) {
1316 grp_start = sw_desc->group_head;
1317
1318 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1319 async_tx_ack(&sw_desc->async_tx);
1320 iop_desc_init_memcpy(grp_start, 0);
1321 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1322 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1323 iop_desc_set_memcpy_src_addr(grp_start, 0);
1324
1325 cookie = iop_chan->common.cookie;
1326 cookie++;
1327 if (cookie <= 1)
1328 cookie = 2;
1329
1330 /* initialize the completed cookie to be less than
1331 * the most recently used cookie
1332 */
1333 iop_chan->completed_cookie = cookie - 1;
1334 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1335
1336 /* channel should not be busy */
1337 BUG_ON(iop_chan_is_busy(iop_chan));
1338
1339 /* clear any prior error-status bits */
1340 iop_adma_device_clear_err_status(iop_chan);
1341
1342 /* disable operation */
1343 iop_chan_disable(iop_chan);
1344
1345 /* set the descriptor address */
1346 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1347
1348 /* 1/ don't add pre-chained descriptors
1349 * 2/ dummy read to flush next_desc write
1350 */
1351 BUG_ON(iop_desc_get_next_desc(sw_desc));
1352
1353 /* run the descriptor */
1354 iop_chan_enable(iop_chan);
1355 } else
1356 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1357 "failed to allocate null descriptor\n");
1358 spin_unlock_bh(&iop_chan->lock);
1359 }
1360
1361 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1362 {
1363 struct iop_adma_desc_slot *sw_desc, *grp_start;
1364 dma_cookie_t cookie;
1365 int slot_cnt, slots_per_op;
1366
1367 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1368
1369 spin_lock_bh(&iop_chan->lock);
1370 slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1371 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1372 if (sw_desc) {
1373 grp_start = sw_desc->group_head;
1374 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1375 async_tx_ack(&sw_desc->async_tx);
1376 iop_desc_init_null_xor(grp_start, 2, 0);
1377 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1378 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1379 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1380 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1381
1382 cookie = iop_chan->common.cookie;
1383 cookie++;
1384 if (cookie <= 1)
1385 cookie = 2;
1386
1387 /* initialize the completed cookie to be less than
1388 * the most recently used cookie
1389 */
1390 iop_chan->completed_cookie = cookie - 1;
1391 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1392
1393 /* channel should not be busy */
1394 BUG_ON(iop_chan_is_busy(iop_chan));
1395
1396 /* clear any prior error-status bits */
1397 iop_adma_device_clear_err_status(iop_chan);
1398
1399 /* disable operation */
1400 iop_chan_disable(iop_chan);
1401
1402 /* set the descriptor address */
1403 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1404
1405 /* 1/ don't add pre-chained descriptors
1406 * 2/ dummy read to flush next_desc write
1407 */
1408 BUG_ON(iop_desc_get_next_desc(sw_desc));
1409
1410 /* run the descriptor */
1411 iop_chan_enable(iop_chan);
1412 } else
1413 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1414 "failed to allocate null descriptor\n");
1415 spin_unlock_bh(&iop_chan->lock);
1416 }
1417
1418 MODULE_ALIAS("platform:iop-adma");
1419
1420 static struct platform_driver iop_adma_driver = {
1421 .probe = iop_adma_probe,
1422 .remove = iop_adma_remove,
1423 .driver = {
1424 .owner = THIS_MODULE,
1425 .name = "iop-adma",
1426 },
1427 };
1428
1429 static int __init iop_adma_init (void)
1430 {
1431 return platform_driver_register(&iop_adma_driver);
1432 }
1433
1434 /* it's currently unsafe to unload this module */
1435 #if 0
1436 static void __exit iop_adma_exit (void)
1437 {
1438 platform_driver_unregister(&iop_adma_driver);
1439 return;
1440 }
1441 module_exit(iop_adma_exit);
1442 #endif
1443
1444 module_init(iop_adma_init);
1445
1446 MODULE_AUTHOR("Intel Corporation");
1447 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1448 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards