include/asm-ppc/pgtable.h

   1 #ifdef __KERNEL__
   2 #ifndef _PPC_PGTABLE_H
   3 #define _PPC_PGTABLE_H
   4
   5 #include <asm-generic/4level-fixup.h>
   6
   7
   8 #ifndef __ASSEMBLY__
   9 #include <linux/sched.h>
  10 #include <linux/threads.h>
  11 #include <asm/processor.h>              /* For TASK_SIZE */
  12 #include <asm/mmu.h>
  13 #include <asm/page.h>
  14 #include <asm/io.h>                     /* For sub-arch specific PPC_PIN_SIZE */
  15 struct mm_struct;
  16
  17 extern unsigned long va_to_phys(unsigned long address);
  18 extern pte_t *va_to_pte(unsigned long address);
  19 extern unsigned long ioremap_bot, ioremap_base;
  20 #endif /* __ASSEMBLY__ */
  21
  22 /*
  23  * The PowerPC MMU uses a hash table containing PTEs, together with
  24  * a set of 16 segment registers (on 32-bit implementations), to define
  25  * the virtual to physical address mapping.
  26  *
  27  * We use the hash table as an extended TLB, i.e. a cache of currently
  28  * active mappings.  We maintain a two-level page table tree, much
  29  * like that used by the i386, for the sake of the Linux memory
  30  * management code.  Low-level assembler code in hashtable.S
  31  * (procedure hash_page) is responsible for extracting ptes from the
  32  * tree and putting them into the hash table when necessary, and
  33  * updating the accessed and modified bits in the page table tree.
  34  */
  35
  36 /*
  37  * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
  38  * We also use the two level tables, but we can put the real bits in them
  39  * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
  40  * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
  41  * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
  42  * based upon user/super access.  The TLB does not have accessed nor write
  43  * protect.  We assume that if the TLB get loaded with an entry it is
  44  * accessed, and overload the changed bit for write protect.  We use
  45  * two bits in the software pte that are supposed to be set to zero in
  46  * the TLB entry (24 and 25) for these indicators.  Although the level 1
  47  * descriptor contains the guarded and writethrough/copyback bits, we can
  48  * set these at the page level since they get copied from the Mx_TWC
  49  * register when the TLB entry is loaded.  We will use bit 27 for guard, since
  50  * that is where it exists in the MD_TWC, and bit 26 for writethrough.
  51  * These will get masked from the level 2 descriptor at TLB load time, and
  52  * copied to the MD_TWC before it gets loaded.
  53  * Large page sizes added.  We currently support two sizes, 4K and 8M.
  54  * This also allows a TLB hander optimization because we can directly
  55  * load the PMD into MD_TWC.  The 8M pages are only used for kernel
  56  * mapping of well known areas.  The PMD (PGD) entries contain control
  57  * flags in addition to the address, so care must be taken that the
  58  * software no longer assumes these are only pointers.
  59  */
  60
  61 /*
  62  * At present, all PowerPC 400-class processors share a similar TLB
  63  * architecture. The instruction and data sides share a unified,
  64  * 64-entry, fully-associative TLB which is maintained totally under
  65  * software control. In addition, the instruction side has a
  66  * hardware-managed, 4-entry, fully-associative TLB which serves as a
  67  * first level to the shared TLB. These two TLBs are known as the UTLB
  68  * and ITLB, respectively (see "mmu.h" for definitions).
  69  */
  70
  71 /*
  72  * The normal case is that PTEs are 32-bits and we have a 1-page
  73  * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
  74  *
  75  * For any >32-bit physical address platform, we can use the following
  76  * two level page table layout where the pgdir is 8KB and the MS 13 bits
  77  * are an index to the second level table.  The combined pgdir/pmd first
  78  * level has 2048 entries and the second level has 512 64-bit PTE entries.
  79  * -Matt
  80  */
  81 /* PMD_SHIFT determines the size of the area mapped by the PTE pages */
  82 #define PMD_SHIFT       (PAGE_SHIFT + PTE_SHIFT)
  83 #define PMD_SIZE        (1UL << PMD_SHIFT)
  84 #define PMD_MASK        (~(PMD_SIZE-1))
  85
  86 /* PGDIR_SHIFT determines what a top-level page table entry can map */
  87 #define PGDIR_SHIFT     PMD_SHIFT
  88 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  89 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  90
  91 /*
  92  * entries per page directory level: our page-table tree is two-level, so
  93  * we don't really have any PMD directory.
  94  */
  95 #define PTRS_PER_PTE    (1 << PTE_SHIFT)
  96 #define PTRS_PER_PMD    1
  97 #define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
  98
  99 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
 100 #define FIRST_USER_ADDRESS      0
 101
 102 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
 103 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
 104
 105 #define pte_ERROR(e) \
 106         printk("%s:%d: bad pte "PTE_FMT".\n", __FILE__, __LINE__, pte_val(e))
 107 #define pmd_ERROR(e) \
 108         printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
 109 #define pgd_ERROR(e) \
 110         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 111
 112 /*
 113  * Just any arbitrary offset to the start of the vmalloc VM area: the
 114  * current 64MB value just means that there will be a 64MB "hole" after the
 115  * physical memory until the kernel virtual memory starts.  That means that
 116  * any out-of-bounds memory accesses will hopefully be caught.
 117  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 118  * area for the same reason. ;)
 119  *
 120  * We no longer map larger than phys RAM with the BATs so we don't have
 121  * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
 122  * about clashes between our early calls to ioremap() that start growing down
 123  * from ioremap_base being run into the VM area allocations (growing upwards
 124  * from VMALLOC_START).  For this reason we have ioremap_bot to check when
 125  * we actually run into our mappings setup in the early boot with the VM
 126  * system.  This really does become a problem for machines with good amounts
 127  * of RAM.  -- Cort
 128  */
 129 #define VMALLOC_OFFSET (0x1000000) /* 16M */
 130 #ifdef PPC_PIN_SIZE
 131 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 132 #else
 133 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 134 #endif
 135 #define VMALLOC_END     ioremap_bot
 136
 137 /*
 138  * Bits in a linux-style PTE.  These match the bits in the
 139  * (hardware-defined) PowerPC PTE as closely as possible.
 140  */
 141
 142 #if defined(CONFIG_40x)
 143
 144 /* There are several potential gotchas here.  The 40x hardware TLBLO
 145    field looks like this:
 146
 147    0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 148    RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
 149
 150    Where possible we make the Linux PTE bits match up with this
 151
 152    - bits 20 and 21 must be cleared, because we use 4k pages (40x can
 153      support down to 1k pages), this is done in the TLBMiss exception
 154      handler.
 155    - We use only zones 0 (for kernel pages) and 1 (for user pages)
 156      of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
 157      miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
 158      zone.
 159    - PRESENT *must* be in the bottom two bits because swap cache
 160      entries use the top 30 bits.  Because 40x doesn't support SMP
 161      anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
 162      is cleared in the TLB miss handler before the TLB entry is loaded.
 163    - All other bits of the PTE are loaded into TLBLO without
 164      modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
 165      software PTE bits.  We actually use use bits 21, 24, 25, and
 166      30 respectively for the software bits: ACCESSED, DIRTY, RW, and
 167      PRESENT.
 168 */
 169
 170 /* Definitions for 40x embedded chips. */
 171 #define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
 172 #define _PAGE_FILE      0x001   /* when !present: nonlinear file mapping */
 173 #define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
 174 #define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
 175 #define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
 176 #define _PAGE_USER      0x010   /* matches one of the zone permission bits */
 177 #define _PAGE_RW        0x040   /* software: Writes permitted */
 178 #define _PAGE_DIRTY     0x080   /* software: dirty page */
 179 #define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
 180 #define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
 181 #define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
 182
 183 #define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
 184 #define _PMD_BAD        0x802
 185 #define _PMD_SIZE       0x0e0   /* size field, != 0 for large-page PMD entry */
 186 #define _PMD_SIZE_4M    0x0c0
 187 #define _PMD_SIZE_16M   0x0e0
 188 #define PMD_PAGE_SIZE(pmdval)   (1024 << (((pmdval) & _PMD_SIZE) >> 4))
 189
 190 #elif defined(CONFIG_44x)
 191 /*
 192  * Definitions for PPC440
 193  *
 194  * Because of the 3 word TLB entries to support 36-bit addressing,
 195  * the attribute are difficult to map in such a fashion that they
 196  * are easily loaded during exception processing.  I decided to
 197  * organize the entry so the ERPN is the only portion in the
 198  * upper word of the PTE and the attribute bits below are packed
 199  * in as sensibly as they can be in the area below a 4KB page size
 200  * oriented RPN.  This at least makes it easy to load the RPN and
 201  * ERPN fields in the TLB. -Matt
 202  *
 203  * Note that these bits preclude future use of a page size
 204  * less than 4KB.
 205  *
 206  *
 207  * PPC 440 core has following TLB attribute fields;
 208  *
 209  *   TLB1:
 210  *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 211  *   RPN.................................  -  -  -  -  -  - ERPN.......
 212  *
 213  *   TLB2:
 214  *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 215  *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
 216  *
 217  * There are some constrains and options, to decide mapping software bits
 218  * into TLB entry.
 219  *
 220  *   - PRESENT *must* be in the bottom three bits because swap cache
 221  *     entries use the top 29 bits for TLB2.
 222  *
 223  *   - FILE *must* be in the bottom three bits because swap cache
 224  *     entries use the top 29 bits for TLB2.
 225  *
 226  *   - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
 227  *     doesn't support SMP. So we can use this as software bit, like
 228  *     DIRTY.
 229  *
 230  * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
 231  * for memory protection related functions (see PTE structure in
 232  * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
 233  * above bits.  Note that the bit values are CPU specific, not architecture
 234  * specific.
 235  *
 236  * The kernel PTE entry holds an arch-dependent swp_entry structure under
 237  * certain situations. In other words, in such situations some portion of
 238  * the PTE bits are used as a swp_entry. In the PPC implementation, the
 239  * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
 240  * hold protection values. That means the three protection bits are
 241  * reserved for both PTE and SWAP entry at the most significant three
 242  * LSBs.
 243  *
 244  * There are three protection bits available for SWAP entry:
 245  *      _PAGE_PRESENT
 246  *      _PAGE_FILE
 247  *      _PAGE_HASHPTE (if HW has)
 248  *
 249  * So those three bits have to be inside of 0-2nd LSB of PTE.
 250  *
 251  */
 252
 253 #define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
 254 #define _PAGE_RW        0x00000002              /* S: Write permission */
 255 #define _PAGE_FILE      0x00000004              /* S: nonlinear file mapping */
 256 #define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
 257 #define _PAGE_HWWRITE   0x00000010              /* H: Dirty & RW */
 258 #define _PAGE_HWEXEC    0x00000020              /* H: Execute permission */
 259 #define _PAGE_USER      0x00000040              /* S: User page */
 260 #define _PAGE_ENDIAN    0x00000080              /* H: E bit */
 261 #define _PAGE_GUARDED   0x00000100              /* H: G bit */
 262 #define _PAGE_DIRTY     0x00000200              /* S: Page dirty */
 263 #define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
 264 #define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
 265
 266 /* TODO: Add large page lowmem mapping support */
 267 #define _PMD_PRESENT    0
 268 #define _PMD_PRESENT_MASK (PAGE_MASK)
 269 #define _PMD_BAD        (~PAGE_MASK)
 270
 271 /* ERPN in a PTE never gets cleared, ignore it */
 272 #define _PTE_NONE_MASK  0xffffffff00000000ULL
 273
 274 #elif defined(CONFIG_8xx)
 275 /* Definitions for 8xx embedded chips. */
 276 #define _PAGE_PRESENT   0x0001  /* Page is valid */
 277 #define _PAGE_FILE      0x0002  /* when !present: nonlinear file mapping */
 278 #define _PAGE_NO_CACHE  0x0002  /* I: cache inhibit */
 279 #define _PAGE_SHARED    0x0004  /* No ASID (context) compare */
 280
 281 /* These five software bits must be masked out when the entry is loaded
 282  * into the TLB.
 283  */
 284 #define _PAGE_EXEC      0x0008  /* software: i-cache coherency required */
 285 #define _PAGE_GUARDED   0x0010  /* software: guarded access */
 286 #define _PAGE_DIRTY     0x0020  /* software: page changed */
 287 #define _PAGE_RW        0x0040  /* software: user write access allowed */
 288 #define _PAGE_ACCESSED  0x0080  /* software: page referenced */
 289
 290 /* Setting any bits in the nibble with the follow two controls will
 291  * require a TLB exception handler change.  It is assumed unused bits
 292  * are always zero.
 293  */
 294 #define _PAGE_HWWRITE   0x0100  /* h/w write enable: never set in Linux PTE */
 295 #define _PAGE_USER      0x0800  /* One of the PP bits, the other is USER&~RW */
 296
 297 #define _PMD_PRESENT    0x0001
 298 #define _PMD_BAD        0x0ff0
 299 #define _PMD_PAGE_MASK  0x000c
 300 #define _PMD_PAGE_8M    0x000c
 301
 302 #define _PTE_NONE_MASK _PAGE_ACCESSED
 303
 304 #else /* CONFIG_6xx */
 305 /* Definitions for 60x, 740/750, etc. */
 306 #define _PAGE_PRESENT   0x001   /* software: pte contains a translation */
 307 #define _PAGE_HASHPTE   0x002   /* hash_page has made an HPTE for this pte */
 308 #define _PAGE_FILE      0x004   /* when !present: nonlinear file mapping */
 309 #define _PAGE_USER      0x004   /* usermode access allowed */
 310 #define _PAGE_GUARDED   0x008   /* G: prohibit speculative access */
 311 #define _PAGE_COHERENT  0x010   /* M: enforce memory coherence (SMP systems) */
 312 #define _PAGE_NO_CACHE  0x020   /* I: cache inhibit */
 313 #define _PAGE_WRITETHRU 0x040   /* W: cache write-through */
 314 #define _PAGE_DIRTY     0x080   /* C: page changed */
 315 #define _PAGE_ACCESSED  0x100   /* R: page referenced */
 316 #define _PAGE_EXEC      0x200   /* software: i-cache coherency required */
 317 #define _PAGE_RW        0x400   /* software: user write access allowed */
 318
 319 #define _PTE_NONE_MASK  _PAGE_HASHPTE
 320
 321 #define _PMD_PRESENT    0
 322 #define _PMD_PRESENT_MASK (PAGE_MASK)
 323 #define _PMD_BAD        (~PAGE_MASK)
 324 #endif
 325
 326 /*
 327  * Some bits are only used on some cpu families...
 328  */
 329 #ifndef _PAGE_HASHPTE
 330 #define _PAGE_HASHPTE   0
 331 #endif
 332 #ifndef _PTE_NONE_MASK
 333 #define _PTE_NONE_MASK 0
 334 #endif
 335 #ifndef _PAGE_SHARED
 336 #define _PAGE_SHARED    0
 337 #endif
 338 #ifndef _PAGE_HWWRITE
 339 #define _PAGE_HWWRITE   0
 340 #endif
 341 #ifndef _PAGE_HWEXEC
 342 #define _PAGE_HWEXEC    0
 343 #endif
 344 #ifndef _PAGE_EXEC
 345 #define _PAGE_EXEC      0
 346 #endif
 347 #ifndef _PMD_PRESENT_MASK
 348 #define _PMD_PRESENT_MASK       _PMD_PRESENT
 349 #endif
 350 #ifndef _PMD_SIZE
 351 #define _PMD_SIZE       0
 352 #define PMD_PAGE_SIZE(pmd)      bad_call_to_PMD_PAGE_SIZE()
 353 #endif
 354
 355 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 356
 357 /*
 358  * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
 359  * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
 360  * to have it in the Linux PTE, and in fact the bit could be reused for
 361  * another purpose.  -- paulus.
 362  */
 363
 364 #ifdef CONFIG_44x
 365 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
 366 #else
 367 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED)
 368 #endif
 369 #define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
 370 #define _PAGE_KERNEL    (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
 371
 372 #ifdef CONFIG_PPC_STD_MMU
 373 /* On standard PPC MMU, no user access implies kernel read/write access,
 374  * so to write-protect kernel memory we must turn on user access */
 375 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
 376 #else
 377 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
 378 #endif
 379
 380 #define _PAGE_IO        (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
 381 #define _PAGE_RAM       (_PAGE_KERNEL | _PAGE_HWEXEC)
 382
 383 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
 384 /* We want the debuggers to be able to set breakpoints anywhere, so
 385  * don't write protect the kernel text */
 386 #define _PAGE_RAM_TEXT  _PAGE_RAM
 387 #else
 388 #define _PAGE_RAM_TEXT  (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
 389 #endif
 390
 391 #define PAGE_NONE       __pgprot(_PAGE_BASE)
 392 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
 393 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 394 #define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
 395 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
 396 #define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
 397 #define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 398
 399 #define PAGE_KERNEL             __pgprot(_PAGE_RAM)
 400 #define PAGE_KERNEL_NOCACHE     __pgprot(_PAGE_IO)
 401
 402 /*
 403  * The PowerPC can only do execute protection on a segment (256MB) basis,
 404  * not on a page basis.  So we consider execute permission the same as read.
 405  * Also, write permissions imply read permissions.
 406  * This is the closest we can get..
 407  */
 408 #define __P000  PAGE_NONE
 409 #define __P001  PAGE_READONLY_X
 410 #define __P010  PAGE_COPY
 411 #define __P011  PAGE_COPY_X
 412 #define __P100  PAGE_READONLY
 413 #define __P101  PAGE_READONLY_X
 414 #define __P110  PAGE_COPY
 415 #define __P111  PAGE_COPY_X
 416
 417 #define __S000  PAGE_NONE
 418 #define __S001  PAGE_READONLY_X
 419 #define __S010  PAGE_SHARED
 420 #define __S011  PAGE_SHARED_X
 421 #define __S100  PAGE_READONLY
 422 #define __S101  PAGE_READONLY_X
 423 #define __S110  PAGE_SHARED
 424 #define __S111  PAGE_SHARED_X
 425
 426 #ifndef __ASSEMBLY__
 427 /* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
 428  * kernel without large page PMD support */
 429 extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
 430
 431 /*
 432  * Conversions between PTE values and page frame numbers.
 433  */
 434
 435 /* in some case we want to additionaly adjust where the pfn is in the pte to
 436  * allow room for more flags */
 437 #define PFN_SHIFT_OFFSET        (PAGE_SHIFT)
 438
 439 #define pte_pfn(x)              (pte_val(x) >> PFN_SHIFT_OFFSET)
 440 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 441
 442 #define pfn_pte(pfn, prot)      __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
 443                                         pgprot_val(prot))
 444 #define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
 445
 446 /*
 447  * ZERO_PAGE is a global shared page that is always zero: used
 448  * for zero-mapped memory areas etc..
 449  */
 450 extern unsigned long empty_zero_page[1024];
 451 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 452
 453 #endif /* __ASSEMBLY__ */
 454
 455 #define pte_none(pte)           ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
 456 #define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
 457 #define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
 458
 459 #define pmd_none(pmd)           (!pmd_val(pmd))
 460 #define pmd_bad(pmd)            (pmd_val(pmd) & _PMD_BAD)
 461 #define pmd_present(pmd)        (pmd_val(pmd) & _PMD_PRESENT_MASK)
 462 #define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
 463
 464 #ifndef __ASSEMBLY__
 465 /*
 466  * The "pgd_xxx()" functions here are trivial for a folded two-level
 467  * setup: the pgd is never bad, and a pmd always exists (as it's folded
 468  * into the pgd entry)
 469  */
 470 static inline int pgd_none(pgd_t pgd)           { return 0; }
 471 static inline int pgd_bad(pgd_t pgd)            { return 0; }
 472 static inline int pgd_present(pgd_t pgd)        { return 1; }
 473 #define pgd_clear(xp)                           do { } while (0)
 474
 475 #define pgd_page_vaddr(pgd) \
 476         ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
 477
 478 /*
 479  * The following only work if pte_present() is true.
 480  * Undefined behaviour if not..
 481  */
 482 static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
 483 static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
 484 static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 485 static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
 486
 487 static inline void pte_uncache(pte_t pte)       { pte_val(pte) |= _PAGE_NO_CACHE; }
 488 static inline void pte_cache(pte_t pte)         { pte_val(pte) &= ~_PAGE_NO_CACHE; }
 489
 490 static inline pte_t pte_wrprotect(pte_t pte) {
 491         pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
 492 static inline pte_t pte_mkclean(pte_t pte) {
 493         pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
 494 static inline pte_t pte_mkold(pte_t pte) {
 495         pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 496
 497 static inline pte_t pte_mkwrite(pte_t pte) {
 498         pte_val(pte) |= _PAGE_RW; return pte; }
 499 static inline pte_t pte_mkdirty(pte_t pte) {
 500         pte_val(pte) |= _PAGE_DIRTY; return pte; }
 501 static inline pte_t pte_mkyoung(pte_t pte) {
 502         pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 503
 504 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 505 {
 506         pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
 507         return pte;
 508 }
 509
 510 /*
 511  * When flushing the tlb entry for a page, we also need to flush the hash
 512  * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
 513  */
 514 extern int flush_hash_pages(unsigned context, unsigned long va,
 515                             unsigned long pmdval, int count);
 516
 517 /* Add an HPTE to the hash table */
 518 extern void add_hash_page(unsigned context, unsigned long va,
 519                           unsigned long pmdval);
 520
 521 /*
 522  * Atomic PTE updates.
 523  *
 524  * pte_update clears and sets bit atomically, and returns
 525  * the old pte value.  In the 64-bit PTE case we lock around the
 526  * low PTE word since we expect ALL flag bits to be there
 527  */
 528 #ifndef CONFIG_PTE_64BIT
 529 static inline unsigned long pte_update(pte_t *p, unsigned long clr,
 530                                        unsigned long set)
 531 {
 532         unsigned long old, tmp;
 533
 534         __asm__ __volatile__("\
 535 1:      lwarx   %0,0,%3\n\
 536         andc    %1,%0,%4\n\
 537         or      %1,%1,%5\n"
 538         PPC405_ERR77(0,%3)
 539 "       stwcx.  %1,0,%3\n\
 540         bne-    1b"
 541         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 542         : "r" (p), "r" (clr), "r" (set), "m" (*p)
 543         : "cc" );
 544         return old;
 545 }
 546 #else
 547 static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
 548                                        unsigned long set)
 549 {
 550         unsigned long long old;
 551         unsigned long tmp;
 552
 553         __asm__ __volatile__("\
 554 1:      lwarx   %L0,0,%4\n\
 555         lwzx    %0,0,%3\n\
 556         andc    %1,%L0,%5\n\
 557         or      %1,%1,%6\n"
 558         PPC405_ERR77(0,%3)
 559 "       stwcx.  %1,0,%4\n\
 560         bne-    1b"
 561         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 562         : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
 563         : "cc" );
 564         return old;
 565 }
 566 #endif
 567
 568 /*
 569  * set_pte stores a linux PTE into the linux page table.
 570  * On machines which use an MMU hash table we avoid changing the
 571  * _PAGE_HASHPTE bit.
 572  */
 573 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 574                               pte_t *ptep, pte_t pte)
 575 {
 576 #if _PAGE_HASHPTE != 0
 577         pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
 578 #else
 579         *ptep = pte;
 580 #endif
 581 }
 582
 583 /*
 584  * 2.6 calles this without flushing the TLB entry, this is wrong
 585  * for our hash-based implementation, we fix that up here
 586  */
 587 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 588 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
 589 {
 590         unsigned long old;
 591         old = pte_update(ptep, _PAGE_ACCESSED, 0);
 592 #if _PAGE_HASHPTE != 0
 593         if (old & _PAGE_HASHPTE) {
 594                 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
 595                 flush_hash_pages(context, addr, ptephys, 1);
 596         }
 597 #endif
 598         return (old & _PAGE_ACCESSED) != 0;
 599 }
 600 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
 601         __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
 602
 603 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 604 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
 605                                        pte_t *ptep)
 606 {
 607         return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
 608 }
 609
 610 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 611 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 612                                       pte_t *ptep)
 613 {
 614         pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
 615 }
 616
 617 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 618 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 619 {
 620         unsigned long bits = pte_val(entry) &
 621                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
 622         pte_update(ptep, 0, bits);
 623 }
 624
 625 #define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
 626 ({                                                                         \
 627         int __changed = !pte_same(*(__ptep), __entry);                     \
 628         if (__changed) {                                                   \
 629                 __ptep_set_access_flags(__ptep, __entry, __dirty);         \
 630                 flush_tlb_page_nohash(__vma, __address);                   \
 631         }                                                                  \
 632         __changed;                                                         \
 633 })
 634
 635 /*
 636  * Macro to mark a page protection value as "uncacheable".
 637  */
 638 #define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
 639
 640 struct file;
 641 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 642                                      unsigned long size, pgprot_t vma_prot);
 643 #define __HAVE_PHYS_MEM_ACCESS_PROT
 644
 645 #define __HAVE_ARCH_PTE_SAME
 646 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
 647
 648 /*
 649  * Note that on Book E processors, the pmd contains the kernel virtual
 650  * (lowmem) address of the pte page.  The physical address is less useful
 651  * because everything runs with translation enabled (even the TLB miss
 652  * handler).  On everything else the pmd contains the physical address
 653  * of the pte page.  -- paulus
 654  */
 655 #ifndef CONFIG_BOOKE
 656 #define pmd_page_vaddr(pmd)     \
 657         ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 658 #define pmd_page(pmd)           \
 659         (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
 660 #else
 661 #define pmd_page_vaddr(pmd)     \
 662         ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
 663 #define pmd_page(pmd)           \
 664         (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
 665 #endif
 666
 667 /* to find an entry in a kernel page-table-directory */
 668 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 669
 670 /* to find an entry in a page-table-directory */
 671 #define pgd_index(address)       ((address) >> PGDIR_SHIFT)
 672 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 673
 674 /* Find an entry in the second-level page table.. */
 675 static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
 676 {
 677         return (pmd_t *) dir;
 678 }
 679
 680 /* Find an entry in the third-level page table.. */
 681 #define pte_index(address)              \
 682         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 683 #define pte_offset_kernel(dir, addr)    \
 684         ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
 685 #define pte_offset_map(dir, addr)               \
 686         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
 687 #define pte_offset_map_nested(dir, addr)        \
 688         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
 689
 690 #define pte_unmap(pte)          kunmap_atomic(pte, KM_PTE0)
 691 #define pte_unmap_nested(pte)   kunmap_atomic(pte, KM_PTE1)
 692
 693 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 694
 695 extern void paging_init(void);
 696
 697 /*
 698  * Encode and decode a swap entry.
 699  * Note that the bits we use in a PTE for representing a swap entry
 700  * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
 701  *_PAGE_HASHPTE bit (if used).  -- paulus
 702  */
 703 #define __swp_type(entry)               ((entry).val & 0x1f)
 704 #define __swp_offset(entry)             ((entry).val >> 5)
 705 #define __swp_entry(type, offset)       ((swp_entry_t) { (type) | ((offset) << 5) })
 706 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 3 })
 707 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 3 })
 708
 709 /* Encode and decode a nonlinear file mapping entry */
 710 #define PTE_FILE_MAX_BITS       29
 711 #define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
 712 #define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
 713
 714 /* Values for nocacheflag and cmode */
 715 /* These are not used by the APUS kernel_map, but prevents
 716    compilation errors. */
 717 #define KERNELMAP_FULL_CACHING          0
 718 #define KERNELMAP_NOCACHE_SER           1
 719 #define KERNELMAP_NOCACHE_NONSER        2
 720 #define KERNELMAP_NO_COPYBACK           3
 721
 722 /*
 723  * Map some physical address range into the kernel address space.
 724  */
 725 extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
 726                                 int nocacheflag, unsigned long *memavailp );
 727
 728 /*
 729  * Set cache mode of (kernel space) address range.
 730  */
 731 extern void kernel_set_cachemode (unsigned long address, unsigned long size,
 732                                  unsigned int cmode);
 733
 734 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 735 #define kern_addr_valid(addr)   (1)
 736
 737 #ifdef CONFIG_PHYS_64BIT
 738 extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
 739                         unsigned long paddr, unsigned long size, pgprot_t prot);
 740
 741 static inline int io_remap_pfn_range(struct vm_area_struct *vma,
 742                                         unsigned long vaddr,
 743                                         unsigned long pfn,
 744                                         unsigned long size,
 745                                         pgprot_t prot)
 746 {
 747         phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
 748         return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
 749 }
 750 #else
 751 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
 752                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 753 #endif
 754
 755 /*
 756  * No page table caches to initialise
 757  */
 758 #define pgtable_cache_init()    do { } while (0)
 759
 760 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
 761                       pmd_t **pmdp);
 762
 763 #include <asm-generic/pgtable.h>
 764
 765 #endif /* !__ASSEMBLY__ */
 766
 767 #endif /* _PPC_PGTABLE_H */
 768 #endif /* __KERNEL__ */