arch/blackfin/include/asm/bfin5xx_spi.h

   1 /*
   2  * Blackfin On-Chip SPI Driver
   3  *
   4  * Copyright 2004-2008 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #ifndef _SPI_CHANNEL_H_
  12 #define _SPI_CHANNEL_H_
  13
  14 #define SPI_READ              0
  15 #define SPI_WRITE             1
  16
  17 #define SPI_CTRL_OFF            0x0
  18 #define SPI_FLAG_OFF            0x4
  19 #define SPI_STAT_OFF            0x8
  20 #define SPI_TXBUFF_OFF          0xc
  21 #define SPI_RXBUFF_OFF          0x10
  22 #define SPI_BAUD_OFF            0x14
  23 #define SPI_SHAW_OFF            0x18
  24
  25
  26 #define BIT_CTL_ENABLE      0x4000
  27 #define BIT_CTL_OPENDRAIN   0x2000
  28 #define BIT_CTL_MASTER      0x1000
  29 #define BIT_CTL_POLAR       0x0800
  30 #define BIT_CTL_PHASE       0x0400
  31 #define BIT_CTL_BITORDER    0x0200
  32 #define BIT_CTL_WORDSIZE    0x0100
  33 #define BIT_CTL_MISOENABLE  0x0020
  34 #define BIT_CTL_RXMOD       0x0000
  35 #define BIT_CTL_TXMOD       0x0001
  36 #define BIT_CTL_TIMOD_DMA_TX 0x0003
  37 #define BIT_CTL_TIMOD_DMA_RX 0x0002
  38 #define BIT_CTL_SENDOPT     0x0004
  39 #define BIT_CTL_TIMOD       0x0003
  40
  41 #define BIT_STAT_SPIF       0x0001
  42 #define BIT_STAT_MODF       0x0002
  43 #define BIT_STAT_TXE        0x0004
  44 #define BIT_STAT_TXS        0x0008
  45 #define BIT_STAT_RBSY       0x0010
  46 #define BIT_STAT_RXS        0x0020
  47 #define BIT_STAT_TXCOL      0x0040
  48 #define BIT_STAT_CLR        0xFFFF
  49
  50 #define BIT_STU_SENDOVER    0x0001
  51 #define BIT_STU_RECVFULL    0x0020
  52
  53 #define CFG_SPI_ENABLE      1
  54 #define CFG_SPI_DISABLE     0
  55
  56 #define CFG_SPI_OUTENABLE   1
  57 #define CFG_SPI_OUTDISABLE  0
  58
  59 #define CFG_SPI_ACTLOW      1
  60 #define CFG_SPI_ACTHIGH     0
  61
  62 #define CFG_SPI_PHASESTART  1
  63 #define CFG_SPI_PHASEMID    0
  64
  65 #define CFG_SPI_MASTER      1
  66 #define CFG_SPI_SLAVE       0
  67
  68 #define CFG_SPI_SENELAST    0
  69 #define CFG_SPI_SENDZERO    1
  70
  71 #define CFG_SPI_RCVFLUSH    1
  72 #define CFG_SPI_RCVDISCARD  0
  73
  74 #define CFG_SPI_LSBFIRST    1
  75 #define CFG_SPI_MSBFIRST    0
  76
  77 #define CFG_SPI_WORDSIZE16  1
  78 #define CFG_SPI_WORDSIZE8   0
  79
  80 #define CFG_SPI_MISOENABLE   1
  81 #define CFG_SPI_MISODISABLE  0
  82
  83 #define CFG_SPI_READ      0x00
  84 #define CFG_SPI_WRITE     0x01
  85 #define CFG_SPI_DMAREAD   0x02
  86 #define CFG_SPI_DMAWRITE  0x03
  87
  88 #define CFG_SPI_CSCLEARALL  0
  89 #define CFG_SPI_CHIPSEL1    1
  90 #define CFG_SPI_CHIPSEL2    2
  91 #define CFG_SPI_CHIPSEL3    3
  92 #define CFG_SPI_CHIPSEL4    4
  93 #define CFG_SPI_CHIPSEL5    5
  94 #define CFG_SPI_CHIPSEL6    6
  95 #define CFG_SPI_CHIPSEL7    7
  96
  97 #define CFG_SPI_CS1VALUE    1
  98 #define CFG_SPI_CS2VALUE    2
  99 #define CFG_SPI_CS3VALUE    3
 100 #define CFG_SPI_CS4VALUE    4
 101 #define CFG_SPI_CS5VALUE    5
 102 #define CFG_SPI_CS6VALUE    6
 103 #define CFG_SPI_CS7VALUE    7
 104
 105 #define CMD_SPI_SET_BAUDRATE  2
 106 #define CMD_SPI_GET_SYSTEMCLOCK   25
 107 #define CMD_SPI_SET_WRITECONTINUOUS     26
 108
 109 /* device.platform_data for SSP controller devices */
 110 struct bfin5xx_spi_master {
 111         u16 num_chipselect;
 112         u8 enable_dma;
 113         u16 pin_req[4];
 114 };
 115
 116 /* spi_board_info.controller_data for SPI slave devices,
 117  * copied to spi_device.platform_data ... mostly for dma tuning
 118  */
 119 struct bfin5xx_spi_chip {
 120         u16 ctl_reg;
 121         u8 enable_dma;
 122         u8 bits_per_word;
 123         u8 cs_change_per_word;
 124         u16 cs_chg_udelay; /* Some devices require 16-bit delays */
 125 };
 126
 127 #endif /* _SPI_CHANNEL_H_ */