include/linux/fsl_devices.h

   1 /*
   2  * include/linux/fsl_devices.h
   3  *
   4  * Definitions for any platform device related flags or structures for
   5  * Freescale processor devices
   6  *
   7  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
   8  *
   9  * Copyright 2004 Freescale Semiconductor, Inc
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16
  17 #ifndef _FSL_DEVICE_H_
  18 #define _FSL_DEVICE_H_
  19
  20 #include <linux/types.h>
  21 #include <linux/phy.h>
  22
  23 /*
  24  * Some conventions on how we handle peripherals on Freescale chips
  25  *
  26  * unique device: a platform_device entry in fsl_plat_devs[] plus
  27  * associated device information in its platform_data structure.
  28  *
  29  * A chip is described by a set of unique devices.
  30  *
  31  * Each sub-arch has its own master list of unique devices and
  32  * enumerates them by enum fsl_devices in a sub-arch specific header
  33  *
  34  * The platform data structure is broken into two parts.  The
  35  * first is device specific information that help identify any
  36  * unique features of a peripheral.  The second is any
  37  * information that may be defined by the board or how the device
  38  * is connected externally of the chip.
  39  *
  40  * naming conventions:
  41  * - platform data structures: <driver>_platform_data
  42  * - platform data device flags: FSL_<driver>_DEV_<FLAG>
  43  * - platform data board flags: FSL_<driver>_BRD_<FLAG>
  44  *
  45  */
  46
  47 struct gianfar_platform_data {
  48         /* device specific information */
  49         u32     device_flags;
  50         /* board specific information */
  51         u32     board_flags;
  52         char    bus_id[MII_BUS_ID_SIZE];
  53         u32     phy_id;
  54         u8      mac_addr[6];
  55         phy_interface_t interface;
  56 };
  57
  58 struct gianfar_mdio_data {
  59         /* board specific information */
  60         int     irq[32];
  61 };
  62
  63 /* Flags related to gianfar device features */
  64 #define FSL_GIANFAR_DEV_HAS_GIGABIT             0x00000001
  65 #define FSL_GIANFAR_DEV_HAS_COALESCE            0x00000002
  66 #define FSL_GIANFAR_DEV_HAS_RMON                0x00000004
  67 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR          0x00000008
  68 #define FSL_GIANFAR_DEV_HAS_CSUM                0x00000010
  69 #define FSL_GIANFAR_DEV_HAS_VLAN                0x00000020
  70 #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH       0x00000040
  71 #define FSL_GIANFAR_DEV_HAS_PADDING             0x00000080
  72 #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET        0x00000100
  73
  74 /* Flags in gianfar_platform_data */
  75 #define FSL_GIANFAR_BRD_HAS_PHY_INTR    0x00000001 /* set or use a timer */
  76 #define FSL_GIANFAR_BRD_IS_REDUCED      0x00000002 /* Set if RGMII, RMII */
  77
  78 struct fsl_i2c_platform_data {
  79         /* device specific information */
  80         u32     device_flags;
  81 };
  82
  83 /* Flags related to I2C device features */
  84 #define FSL_I2C_DEV_SEPARATE_DFSRR      0x00000001
  85 #define FSL_I2C_DEV_CLOCK_5200          0x00000002
  86
  87 enum fsl_usb2_operating_modes {
  88         FSL_USB2_MPH_HOST,
  89         FSL_USB2_DR_HOST,
  90         FSL_USB2_DR_DEVICE,
  91         FSL_USB2_DR_OTG,
  92 };
  93
  94 enum fsl_usb2_phy_modes {
  95         FSL_USB2_PHY_NONE,
  96         FSL_USB2_PHY_ULPI,
  97         FSL_USB2_PHY_UTMI,
  98         FSL_USB2_PHY_UTMI_WIDE,
  99         FSL_USB2_PHY_SERIAL,
 100 };
 101
 102 struct fsl_usb2_platform_data {
 103         /* board specific information */
 104         enum fsl_usb2_operating_modes   operating_mode;
 105         enum fsl_usb2_phy_modes         phy_mode;
 106         unsigned int                    port_enables;
 107 };
 108
 109 /* Flags in fsl_usb2_mph_platform_data */
 110 #define FSL_USB2_PORT0_ENABLED  0x00000001
 111 #define FSL_USB2_PORT1_ENABLED  0x00000002
 112
 113 struct fsl_spi_platform_data {
 114         u32     initial_spmode; /* initial SPMODE value */
 115         u16     bus_num;
 116         bool    qe_mode;
 117         /* board specific information */
 118         u16     max_chipselect;
 119         void    (*activate_cs)(u8 cs, u8 polarity);
 120         void    (*deactivate_cs)(u8 cs, u8 polarity);
 121         u32     sysclk;
 122 };
 123
 124 struct mpc8xx_pcmcia_ops {
 125         void(*hw_ctrl)(int slot, int enable);
 126         int(*voltage_set)(int slot, int vcc, int vpp);
 127 };
 128
 129 /* Returns non-zero if the current suspend operation would
 130  * lead to a deep sleep (i.e. power removed from the core,
 131  * instead of just the clock).
 132  */
 133 int fsl_deep_sleep(void);
 134
 135 #endif /* _FSL_DEVICE_H_ */