1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Copper)
32 * 82571EB Gigabit Ethernet Controller (Fiber)
33 * 82571EB Dual Port Gigabit Mezzanine Adapter
34 * 82571EB Quad Port Gigabit Mezzanine Adapter
35 * 82571PT Gigabit PT Quad Port Server ExpressModule
36 * 82572EI Gigabit Ethernet Controller (Copper)
37 * 82572EI Gigabit Ethernet Controller (Fiber)
38 * 82572EI Gigabit Ethernet Controller
39 * 82573V Gigabit Ethernet Controller (Copper)
40 * 82573E Gigabit Ethernet Controller (Copper)
41 * 82573L Gigabit Ethernet Controller
42 * 82574L Gigabit Network Connection
45 #include <linux/netdevice.h>
46 #include <linux/delay.h>
47 #include <linux/pci.h>
51 #define ID_LED_RESERVED_F746 0xF746
52 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
53 (ID_LED_OFF1_ON2 << 8) | \
54 (ID_LED_DEF1_DEF2 << 4) | \
57 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
59 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
61 static s32
e1000_get_phy_id_82571(struct e1000_hw
*hw
);
62 static s32
e1000_setup_copper_link_82571(struct e1000_hw
*hw
);
63 static s32
e1000_setup_fiber_serdes_link_82571(struct e1000_hw
*hw
);
64 static s32
e1000_write_nvm_eewr_82571(struct e1000_hw
*hw
, u16 offset
,
65 u16 words
, u16
*data
);
66 static s32
e1000_fix_nvm_checksum_82571(struct e1000_hw
*hw
);
67 static void e1000_initialize_hw_bits_82571(struct e1000_hw
*hw
);
68 static s32
e1000_setup_link_82571(struct e1000_hw
*hw
);
69 static void e1000_clear_hw_cntrs_82571(struct e1000_hw
*hw
);
70 static bool e1000_check_mng_mode_82574(struct e1000_hw
*hw
);
71 static s32
e1000_led_on_82574(struct e1000_hw
*hw
);
74 * e1000_init_phy_params_82571 - Init PHY func ptrs.
75 * @hw: pointer to the HW structure
77 * This is a function pointer entry point called by the api module.
79 static s32
e1000_init_phy_params_82571(struct e1000_hw
*hw
)
81 struct e1000_phy_info
*phy
= &hw
->phy
;
84 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
85 phy
->type
= e1000_phy_none
;
90 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
91 phy
->reset_delay_us
= 100;
93 switch (hw
->mac
.type
) {
96 phy
->type
= e1000_phy_igp_2
;
99 phy
->type
= e1000_phy_m88
;
102 phy
->type
= e1000_phy_bm
;
105 return -E1000_ERR_PHY
;
109 /* This can only be done after all function pointers are setup. */
110 ret_val
= e1000_get_phy_id_82571(hw
);
113 switch (hw
->mac
.type
) {
116 if (phy
->id
!= IGP01E1000_I_PHY_ID
)
117 return -E1000_ERR_PHY
;
120 if (phy
->id
!= M88E1111_I_PHY_ID
)
121 return -E1000_ERR_PHY
;
124 if (phy
->id
!= BME1000_E_PHY_ID_R2
)
125 return -E1000_ERR_PHY
;
128 return -E1000_ERR_PHY
;
136 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
137 * @hw: pointer to the HW structure
139 * This is a function pointer entry point called by the api module.
141 static s32
e1000_init_nvm_params_82571(struct e1000_hw
*hw
)
143 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
144 u32 eecd
= er32(EECD
);
147 nvm
->opcode_bits
= 8;
149 switch (nvm
->override
) {
150 case e1000_nvm_override_spi_large
:
152 nvm
->address_bits
= 16;
154 case e1000_nvm_override_spi_small
:
156 nvm
->address_bits
= 8;
159 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
160 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
? 16 : 8;
164 switch (hw
->mac
.type
) {
167 if (((eecd
>> 15) & 0x3) == 0x3) {
168 nvm
->type
= e1000_nvm_flash_hw
;
169 nvm
->word_size
= 2048;
171 * Autonomous Flash update bit must be cleared due
172 * to Flash update issue.
174 eecd
&= ~E1000_EECD_AUPDEN
;
180 nvm
->type
= e1000_nvm_eeprom_spi
;
181 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
182 E1000_EECD_SIZE_EX_SHIFT
);
184 * Added to a constant, "size" becomes the left-shift value
185 * for setting word_size.
187 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
189 /* EEPROM access above 16k is unsupported */
192 nvm
->word_size
= 1 << size
;
200 * e1000_init_mac_params_82571 - Init MAC func ptrs.
201 * @hw: pointer to the HW structure
203 * This is a function pointer entry point called by the api module.
205 static s32
e1000_init_mac_params_82571(struct e1000_adapter
*adapter
)
207 struct e1000_hw
*hw
= &adapter
->hw
;
208 struct e1000_mac_info
*mac
= &hw
->mac
;
209 struct e1000_mac_operations
*func
= &mac
->ops
;
212 switch (adapter
->pdev
->device
) {
213 case E1000_DEV_ID_82571EB_FIBER
:
214 case E1000_DEV_ID_82572EI_FIBER
:
215 case E1000_DEV_ID_82571EB_QUAD_FIBER
:
216 hw
->phy
.media_type
= e1000_media_type_fiber
;
218 case E1000_DEV_ID_82571EB_SERDES
:
219 case E1000_DEV_ID_82572EI_SERDES
:
220 case E1000_DEV_ID_82571EB_SERDES_DUAL
:
221 case E1000_DEV_ID_82571EB_SERDES_QUAD
:
222 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
225 hw
->phy
.media_type
= e1000_media_type_copper
;
229 /* Set mta register count */
230 mac
->mta_reg_count
= 128;
231 /* Set rar entry count */
232 mac
->rar_entry_count
= E1000_RAR_ENTRIES
;
233 /* Set if manageability features are enabled. */
234 mac
->arc_subsystem_valid
= (er32(FWSM
) & E1000_FWSM_MODE_MASK
) ? 1 : 0;
237 switch (hw
->phy
.media_type
) {
238 case e1000_media_type_copper
:
239 func
->setup_physical_interface
= e1000_setup_copper_link_82571
;
240 func
->check_for_link
= e1000e_check_for_copper_link
;
241 func
->get_link_up_info
= e1000e_get_speed_and_duplex_copper
;
243 case e1000_media_type_fiber
:
244 func
->setup_physical_interface
=
245 e1000_setup_fiber_serdes_link_82571
;
246 func
->check_for_link
= e1000e_check_for_fiber_link
;
247 func
->get_link_up_info
=
248 e1000e_get_speed_and_duplex_fiber_serdes
;
250 case e1000_media_type_internal_serdes
:
251 func
->setup_physical_interface
=
252 e1000_setup_fiber_serdes_link_82571
;
253 func
->check_for_link
= e1000e_check_for_serdes_link
;
254 func
->get_link_up_info
=
255 e1000e_get_speed_and_duplex_fiber_serdes
;
258 return -E1000_ERR_CONFIG
;
262 switch (hw
->mac
.type
) {
264 func
->check_mng_mode
= e1000_check_mng_mode_82574
;
265 func
->led_on
= e1000_led_on_82574
;
268 func
->check_mng_mode
= e1000e_check_mng_mode_generic
;
269 func
->led_on
= e1000e_led_on_generic
;
276 static s32
e1000_get_variants_82571(struct e1000_adapter
*adapter
)
278 struct e1000_hw
*hw
= &adapter
->hw
;
279 static int global_quad_port_a
; /* global port a indication */
280 struct pci_dev
*pdev
= adapter
->pdev
;
282 int is_port_b
= er32(STATUS
) & E1000_STATUS_FUNC_1
;
285 rc
= e1000_init_mac_params_82571(adapter
);
289 rc
= e1000_init_nvm_params_82571(hw
);
293 rc
= e1000_init_phy_params_82571(hw
);
297 /* tag quad port adapters first, it's used below */
298 switch (pdev
->device
) {
299 case E1000_DEV_ID_82571EB_QUAD_COPPER
:
300 case E1000_DEV_ID_82571EB_QUAD_FIBER
:
301 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP
:
302 case E1000_DEV_ID_82571PT_QUAD_COPPER
:
303 adapter
->flags
|= FLAG_IS_QUAD_PORT
;
304 /* mark the first port */
305 if (global_quad_port_a
== 0)
306 adapter
->flags
|= FLAG_IS_QUAD_PORT_A
;
307 /* Reset for multiple quad port adapters */
308 global_quad_port_a
++;
309 if (global_quad_port_a
== 4)
310 global_quad_port_a
= 0;
316 switch (adapter
->hw
.mac
.type
) {
318 /* these dual ports don't have WoL on port B at all */
319 if (((pdev
->device
== E1000_DEV_ID_82571EB_FIBER
) ||
320 (pdev
->device
== E1000_DEV_ID_82571EB_SERDES
) ||
321 (pdev
->device
== E1000_DEV_ID_82571EB_COPPER
)) &&
323 adapter
->flags
&= ~FLAG_HAS_WOL
;
324 /* quad ports only support WoL on port A */
325 if (adapter
->flags
& FLAG_IS_QUAD_PORT
&&
326 (!(adapter
->flags
& FLAG_IS_QUAD_PORT_A
)))
327 adapter
->flags
&= ~FLAG_HAS_WOL
;
328 /* Does not support WoL on any port */
329 if (pdev
->device
== E1000_DEV_ID_82571EB_SERDES_QUAD
)
330 adapter
->flags
&= ~FLAG_HAS_WOL
;
334 if (pdev
->device
== E1000_DEV_ID_82573L
) {
335 e1000_read_nvm(&adapter
->hw
, NVM_INIT_3GIO_3
, 1,
337 if (eeprom_data
& NVM_WORD1A_ASPM_MASK
)
338 adapter
->flags
&= ~FLAG_HAS_JUMBO_FRAMES
;
349 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
350 * @hw: pointer to the HW structure
352 * Reads the PHY registers and stores the PHY ID and possibly the PHY
353 * revision in the hardware structure.
355 static s32
e1000_get_phy_id_82571(struct e1000_hw
*hw
)
357 struct e1000_phy_info
*phy
= &hw
->phy
;
361 switch (hw
->mac
.type
) {
365 * The 82571 firmware may still be configuring the PHY.
366 * In this case, we cannot access the PHY until the
367 * configuration is done. So we explicitly set the
370 phy
->id
= IGP01E1000_I_PHY_ID
;
373 return e1000e_get_phy_id(hw
);
376 ret_val
= e1e_rphy(hw
, PHY_ID1
, &phy_id
);
380 phy
->id
= (u32
)(phy_id
<< 16);
382 ret_val
= e1e_rphy(hw
, PHY_ID2
, &phy_id
);
386 phy
->id
|= (u32
)(phy_id
);
387 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
390 return -E1000_ERR_PHY
;
398 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
399 * @hw: pointer to the HW structure
401 * Acquire the HW semaphore to access the PHY or NVM
403 static s32
e1000_get_hw_semaphore_82571(struct e1000_hw
*hw
)
406 s32 timeout
= hw
->nvm
.word_size
+ 1;
409 /* Get the FW semaphore. */
410 for (i
= 0; i
< timeout
; i
++) {
412 ew32(SWSM
, swsm
| E1000_SWSM_SWESMBI
);
414 /* Semaphore acquired if bit latched */
415 if (er32(SWSM
) & E1000_SWSM_SWESMBI
)
422 /* Release semaphores */
423 e1000e_put_hw_semaphore(hw
);
424 hw_dbg(hw
, "Driver can't access the NVM\n");
425 return -E1000_ERR_NVM
;
432 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
433 * @hw: pointer to the HW structure
435 * Release hardware semaphore used to access the PHY or NVM
437 static void e1000_put_hw_semaphore_82571(struct e1000_hw
*hw
)
443 swsm
&= ~E1000_SWSM_SWESMBI
;
449 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
450 * @hw: pointer to the HW structure
452 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
453 * Then for non-82573 hardware, set the EEPROM access request bit and wait
454 * for EEPROM access grant bit. If the access grant bit is not set, release
455 * hardware semaphore.
457 static s32
e1000_acquire_nvm_82571(struct e1000_hw
*hw
)
461 ret_val
= e1000_get_hw_semaphore_82571(hw
);
465 if (hw
->mac
.type
!= e1000_82573
&& hw
->mac
.type
!= e1000_82574
)
466 ret_val
= e1000e_acquire_nvm(hw
);
469 e1000_put_hw_semaphore_82571(hw
);
475 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
476 * @hw: pointer to the HW structure
478 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
480 static void e1000_release_nvm_82571(struct e1000_hw
*hw
)
482 e1000e_release_nvm(hw
);
483 e1000_put_hw_semaphore_82571(hw
);
487 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
488 * @hw: pointer to the HW structure
489 * @offset: offset within the EEPROM to be written to
490 * @words: number of words to write
491 * @data: 16 bit word(s) to be written to the EEPROM
493 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
495 * If e1000e_update_nvm_checksum is not called after this function, the
496 * EEPROM will most likely contain an invalid checksum.
498 static s32
e1000_write_nvm_82571(struct e1000_hw
*hw
, u16 offset
, u16 words
,
503 switch (hw
->mac
.type
) {
506 ret_val
= e1000_write_nvm_eewr_82571(hw
, offset
, words
, data
);
510 ret_val
= e1000e_write_nvm_spi(hw
, offset
, words
, data
);
513 ret_val
= -E1000_ERR_NVM
;
521 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
522 * @hw: pointer to the HW structure
524 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
525 * up to the checksum. Then calculates the EEPROM checksum and writes the
526 * value to the EEPROM.
528 static s32
e1000_update_nvm_checksum_82571(struct e1000_hw
*hw
)
534 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
539 * If our nvm is an EEPROM, then we're done
540 * otherwise, commit the checksum to the flash NVM.
542 if (hw
->nvm
.type
!= e1000_nvm_flash_hw
)
545 /* Check for pending operations. */
546 for (i
= 0; i
< E1000_FLASH_UPDATES
; i
++) {
548 if ((er32(EECD
) & E1000_EECD_FLUPD
) == 0)
552 if (i
== E1000_FLASH_UPDATES
)
553 return -E1000_ERR_NVM
;
555 /* Reset the firmware if using STM opcode. */
556 if ((er32(FLOP
) & 0xFF00) == E1000_STM_OPCODE
) {
558 * The enabling of and the actual reset must be done
559 * in two write cycles.
561 ew32(HICR
, E1000_HICR_FW_RESET_ENABLE
);
563 ew32(HICR
, E1000_HICR_FW_RESET
);
566 /* Commit the write to flash */
567 eecd
= er32(EECD
) | E1000_EECD_FLUPD
;
570 for (i
= 0; i
< E1000_FLASH_UPDATES
; i
++) {
572 if ((er32(EECD
) & E1000_EECD_FLUPD
) == 0)
576 if (i
== E1000_FLASH_UPDATES
)
577 return -E1000_ERR_NVM
;
583 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
584 * @hw: pointer to the HW structure
586 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
587 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
589 static s32
e1000_validate_nvm_checksum_82571(struct e1000_hw
*hw
)
591 if (hw
->nvm
.type
== e1000_nvm_flash_hw
)
592 e1000_fix_nvm_checksum_82571(hw
);
594 return e1000e_validate_nvm_checksum_generic(hw
);
598 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
599 * @hw: pointer to the HW structure
600 * @offset: offset within the EEPROM to be written to
601 * @words: number of words to write
602 * @data: 16 bit word(s) to be written to the EEPROM
604 * After checking for invalid values, poll the EEPROM to ensure the previous
605 * command has completed before trying to write the next word. After write
606 * poll for completion.
608 * If e1000e_update_nvm_checksum is not called after this function, the
609 * EEPROM will most likely contain an invalid checksum.
611 static s32
e1000_write_nvm_eewr_82571(struct e1000_hw
*hw
, u16 offset
,
612 u16 words
, u16
*data
)
614 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
620 * A check for invalid values: offset too large, too many words,
621 * and not enough words.
623 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
625 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
626 return -E1000_ERR_NVM
;
629 for (i
= 0; i
< words
; i
++) {
630 eewr
= (data
[i
] << E1000_NVM_RW_REG_DATA
) |
631 ((offset
+i
) << E1000_NVM_RW_ADDR_SHIFT
) |
632 E1000_NVM_RW_REG_START
;
634 ret_val
= e1000e_poll_eerd_eewr_done(hw
, E1000_NVM_POLL_WRITE
);
640 ret_val
= e1000e_poll_eerd_eewr_done(hw
, E1000_NVM_POLL_WRITE
);
649 * e1000_get_cfg_done_82571 - Poll for configuration done
650 * @hw: pointer to the HW structure
652 * Reads the management control register for the config done bit to be set.
654 static s32
e1000_get_cfg_done_82571(struct e1000_hw
*hw
)
656 s32 timeout
= PHY_CFG_TIMEOUT
;
660 E1000_NVM_CFG_DONE_PORT_0
)
666 hw_dbg(hw
, "MNG configuration cycle has not completed.\n");
667 return -E1000_ERR_RESET
;
674 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
675 * @hw: pointer to the HW structure
676 * @active: TRUE to enable LPLU, FALSE to disable
678 * Sets the LPLU D0 state according to the active flag. When activating LPLU
679 * this function also disables smart speed and vice versa. LPLU will not be
680 * activated unless the device autonegotiation advertisement meets standards
681 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
682 * pointer entry point only called by PHY setup routines.
684 static s32
e1000_set_d0_lplu_state_82571(struct e1000_hw
*hw
, bool active
)
686 struct e1000_phy_info
*phy
= &hw
->phy
;
690 ret_val
= e1e_rphy(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
695 data
|= IGP02E1000_PM_D0_LPLU
;
696 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
700 /* When LPLU is enabled, we should disable SmartSpeed */
701 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
702 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
703 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
707 data
&= ~IGP02E1000_PM_D0_LPLU
;
708 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
710 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
711 * during Dx states where the power conservation is most
712 * important. During driver activity we should enable
713 * SmartSpeed, so performance is maintained.
715 if (phy
->smart_speed
== e1000_smart_speed_on
) {
716 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
721 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
722 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
726 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
727 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
732 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
733 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
744 * e1000_reset_hw_82571 - Reset hardware
745 * @hw: pointer to the HW structure
747 * This resets the hardware into a known state. This is a
748 * function pointer entry point called by the api module.
750 static s32
e1000_reset_hw_82571(struct e1000_hw
*hw
)
760 * Prevent the PCI-E bus from sticking if there is no TLP connection
761 * on the last TLP read/write transaction when MAC is reset.
763 ret_val
= e1000e_disable_pcie_master(hw
);
765 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
767 hw_dbg(hw
, "Masking off all interrupts\n");
768 ew32(IMC
, 0xffffffff);
771 ew32(TCTL
, E1000_TCTL_PSP
);
777 * Must acquire the MDIO ownership before MAC reset.
778 * Ownership defaults to firmware after a reset.
780 if (hw
->mac
.type
== e1000_82573
|| hw
->mac
.type
== e1000_82574
) {
781 extcnf_ctrl
= er32(EXTCNF_CTRL
);
782 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
785 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
786 extcnf_ctrl
= er32(EXTCNF_CTRL
);
788 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
)
791 extcnf_ctrl
|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP
;
795 } while (i
< MDIO_OWNERSHIP_TIMEOUT
);
800 hw_dbg(hw
, "Issuing a global reset to MAC\n");
801 ew32(CTRL
, ctrl
| E1000_CTRL_RST
);
803 if (hw
->nvm
.type
== e1000_nvm_flash_hw
) {
805 ctrl_ext
= er32(CTRL_EXT
);
806 ctrl_ext
|= E1000_CTRL_EXT_EE_RST
;
807 ew32(CTRL_EXT
, ctrl_ext
);
811 ret_val
= e1000e_get_auto_rd_done(hw
);
813 /* We don't want to continue accessing MAC registers. */
817 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
818 * Need to wait for Phy configuration completion before accessing
821 if (hw
->mac
.type
== e1000_82573
|| hw
->mac
.type
== e1000_82574
)
824 /* Clear any pending interrupt events. */
825 ew32(IMC
, 0xffffffff);
828 if (hw
->mac
.type
== e1000_82571
&&
829 hw
->dev_spec
.e82571
.alt_mac_addr_is_present
)
830 e1000e_set_laa_state_82571(hw
, true);
836 * e1000_init_hw_82571 - Initialize hardware
837 * @hw: pointer to the HW structure
839 * This inits the hardware readying it for operation.
841 static s32
e1000_init_hw_82571(struct e1000_hw
*hw
)
843 struct e1000_mac_info
*mac
= &hw
->mac
;
847 u16 rar_count
= mac
->rar_entry_count
;
849 e1000_initialize_hw_bits_82571(hw
);
851 /* Initialize identification LED */
852 ret_val
= e1000e_id_led_init(hw
);
854 hw_dbg(hw
, "Error initializing identification LED\n");
858 /* Disabling VLAN filtering */
859 hw_dbg(hw
, "Initializing the IEEE VLAN\n");
860 e1000e_clear_vfta(hw
);
862 /* Setup the receive address. */
864 * If, however, a locally administered address was assigned to the
865 * 82571, we must reserve a RAR for it to work around an issue where
866 * resetting one port will reload the MAC on the other port.
868 if (e1000e_get_laa_state_82571(hw
))
870 e1000e_init_rx_addrs(hw
, rar_count
);
872 /* Zero out the Multicast HASH table */
873 hw_dbg(hw
, "Zeroing the MTA\n");
874 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
875 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
877 /* Setup link and flow control */
878 ret_val
= e1000_setup_link_82571(hw
);
880 /* Set the transmit descriptor write-back policy */
881 reg_data
= er32(TXDCTL(0));
882 reg_data
= (reg_data
& ~E1000_TXDCTL_WTHRESH
) |
883 E1000_TXDCTL_FULL_TX_DESC_WB
|
884 E1000_TXDCTL_COUNT_DESC
;
885 ew32(TXDCTL(0), reg_data
);
887 /* ...for both queues. */
888 if (mac
->type
!= e1000_82573
&& mac
->type
!= e1000_82574
) {
889 reg_data
= er32(TXDCTL(1));
890 reg_data
= (reg_data
& ~E1000_TXDCTL_WTHRESH
) |
891 E1000_TXDCTL_FULL_TX_DESC_WB
|
892 E1000_TXDCTL_COUNT_DESC
;
893 ew32(TXDCTL(1), reg_data
);
895 e1000e_enable_tx_pkt_filtering(hw
);
896 reg_data
= er32(GCR
);
897 reg_data
|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX
;
902 * Clear all of the statistics registers (clear on read). It is
903 * important that we do this after we have tried to establish link
904 * because the symbol error count will increment wildly if there
907 e1000_clear_hw_cntrs_82571(hw
);
913 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
914 * @hw: pointer to the HW structure
916 * Initializes required hardware-dependent bits needed for normal operation.
918 static void e1000_initialize_hw_bits_82571(struct e1000_hw
*hw
)
922 /* Transmit Descriptor Control 0 */
923 reg
= er32(TXDCTL(0));
925 ew32(TXDCTL(0), reg
);
927 /* Transmit Descriptor Control 1 */
928 reg
= er32(TXDCTL(1));
930 ew32(TXDCTL(1), reg
);
932 /* Transmit Arbitration Control 0 */
934 reg
&= ~(0xF << 27); /* 30:27 */
935 switch (hw
->mac
.type
) {
938 reg
|= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
945 /* Transmit Arbitration Control 1 */
947 switch (hw
->mac
.type
) {
950 reg
&= ~((1 << 29) | (1 << 30));
951 reg
|= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
952 if (er32(TCTL
) & E1000_TCTL_MULR
)
963 if (hw
->mac
.type
== e1000_82573
|| hw
->mac
.type
== e1000_82574
) {
969 /* Extended Device Control */
970 if (hw
->mac
.type
== e1000_82573
|| hw
->mac
.type
== e1000_82574
) {
971 reg
= er32(CTRL_EXT
);
977 if (hw
->mac
.type
== e1000_82571
) {
979 reg
|= E1000_PBA_ECC_CORR_EN
;
983 /* PCI-Ex Control Register */
984 if (hw
->mac
.type
== e1000_82574
) {
994 * e1000e_clear_vfta - Clear VLAN filter table
995 * @hw: pointer to the HW structure
997 * Clears the register array which contains the VLAN filter table by
998 * setting all the values to 0.
1000 void e1000e_clear_vfta(struct e1000_hw
*hw
)
1004 u32 vfta_offset
= 0;
1005 u32 vfta_bit_in_reg
= 0;
1007 if (hw
->mac
.type
== e1000_82573
|| hw
->mac
.type
== e1000_82574
) {
1008 if (hw
->mng_cookie
.vlan_id
!= 0) {
1010 * The VFTA is a 4096b bit-field, each identifying
1011 * a single VLAN ID. The following operations
1012 * determine which 32b entry (i.e. offset) into the
1013 * array we want to set the VLAN ID (i.e. bit) of
1014 * the manageability unit.
1016 vfta_offset
= (hw
->mng_cookie
.vlan_id
>>
1017 E1000_VFTA_ENTRY_SHIFT
) &
1018 E1000_VFTA_ENTRY_MASK
;
1019 vfta_bit_in_reg
= 1 << (hw
->mng_cookie
.vlan_id
&
1020 E1000_VFTA_ENTRY_BIT_SHIFT_MASK
);
1023 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
1025 * If the offset we want to clear is the same offset of the
1026 * manageability VLAN ID, then clear all bits except that of
1027 * the manageability unit.
1029 vfta_value
= (offset
== vfta_offset
) ? vfta_bit_in_reg
: 0;
1030 E1000_WRITE_REG_ARRAY(hw
, E1000_VFTA
, offset
, vfta_value
);
1036 * e1000_check_mng_mode_82574 - Check manageability is enabled
1037 * @hw: pointer to the HW structure
1039 * Reads the NVM Initialization Control Word 2 and returns true
1040 * (>0) if any manageability is enabled, else false (0).
1042 static bool e1000_check_mng_mode_82574(struct e1000_hw
*hw
)
1046 e1000_read_nvm(hw
, NVM_INIT_CONTROL2_REG
, 1, &data
);
1047 return (data
& E1000_NVM_INIT_CTRL2_MNGM
) != 0;
1051 * e1000_led_on_82574 - Turn LED on
1052 * @hw: pointer to the HW structure
1056 static s32
e1000_led_on_82574(struct e1000_hw
*hw
)
1061 ctrl
= hw
->mac
.ledctl_mode2
;
1062 if (!(E1000_STATUS_LU
& er32(STATUS
))) {
1064 * If no link, then turn LED on by setting the invert bit
1065 * for each LED that's "on" (0x0E) in ledctl_mode2.
1067 for (i
= 0; i
< 4; i
++)
1068 if (((hw
->mac
.ledctl_mode2
>> (i
* 8)) & 0xFF) ==
1069 E1000_LEDCTL_MODE_LED_ON
)
1070 ctrl
|= (E1000_LEDCTL_LED0_IVRT
<< (i
* 8));
1078 * e1000_update_mc_addr_list_82571 - Update Multicast addresses
1079 * @hw: pointer to the HW structure
1080 * @mc_addr_list: array of multicast addresses to program
1081 * @mc_addr_count: number of multicast addresses to program
1082 * @rar_used_count: the first RAR register free to program
1083 * @rar_count: total number of supported Receive Address Registers
1085 * Updates the Receive Address Registers and Multicast Table Array.
1086 * The caller must have a packed mc_addr_list of multicast addresses.
1087 * The parameter rar_count will usually be hw->mac.rar_entry_count
1088 * unless there are workarounds that change this.
1090 static void e1000_update_mc_addr_list_82571(struct e1000_hw
*hw
,
1096 if (e1000e_get_laa_state_82571(hw
))
1099 e1000e_update_mc_addr_list_generic(hw
, mc_addr_list
, mc_addr_count
,
1100 rar_used_count
, rar_count
);
1104 * e1000_setup_link_82571 - Setup flow control and link settings
1105 * @hw: pointer to the HW structure
1107 * Determines which flow control settings to use, then configures flow
1108 * control. Calls the appropriate media-specific link configuration
1109 * function. Assuming the adapter has a valid link partner, a valid link
1110 * should be established. Assumes the hardware has previously been reset
1111 * and the transmitter and receiver are not enabled.
1113 static s32
e1000_setup_link_82571(struct e1000_hw
*hw
)
1116 * 82573 does not have a word in the NVM to determine
1117 * the default flow control setting, so we explicitly
1120 if ((hw
->mac
.type
== e1000_82573
|| hw
->mac
.type
== e1000_82574
) &&
1121 hw
->fc
.type
== e1000_fc_default
)
1122 hw
->fc
.type
= e1000_fc_full
;
1124 return e1000e_setup_link(hw
);
1128 * e1000_setup_copper_link_82571 - Configure copper link settings
1129 * @hw: pointer to the HW structure
1131 * Configures the link for auto-neg or forced speed and duplex. Then we check
1132 * for link, once link is established calls to configure collision distance
1133 * and flow control are called.
1135 static s32
e1000_setup_copper_link_82571(struct e1000_hw
*hw
)
1142 ctrl
|= E1000_CTRL_SLU
;
1143 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1146 switch (hw
->phy
.type
) {
1149 ret_val
= e1000e_copper_link_setup_m88(hw
);
1151 case e1000_phy_igp_2
:
1152 ret_val
= e1000e_copper_link_setup_igp(hw
);
1153 /* Setup activity LED */
1154 led_ctrl
= er32(LEDCTL
);
1155 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
1156 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
1157 ew32(LEDCTL
, led_ctrl
);
1160 return -E1000_ERR_PHY
;
1167 ret_val
= e1000e_setup_copper_link(hw
);
1173 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1174 * @hw: pointer to the HW structure
1176 * Configures collision distance and flow control for fiber and serdes links.
1177 * Upon successful setup, poll for link.
1179 static s32
e1000_setup_fiber_serdes_link_82571(struct e1000_hw
*hw
)
1181 switch (hw
->mac
.type
) {
1185 * If SerDes loopback mode is entered, there is no form
1186 * of reset to take the adapter out of that mode. So we
1187 * have to explicitly take the adapter out of loopback
1188 * mode. This prevents drivers from twiddling their thumbs
1189 * if another tool failed to take it out of loopback mode.
1191 ew32(SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1197 return e1000e_setup_fiber_serdes_link(hw
);
1201 * e1000_valid_led_default_82571 - Verify a valid default LED config
1202 * @hw: pointer to the HW structure
1203 * @data: pointer to the NVM (EEPROM)
1205 * Read the EEPROM for the current default LED configuration. If the
1206 * LED configuration is not valid, set to a valid LED configuration.
1208 static s32
e1000_valid_led_default_82571(struct e1000_hw
*hw
, u16
*data
)
1212 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1214 hw_dbg(hw
, "NVM Read Error\n");
1218 if ((hw
->mac
.type
== e1000_82573
|| hw
->mac
.type
== e1000_82574
) &&
1219 *data
== ID_LED_RESERVED_F746
)
1220 *data
= ID_LED_DEFAULT_82573
;
1221 else if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
)
1222 *data
= ID_LED_DEFAULT
;
1228 * e1000e_get_laa_state_82571 - Get locally administered address state
1229 * @hw: pointer to the HW structure
1231 * Retrieve and return the current locally administered address state.
1233 bool e1000e_get_laa_state_82571(struct e1000_hw
*hw
)
1235 if (hw
->mac
.type
!= e1000_82571
)
1238 return hw
->dev_spec
.e82571
.laa_is_present
;
1242 * e1000e_set_laa_state_82571 - Set locally administered address state
1243 * @hw: pointer to the HW structure
1244 * @state: enable/disable locally administered address
1246 * Enable/Disable the current locally administers address state.
1248 void e1000e_set_laa_state_82571(struct e1000_hw
*hw
, bool state
)
1250 if (hw
->mac
.type
!= e1000_82571
)
1253 hw
->dev_spec
.e82571
.laa_is_present
= state
;
1255 /* If workaround is activated... */
1258 * Hold a copy of the LAA in RAR[14] This is done so that
1259 * between the time RAR[0] gets clobbered and the time it
1260 * gets fixed, the actual LAA is in one of the RARs and no
1261 * incoming packets directed to this port are dropped.
1262 * Eventually the LAA will be in RAR[0] and RAR[14].
1264 e1000e_rar_set(hw
, hw
->mac
.addr
, hw
->mac
.rar_entry_count
- 1);
1268 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1269 * @hw: pointer to the HW structure
1271 * Verifies that the EEPROM has completed the update. After updating the
1272 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1273 * the checksum fix is not implemented, we need to set the bit and update
1274 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1275 * we need to return bad checksum.
1277 static s32
e1000_fix_nvm_checksum_82571(struct e1000_hw
*hw
)
1279 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1283 if (nvm
->type
!= e1000_nvm_flash_hw
)
1287 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1288 * 10h-12h. Checksum may need to be fixed.
1290 ret_val
= e1000_read_nvm(hw
, 0x10, 1, &data
);
1294 if (!(data
& 0x10)) {
1296 * Read 0x23 and check bit 15. This bit is a 1
1297 * when the checksum has already been fixed. If
1298 * the checksum is still wrong and this bit is a
1299 * 1, we need to return bad checksum. Otherwise,
1300 * we need to set this bit to a 1 and update the
1303 ret_val
= e1000_read_nvm(hw
, 0x23, 1, &data
);
1307 if (!(data
& 0x8000)) {
1309 ret_val
= e1000_write_nvm(hw
, 0x23, 1, &data
);
1312 ret_val
= e1000e_update_nvm_checksum(hw
);
1320 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1321 * @hw: pointer to the HW structure
1323 * Clears the hardware counters by reading the counter registers.
1325 static void e1000_clear_hw_cntrs_82571(struct e1000_hw
*hw
)
1329 e1000e_clear_hw_cntrs_base(hw
);
1332 temp
= er32(PRC127
);
1333 temp
= er32(PRC255
);
1334 temp
= er32(PRC511
);
1335 temp
= er32(PRC1023
);
1336 temp
= er32(PRC1522
);
1338 temp
= er32(PTC127
);
1339 temp
= er32(PTC255
);
1340 temp
= er32(PTC511
);
1341 temp
= er32(PTC1023
);
1342 temp
= er32(PTC1522
);
1344 temp
= er32(ALGNERRC
);
1345 temp
= er32(RXERRC
);
1347 temp
= er32(CEXTERR
);
1349 temp
= er32(TSCTFC
);
1351 temp
= er32(MGTPRC
);
1352 temp
= er32(MGTPDC
);
1353 temp
= er32(MGTPTC
);
1356 temp
= er32(ICRXOC
);
1358 temp
= er32(ICRXPTC
);
1359 temp
= er32(ICRXATC
);
1360 temp
= er32(ICTXPTC
);
1361 temp
= er32(ICTXATC
);
1362 temp
= er32(ICTXQEC
);
1363 temp
= er32(ICTXQMTC
);
1364 temp
= er32(ICRXDMTC
);
1367 static struct e1000_mac_operations e82571_mac_ops
= {
1368 /* .check_mng_mode: mac type dependent */
1369 /* .check_for_link: media type dependent */
1370 .cleanup_led
= e1000e_cleanup_led_generic
,
1371 .clear_hw_cntrs
= e1000_clear_hw_cntrs_82571
,
1372 .get_bus_info
= e1000e_get_bus_info_pcie
,
1373 /* .get_link_up_info: media type dependent */
1374 /* .led_on: mac type dependent */
1375 .led_off
= e1000e_led_off_generic
,
1376 .update_mc_addr_list
= e1000_update_mc_addr_list_82571
,
1377 .reset_hw
= e1000_reset_hw_82571
,
1378 .init_hw
= e1000_init_hw_82571
,
1379 .setup_link
= e1000_setup_link_82571
,
1380 /* .setup_physical_interface: media type dependent */
1383 static struct e1000_phy_operations e82_phy_ops_igp
= {
1384 .acquire_phy
= e1000_get_hw_semaphore_82571
,
1385 .check_reset_block
= e1000e_check_reset_block_generic
,
1387 .force_speed_duplex
= e1000e_phy_force_speed_duplex_igp
,
1388 .get_cfg_done
= e1000_get_cfg_done_82571
,
1389 .get_cable_length
= e1000e_get_cable_length_igp_2
,
1390 .get_phy_info
= e1000e_get_phy_info_igp
,
1391 .read_phy_reg
= e1000e_read_phy_reg_igp
,
1392 .release_phy
= e1000_put_hw_semaphore_82571
,
1393 .reset_phy
= e1000e_phy_hw_reset_generic
,
1394 .set_d0_lplu_state
= e1000_set_d0_lplu_state_82571
,
1395 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1396 .write_phy_reg
= e1000e_write_phy_reg_igp
,
1399 static struct e1000_phy_operations e82_phy_ops_m88
= {
1400 .acquire_phy
= e1000_get_hw_semaphore_82571
,
1401 .check_reset_block
= e1000e_check_reset_block_generic
,
1402 .commit_phy
= e1000e_phy_sw_reset
,
1403 .force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
,
1404 .get_cfg_done
= e1000e_get_cfg_done
,
1405 .get_cable_length
= e1000e_get_cable_length_m88
,
1406 .get_phy_info
= e1000e_get_phy_info_m88
,
1407 .read_phy_reg
= e1000e_read_phy_reg_m88
,
1408 .release_phy
= e1000_put_hw_semaphore_82571
,
1409 .reset_phy
= e1000e_phy_hw_reset_generic
,
1410 .set_d0_lplu_state
= e1000_set_d0_lplu_state_82571
,
1411 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1412 .write_phy_reg
= e1000e_write_phy_reg_m88
,
1415 static struct e1000_phy_operations e82_phy_ops_bm
= {
1416 .acquire_phy
= e1000_get_hw_semaphore_82571
,
1417 .check_reset_block
= e1000e_check_reset_block_generic
,
1418 .commit_phy
= e1000e_phy_sw_reset
,
1419 .force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
,
1420 .get_cfg_done
= e1000e_get_cfg_done
,
1421 .get_cable_length
= e1000e_get_cable_length_m88
,
1422 .get_phy_info
= e1000e_get_phy_info_m88
,
1423 .read_phy_reg
= e1000e_read_phy_reg_bm2
,
1424 .release_phy
= e1000_put_hw_semaphore_82571
,
1425 .reset_phy
= e1000e_phy_hw_reset_generic
,
1426 .set_d0_lplu_state
= e1000_set_d0_lplu_state_82571
,
1427 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1428 .write_phy_reg
= e1000e_write_phy_reg_bm2
,
1431 static struct e1000_nvm_operations e82571_nvm_ops
= {
1432 .acquire_nvm
= e1000_acquire_nvm_82571
,
1433 .read_nvm
= e1000e_read_nvm_eerd
,
1434 .release_nvm
= e1000_release_nvm_82571
,
1435 .update_nvm
= e1000_update_nvm_checksum_82571
,
1436 .valid_led_default
= e1000_valid_led_default_82571
,
1437 .validate_nvm
= e1000_validate_nvm_checksum_82571
,
1438 .write_nvm
= e1000_write_nvm_82571
,
1441 struct e1000_info e1000_82571_info
= {
1443 .flags
= FLAG_HAS_HW_VLAN_FILTER
1444 | FLAG_HAS_JUMBO_FRAMES
1446 | FLAG_APME_IN_CTRL3
1447 | FLAG_RX_CSUM_ENABLED
1448 | FLAG_HAS_CTRLEXT_ON_LOAD
1449 | FLAG_HAS_SMART_POWER_DOWN
1450 | FLAG_RESET_OVERWRITES_LAA
/* errata */
1451 | FLAG_TARC_SPEED_MODE_BIT
/* errata */
1452 | FLAG_APME_CHECK_PORT_B
,
1454 .get_variants
= e1000_get_variants_82571
,
1455 .mac_ops
= &e82571_mac_ops
,
1456 .phy_ops
= &e82_phy_ops_igp
,
1457 .nvm_ops
= &e82571_nvm_ops
,
1460 struct e1000_info e1000_82572_info
= {
1462 .flags
= FLAG_HAS_HW_VLAN_FILTER
1463 | FLAG_HAS_JUMBO_FRAMES
1465 | FLAG_APME_IN_CTRL3
1466 | FLAG_RX_CSUM_ENABLED
1467 | FLAG_HAS_CTRLEXT_ON_LOAD
1468 | FLAG_TARC_SPEED_MODE_BIT
, /* errata */
1470 .get_variants
= e1000_get_variants_82571
,
1471 .mac_ops
= &e82571_mac_ops
,
1472 .phy_ops
= &e82_phy_ops_igp
,
1473 .nvm_ops
= &e82571_nvm_ops
,
1476 struct e1000_info e1000_82573_info
= {
1478 .flags
= FLAG_HAS_HW_VLAN_FILTER
1479 | FLAG_HAS_JUMBO_FRAMES
1481 | FLAG_APME_IN_CTRL3
1482 | FLAG_RX_CSUM_ENABLED
1483 | FLAG_HAS_SMART_POWER_DOWN
1486 | FLAG_HAS_SWSM_ON_LOAD
,
1488 .get_variants
= e1000_get_variants_82571
,
1489 .mac_ops
= &e82571_mac_ops
,
1490 .phy_ops
= &e82_phy_ops_m88
,
1491 .nvm_ops
= &e82571_nvm_ops
,
1494 struct e1000_info e1000_82574_info
= {
1496 .flags
= FLAG_HAS_HW_VLAN_FILTER
1498 | FLAG_HAS_JUMBO_FRAMES
1500 | FLAG_APME_IN_CTRL3
1501 | FLAG_RX_CSUM_ENABLED
1502 | FLAG_HAS_SMART_POWER_DOWN
1504 | FLAG_HAS_CTRLEXT_ON_LOAD
,
1506 .get_variants
= e1000_get_variants_82571
,
1507 .mac_ops
= &e82571_mac_ops
,
1508 .phy_ops
= &e82_phy_ops_bm
,
1509 .nvm_ops
= &e82571_nvm_ops
,