1 /*******************************************************************************
3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the adapter
36 /* Local function prototypes */
38 static u32
ixgb_hash_mc_addr(struct ixgb_hw
*hw
, u8
* mc_addr
);
40 static void ixgb_mta_set(struct ixgb_hw
*hw
, u32 hash_value
);
42 static void ixgb_get_bus_info(struct ixgb_hw
*hw
);
44 static bool ixgb_link_reset(struct ixgb_hw
*hw
);
46 static void ixgb_optics_reset(struct ixgb_hw
*hw
);
48 static void ixgb_optics_reset_bcm(struct ixgb_hw
*hw
);
50 static ixgb_phy_type
ixgb_identify_phy(struct ixgb_hw
*hw
);
52 static void ixgb_clear_hw_cntrs(struct ixgb_hw
*hw
);
54 static void ixgb_clear_vfta(struct ixgb_hw
*hw
);
56 static void ixgb_init_rx_addrs(struct ixgb_hw
*hw
);
58 static u16
ixgb_read_phy_reg(struct ixgb_hw
*hw
,
63 static bool ixgb_setup_fc(struct ixgb_hw
*hw
);
65 static bool mac_addr_valid(u8
*mac_addr
);
67 static u32
ixgb_mac_reset(struct ixgb_hw
*hw
)
71 ctrl_reg
= IXGB_CTRL0_RST
|
72 IXGB_CTRL0_SDP3_DIR
| /* All pins are Output=1 */
76 IXGB_CTRL0_SDP3
| /* Initial value 1101 */
81 /* Workaround for 82597EX reset errata */
82 IXGB_WRITE_REG_IO(hw
, CTRL0
, ctrl_reg
);
84 IXGB_WRITE_REG(hw
, CTRL0
, ctrl_reg
);
87 /* Delay a few ms just to allow the reset to complete */
88 msleep(IXGB_DELAY_AFTER_RESET
);
89 ctrl_reg
= IXGB_READ_REG(hw
, CTRL0
);
91 /* Make sure the self-clearing global reset bit did self clear */
92 ASSERT(!(ctrl_reg
& IXGB_CTRL0_RST
));
95 if (hw
->subsystem_vendor_id
== SUN_SUBVENDOR_ID
) {
96 ctrl_reg
= /* Enable interrupt from XFP and SerDes */
102 IXGB_WRITE_REG(hw
, CTRL1
, ctrl_reg
);
103 ixgb_optics_reset_bcm(hw
);
106 if (hw
->phy_type
== ixgb_phy_type_txn17401
)
107 ixgb_optics_reset(hw
);
112 /******************************************************************************
113 * Reset the transmit and receive units; mask and clear all interrupts.
115 * hw - Struct containing variables accessed by shared code
116 *****************************************************************************/
118 ixgb_adapter_stop(struct ixgb_hw
*hw
)
123 DEBUGFUNC("ixgb_adapter_stop");
125 /* If we are stopped or resetting exit gracefully and wait to be
126 * started again before accessing the hardware.
128 if (hw
->adapter_stopped
) {
129 DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
133 /* Set the Adapter Stopped flag so other driver functions stop
134 * touching the Hardware.
136 hw
->adapter_stopped
= true;
138 /* Clear interrupt mask to stop board from generating interrupts */
139 DEBUGOUT("Masking off all interrupts\n");
140 IXGB_WRITE_REG(hw
, IMC
, 0xFFFFFFFF);
142 /* Disable the Transmit and Receive units. Then delay to allow
143 * any pending transactions to complete before we hit the MAC with
146 IXGB_WRITE_REG(hw
, RCTL
, IXGB_READ_REG(hw
, RCTL
) & ~IXGB_RCTL_RXEN
);
147 IXGB_WRITE_REG(hw
, TCTL
, IXGB_READ_REG(hw
, TCTL
) & ~IXGB_TCTL_TXEN
);
148 msleep(IXGB_DELAY_BEFORE_RESET
);
150 /* Issue a global reset to the MAC. This will reset the chip's
151 * transmit, receive, DMA, and link units. It will not effect
152 * the current PCI configuration. The global reset bit is self-
153 * clearing, and should clear within a microsecond.
155 DEBUGOUT("Issuing a global reset to MAC\n");
157 ctrl_reg
= ixgb_mac_reset(hw
);
159 /* Clear interrupt mask to stop board from generating interrupts */
160 DEBUGOUT("Masking off all interrupts\n");
161 IXGB_WRITE_REG(hw
, IMC
, 0xffffffff);
163 /* Clear any pending interrupt events. */
164 icr_reg
= IXGB_READ_REG(hw
, ICR
);
166 return (ctrl_reg
& IXGB_CTRL0_RST
);
170 /******************************************************************************
171 * Identifies the vendor of the optics module on the adapter. The SR adapters
172 * support two different types of XPAK optics, so it is necessary to determine
173 * which optics are present before applying any optics-specific workarounds.
175 * hw - Struct containing variables accessed by shared code.
177 * Returns: the vendor of the XPAK optics module.
178 *****************************************************************************/
179 static ixgb_xpak_vendor
180 ixgb_identify_xpak_vendor(struct ixgb_hw
*hw
)
184 ixgb_xpak_vendor xpak_vendor
;
186 DEBUGFUNC("ixgb_identify_xpak_vendor");
188 /* Read the first few bytes of the vendor string from the XPAK NVR
189 * registers. These are standard XENPAK/XPAK registers, so all XPAK
190 * devices should implement them. */
191 for (i
= 0; i
< 5; i
++) {
192 vendor_name
[i
] = ixgb_read_phy_reg(hw
,
193 MDIO_PMA_PMD_XPAK_VENDOR_NAME
194 + i
, IXGB_PHY_ADDRESS
,
198 /* Determine the actual vendor */
199 if (vendor_name
[0] == 'I' &&
200 vendor_name
[1] == 'N' &&
201 vendor_name
[2] == 'T' &&
202 vendor_name
[3] == 'E' && vendor_name
[4] == 'L') {
203 xpak_vendor
= ixgb_xpak_vendor_intel
;
205 xpak_vendor
= ixgb_xpak_vendor_infineon
;
208 return (xpak_vendor
);
211 /******************************************************************************
212 * Determine the physical layer module on the adapter.
214 * hw - Struct containing variables accessed by shared code. The device_id
215 * field must be (correctly) populated before calling this routine.
217 * Returns: the phy type of the adapter.
218 *****************************************************************************/
220 ixgb_identify_phy(struct ixgb_hw
*hw
)
222 ixgb_phy_type phy_type
;
223 ixgb_xpak_vendor xpak_vendor
;
225 DEBUGFUNC("ixgb_identify_phy");
227 /* Infer the transceiver/phy type from the device id */
228 switch (hw
->device_id
) {
229 case IXGB_DEVICE_ID_82597EX
:
230 DEBUGOUT("Identified TXN17401 optics\n");
231 phy_type
= ixgb_phy_type_txn17401
;
234 case IXGB_DEVICE_ID_82597EX_SR
:
235 /* The SR adapters carry two different types of XPAK optics
236 * modules; read the vendor identifier to determine the exact
238 xpak_vendor
= ixgb_identify_xpak_vendor(hw
);
239 if (xpak_vendor
== ixgb_xpak_vendor_intel
) {
240 DEBUGOUT("Identified TXN17201 optics\n");
241 phy_type
= ixgb_phy_type_txn17201
;
243 DEBUGOUT("Identified G6005 optics\n");
244 phy_type
= ixgb_phy_type_g6005
;
247 case IXGB_DEVICE_ID_82597EX_LR
:
248 DEBUGOUT("Identified G6104 optics\n");
249 phy_type
= ixgb_phy_type_g6104
;
251 case IXGB_DEVICE_ID_82597EX_CX4
:
252 DEBUGOUT("Identified CX4\n");
253 xpak_vendor
= ixgb_identify_xpak_vendor(hw
);
254 if (xpak_vendor
== ixgb_xpak_vendor_intel
) {
255 DEBUGOUT("Identified TXN17201 optics\n");
256 phy_type
= ixgb_phy_type_txn17201
;
258 DEBUGOUT("Identified G6005 optics\n");
259 phy_type
= ixgb_phy_type_g6005
;
263 DEBUGOUT("Unknown physical layer module\n");
264 phy_type
= ixgb_phy_type_unknown
;
268 /* update phy type for sun specific board */
269 if (hw
->subsystem_vendor_id
== SUN_SUBVENDOR_ID
)
270 phy_type
= ixgb_phy_type_bcm
;
275 /******************************************************************************
276 * Performs basic configuration of the adapter.
278 * hw - Struct containing variables accessed by shared code
280 * Resets the controller.
281 * Reads and validates the EEPROM.
282 * Initializes the receive address registers.
283 * Initializes the multicast table.
284 * Clears all on-chip counters.
285 * Calls routine to setup flow control settings.
286 * Leaves the transmit and receive units disabled and uninitialized.
289 * true if successful,
290 * false if unrecoverable problems were encountered.
291 *****************************************************************************/
293 ixgb_init_hw(struct ixgb_hw
*hw
)
299 DEBUGFUNC("ixgb_init_hw");
301 /* Issue a global reset to the MAC. This will reset the chip's
302 * transmit, receive, DMA, and link units. It will not effect
303 * the current PCI configuration. The global reset bit is self-
304 * clearing, and should clear within a microsecond.
306 DEBUGOUT("Issuing a global reset to MAC\n");
308 ctrl_reg
= ixgb_mac_reset(hw
);
310 DEBUGOUT("Issuing an EE reset to MAC\n");
312 /* Workaround for 82597EX reset errata */
313 IXGB_WRITE_REG_IO(hw
, CTRL1
, IXGB_CTRL1_EE_RST
);
315 IXGB_WRITE_REG(hw
, CTRL1
, IXGB_CTRL1_EE_RST
);
318 /* Delay a few ms just to allow the reset to complete */
319 msleep(IXGB_DELAY_AFTER_EE_RESET
);
321 if (!ixgb_get_eeprom_data(hw
))
324 /* Use the device id to determine the type of phy/transceiver. */
325 hw
->device_id
= ixgb_get_ee_device_id(hw
);
326 hw
->phy_type
= ixgb_identify_phy(hw
);
328 /* Setup the receive addresses.
329 * Receive Address Registers (RARs 0 - 15).
331 ixgb_init_rx_addrs(hw
);
334 * Check that a valid MAC address has been set.
335 * If it is not valid, we fail hardware init.
337 if (!mac_addr_valid(hw
->curr_mac_addr
)) {
338 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
342 /* tell the routines in this file they can access hardware again */
343 hw
->adapter_stopped
= false;
345 /* Fill in the bus_info structure */
346 ixgb_get_bus_info(hw
);
348 /* Zero out the Multicast HASH table */
349 DEBUGOUT("Zeroing the MTA\n");
350 for (i
= 0; i
< IXGB_MC_TBL_SIZE
; i
++)
351 IXGB_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
353 /* Zero out the VLAN Filter Table Array */
356 /* Zero all of the hardware counters */
357 ixgb_clear_hw_cntrs(hw
);
359 /* Call a subroutine to setup flow control. */
360 status
= ixgb_setup_fc(hw
);
362 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
363 ixgb_check_for_link(hw
);
368 /******************************************************************************
369 * Initializes receive address filters.
371 * hw - Struct containing variables accessed by shared code
373 * Places the MAC address in receive address register 0 and clears the rest
374 * of the receive address registers. Clears the multicast table. Assumes
375 * the receiver is in reset when the routine is called.
376 *****************************************************************************/
378 ixgb_init_rx_addrs(struct ixgb_hw
*hw
)
382 DEBUGFUNC("ixgb_init_rx_addrs");
385 * If the current mac address is valid, assume it is a software override
386 * to the permanent address.
387 * Otherwise, use the permanent address from the eeprom.
389 if (!mac_addr_valid(hw
->curr_mac_addr
)) {
391 /* Get the MAC address from the eeprom for later reference */
392 ixgb_get_ee_mac_addr(hw
, hw
->curr_mac_addr
);
394 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
395 hw
->curr_mac_addr
[0],
396 hw
->curr_mac_addr
[1], hw
->curr_mac_addr
[2]);
397 DEBUGOUT3("%.2X %.2X %.2X\n",
398 hw
->curr_mac_addr
[3],
399 hw
->curr_mac_addr
[4], hw
->curr_mac_addr
[5]);
402 /* Setup the receive address. */
403 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
404 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
405 hw
->curr_mac_addr
[0],
406 hw
->curr_mac_addr
[1], hw
->curr_mac_addr
[2]);
407 DEBUGOUT3("%.2X %.2X %.2X\n",
408 hw
->curr_mac_addr
[3],
409 hw
->curr_mac_addr
[4], hw
->curr_mac_addr
[5]);
411 ixgb_rar_set(hw
, hw
->curr_mac_addr
, 0);
414 /* Zero out the other 15 receive addresses. */
415 DEBUGOUT("Clearing RAR[1-15]\n");
416 for (i
= 1; i
< IXGB_RAR_ENTRIES
; i
++) {
417 /* Write high reg first to disable the AV bit first */
418 IXGB_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
419 IXGB_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
425 /******************************************************************************
426 * Updates the MAC's list of multicast addresses.
428 * hw - Struct containing variables accessed by shared code
429 * mc_addr_list - the list of new multicast addresses
430 * mc_addr_count - number of addresses
431 * pad - number of bytes between addresses in the list
433 * The given list replaces any existing list. Clears the last 15 receive
434 * address registers and the multicast table. Uses receive address registers
435 * for the first 15 multicast addresses, and hashes the rest into the
437 *****************************************************************************/
439 ixgb_mc_addr_list_update(struct ixgb_hw
*hw
,
446 u32 rar_used_count
= 1; /* RAR[0] is used for our MAC address */
448 DEBUGFUNC("ixgb_mc_addr_list_update");
450 /* Set the new number of MC addresses that we are being requested to use. */
451 hw
->num_mc_addrs
= mc_addr_count
;
453 /* Clear RAR[1-15] */
454 DEBUGOUT(" Clearing RAR[1-15]\n");
455 for (i
= rar_used_count
; i
< IXGB_RAR_ENTRIES
; i
++) {
456 IXGB_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
457 IXGB_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
461 DEBUGOUT(" Clearing MTA\n");
462 for (i
= 0; i
< IXGB_MC_TBL_SIZE
; i
++)
463 IXGB_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
465 /* Add the new addresses */
466 for (i
= 0; i
< mc_addr_count
; i
++) {
467 DEBUGOUT(" Adding the multicast addresses:\n");
468 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i
,
469 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
)],
470 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
472 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
474 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
476 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
478 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
481 /* Place this multicast address in the RAR if there is room, *
482 * else put it in the MTA
484 if (rar_used_count
< IXGB_RAR_ENTRIES
) {
487 (i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
)),
489 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i
);
492 hash_value
= ixgb_hash_mc_addr(hw
,
495 (IXGB_ETH_LENGTH_OF_ADDRESS
498 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value
);
500 ixgb_mta_set(hw
, hash_value
);
504 DEBUGOUT("MC Update Complete\n");
508 /******************************************************************************
509 * Hashes an address to determine its location in the multicast table
511 * hw - Struct containing variables accessed by shared code
512 * mc_addr - the multicast address to hash
516 *****************************************************************************/
518 ixgb_hash_mc_addr(struct ixgb_hw
*hw
,
523 DEBUGFUNC("ixgb_hash_mc_addr");
525 /* The portion of the address that is used for the hash table is
526 * determined by the mc_filter_type setting.
528 switch (hw
->mc_filter_type
) {
529 /* [0] [1] [2] [3] [4] [5]
531 * LSB MSB - According to H/W docs */
533 /* [47:36] i.e. 0x563 for above example address */
535 ((mc_addr
[4] >> 4) | (((u16
) mc_addr
[5]) << 4));
537 case 1: /* [46:35] i.e. 0xAC6 for above example address */
539 ((mc_addr
[4] >> 3) | (((u16
) mc_addr
[5]) << 5));
541 case 2: /* [45:34] i.e. 0x5D8 for above example address */
543 ((mc_addr
[4] >> 2) | (((u16
) mc_addr
[5]) << 6));
545 case 3: /* [43:32] i.e. 0x634 for above example address */
546 hash_value
= ((mc_addr
[4]) | (((u16
) mc_addr
[5]) << 8));
549 /* Invalid mc_filter_type, what should we do? */
550 DEBUGOUT("MC filter type param set incorrectly\n");
559 /******************************************************************************
560 * Sets the bit in the multicast table corresponding to the hash value.
562 * hw - Struct containing variables accessed by shared code
563 * hash_value - Multicast address hash value
564 *****************************************************************************/
566 ixgb_mta_set(struct ixgb_hw
*hw
,
569 u32 hash_bit
, hash_reg
;
572 /* The MTA is a register array of 128 32-bit registers.
573 * It is treated like an array of 4096 bits. We want to set
574 * bit BitArray[hash_value]. So we figure out what register
575 * the bit is in, read it, OR in the new bit, then write
576 * back the new value. The register is determined by the
577 * upper 7 bits of the hash value and the bit within that
578 * register are determined by the lower 5 bits of the value.
580 hash_reg
= (hash_value
>> 5) & 0x7F;
581 hash_bit
= hash_value
& 0x1F;
583 mta_reg
= IXGB_READ_REG_ARRAY(hw
, MTA
, hash_reg
);
585 mta_reg
|= (1 << hash_bit
);
587 IXGB_WRITE_REG_ARRAY(hw
, MTA
, hash_reg
, mta_reg
);
592 /******************************************************************************
593 * Puts an ethernet address into a receive address register.
595 * hw - Struct containing variables accessed by shared code
596 * addr - Address to put into receive address register
597 * index - Receive address register to write
598 *****************************************************************************/
600 ixgb_rar_set(struct ixgb_hw
*hw
,
604 u32 rar_low
, rar_high
;
606 DEBUGFUNC("ixgb_rar_set");
608 /* HW expects these in little endian so we reverse the byte order
609 * from network order (big endian) to little endian
611 rar_low
= ((u32
) addr
[0] |
612 ((u32
)addr
[1] << 8) |
613 ((u32
)addr
[2] << 16) |
614 ((u32
)addr
[3] << 24));
616 rar_high
= ((u32
) addr
[4] |
617 ((u32
)addr
[5] << 8) |
620 IXGB_WRITE_REG_ARRAY(hw
, RA
, (index
<< 1), rar_low
);
621 IXGB_WRITE_REG_ARRAY(hw
, RA
, ((index
<< 1) + 1), rar_high
);
625 /******************************************************************************
626 * Writes a value to the specified offset in the VLAN filter table.
628 * hw - Struct containing variables accessed by shared code
629 * offset - Offset in VLAN filer table to write
630 * value - Value to write into VLAN filter table
631 *****************************************************************************/
633 ixgb_write_vfta(struct ixgb_hw
*hw
,
637 IXGB_WRITE_REG_ARRAY(hw
, VFTA
, offset
, value
);
641 /******************************************************************************
642 * Clears the VLAN filer table
644 * hw - Struct containing variables accessed by shared code
645 *****************************************************************************/
647 ixgb_clear_vfta(struct ixgb_hw
*hw
)
651 for (offset
= 0; offset
< IXGB_VLAN_FILTER_TBL_SIZE
; offset
++)
652 IXGB_WRITE_REG_ARRAY(hw
, VFTA
, offset
, 0);
656 /******************************************************************************
657 * Configures the flow control settings based on SW configuration.
659 * hw - Struct containing variables accessed by shared code
660 *****************************************************************************/
663 ixgb_setup_fc(struct ixgb_hw
*hw
)
666 u32 pap_reg
= 0; /* by default, assume no pause time */
669 DEBUGFUNC("ixgb_setup_fc");
671 /* Get the current control reg 0 settings */
672 ctrl_reg
= IXGB_READ_REG(hw
, CTRL0
);
674 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
675 ctrl_reg
&= ~(IXGB_CTRL0_RPE
| IXGB_CTRL0_TPE
);
677 /* The possible values of the "flow_control" parameter are:
678 * 0: Flow control is completely disabled
679 * 1: Rx flow control is enabled (we can receive pause frames
680 * but not send pause frames).
681 * 2: Tx flow control is enabled (we can send pause frames
682 * but we do not support receiving pause frames).
683 * 3: Both Rx and TX flow control (symmetric) are enabled.
686 switch (hw
->fc
.type
) {
687 case ixgb_fc_none
: /* 0 */
688 /* Set CMDC bit to disable Rx Flow control */
689 ctrl_reg
|= (IXGB_CTRL0_CMDC
);
691 case ixgb_fc_rx_pause
: /* 1 */
692 /* RX Flow control is enabled, and TX Flow control is
695 ctrl_reg
|= (IXGB_CTRL0_RPE
);
697 case ixgb_fc_tx_pause
: /* 2 */
698 /* TX Flow control is enabled, and RX Flow control is
699 * disabled, by a software over-ride.
701 ctrl_reg
|= (IXGB_CTRL0_TPE
);
702 pap_reg
= hw
->fc
.pause_time
;
704 case ixgb_fc_full
: /* 3 */
705 /* Flow control (both RX and TX) is enabled by a software
708 ctrl_reg
|= (IXGB_CTRL0_RPE
| IXGB_CTRL0_TPE
);
709 pap_reg
= hw
->fc
.pause_time
;
712 /* We should never get here. The value should be 0-3. */
713 DEBUGOUT("Flow control param set incorrectly\n");
718 /* Write the new settings */
719 IXGB_WRITE_REG(hw
, CTRL0
, ctrl_reg
);
722 IXGB_WRITE_REG(hw
, PAP
, pap_reg
);
724 /* Set the flow control receive threshold registers. Normally,
725 * these registers will be set to a default threshold that may be
726 * adjusted later by the driver's runtime code. However, if the
727 * ability to transmit pause frames in not enabled, then these
728 * registers will be set to 0.
730 if (!(hw
->fc
.type
& ixgb_fc_tx_pause
)) {
731 IXGB_WRITE_REG(hw
, FCRTL
, 0);
732 IXGB_WRITE_REG(hw
, FCRTH
, 0);
734 /* We need to set up the Receive Threshold high and low water
735 * marks as well as (optionally) enabling the transmission of XON
737 if (hw
->fc
.send_xon
) {
738 IXGB_WRITE_REG(hw
, FCRTL
,
739 (hw
->fc
.low_water
| IXGB_FCRTL_XONE
));
741 IXGB_WRITE_REG(hw
, FCRTL
, hw
->fc
.low_water
);
743 IXGB_WRITE_REG(hw
, FCRTH
, hw
->fc
.high_water
);
748 /******************************************************************************
749 * Reads a word from a device over the Management Data Interface (MDI) bus.
750 * This interface is used to manage Physical layer devices.
752 * hw - Struct containing variables accessed by hw code
753 * reg_address - Offset of device register being read.
754 * phy_address - Address of device on MDI.
756 * Returns: Data word (16 bits) from MDI device.
758 * The 82597EX has support for several MDI access methods. This routine
759 * uses the new protocol MDI Single Command and Address Operation.
760 * This requires that first an address cycle command is sent, followed by a
762 *****************************************************************************/
764 ixgb_read_phy_reg(struct ixgb_hw
*hw
,
773 ASSERT(reg_address
<= IXGB_MAX_PHY_REG_ADDRESS
);
774 ASSERT(phy_address
<= IXGB_MAX_PHY_ADDRESS
);
775 ASSERT(device_type
<= IXGB_MAX_PHY_DEV_TYPE
);
777 /* Setup and write the address cycle command */
778 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
779 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
780 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
781 (IXGB_MSCA_ADDR_CYCLE
| IXGB_MSCA_MDI_COMMAND
));
783 IXGB_WRITE_REG(hw
, MSCA
, command
);
785 /**************************************************************
786 ** Check every 10 usec to see if the address cycle completed
787 ** The COMMAND bit will clear when the operation is complete.
788 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
789 ** from the CPU Write to the Ready bit assertion.
790 **************************************************************/
792 for (i
= 0; i
< 10; i
++)
796 command
= IXGB_READ_REG(hw
, MSCA
);
798 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
802 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
804 /* Address cycle complete, setup and write the read command */
805 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
806 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
807 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
808 (IXGB_MSCA_READ
| IXGB_MSCA_MDI_COMMAND
));
810 IXGB_WRITE_REG(hw
, MSCA
, command
);
812 /**************************************************************
813 ** Check every 10 usec to see if the read command completed
814 ** The COMMAND bit will clear when the operation is complete.
815 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
816 ** from the CPU Write to the Ready bit assertion.
817 **************************************************************/
819 for (i
= 0; i
< 10; i
++)
823 command
= IXGB_READ_REG(hw
, MSCA
);
825 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
829 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
831 /* Operation is complete, get the data from the MDIO Read/Write Data
832 * register and return.
834 data
= IXGB_READ_REG(hw
, MSRWD
);
835 data
>>= IXGB_MSRWD_READ_DATA_SHIFT
;
839 /******************************************************************************
840 * Writes a word to a device over the Management Data Interface (MDI) bus.
841 * This interface is used to manage Physical layer devices.
843 * hw - Struct containing variables accessed by hw code
844 * reg_address - Offset of device register being read.
845 * phy_address - Address of device on MDI.
846 * device_type - Also known as the Device ID or DID.
847 * data - 16-bit value to be written
851 * The 82597EX has support for several MDI access methods. This routine
852 * uses the new protocol MDI Single Command and Address Operation.
853 * This requires that first an address cycle command is sent, followed by a
855 *****************************************************************************/
857 ixgb_write_phy_reg(struct ixgb_hw
*hw
,
866 ASSERT(reg_address
<= IXGB_MAX_PHY_REG_ADDRESS
);
867 ASSERT(phy_address
<= IXGB_MAX_PHY_ADDRESS
);
868 ASSERT(device_type
<= IXGB_MAX_PHY_DEV_TYPE
);
870 /* Put the data in the MDIO Read/Write Data register */
871 IXGB_WRITE_REG(hw
, MSRWD
, (u32
)data
);
873 /* Setup and write the address cycle command */
874 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
875 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
876 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
877 (IXGB_MSCA_ADDR_CYCLE
| IXGB_MSCA_MDI_COMMAND
));
879 IXGB_WRITE_REG(hw
, MSCA
, command
);
881 /**************************************************************
882 ** Check every 10 usec to see if the address cycle completed
883 ** The COMMAND bit will clear when the operation is complete.
884 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
885 ** from the CPU Write to the Ready bit assertion.
886 **************************************************************/
888 for (i
= 0; i
< 10; i
++)
892 command
= IXGB_READ_REG(hw
, MSCA
);
894 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
898 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
900 /* Address cycle complete, setup and write the write command */
901 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
902 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
903 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
904 (IXGB_MSCA_WRITE
| IXGB_MSCA_MDI_COMMAND
));
906 IXGB_WRITE_REG(hw
, MSCA
, command
);
908 /**************************************************************
909 ** Check every 10 usec to see if the read command completed
910 ** The COMMAND bit will clear when the operation is complete.
911 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
912 ** from the CPU Write to the Ready bit assertion.
913 **************************************************************/
915 for (i
= 0; i
< 10; i
++)
919 command
= IXGB_READ_REG(hw
, MSCA
);
921 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
925 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
927 /* Operation is complete, return. */
930 /******************************************************************************
931 * Checks to see if the link status of the hardware has changed.
933 * hw - Struct containing variables accessed by hw code
935 * Called by any function that needs to check the link status of the adapter.
936 *****************************************************************************/
938 ixgb_check_for_link(struct ixgb_hw
*hw
)
943 DEBUGFUNC("ixgb_check_for_link");
945 xpcss_reg
= IXGB_READ_REG(hw
, XPCSS
);
946 status_reg
= IXGB_READ_REG(hw
, STATUS
);
948 if ((xpcss_reg
& IXGB_XPCSS_ALIGN_STATUS
) &&
949 (status_reg
& IXGB_STATUS_LU
)) {
951 } else if (!(xpcss_reg
& IXGB_XPCSS_ALIGN_STATUS
) &&
952 (status_reg
& IXGB_STATUS_LU
)) {
953 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
954 hw
->link_up
= ixgb_link_reset(hw
);
957 * 82597EX errata. Since the lane deskew problem may prevent
958 * link, reset the link before reporting link down.
960 hw
->link_up
= ixgb_link_reset(hw
);
962 /* Anything else for 10 Gig?? */
965 /******************************************************************************
966 * Check for a bad link condition that may have occurred.
967 * The indication is that the RFC / LFC registers may be incrementing
968 * continually. A full adapter reset is required to recover.
970 * hw - Struct containing variables accessed by hw code
972 * Called by any function that needs to check the link status of the adapter.
973 *****************************************************************************/
974 bool ixgb_check_for_bad_link(struct ixgb_hw
*hw
)
977 bool bad_link_returncode
= false;
979 if (hw
->phy_type
== ixgb_phy_type_txn17401
) {
980 newLFC
= IXGB_READ_REG(hw
, LFC
);
981 newRFC
= IXGB_READ_REG(hw
, RFC
);
982 if ((hw
->lastLFC
+ 250 < newLFC
)
983 || (hw
->lastRFC
+ 250 < newRFC
)) {
985 ("BAD LINK! too many LFC/RFC since last check\n");
986 bad_link_returncode
= true;
988 hw
->lastLFC
= newLFC
;
989 hw
->lastRFC
= newRFC
;
992 return bad_link_returncode
;
995 /******************************************************************************
996 * Clears all hardware statistics counters.
998 * hw - Struct containing variables accessed by shared code
999 *****************************************************************************/
1001 ixgb_clear_hw_cntrs(struct ixgb_hw
*hw
)
1003 volatile u32 temp_reg
;
1005 DEBUGFUNC("ixgb_clear_hw_cntrs");
1007 /* if we are stopped or resetting exit gracefully */
1008 if (hw
->adapter_stopped
) {
1009 DEBUGOUT("Exiting because the adapter is stopped!!!\n");
1013 temp_reg
= IXGB_READ_REG(hw
, TPRL
);
1014 temp_reg
= IXGB_READ_REG(hw
, TPRH
);
1015 temp_reg
= IXGB_READ_REG(hw
, GPRCL
);
1016 temp_reg
= IXGB_READ_REG(hw
, GPRCH
);
1017 temp_reg
= IXGB_READ_REG(hw
, BPRCL
);
1018 temp_reg
= IXGB_READ_REG(hw
, BPRCH
);
1019 temp_reg
= IXGB_READ_REG(hw
, MPRCL
);
1020 temp_reg
= IXGB_READ_REG(hw
, MPRCH
);
1021 temp_reg
= IXGB_READ_REG(hw
, UPRCL
);
1022 temp_reg
= IXGB_READ_REG(hw
, UPRCH
);
1023 temp_reg
= IXGB_READ_REG(hw
, VPRCL
);
1024 temp_reg
= IXGB_READ_REG(hw
, VPRCH
);
1025 temp_reg
= IXGB_READ_REG(hw
, JPRCL
);
1026 temp_reg
= IXGB_READ_REG(hw
, JPRCH
);
1027 temp_reg
= IXGB_READ_REG(hw
, GORCL
);
1028 temp_reg
= IXGB_READ_REG(hw
, GORCH
);
1029 temp_reg
= IXGB_READ_REG(hw
, TORL
);
1030 temp_reg
= IXGB_READ_REG(hw
, TORH
);
1031 temp_reg
= IXGB_READ_REG(hw
, RNBC
);
1032 temp_reg
= IXGB_READ_REG(hw
, RUC
);
1033 temp_reg
= IXGB_READ_REG(hw
, ROC
);
1034 temp_reg
= IXGB_READ_REG(hw
, RLEC
);
1035 temp_reg
= IXGB_READ_REG(hw
, CRCERRS
);
1036 temp_reg
= IXGB_READ_REG(hw
, ICBC
);
1037 temp_reg
= IXGB_READ_REG(hw
, ECBC
);
1038 temp_reg
= IXGB_READ_REG(hw
, MPC
);
1039 temp_reg
= IXGB_READ_REG(hw
, TPTL
);
1040 temp_reg
= IXGB_READ_REG(hw
, TPTH
);
1041 temp_reg
= IXGB_READ_REG(hw
, GPTCL
);
1042 temp_reg
= IXGB_READ_REG(hw
, GPTCH
);
1043 temp_reg
= IXGB_READ_REG(hw
, BPTCL
);
1044 temp_reg
= IXGB_READ_REG(hw
, BPTCH
);
1045 temp_reg
= IXGB_READ_REG(hw
, MPTCL
);
1046 temp_reg
= IXGB_READ_REG(hw
, MPTCH
);
1047 temp_reg
= IXGB_READ_REG(hw
, UPTCL
);
1048 temp_reg
= IXGB_READ_REG(hw
, UPTCH
);
1049 temp_reg
= IXGB_READ_REG(hw
, VPTCL
);
1050 temp_reg
= IXGB_READ_REG(hw
, VPTCH
);
1051 temp_reg
= IXGB_READ_REG(hw
, JPTCL
);
1052 temp_reg
= IXGB_READ_REG(hw
, JPTCH
);
1053 temp_reg
= IXGB_READ_REG(hw
, GOTCL
);
1054 temp_reg
= IXGB_READ_REG(hw
, GOTCH
);
1055 temp_reg
= IXGB_READ_REG(hw
, TOTL
);
1056 temp_reg
= IXGB_READ_REG(hw
, TOTH
);
1057 temp_reg
= IXGB_READ_REG(hw
, DC
);
1058 temp_reg
= IXGB_READ_REG(hw
, PLT64C
);
1059 temp_reg
= IXGB_READ_REG(hw
, TSCTC
);
1060 temp_reg
= IXGB_READ_REG(hw
, TSCTFC
);
1061 temp_reg
= IXGB_READ_REG(hw
, IBIC
);
1062 temp_reg
= IXGB_READ_REG(hw
, RFC
);
1063 temp_reg
= IXGB_READ_REG(hw
, LFC
);
1064 temp_reg
= IXGB_READ_REG(hw
, PFRC
);
1065 temp_reg
= IXGB_READ_REG(hw
, PFTC
);
1066 temp_reg
= IXGB_READ_REG(hw
, MCFRC
);
1067 temp_reg
= IXGB_READ_REG(hw
, MCFTC
);
1068 temp_reg
= IXGB_READ_REG(hw
, XONRXC
);
1069 temp_reg
= IXGB_READ_REG(hw
, XONTXC
);
1070 temp_reg
= IXGB_READ_REG(hw
, XOFFRXC
);
1071 temp_reg
= IXGB_READ_REG(hw
, XOFFTXC
);
1072 temp_reg
= IXGB_READ_REG(hw
, RJC
);
1076 /******************************************************************************
1077 * Turns on the software controllable LED
1079 * hw - Struct containing variables accessed by shared code
1080 *****************************************************************************/
1082 ixgb_led_on(struct ixgb_hw
*hw
)
1084 u32 ctrl0_reg
= IXGB_READ_REG(hw
, CTRL0
);
1086 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1087 ctrl0_reg
&= ~IXGB_CTRL0_SDP0
;
1088 IXGB_WRITE_REG(hw
, CTRL0
, ctrl0_reg
);
1092 /******************************************************************************
1093 * Turns off the software controllable LED
1095 * hw - Struct containing variables accessed by shared code
1096 *****************************************************************************/
1098 ixgb_led_off(struct ixgb_hw
*hw
)
1100 u32 ctrl0_reg
= IXGB_READ_REG(hw
, CTRL0
);
1102 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1103 ctrl0_reg
|= IXGB_CTRL0_SDP0
;
1104 IXGB_WRITE_REG(hw
, CTRL0
, ctrl0_reg
);
1108 /******************************************************************************
1109 * Gets the current PCI bus type, speed, and width of the hardware
1111 * hw - Struct containing variables accessed by shared code
1112 *****************************************************************************/
1114 ixgb_get_bus_info(struct ixgb_hw
*hw
)
1118 status_reg
= IXGB_READ_REG(hw
, STATUS
);
1120 hw
->bus
.type
= (status_reg
& IXGB_STATUS_PCIX_MODE
) ?
1121 ixgb_bus_type_pcix
: ixgb_bus_type_pci
;
1123 if (hw
->bus
.type
== ixgb_bus_type_pci
) {
1124 hw
->bus
.speed
= (status_reg
& IXGB_STATUS_PCI_SPD
) ?
1125 ixgb_bus_speed_66
: ixgb_bus_speed_33
;
1127 switch (status_reg
& IXGB_STATUS_PCIX_SPD_MASK
) {
1128 case IXGB_STATUS_PCIX_SPD_66
:
1129 hw
->bus
.speed
= ixgb_bus_speed_66
;
1131 case IXGB_STATUS_PCIX_SPD_100
:
1132 hw
->bus
.speed
= ixgb_bus_speed_100
;
1134 case IXGB_STATUS_PCIX_SPD_133
:
1135 hw
->bus
.speed
= ixgb_bus_speed_133
;
1138 hw
->bus
.speed
= ixgb_bus_speed_reserved
;
1143 hw
->bus
.width
= (status_reg
& IXGB_STATUS_BUS64
) ?
1144 ixgb_bus_width_64
: ixgb_bus_width_32
;
1149 /******************************************************************************
1150 * Tests a MAC address to ensure it is a valid Individual Address
1152 * mac_addr - pointer to MAC address.
1154 *****************************************************************************/
1156 mac_addr_valid(u8
*mac_addr
)
1158 bool is_valid
= true;
1159 DEBUGFUNC("mac_addr_valid");
1161 /* Make sure it is not a multicast address */
1162 if (IS_MULTICAST(mac_addr
)) {
1163 DEBUGOUT("MAC address is multicast\n");
1166 /* Not a broadcast address */
1167 else if (IS_BROADCAST(mac_addr
)) {
1168 DEBUGOUT("MAC address is broadcast\n");
1171 /* Reject the zero address */
1172 else if (mac_addr
[0] == 0 &&
1178 DEBUGOUT("MAC address is all zeros\n");
1184 /******************************************************************************
1185 * Resets the 10GbE link. Waits the settle time and returns the state of
1188 * hw - Struct containing variables accessed by shared code
1189 *****************************************************************************/
1191 ixgb_link_reset(struct ixgb_hw
*hw
)
1193 bool link_status
= false;
1194 u8 wait_retries
= MAX_RESET_ITERATIONS
;
1195 u8 lrst_retries
= MAX_RESET_ITERATIONS
;
1198 /* Reset the link */
1199 IXGB_WRITE_REG(hw
, CTRL0
,
1200 IXGB_READ_REG(hw
, CTRL0
) | IXGB_CTRL0_LRST
);
1202 /* Wait for link-up and lane re-alignment */
1204 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET
);
1206 ((IXGB_READ_REG(hw
, STATUS
) & IXGB_STATUS_LU
)
1207 && (IXGB_READ_REG(hw
, XPCSS
) &
1208 IXGB_XPCSS_ALIGN_STATUS
)) ? true : false;
1209 } while (!link_status
&& --wait_retries
);
1211 } while (!link_status
&& --lrst_retries
);
1216 /******************************************************************************
1217 * Resets the 10GbE optics module.
1219 * hw - Struct containing variables accessed by shared code
1220 *****************************************************************************/
1222 ixgb_optics_reset(struct ixgb_hw
*hw
)
1224 if (hw
->phy_type
== ixgb_phy_type_txn17401
) {
1227 ixgb_write_phy_reg(hw
,
1231 MDIO_PMA_PMD_CR1_RESET
);
1233 mdio_reg
= ixgb_read_phy_reg( hw
,
1242 /******************************************************************************
1243 * Resets the 10GbE optics module for Sun variant NIC.
1245 * hw - Struct containing variables accessed by shared code
1246 *****************************************************************************/
1248 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
1249 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
1250 #define IXGB_BCM8704_USER_CTRL_REG 0xC800
1251 #define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
1252 #define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
1253 #define IXGB_SUN_PHY_ADDRESS 0x0000
1254 #define IXGB_SUN_PHY_RESET_DELAY 305
1257 ixgb_optics_reset_bcm(struct ixgb_hw
*hw
)
1259 u32 ctrl
= IXGB_READ_REG(hw
, CTRL0
);
1260 ctrl
&= ~IXGB_CTRL0_SDP2
;
1261 ctrl
|= IXGB_CTRL0_SDP3
;
1262 IXGB_WRITE_REG(hw
, CTRL0
, ctrl
);
1264 /* SerDes needs extra delay */
1265 msleep(IXGB_SUN_PHY_RESET_DELAY
);
1267 /* Broadcom 7408L configuration */
1268 /* Reference clock config */
1269 ixgb_write_phy_reg(hw
,
1270 IXGB_BCM8704_USER_PMD_TX_CTRL_REG
,
1271 IXGB_SUN_PHY_ADDRESS
,
1272 IXGB_BCM8704_USER_DEV3_ADDR
,
1273 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL
);
1274 /* we must read the registers twice */
1275 ixgb_read_phy_reg(hw
,
1276 IXGB_BCM8704_USER_PMD_TX_CTRL_REG
,
1277 IXGB_SUN_PHY_ADDRESS
,
1278 IXGB_BCM8704_USER_DEV3_ADDR
);
1279 ixgb_read_phy_reg(hw
,
1280 IXGB_BCM8704_USER_PMD_TX_CTRL_REG
,
1281 IXGB_SUN_PHY_ADDRESS
,
1282 IXGB_BCM8704_USER_DEV3_ADDR
);
1284 ixgb_write_phy_reg(hw
,
1285 IXGB_BCM8704_USER_CTRL_REG
,
1286 IXGB_SUN_PHY_ADDRESS
,
1287 IXGB_BCM8704_USER_DEV3_ADDR
,
1288 IXGB_BCM8704_USER_CTRL_REG_VAL
);
1289 ixgb_read_phy_reg(hw
,
1290 IXGB_BCM8704_USER_CTRL_REG
,
1291 IXGB_SUN_PHY_ADDRESS
,
1292 IXGB_BCM8704_USER_DEV3_ADDR
);
1293 ixgb_read_phy_reg(hw
,
1294 IXGB_BCM8704_USER_CTRL_REG
,
1295 IXGB_SUN_PHY_ADDRESS
,
1296 IXGB_BCM8704_USER_DEV3_ADDR
);
1298 /* SerDes needs extra delay */
1299 msleep(IXGB_SUN_PHY_RESET_DELAY
);