arch/x86/kernel/cpu/amd.c

   1 #include <linux/init.h>
   2 #include <linux/bitops.h>
   3 #include <linux/mm.h>
   4
   5 #include <asm/io.h>
   6 #include <asm/processor.h>
   7 #include <asm/apic.h>
   8
   9 #ifdef CONFIG_X86_64
  10 # include <asm/numa_64.h>
  11 # include <asm/mmconfig.h>
  12 # include <asm/cacheflush.h>
  13 #endif
  14
  15 #include <mach_apic.h>
  16
  17 #include "cpu.h"
  18
  19 #ifdef CONFIG_X86_32
  20 /*
  21  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
  22  *      misexecution of code under Linux. Owners of such processors should
  23  *      contact AMD for precise details and a CPU swap.
  24  *
  25  *      See     http://www.multimania.com/poulot/k6bug.html
  26  *              http://www.amd.com/K6/k6docs/revgd.html
  27  *
  28  *      The following test is erm.. interesting. AMD neglected to up
  29  *      the chip setting when fixing the bug but they also tweaked some
  30  *      performance at the same time..
  31  */
  32
  33 extern void vide(void);
  34 __asm__(".align 4\nvide: ret");
  35
  36 static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
  37 {
  38 /*
  39  * General Systems BIOSen alias the cpu frequency registers
  40  * of the Elan at 0x000df000. Unfortuantly, one of the Linux
  41  * drivers subsequently pokes it, and changes the CPU speed.
  42  * Workaround : Remove the unneeded alias.
  43  */
  44 #define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
  45 #define CBAR_ENB        (0x80000000)
  46 #define CBAR_KEY        (0X000000CB)
  47         if (c->x86_model == 9 || c->x86_model == 10) {
  48                 if (inl (CBAR) & CBAR_ENB)
  49                         outl (0 | CBAR_KEY, CBAR);
  50         }
  51 }
  52
  53
  54 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
  55 {
  56         u32 l, h;
  57         int mbytes = num_physpages >> (20-PAGE_SHIFT);
  58
  59         if (c->x86_model < 6) {
  60                 /* Based on AMD doc 20734R - June 2000 */
  61                 if (c->x86_model == 0) {
  62                         clear_cpu_cap(c, X86_FEATURE_APIC);
  63                         set_cpu_cap(c, X86_FEATURE_PGE);
  64                 }
  65                 return;
  66         }
  67
  68         if (c->x86_model == 6 && c->x86_mask == 1) {
  69                 const int K6_BUG_LOOP = 1000000;
  70                 int n;
  71                 void (*f_vide)(void);
  72                 unsigned long d, d2;
  73
  74                 printk(KERN_INFO "AMD K6 stepping B detected - ");
  75
  76                 /*
  77                  * It looks like AMD fixed the 2.6.2 bug and improved indirect
  78                  * calls at the same time.
  79                  */
  80
  81                 n = K6_BUG_LOOP;
  82                 f_vide = vide;
  83                 rdtscl(d);
  84                 while (n--)
  85                         f_vide();
  86                 rdtscl(d2);
  87                 d = d2-d;
  88
  89                 if (d > 20*K6_BUG_LOOP)
  90                         printk("system stability may be impaired when more than 32 MB are used.\n");
  91                 else
  92                         printk("probably OK (after B9730xxxx).\n");
  93                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
  94         }
  95
  96         /* K6 with old style WHCR */
  97         if (c->x86_model < 8 ||
  98            (c->x86_model == 8 && c->x86_mask < 8)) {
  99                 /* We can only write allocate on the low 508Mb */
 100                 if (mbytes > 508)
 101                         mbytes = 508;
 102
 103                 rdmsr(MSR_K6_WHCR, l, h);
 104                 if ((l&0x0000FFFF) == 0) {
 105                         unsigned long flags;
 106                         l = (1<<0)|((mbytes/4)<<1);
 107                         local_irq_save(flags);
 108                         wbinvd();
 109                         wrmsr(MSR_K6_WHCR, l, h);
 110                         local_irq_restore(flags);
 111                         printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
 112                                 mbytes);
 113                 }
 114                 return;
 115         }
 116
 117         if ((c->x86_model == 8 && c->x86_mask > 7) ||
 118              c->x86_model == 9 || c->x86_model == 13) {
 119                 /* The more serious chips .. */
 120
 121                 if (mbytes > 4092)
 122                         mbytes = 4092;
 123
 124                 rdmsr(MSR_K6_WHCR, l, h);
 125                 if ((l&0xFFFF0000) == 0) {
 126                         unsigned long flags;
 127                         l = ((mbytes>>2)<<22)|(1<<16);
 128                         local_irq_save(flags);
 129                         wbinvd();
 130                         wrmsr(MSR_K6_WHCR, l, h);
 131                         local_irq_restore(flags);
 132                         printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
 133                                 mbytes);
 134                 }
 135
 136                 return;
 137         }
 138
 139         if (c->x86_model == 10) {
 140                 /* AMD Geode LX is model 10 */
 141                 /* placeholder for any needed mods */
 142                 return;
 143         }
 144 }
 145
 146 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
 147 {
 148         u32 l, h;
 149
 150         /*
 151          * Bit 15 of Athlon specific MSR 15, needs to be 0
 152          * to enable SSE on Palomino/Morgan/Barton CPU's.
 153          * If the BIOS didn't enable it already, enable it here.
 154          */
 155         if (c->x86_model >= 6 && c->x86_model <= 10) {
 156                 if (!cpu_has(c, X86_FEATURE_XMM)) {
 157                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
 158                         rdmsr(MSR_K7_HWCR, l, h);
 159                         l &= ~0x00008000;
 160                         wrmsr(MSR_K7_HWCR, l, h);
 161                         set_cpu_cap(c, X86_FEATURE_XMM);
 162                 }
 163         }
 164
 165         /*
 166          * It's been determined by AMD that Athlons since model 8 stepping 1
 167          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
 168          * As per AMD technical note 27212 0.2
 169          */
 170         if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
 171                 rdmsr(MSR_K7_CLK_CTL, l, h);
 172                 if ((l & 0xfff00000) != 0x20000000) {
 173                         printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
 174                                 ((l & 0x000fffff)|0x20000000));
 175                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
 176                 }
 177         }
 178
 179         set_cpu_cap(c, X86_FEATURE_K7);
 180 }
 181 #endif
 182
 183 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 184 static int __cpuinit nearby_node(int apicid)
 185 {
 186         int i, node;
 187
 188         for (i = apicid - 1; i >= 0; i--) {
 189                 node = apicid_to_node[i];
 190                 if (node != NUMA_NO_NODE && node_online(node))
 191                         return node;
 192         }
 193         for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
 194                 node = apicid_to_node[i];
 195                 if (node != NUMA_NO_NODE && node_online(node))
 196                         return node;
 197         }
 198         return first_node(node_online_map); /* Shouldn't happen */
 199 }
 200 #endif
 201
 202 /*
 203  * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
 204  * Assumes number of cores is a power of two.
 205  */
 206 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
 207 {
 208 #ifdef CONFIG_X86_HT
 209         unsigned bits;
 210         int cpu = smp_processor_id();
 211
 212         bits = c->x86_coreid_bits;
 213         /* Low order bits define the core id (index of core in socket) */
 214         c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
 215         /* Convert the initial APIC ID into the socket ID */
 216         c->phys_proc_id = c->initial_apicid >> bits;
 217         /* use socket ID also for last level cache */
 218         per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
 219 #endif
 220 }
 221
 222 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
 223 {
 224 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 225         int cpu = smp_processor_id();
 226         int node;
 227         unsigned apicid = hard_smp_processor_id();
 228
 229         node = c->phys_proc_id;
 230         if (apicid_to_node[apicid] != NUMA_NO_NODE)
 231                 node = apicid_to_node[apicid];
 232         if (!node_online(node)) {
 233                 /* Two possibilities here:
 234                    - The CPU is missing memory and no node was created.
 235                    In that case try picking one from a nearby CPU
 236                    - The APIC IDs differ from the HyperTransport node IDs
 237                    which the K8 northbridge parsing fills in.
 238                    Assume they are all increased by a constant offset,
 239                    but in the same order as the HT nodeids.
 240                    If that doesn't result in a usable node fall back to the
 241                    path for the previous case.  */
 242
 243                 int ht_nodeid = c->initial_apicid;
 244
 245                 if (ht_nodeid >= 0 &&
 246                     apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
 247                         node = apicid_to_node[ht_nodeid];
 248                 /* Pick a nearby node */
 249                 if (!node_online(node))
 250                         node = nearby_node(apicid);
 251         }
 252         numa_set_node(cpu, node);
 253
 254         printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
 255 #endif
 256 }
 257
 258 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
 259 {
 260 #ifdef CONFIG_X86_HT
 261         unsigned bits, ecx;
 262
 263         /* Multi core CPU? */
 264         if (c->extended_cpuid_level < 0x80000008)
 265                 return;
 266
 267         ecx = cpuid_ecx(0x80000008);
 268
 269         c->x86_max_cores = (ecx & 0xff) + 1;
 270
 271         /* CPU telling us the core id bits shift? */
 272         bits = (ecx >> 12) & 0xF;
 273
 274         /* Otherwise recompute */
 275         if (bits == 0) {
 276                 while ((1 << bits) < c->x86_max_cores)
 277                         bits++;
 278         }
 279
 280         c->x86_coreid_bits = bits;
 281 #endif
 282 }
 283
 284 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 285 {
 286         early_init_amd_mc(c);
 287
 288         /*
 289          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
 290          * with P/T states and does not stop in deep C-states
 291          */
 292         if (c->x86_power & (1 << 8)) {
 293                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 294                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 295         }
 296
 297 #ifdef CONFIG_X86_64
 298         set_cpu_cap(c, X86_FEATURE_SYSCALL32);
 299 #else
 300         /*  Set MTRR capability flag if appropriate */
 301         if (c->x86 == 5)
 302                 if (c->x86_model == 13 || c->x86_model == 9 ||
 303                     (c->x86_model == 8 && c->x86_mask >= 8))
 304                         set_cpu_cap(c, X86_FEATURE_K6_MTRR);
 305 #endif
 306 }
 307
 308 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 309 {
 310 #ifdef CONFIG_SMP
 311         unsigned long long value;
 312
 313         /*
 314          * Disable TLB flush filter by setting HWCR.FFDIS on K8
 315          * bit 6 of msr C001_0015
 316          *
 317          * Errata 63 for SH-B3 steppings
 318          * Errata 122 for all steppings (F+ have it disabled by default)
 319          */
 320         if (c->x86 == 0xf) {
 321                 rdmsrl(MSR_K7_HWCR, value);
 322                 value |= 1 << 6;
 323                 wrmsrl(MSR_K7_HWCR, value);
 324         }
 325 #endif
 326
 327         early_init_amd(c);
 328
 329         /*
 330          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 331          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
 332          */
 333         clear_cpu_cap(c, 0*32+31);
 334
 335 #ifdef CONFIG_X86_64
 336         /* On C+ stepping K8 rep microcode works well for copy/memset */
 337         if (c->x86 == 0xf) {
 338                 u32 level;
 339
 340                 level = cpuid_eax(1);
 341                 if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
 342                         set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 343         }
 344         if (c->x86 == 0x10 || c->x86 == 0x11)
 345                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 346 #else
 347
 348         /*
 349          *      FIXME: We should handle the K5 here. Set up the write
 350          *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
 351          *      no bus pipeline)
 352          */
 353
 354         switch (c->x86) {
 355         case 4:
 356                 init_amd_k5(c);
 357                 break;
 358         case 5:
 359                 init_amd_k6(c);
 360                 break;
 361         case 6: /* An Athlon/Duron */
 362                 init_amd_k7(c);
 363                 break;
 364         }
 365
 366         /* K6s reports MCEs but don't actually have all the MSRs */
 367         if (c->x86 < 6)
 368                 clear_cpu_cap(c, X86_FEATURE_MCE);
 369 #endif
 370
 371         /* Enable workaround for FXSAVE leak */
 372         if (c->x86 >= 6)
 373                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
 374
 375         if (!c->x86_model_id[0]) {
 376                 switch (c->x86) {
 377                 case 0xf:
 378                         /* Should distinguish Models here, but this is only
 379                            a fallback anyways. */
 380                         strcpy(c->x86_model_id, "Hammer");
 381                         break;
 382                 }
 383         }
 384
 385         display_cacheinfo(c);
 386
 387         /* Multi core CPU? */
 388         if (c->extended_cpuid_level >= 0x80000008) {
 389                 amd_detect_cmp(c);
 390                 srat_detect_node(c);
 391         }
 392
 393 #ifdef CONFIG_X86_32
 394         detect_ht(c);
 395 #endif
 396
 397         if (c->extended_cpuid_level >= 0x80000006) {
 398                 if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
 399                         num_cache_leaves = 4;
 400                 else
 401                         num_cache_leaves = 3;
 402         }
 403
 404         if (c->x86 >= 0xf && c->x86 <= 0x11)
 405                 set_cpu_cap(c, X86_FEATURE_K8);
 406
 407         if (cpu_has_xmm2) {
 408                 /* MFENCE stops RDTSC speculation */
 409                 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 410         }
 411
 412 #ifdef CONFIG_X86_64
 413         if (c->x86 == 0x10) {
 414                 /* do this for boot cpu */
 415                 if (c == &boot_cpu_data)
 416                         check_enable_amd_mmconf_dmi();
 417
 418                 fam10h_check_enable_mmcfg();
 419         }
 420
 421         if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
 422                 unsigned long long tseg;
 423
 424                 /*
 425                  * Split up direct mapping around the TSEG SMM area.
 426                  * Don't do it for gbpages because there seems very little
 427                  * benefit in doing so.
 428                  */
 429                 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
 430                     printk(KERN_DEBUG "tseg: %010llx\n", tseg);
 431                     if ((tseg>>PMD_SHIFT) <
 432                                 (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
 433                         ((tseg>>PMD_SHIFT) <
 434                                 (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
 435                          (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
 436                         set_memory_4k((unsigned long)__va(tseg), 1);
 437                 }
 438         }
 439 #endif
 440 }
 441
 442 #ifdef CONFIG_X86_32
 443 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 444 {
 445         /* AMD errata T13 (order #21922) */
 446         if ((c->x86 == 6)) {
 447                 if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
 448                         size = 64;
 449                 if (c->x86_model == 4 &&
 450                     (c->x86_mask == 0 || c->x86_mask == 1))     /* Tbird rev A1/A2 */
 451                         size = 256;
 452         }
 453         return size;
 454 }
 455 #endif
 456
 457 static struct cpu_dev amd_cpu_dev __cpuinitdata = {
 458         .c_vendor       = "AMD",
 459         .c_ident        = { "AuthenticAMD" },
 460 #ifdef CONFIG_X86_32
 461         .c_models = {
 462                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
 463                   {
 464                           [3] = "486 DX/2",
 465                           [7] = "486 DX/2-WB",
 466                           [8] = "486 DX/4",
 467                           [9] = "486 DX/4-WB",
 468                           [14] = "Am5x86-WT",
 469                           [15] = "Am5x86-WB"
 470                   }
 471                 },
 472         },
 473         .c_size_cache   = amd_size_cache,
 474 #endif
 475         .c_early_init   = early_init_amd,
 476         .c_init         = init_amd,
 477         .c_x86_vendor   = X86_VENDOR_AMD,
 478 };
 479
 480 cpu_dev_register(amd_cpu_dev);