1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
13 #include <asm/mmu_context.h>
16 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/mpspec.h>
19 #include <mach_apic.h>
24 DEFINE_PER_CPU(struct gdt_page
, gdt_page
) = { .gdt
= {
25 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00cf9a00 } } },
26 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9200 } } },
27 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00cffa00 } } },
28 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff200 } } },
30 * Segments used for calling PnP BIOS have byte granularity.
31 * They code segments and data segments have fixed 64k limits,
32 * the transfer segment sizes are set at run time.
35 [GDT_ENTRY_PNPBIOS_CS32
] = { { { 0x0000ffff, 0x00409a00 } } },
37 [GDT_ENTRY_PNPBIOS_CS16
] = { { { 0x0000ffff, 0x00009a00 } } },
39 [GDT_ENTRY_PNPBIOS_DS
] = { { { 0x0000ffff, 0x00009200 } } },
41 [GDT_ENTRY_PNPBIOS_TS1
] = { { { 0x00000000, 0x00009200 } } },
43 [GDT_ENTRY_PNPBIOS_TS2
] = { { { 0x00000000, 0x00009200 } } },
45 * The APM segments have byte granularity and their bases
46 * are set at run time. All have 64k limits.
49 [GDT_ENTRY_APMBIOS_BASE
] = { { { 0x0000ffff, 0x00409a00 } } },
51 [GDT_ENTRY_APMBIOS_BASE
+1] = { { { 0x0000ffff, 0x00009a00 } } },
53 [GDT_ENTRY_APMBIOS_BASE
+2] = { { { 0x0000ffff, 0x00409200 } } },
55 [GDT_ENTRY_ESPFIX_SS
] = { { { 0x00000000, 0x00c09200 } } },
56 [GDT_ENTRY_PERCPU
] = { { { 0x00000000, 0x00000000 } } },
58 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
60 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
62 static int cachesize_override __cpuinitdata
= -1;
63 static int disable_x86_serial_nr __cpuinitdata
= 1;
65 struct cpu_dev
* cpu_devs
[X86_VENDOR_NUM
] = {};
67 static void __cpuinit
default_init(struct cpuinfo_x86
* c
)
69 /* Not much we can do here... */
70 /* Check if at least it has cpuid */
71 if (c
->cpuid_level
== -1) {
72 /* No cpuid. It must be an ancient CPU */
74 strcpy(c
->x86_model_id
, "486");
76 strcpy(c
->x86_model_id
, "386");
80 static struct cpu_dev __cpuinitdata default_cpu
= {
81 .c_init
= default_init
,
82 .c_vendor
= "Unknown",
84 static struct cpu_dev
* this_cpu __cpuinitdata
= &default_cpu
;
86 static int __init
cachesize_setup(char *str
)
88 get_option (&str
, &cachesize_override
);
91 __setup("cachesize=", cachesize_setup
);
93 int __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
98 if (cpuid_eax(0x80000000) < 0x80000004)
101 v
= (unsigned int *) c
->x86_model_id
;
102 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
103 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
104 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
105 c
->x86_model_id
[48] = 0;
107 /* Intel chips right-justify this string for some dumb reason;
108 undo that brain damage */
109 p
= q
= &c
->x86_model_id
[0];
115 while ( q
<= &c
->x86_model_id
[48] )
116 *q
++ = '\0'; /* Zero-pad the rest */
123 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
125 unsigned int n
, dummy
, ecx
, edx
, l2size
;
127 n
= cpuid_eax(0x80000000);
129 if (n
>= 0x80000005) {
130 cpuid(0x80000005, &dummy
, &dummy
, &ecx
, &edx
);
131 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
132 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
133 c
->x86_cache_size
=(ecx
>>24)+(edx
>>24);
136 if (n
< 0x80000006) /* Some chips just has a large L1. */
139 ecx
= cpuid_ecx(0x80000006);
142 /* do processor-specific cache resizing */
143 if (this_cpu
->c_size_cache
)
144 l2size
= this_cpu
->c_size_cache(c
,l2size
);
146 /* Allow user to override all this if necessary. */
147 if (cachesize_override
!= -1)
148 l2size
= cachesize_override
;
151 return; /* Again, no L2 cache is possible */
153 c
->x86_cache_size
= l2size
;
155 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
159 /* Naming convention should be: <Name> [(<Codename>)] */
160 /* This table only is used unless init_<vendor>() below doesn't set it; */
161 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
163 /* Look up CPU names by table lookup. */
164 static char __cpuinit
*table_lookup_model(struct cpuinfo_x86
*c
)
166 struct cpu_model_info
*info
;
168 if ( c
->x86_model
>= 16 )
169 return NULL
; /* Range check */
174 info
= this_cpu
->c_models
;
176 while (info
&& info
->family
) {
177 if (info
->family
== c
->x86
)
178 return info
->model_names
[c
->x86_model
];
181 return NULL
; /* Not found */
185 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
, int early
)
187 char *v
= c
->x86_vendor_id
;
191 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
193 if (!strcmp(v
,cpu_devs
[i
]->c_ident
[0]) ||
194 (cpu_devs
[i
]->c_ident
[1] &&
195 !strcmp(v
,cpu_devs
[i
]->c_ident
[1]))) {
198 this_cpu
= cpu_devs
[i
];
205 printk(KERN_ERR
"CPU: Vendor unknown, using generic init.\n");
206 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
208 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
209 this_cpu
= &default_cpu
;
213 static int __init
x86_fxsr_setup(char * s
)
215 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
216 setup_clear_cpu_cap(X86_FEATURE_XMM
);
219 __setup("nofxsr", x86_fxsr_setup
);
222 static int __init
x86_sep_setup(char * s
)
224 setup_clear_cpu_cap(X86_FEATURE_SEP
);
227 __setup("nosep", x86_sep_setup
);
230 /* Standard macro to see if a specific flag is changeable */
231 static inline int flag_is_changeable_p(u32 flag
)
245 : "=&r" (f1
), "=&r" (f2
)
248 return ((f1
^f2
) & flag
) != 0;
252 /* Probe for the CPUID instruction */
253 static int __cpuinit
have_cpuid_p(void)
255 return flag_is_changeable_p(X86_EFLAGS_ID
);
258 void __init
cpu_detect(struct cpuinfo_x86
*c
)
260 /* Get vendor name */
261 cpuid(0x00000000, &c
->cpuid_level
,
262 (int *)&c
->x86_vendor_id
[0],
263 (int *)&c
->x86_vendor_id
[8],
264 (int *)&c
->x86_vendor_id
[4]);
267 if (c
->cpuid_level
>= 0x00000001) {
268 u32 junk
, tfms
, cap0
, misc
;
269 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
270 c
->x86
= (tfms
>> 8) & 15;
271 c
->x86_model
= (tfms
>> 4) & 15;
273 c
->x86
+= (tfms
>> 20) & 0xff;
275 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
276 c
->x86_mask
= tfms
& 15;
278 c
->x86_cache_alignment
= ((misc
>> 8) & 0xff) * 8;
282 /* Do minimum CPU detection early.
283 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
284 The others are not touched to avoid unwanted side effects.
286 WARNING: this function is only called on the BP. Don't add code here
287 that is supposed to run on all CPUs. */
288 static void __init
early_cpu_detect(void)
290 struct cpuinfo_x86
*c
= &boot_cpu_data
;
292 c
->x86_cache_alignment
= 32;
299 get_cpu_vendor(c
, 1);
301 switch (c
->x86_vendor
) {
305 case X86_VENDOR_INTEL
:
311 static void __cpuinit
generic_identify(struct cpuinfo_x86
* c
)
316 if (have_cpuid_p()) {
317 /* Get vendor name */
318 cpuid(0x00000000, &c
->cpuid_level
,
319 (int *)&c
->x86_vendor_id
[0],
320 (int *)&c
->x86_vendor_id
[8],
321 (int *)&c
->x86_vendor_id
[4]);
323 get_cpu_vendor(c
, 0);
324 /* Initialize the standard set of capabilities */
325 /* Note that the vendor-specific code below might override */
327 /* Intel-defined flags: level 0x00000001 */
328 if ( c
->cpuid_level
>= 0x00000001 ) {
329 u32 capability
, excap
;
330 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
331 c
->x86_capability
[0] = capability
;
332 c
->x86_capability
[4] = excap
;
333 c
->x86
= (tfms
>> 8) & 15;
334 c
->x86_model
= (tfms
>> 4) & 15;
336 c
->x86
+= (tfms
>> 20) & 0xff;
338 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
339 c
->x86_mask
= tfms
& 15;
341 c
->apicid
= phys_pkg_id((ebx
>> 24) & 0xFF, 0);
343 c
->apicid
= (ebx
>> 24) & 0xFF;
345 if (c
->x86_capability
[0] & (1<<19))
346 c
->x86_clflush_size
= ((ebx
>> 8) & 0xff) * 8;
348 /* Have CPUID level 0 only - unheard of */
352 /* AMD-defined flags: level 0x80000001 */
353 xlvl
= cpuid_eax(0x80000000);
354 if ( (xlvl
& 0xffff0000) == 0x80000000 ) {
355 if ( xlvl
>= 0x80000001 ) {
356 c
->x86_capability
[1] = cpuid_edx(0x80000001);
357 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
359 if ( xlvl
>= 0x80000004 )
360 get_model_name(c
); /* Default name */
363 init_scattered_cpuid_features(c
);
367 c
->phys_proc_id
= (cpuid_ebx(1) >> 24) & 0xff;
371 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
373 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
374 /* Disable processor serial number */
376 rdmsr(MSR_IA32_BBL_CR_CTL
,lo
,hi
);
378 wrmsr(MSR_IA32_BBL_CR_CTL
,lo
,hi
);
379 printk(KERN_NOTICE
"CPU serial number disabled.\n");
380 clear_bit(X86_FEATURE_PN
, c
->x86_capability
);
382 /* Disabling the serial number may affect the cpuid level */
383 c
->cpuid_level
= cpuid_eax(0);
387 static int __init
x86_serial_nr_setup(char *s
)
389 disable_x86_serial_nr
= 0;
392 __setup("serialnumber", x86_serial_nr_setup
);
397 * This does the hard work of actually picking apart the CPU stuff...
399 void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
403 c
->loops_per_jiffy
= loops_per_jiffy
;
404 c
->x86_cache_size
= -1;
405 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
406 c
->cpuid_level
= -1; /* CPUID not detected */
407 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
408 c
->x86_vendor_id
[0] = '\0'; /* Unset */
409 c
->x86_model_id
[0] = '\0'; /* Unset */
410 c
->x86_max_cores
= 1;
411 c
->x86_clflush_size
= 32;
412 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
414 if (!have_cpuid_p()) {
415 /* First of all, decide if this is a 486 or higher */
416 /* It's a 486 if we can modify the AC flag */
417 if ( flag_is_changeable_p(X86_EFLAGS_AC
) )
425 if (this_cpu
->c_identify
)
426 this_cpu
->c_identify(c
);
429 * Vendor-specific initialization. In this section we
430 * canonicalize the feature flags, meaning if there are
431 * features a certain CPU supports which CPUID doesn't
432 * tell us, CPUID claiming incorrect flags, or other bugs,
433 * we handle them here.
435 * At the end of this section, c->x86_capability better
436 * indicate the features this CPU genuinely supports!
438 if (this_cpu
->c_init
)
441 /* Disable the PN if appropriate */
442 squash_the_stupid_serial_number(c
);
445 * The vendor-specific functions might have changed features. Now
446 * we do "generic changes."
451 clear_bit(X86_FEATURE_TSC
, c
->x86_capability
);
453 /* If the model name is still unset, do table lookup. */
454 if ( !c
->x86_model_id
[0] ) {
456 p
= table_lookup_model(c
);
458 strcpy(c
->x86_model_id
, p
);
461 sprintf(c
->x86_model_id
, "%02x/%02x",
462 c
->x86
, c
->x86_model
);
466 * On SMP, boot_cpu_data holds the common feature set between
467 * all CPUs; so make sure that we indicate which features are
468 * common between the CPUs. The first time this routine gets
469 * executed, c == &boot_cpu_data.
471 if ( c
!= &boot_cpu_data
) {
472 /* AND the already accumulated flags with these */
473 for ( i
= 0 ; i
< NCAPINTS
; i
++ )
474 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
477 /* Clear all flags overriden by options */
478 for (i
= 0; i
< NCAPINTS
; i
++)
479 c
->x86_capability
[i
] ^= cleared_cpu_caps
[i
];
481 /* Init Machine Check Exception if available. */
484 select_idle_routine(c
);
487 void __init
identify_boot_cpu(void)
489 identify_cpu(&boot_cpu_data
);
495 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
497 BUG_ON(c
== &boot_cpu_data
);
504 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
506 u32 eax
, ebx
, ecx
, edx
;
507 int index_msb
, core_bits
;
509 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
511 if (!cpu_has(c
, X86_FEATURE_HT
) || cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
514 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
516 if (smp_num_siblings
== 1) {
517 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
518 } else if (smp_num_siblings
> 1 ) {
520 if (smp_num_siblings
> NR_CPUS
) {
521 printk(KERN_WARNING
"CPU: Unsupported number of the "
522 "siblings %d", smp_num_siblings
);
523 smp_num_siblings
= 1;
527 index_msb
= get_count_order(smp_num_siblings
);
528 c
->phys_proc_id
= phys_pkg_id((ebx
>> 24) & 0xFF, index_msb
);
530 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
533 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
535 index_msb
= get_count_order(smp_num_siblings
) ;
537 core_bits
= get_count_order(c
->x86_max_cores
);
539 c
->cpu_core_id
= phys_pkg_id((ebx
>> 24) & 0xFF, index_msb
) &
540 ((1 << core_bits
) - 1);
542 if (c
->x86_max_cores
> 1)
543 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
549 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
553 if (c
->x86_vendor
< X86_VENDOR_NUM
)
554 vendor
= this_cpu
->c_vendor
;
555 else if (c
->cpuid_level
>= 0)
556 vendor
= c
->x86_vendor_id
;
558 if (vendor
&& strncmp(c
->x86_model_id
, vendor
, strlen(vendor
)))
559 printk("%s ", vendor
);
561 if (!c
->x86_model_id
[0])
562 printk("%d86", c
->x86
);
564 printk("%s", c
->x86_model_id
);
566 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
567 printk(" stepping %02x\n", c
->x86_mask
);
572 cpumask_t cpu_initialized __cpuinitdata
= CPU_MASK_NONE
;
575 * We're emulating future behavior.
576 * In the future, the cpu-specific init functions will be called implicitly
577 * via the magic of initcalls.
578 * They will insert themselves into the cpu_devs structure.
579 * Then, when cpu_init() is called, we can just iterate over that array.
582 extern int intel_cpu_init(void);
583 extern int cyrix_init_cpu(void);
584 extern int nsc_init_cpu(void);
585 extern int amd_init_cpu(void);
586 extern int centaur_init_cpu(void);
587 extern int transmeta_init_cpu(void);
588 extern int nexgen_init_cpu(void);
589 extern int umc_init_cpu(void);
591 void __init
early_cpu_init(void)
598 transmeta_init_cpu();
603 #ifdef CONFIG_DEBUG_PAGEALLOC
604 /* pse is not compatible with on-the-fly unmapping,
605 * disable it even if the cpus claim to support it.
607 setup_clear_cpu_cap(X86_FEATURE_PSE
);
611 /* Make sure %fs is initialized properly in idle threads */
612 struct pt_regs
* __devinit
idle_regs(struct pt_regs
*regs
)
614 memset(regs
, 0, sizeof(struct pt_regs
));
615 regs
->fs
= __KERNEL_PERCPU
;
619 /* Current gdt points %fs at the "master" per-cpu area: after this,
620 * it's on the real one. */
621 void switch_to_new_gdt(void)
623 struct desc_ptr gdt_descr
;
625 gdt_descr
.address
= (long)get_cpu_gdt_table(smp_processor_id());
626 gdt_descr
.size
= GDT_SIZE
- 1;
627 load_gdt(&gdt_descr
);
628 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU
) : "memory");
632 * cpu_init() initializes state that is per-CPU. Some data is already
633 * initialized (naturally) in the bootstrap process, such as the GDT
634 * and IDT. We reload them nevertheless, this function acts as a
635 * 'CPU state barrier', nothing should get across.
637 void __cpuinit
cpu_init(void)
639 int cpu
= smp_processor_id();
640 struct task_struct
*curr
= current
;
641 struct tss_struct
* t
= &per_cpu(init_tss
, cpu
);
642 struct thread_struct
*thread
= &curr
->thread
;
644 if (cpu_test_and_set(cpu
, cpu_initialized
)) {
645 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
646 for (;;) local_irq_enable();
649 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
651 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
652 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
653 if (tsc_disable
&& cpu_has_tsc
) {
654 printk(KERN_NOTICE
"Disabling TSC...\n");
655 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
656 clear_bit(X86_FEATURE_TSC
, boot_cpu_data
.x86_capability
);
657 set_in_cr4(X86_CR4_TSD
);
660 load_idt(&idt_descr
);
664 * Set up and load the per-CPU TSS and LDT
666 atomic_inc(&init_mm
.mm_count
);
667 curr
->active_mm
= &init_mm
;
670 enter_lazy_tlb(&init_mm
, curr
);
675 load_LDT(&init_mm
.context
);
677 #ifdef CONFIG_DOUBLEFAULT
678 /* Set up doublefault TSS pointer in the GDT */
679 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
683 asm volatile ("mov %0, %%gs" : : "r" (0));
685 /* Clear all 6 debug registers: */
694 * Force FPU initialization:
696 current_thread_info()->status
= 0;
698 mxcsr_feature_mask_init();
701 #ifdef CONFIG_HOTPLUG_CPU
702 void __cpuinit
cpu_uninit(void)
704 int cpu
= raw_smp_processor_id();
705 cpu_clear(cpu
, cpu_initialized
);
708 per_cpu(cpu_tlbstate
, cpu
).state
= 0;
709 per_cpu(cpu_tlbstate
, cpu
).active_mm
= &init_mm
;