1 /* setup.c: FRV specific setup
3 * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 * - Derived from arch/m68k/kernel/setup.c
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <linux/config.h>
14 #include <linux/version.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
22 #include <linux/console.h>
23 #include <linux/genhd.h>
24 #include <linux/errno.h>
25 #include <linux/string.h>
26 #include <linux/major.h>
27 #include <linux/bootmem.h>
28 #include <linux/highmem.h>
29 #include <linux/seq_file.h>
30 #include <linux/serial.h>
31 #include <linux/serial_core.h>
32 #include <linux/serial_reg.h>
34 #include <asm/setup.h>
35 #include <asm/serial.h>
37 #include <asm/sections.h>
38 #include <asm/pgalloc.h>
39 #include <asm/busctl-regs.h>
40 #include <asm/serial-regs.h>
41 #include <asm/timer-regs.h>
42 #include <asm/irc-regs.h>
43 #include <asm/spr-regs.h>
44 #include <asm/mb-regs.h>
45 #include <asm/mb93493-regs.h>
46 #include <asm/gdb-stub.h>
47 #include <asm/irq-routing.h>
50 #ifdef CONFIG_BLK_DEV_INITRD
51 #include <linux/blk.h>
52 #include <asm/pgtable.h>
57 #ifdef CONFIG_MB93090_MB00
58 static void __init
mb93090_display(void);
61 static void __init
setup_linux_memory(void);
63 static void __init
setup_uclinux_memory(void);
67 extern struct consw
*conswitchp
;
70 #ifdef CONFIG_MB93090_MB00
71 static char __initdata mb93090_banner
[] = "FJ/RH FR-V Linux";
72 static char __initdata mb93090_version
[] = UTS_RELEASE
;
74 int __nongprelbss mb93090_mb00_detected
;
77 const char __frv_unknown_system
[] = "unknown";
78 const char __frv_mb93091_cb10
[] = "mb93091-cb10";
79 const char __frv_mb93091_cb11
[] = "mb93091-cb11";
80 const char __frv_mb93091_cb30
[] = "mb93091-cb30";
81 const char __frv_mb93091_cb41
[] = "mb93091-cb41";
82 const char __frv_mb93091_cb60
[] = "mb93091-cb60";
83 const char __frv_mb93091_cb70
[] = "mb93091-cb70";
84 const char __frv_mb93091_cb451
[] = "mb93091-cb451";
85 const char __frv_mb93090_mb00
[] = "mb93090-mb00";
87 const char __frv_mb93493
[] = "mb93493";
89 const char __frv_mb93093
[] = "mb93093";
91 static const char *__nongprelbss cpu_series
;
92 static const char *__nongprelbss cpu_core
;
93 static const char *__nongprelbss cpu_silicon
;
94 static const char *__nongprelbss cpu_mmu
;
95 static const char *__nongprelbss cpu_system
;
96 static const char *__nongprelbss cpu_board1
;
97 static const char *__nongprelbss cpu_board2
;
99 static unsigned long __nongprelbss cpu_psr_all
;
100 static unsigned long __nongprelbss cpu_hsr0_all
;
102 unsigned long __nongprelbss pdm_suspend_mode
;
104 unsigned long __nongprelbss rom_length
;
105 unsigned long __nongprelbss memory_start
;
106 unsigned long __nongprelbss memory_end
;
108 unsigned long __nongprelbss dma_coherent_mem_start
;
109 unsigned long __nongprelbss dma_coherent_mem_end
;
111 unsigned long __initdata __sdram_old_base
;
112 unsigned long __initdata num_mappedpages
;
114 struct cpuinfo_frv __nongprelbss boot_cpu_data
;
116 char command_line
[COMMAND_LINE_SIZE
];
117 char __initdata redboot_command_line
[COMMAND_LINE_SIZE
];
123 #define __pminit __init
124 #define __pminitdata __initdata
128 uint8_t xbus
, sdram
, corebus
, core
, dsu
;
131 #define _frac(N,D) ((N)<<4 | (D))
132 #define _x0_16 _frac(1,6)
133 #define _x0_25 _frac(1,4)
134 #define _x0_33 _frac(1,3)
135 #define _x0_375 _frac(3,8)
136 #define _x0_5 _frac(1,2)
137 #define _x0_66 _frac(2,3)
138 #define _x0_75 _frac(3,4)
139 #define _x1 _frac(1,1)
140 #define _x1_5 _frac(3,2)
141 #define _x2 _frac(2,1)
142 #define _x3 _frac(3,1)
143 #define _x4 _frac(4,1)
144 #define _x4_5 _frac(9,2)
145 #define _x6 _frac(6,1)
146 #define _x8 _frac(8,1)
147 #define _x9 _frac(9,1)
149 int __nongprelbss clock_p0_current
;
150 int __nongprelbss clock_cm_current
;
151 int __nongprelbss clock_cmode_current
;
153 int __nongprelbss clock_cmodes_permitted
;
154 unsigned long __nongprelbss clock_bits_settable
;
157 static struct clock_cmode __pminitdata undef_clock_cmode
= { _x1
, _x1
, _x1
, _x1
, _x1
};
159 static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403
[16] = {
160 [4] = { _x1
, _x1
, _x2
, _x2
, _x0_25
},
161 [5] = { _x1
, _x2
, _x4
, _x4
, _x0_5
},
162 [8] = { _x1
, _x1
, _x1
, _x2
, _x0_25
},
163 [9] = { _x1
, _x2
, _x2
, _x4
, _x0_5
},
164 [11] = { _x1
, _x4
, _x4
, _x8
, _x1
},
165 [12] = { _x1
, _x1
, _x2
, _x4
, _x0_5
},
166 [13] = { _x1
, _x2
, _x4
, _x8
, _x1
},
169 static struct clock_cmode __pminitdata clock_cmodes_fr405
[16] = {
170 [0] = { _x1
, _x1
, _x1
, _x1
, _x0_5
},
171 [1] = { _x1
, _x1
, _x1
, _x3
, _x0_25
},
172 [2] = { _x1
, _x1
, _x2
, _x6
, _x0_5
},
173 [3] = { _x1
, _x2
, _x2
, _x6
, _x0_5
},
174 [4] = { _x1
, _x1
, _x2
, _x2
, _x0_16
},
175 [8] = { _x1
, _x1
, _x1
, _x2
, _x0_16
},
176 [9] = { _x1
, _x2
, _x2
, _x4
, _x0_33
},
177 [12] = { _x1
, _x1
, _x2
, _x4
, _x0_33
},
178 [14] = { _x1
, _x3
, _x3
, _x9
, _x0_75
},
179 [15] = { _x1
, _x1_5
, _x1_5
, _x4_5
, _x0_375
},
181 #define CLOCK_CMODES_PERMITTED_FR405 0xd31f
184 static struct clock_cmode __pminitdata clock_cmodes_fr555
[16] = {
185 [0] = { _x1
, _x2
, _x2
, _x4
, _x0_33
},
186 [1] = { _x1
, _x3
, _x3
, _x6
, _x0_5
},
187 [2] = { _x1
, _x2
, _x4
, _x8
, _x0_66
},
188 [3] = { _x1
, _x1_5
, _x3
, _x6
, _x0_5
},
189 [4] = { _x1
, _x3
, _x3
, _x9
, _x0_75
},
190 [5] = { _x1
, _x2
, _x2
, _x6
, _x0_5
},
191 [6] = { _x1
, _x1_5
, _x1_5
, _x4_5
, _x0_375
},
194 static const struct clock_cmode __pminitdata
*clock_cmodes
;
195 static int __pminitdata clock_doubled
;
197 static struct uart_port __initdata __frv_uart0
= {
199 .membase
= (char *) UART0_BASE
,
200 .irq
= IRQ_CPU_UART0
,
203 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
,
206 static struct uart_port __initdata __frv_uart1
= {
208 .membase
= (char *) UART1_BASE
,
209 .irq
= IRQ_CPU_UART1
,
212 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
,
216 static void __init
printk_xampr(unsigned long ampr
, unsigned long amlr
, char i_d
, int n
)
218 unsigned long phys
, virt
, cxn
, size
;
221 virt
= amlr
& 0xffffc000;
224 virt
= ampr
& 0xffffc000;
227 phys
= ampr
& xAMPRx_PPFN
;
228 size
= 1 << (((ampr
& xAMPRx_SS
) >> 4) + 17);
230 printk("%cAMPR%d: va %08lx-%08lx [pa %08lx] %c%c%c%c [cxn:%04lx]\n",
232 virt
, virt
+ size
- 1,
234 ampr
& xAMPRx_S
? 'S' : '-',
235 ampr
& xAMPRx_C
? 'C' : '-',
236 ampr
& DAMPRx_WP
? 'W' : '-',
237 ampr
& xAMPRx_V
? 'V' : '-',
243 /*****************************************************************************/
245 * dump the memory map
247 static void __init
dump_memory_map(void)
251 /* dump the protection map */
252 printk_xampr(__get_IAMPR(0), __get_IAMLR(0), 'I', 0);
253 printk_xampr(__get_IAMPR(1), __get_IAMLR(1), 'I', 1);
254 printk_xampr(__get_IAMPR(2), __get_IAMLR(2), 'I', 2);
255 printk_xampr(__get_IAMPR(3), __get_IAMLR(3), 'I', 3);
256 printk_xampr(__get_IAMPR(4), __get_IAMLR(4), 'I', 4);
257 printk_xampr(__get_IAMPR(5), __get_IAMLR(5), 'I', 5);
258 printk_xampr(__get_IAMPR(6), __get_IAMLR(6), 'I', 6);
259 printk_xampr(__get_IAMPR(7), __get_IAMLR(7), 'I', 7);
260 printk_xampr(__get_IAMPR(8), __get_IAMLR(8), 'I', 8);
261 printk_xampr(__get_IAMPR(9), __get_IAMLR(9), 'i', 9);
262 printk_xampr(__get_IAMPR(10), __get_IAMLR(10), 'I', 10);
263 printk_xampr(__get_IAMPR(11), __get_IAMLR(11), 'I', 11);
264 printk_xampr(__get_IAMPR(12), __get_IAMLR(12), 'I', 12);
265 printk_xampr(__get_IAMPR(13), __get_IAMLR(13), 'I', 13);
266 printk_xampr(__get_IAMPR(14), __get_IAMLR(14), 'I', 14);
267 printk_xampr(__get_IAMPR(15), __get_IAMLR(15), 'I', 15);
269 printk_xampr(__get_DAMPR(0), __get_DAMLR(0), 'D', 0);
270 printk_xampr(__get_DAMPR(1), __get_DAMLR(1), 'D', 1);
271 printk_xampr(__get_DAMPR(2), __get_DAMLR(2), 'D', 2);
272 printk_xampr(__get_DAMPR(3), __get_DAMLR(3), 'D', 3);
273 printk_xampr(__get_DAMPR(4), __get_DAMLR(4), 'D', 4);
274 printk_xampr(__get_DAMPR(5), __get_DAMLR(5), 'D', 5);
275 printk_xampr(__get_DAMPR(6), __get_DAMLR(6), 'D', 6);
276 printk_xampr(__get_DAMPR(7), __get_DAMLR(7), 'D', 7);
277 printk_xampr(__get_DAMPR(8), __get_DAMLR(8), 'D', 8);
278 printk_xampr(__get_DAMPR(9), __get_DAMLR(9), 'D', 9);
279 printk_xampr(__get_DAMPR(10), __get_DAMLR(10), 'D', 10);
280 printk_xampr(__get_DAMPR(11), __get_DAMLR(11), 'D', 11);
281 printk_xampr(__get_DAMPR(12), __get_DAMLR(12), 'D', 12);
282 printk_xampr(__get_DAMPR(13), __get_DAMLR(13), 'D', 13);
283 printk_xampr(__get_DAMPR(14), __get_DAMLR(14), 'D', 14);
284 printk_xampr(__get_DAMPR(15), __get_DAMLR(15), 'D', 15);
288 /* dump the bus controller registers */
289 printk("LGCR: %08lx\n", __get_LGCR());
290 printk("Master: %08lx-%08lx CR=%08lx\n",
291 __get_LEMBR(), __get_LEMBR() + __get_LEMAM(),
295 for (loop
= 1; loop
<= 7; loop
++) {
296 unsigned long lcr
= __get_LCR(loop
), lsbr
= __get_LSBR(loop
);
297 printk("CS#%d: %08lx-%08lx %c%c%c%c%c%c%c%c%c\n",
299 lsbr
, lsbr
+ __get_LSAM(loop
),
300 lcr
& 0x80000000 ? 'r' : '-',
301 lcr
& 0x40000000 ? 'w' : '-',
302 lcr
& 0x08000000 ? 'b' : '-',
303 lcr
& 0x04000000 ? 'B' : '-',
304 lcr
& 0x02000000 ? 'C' : '-',
305 lcr
& 0x01000000 ? 'D' : '-',
306 lcr
& 0x00800000 ? 'W' : '-',
307 lcr
& 0x00400000 ? 'R' : '-',
308 (lcr
& 0x00030000) == 0x00000000 ? '4' :
309 (lcr
& 0x00030000) == 0x00010000 ? '2' :
310 (lcr
& 0x00030000) == 0x00020000 ? '1' :
319 } /* end dump_memory_map() */
321 /*****************************************************************************/
323 * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system
325 #ifdef CONFIG_MB93091_VDK
326 static void __init
detect_mb93091(void)
328 #ifdef CONFIG_MB93090_MB00
329 /* Detect CB70 without motherboard */
330 if (!(cpu_system
== __frv_mb93091_cb70
&& ((*(unsigned short *)0xffc00030) & 0x100))) {
331 cpu_board1
= __frv_mb93090_mb00
;
332 mb93090_mb00_detected
= 1;
336 #ifdef CONFIG_FUJITSU_MB93493
337 cpu_board2
= __frv_mb93493
;
340 } /* end detect_mb93091() */
343 /*****************************************************************************/
345 * determine the CPU type and set appropriate parameters
347 * Family Series CPU Core Silicon Imple Vers
348 * ----------------------------------------------------------
349 * FR-V --+-> FR400 --+-> FR401 --+-> MB93401 02 00 [1]
351 * | | +-> MB93401/A 02 01
353 * | | +-> MB93403 02 02
355 * | +-> FR405 ----> MB93405 04 00
357 * +-> FR450 ----> FR451 ----> MB93451 05 00
359 * +-> FR500 ----> FR501 --+-> MB93501 01 01 [2]
361 * | +-> MB93501/A 01 02
363 * +-> FR550 --+-> FR551 ----> MB93555 03 01
365 * [1] The MB93401 is an obsolete CPU replaced by the MB93401A
366 * [2] The MB93501 is an obsolete CPU replaced by the MB93501A
368 * Imple is PSR(Processor Status Register)[31:28].
369 * Vers is PSR(Processor Status Register)[27:24].
371 * A "Silicon" consists of CPU core and some on-chip peripherals.
373 static void __init
determine_cpu(void)
375 unsigned long hsr0
= __get_HSR(0);
376 unsigned long psr
= __get_PSR();
378 /* work out what selectable services the CPU supports */
379 __set_PSR(psr
| PSR_EM
| PSR_EF
| PSR_CM
| PSR_NEM
);
380 cpu_psr_all
= __get_PSR();
383 __set_HSR(0, hsr0
| HSR0_GRLE
| HSR0_GRHE
| HSR0_FRLE
| HSR0_FRHE
);
384 cpu_hsr0_all
= __get_HSR(0);
387 /* derive other service specs from the CPU type */
388 cpu_series
= "unknown";
389 cpu_core
= "unknown";
390 cpu_silicon
= "unknown";
392 cpu_system
= __frv_unknown_system
;
396 clock_bits_settable
= CLOCK_BIT_CM_H
| CLOCK_BIT_CM_M
| CLOCK_BIT_P0
;
399 switch (PSR_IMPLE(psr
)) {
400 case PSR_IMPLE_FR401
:
401 cpu_series
= "fr400";
403 pdm_suspend_mode
= HSR0_PDM_PLL_RUN
;
405 switch (PSR_VERSION(psr
)) {
406 case PSR_VERSION_FR401_MB93401
:
407 cpu_silicon
= "mb93401";
408 cpu_system
= __frv_mb93091_cb10
;
409 clock_cmodes
= clock_cmodes_fr401_fr403
;
412 case PSR_VERSION_FR401_MB93401A
:
413 cpu_silicon
= "mb93401/A";
414 cpu_system
= __frv_mb93091_cb11
;
415 clock_cmodes
= clock_cmodes_fr401_fr403
;
417 case PSR_VERSION_FR401_MB93403
:
418 cpu_silicon
= "mb93403";
419 #ifndef CONFIG_MB93093_PDK
420 cpu_system
= __frv_mb93091_cb30
;
422 cpu_system
= __frv_mb93093
;
424 clock_cmodes
= clock_cmodes_fr401_fr403
;
431 case PSR_IMPLE_FR405
:
432 cpu_series
= "fr400";
434 pdm_suspend_mode
= HSR0_PDM_PLL_STOP
;
436 switch (PSR_VERSION(psr
)) {
437 case PSR_VERSION_FR405_MB93405
:
438 cpu_silicon
= "mb93405";
439 cpu_system
= __frv_mb93091_cb60
;
440 clock_cmodes
= clock_cmodes_fr405
;
442 clock_bits_settable
|= CLOCK_BIT_CMODE
;
443 clock_cmodes_permitted
= CLOCK_CMODES_PERMITTED_FR405
;
446 /* the FPGA on the CB70 has extra registers
447 * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
448 * how we tell the difference between it and a CB60
450 if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
451 cpu_system
= __frv_mb93091_cb70
;
458 case PSR_IMPLE_FR451
:
459 cpu_series
= "fr450";
461 pdm_suspend_mode
= HSR0_PDM_PLL_STOP
;
463 clock_bits_settable
|= CLOCK_BIT_CMODE
;
464 clock_cmodes_permitted
= CLOCK_CMODES_PERMITTED_FR405
;
466 switch (PSR_VERSION(psr
)) {
467 case PSR_VERSION_FR451_MB93451
:
468 cpu_silicon
= "mb93451";
469 cpu_mmu
= "Prot, SAT, xSAT, DAT";
470 cpu_system
= __frv_mb93091_cb451
;
471 clock_cmodes
= clock_cmodes_fr405
;
478 case PSR_IMPLE_FR501
:
479 cpu_series
= "fr500";
481 pdm_suspend_mode
= HSR0_PDM_PLL_STOP
;
483 switch (PSR_VERSION(psr
)) {
484 case PSR_VERSION_FR501_MB93501
: cpu_silicon
= "mb93501"; break;
485 case PSR_VERSION_FR501_MB93501A
: cpu_silicon
= "mb93501/A"; break;
491 case PSR_IMPLE_FR551
:
492 cpu_series
= "fr550";
494 pdm_suspend_mode
= HSR0_PDM_PLL_RUN
;
496 switch (PSR_VERSION(psr
)) {
497 case PSR_VERSION_FR551_MB93555
:
498 cpu_silicon
= "mb93555";
499 cpu_mmu
= "Prot, SAT";
500 cpu_system
= __frv_mb93091_cb41
;
501 clock_cmodes
= clock_cmodes_fr555
;
513 printk("- Series:%s CPU:%s Silicon:%s\n",
514 cpu_series
, cpu_core
, cpu_silicon
);
516 #ifdef CONFIG_MB93091_VDK
520 #if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
521 cpu_board2
= __frv_mb93493
;
524 } /* end determine_cpu() */
526 /*****************************************************************************/
528 * calculate the bus clock speed
530 void __pminit
determine_clocks(int verbose
)
532 const struct clock_cmode
*mode
, *tmode
;
533 unsigned long clkc
, psr
, quot
;
538 clock_p0_current
= !!(clkc
& CLKC_P0
);
539 clock_cm_current
= clkc
& CLKC_CM
;
540 clock_cmode_current
= (clkc
& CLKC_CMODE
) >> CLKC_CMODE_s
;
543 printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr
, __get_HSR(0), clkc
);
545 /* the CB70 has some alternative ways of setting the clock speed through switches accessed
546 * through the FPGA. */
547 if (cpu_system
== __frv_mb93091_cb70
) {
548 unsigned short clkswr
= *(volatile unsigned short *) 0xffc00104UL
& 0x1fffUL
;
551 __clkin_clock_speed_HZ
= 60000000UL;
553 __clkin_clock_speed_HZ
=
554 ((clkswr
>> 8) & 0xf) * 10000000 +
555 ((clkswr
>> 4) & 0xf) * 1000000 +
556 ((clkswr
) & 0xf) * 100000;
558 /* the FR451 is currently fixed at 24MHz */
559 else if (cpu_system
== __frv_mb93091_cb451
) {
560 //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
561 unsigned short clkswr
= *(volatile unsigned short *) 0xffc00104UL
& 0x1fffUL
;
564 __clkin_clock_speed_HZ
= 60000000UL;
566 __clkin_clock_speed_HZ
=
567 ((clkswr
>> 8) & 0xf) * 10000000 +
568 ((clkswr
>> 4) & 0xf) * 1000000 +
569 ((clkswr
) & 0xf) * 100000;
571 /* otherwise determine the clockspeed from VDK or other registers */
573 __clkin_clock_speed_HZ
= __get_CLKIN();
576 /* look up the appropriate clock relationships table entry */
577 mode
= &undef_clock_cmode
;
579 tmode
= &clock_cmodes
[(clkc
& CLKC_CMODE
) >> CLKC_CMODE_s
];
584 #define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))
587 __clkin_clock_speed_HZ
<<= 1;
589 __ext_bus_clock_speed_HZ
= CLOCK(__clkin_clock_speed_HZ
, mode
->xbus
);
590 __sdram_clock_speed_HZ
= CLOCK(__clkin_clock_speed_HZ
, mode
->sdram
);
591 __dsu_clock_speed_HZ
= CLOCK(__clkin_clock_speed_HZ
, mode
->dsu
);
593 switch (clkc
& CLKC_CM
) {
595 __core_bus_clock_speed_HZ
= CLOCK(__clkin_clock_speed_HZ
, mode
->corebus
);
596 __core_clock_speed_HZ
= CLOCK(__clkin_clock_speed_HZ
, mode
->core
);
599 __core_bus_clock_speed_HZ
= CLOCK(__clkin_clock_speed_HZ
, mode
->sdram
);
600 __core_clock_speed_HZ
= CLOCK(__clkin_clock_speed_HZ
, mode
->sdram
);
602 case 2: /* Low; not supported */
604 printk("Unsupported CLKC CM %ld\n", clkc
& CLKC_CM
);
608 __res_bus_clock_speed_HZ
= __ext_bus_clock_speed_HZ
;
610 __res_bus_clock_speed_HZ
>>= 1;
613 printk("CLKIN: %lu.%3.3luMHz\n",
614 __clkin_clock_speed_HZ
/ 1000000,
615 (__clkin_clock_speed_HZ
/ 1000) % 1000);
618 " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
619 __ext_bus_clock_speed_HZ
/ 1000000,
620 __res_bus_clock_speed_HZ
/ 1000000,
621 __sdram_clock_speed_HZ
/ 1000000,
622 __core_bus_clock_speed_HZ
/ 1000000,
623 __core_clock_speed_HZ
/ 1000000,
624 __dsu_clock_speed_HZ
/ 1000000
628 /* calculate the number of __delay() loop iterations per sec (2 insn loop) */
629 __delay_loops_MHz
= __core_clock_speed_HZ
/ (1000000 * 2);
631 /* set the serial prescaler */
632 __serial_clock_speed_HZ
= __res_bus_clock_speed_HZ
;
634 while (__serial_clock_speed_HZ
/ quot
/ 16 / 65536 > 3000)
637 /* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
638 * - we have to be careful - dividing too much can mean we can't get 115200 baud
640 if (__serial_clock_speed_HZ
> 32000000 && !(clkc
& CLKC_P0
))
643 __serial_clock_speed_HZ
/= quot
;
644 __frv_uart0
.uartclk
= __serial_clock_speed_HZ
;
645 __frv_uart1
.uartclk
= __serial_clock_speed_HZ
;
648 printk(" uart=%luMHz\n", __serial_clock_speed_HZ
/ 1000000 * quot
);
650 while (!(__get_UART0_LSR() & UART_LSR_TEMT
))
653 while (!(__get_UART1_LSR() & UART_LSR_TEMT
))
658 } /* end determine_clocks() */
660 /*****************************************************************************/
662 * reserve some DMA consistent memory
664 #ifdef CONFIG_RESERVE_DMA_COHERENT
665 static void __init
reserve_dma_coherent(void)
669 /* find the first non-kernel memory tile and steal it */
670 #define __steal_AMPR(r) \
671 if (__get_DAMPR(r) & xAMPRx_V) { \
672 ampr = __get_DAMPR(r); \
673 __set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C); \
685 if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551
) {
696 /* unable to grant any DMA consistent memory */
697 printk("No DMA consistent memory reserved\n");
701 dma_coherent_mem_start
= ampr
& xAMPRx_PPFN
;
704 ampr
= 1 << (ampr
- 3 + 20);
705 dma_coherent_mem_end
= dma_coherent_mem_start
+ ampr
;
707 printk("DMA consistent memory reserved %lx-%lx\n",
708 dma_coherent_mem_start
, dma_coherent_mem_end
);
710 } /* end reserve_dma_coherent() */
713 /*****************************************************************************/
715 * calibrate the delay loop
717 void __init
calibrate_delay(void)
719 loops_per_jiffy
= __delay_loops_MHz
* (1000000 / HZ
);
721 printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
722 loops_per_jiffy
/ (500000 / HZ
),
723 (loops_per_jiffy
/ (5000 / HZ
)) % 100);
725 } /* end calibrate_delay() */
727 /*****************************************************************************/
729 * look through the command line for some things we need to know immediately
731 static void __init
parse_cmdline_early(char *cmdline
)
740 /* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
741 * out from the SDRAM controller mask register
743 if (!memcmp(cmdline
, "mem=", 4)) {
744 unsigned long long mem_size
;
746 mem_size
= memparse(cmdline
+ 4, &cmdline
);
747 memory_end
= memory_start
+ mem_size
;
750 while (*cmdline
&& *cmdline
!= ' ')
754 } /* end parse_cmdline_early() */
756 /*****************************************************************************/
760 void __init
setup_arch(char **cmdline_p
)
763 printk("Linux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
765 printk("uClinux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
768 memcpy(saved_command_line
, redboot_command_line
, COMMAND_LINE_SIZE
);
773 /* For printk-directly-beats-on-serial-hardware hack */
774 console_set_baud(115200);
775 #ifdef CONFIG_GDBSTUB
776 gdbstub_set_baud(115200);
779 #ifdef CONFIG_RESERVE_DMA_COHERENT
780 reserve_dma_coherent();
784 #ifdef CONFIG_MB93090_MB00
785 if (mb93090_mb00_detected
)
789 /* register those serial ports that are available */
790 #ifdef CONFIG_FRV_ONCPU_SERIAL
791 #ifndef CONFIG_GDBSTUB_UART0
792 __reg(UART0_BASE
+ UART_IER
* 8) = 0;
793 early_serial_setup(&__frv_uart0
);
795 #ifndef CONFIG_GDBSTUB_UART1
796 __reg(UART1_BASE
+ UART_IER
* 8) = 0;
797 early_serial_setup(&__frv_uart1
);
801 #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
802 /* we need to initialize the Flashrom device here since we might
803 * do things with flash early on in the boot
808 /* deal with the command line - RedBoot may have passed one to the kernel */
809 memcpy(command_line
, saved_command_line
, sizeof(command_line
));
810 *cmdline_p
= &command_line
[0];
811 parse_cmdline_early(command_line
);
813 /* set up the memory description
814 * - by now the stack is part of the init task */
815 printk("Memory %08lx-%08lx\n", memory_start
, memory_end
);
817 BUG_ON(memory_start
== memory_end
);
819 init_mm
.start_code
= (unsigned long) &_stext
;
820 init_mm
.end_code
= (unsigned long) &_etext
;
821 init_mm
.end_data
= (unsigned long) &_edata
;
822 #if 0 /* DAVIDM - don't set brk just incase someone decides to use it */
823 init_mm
.brk
= (unsigned long) &_end
;
825 init_mm
.brk
= (unsigned long) 0;
829 printk("KERNEL -> TEXT=0x%06x-0x%06x DATA=0x%06x-0x%06x BSS=0x%06x-0x%06x\n",
830 (int) &_stext
, (int) &_etext
,
831 (int) &_sdata
, (int) &_edata
,
832 (int) &_sbss
, (int) &_ebss
);
836 #if defined(CONFIG_VGA_CONSOLE)
837 conswitchp
= &vga_con
;
838 #elif defined(CONFIG_DUMMY_CONSOLE)
839 conswitchp
= &dummy_con
;
843 #ifdef CONFIG_BLK_DEV_BLKMEM
844 ROOT_DEV
= MKDEV(BLKMEM_MAJOR
,0);
846 /*rom_length = (unsigned long)&_flashend - (unsigned long)&_romvec;*/
849 setup_linux_memory();
851 setup_uclinux_memory();
854 /* get kmalloc into gear */
860 printk("Done setup_arch\n");
863 /* start the decrement timer running */
864 // asm volatile("movgs %0,timerd" :: "r"(10000000));
865 // __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
867 } /* end setup_arch() */
870 /*****************************************************************************/
874 static int __devinit
setup_arch_serial(void)
876 /* register those serial ports that are available */
877 #ifndef CONFIG_GDBSTUB_UART0
878 early_serial_setup(&__frv_uart0
);
880 #ifndef CONFIG_GDBSTUB_UART1
881 early_serial_setup(&__frv_uart1
);
885 } /* end setup_arch_serial() */
887 late_initcall(setup_arch_serial
);
890 /*****************************************************************************/
892 * set up the memory map for normal MMU linux
895 static void __init
setup_linux_memory(void)
897 unsigned long bootmap_size
, low_top_pfn
, kstart
, kend
, high_mem
;
899 kstart
= (unsigned long) &__kernel_image_start
- PAGE_OFFSET
;
900 kend
= (unsigned long) &__kernel_image_end
- PAGE_OFFSET
;
902 kstart
= kstart
& PAGE_MASK
;
903 kend
= (kend
+ PAGE_SIZE
- 1) & PAGE_MASK
;
905 /* give all the memory to the bootmap allocator, tell it to put the
906 * boot mem_map immediately following the kernel image
908 bootmap_size
= init_bootmem_node(NODE_DATA(0),
909 kend
>> PAGE_SHIFT
, /* map addr */
910 memory_start
>> PAGE_SHIFT
, /* start of RAM */
911 memory_end
>> PAGE_SHIFT
/* end of RAM */
914 /* pass the memory that the kernel can immediately use over to the bootmem allocator */
915 max_mapnr
= num_physpages
= (memory_end
- memory_start
) >> PAGE_SHIFT
;
916 low_top_pfn
= (KERNEL_LOWMEM_END
- KERNEL_LOWMEM_START
) >> PAGE_SHIFT
;
919 if (num_physpages
> low_top_pfn
) {
920 #ifdef CONFIG_HIGHMEM
921 high_mem
= num_physpages
- low_top_pfn
;
923 max_mapnr
= num_physpages
= low_top_pfn
;
927 low_top_pfn
= num_physpages
;
930 min_low_pfn
= memory_start
>> PAGE_SHIFT
;
931 max_low_pfn
= low_top_pfn
;
932 max_pfn
= memory_end
>> PAGE_SHIFT
;
934 num_mappedpages
= low_top_pfn
;
936 printk(KERN_NOTICE
"%ldMB LOWMEM available.\n", low_top_pfn
>> (20 - PAGE_SHIFT
));
938 free_bootmem(memory_start
, low_top_pfn
<< PAGE_SHIFT
);
940 #ifdef CONFIG_HIGHMEM
942 printk(KERN_NOTICE
"%ldMB HIGHMEM available.\n", high_mem
>> (20 - PAGE_SHIFT
));
945 /* take back the memory occupied by the kernel image and the bootmem alloc map */
946 reserve_bootmem(kstart
, kend
- kstart
+ bootmap_size
);
948 /* reserve the memory occupied by the initial ramdisk */
949 #ifdef CONFIG_BLK_DEV_INITRD
950 if (LOADER_TYPE
&& INITRD_START
) {
951 if (INITRD_START
+ INITRD_SIZE
<= (low_top_pfn
<< PAGE_SHIFT
)) {
952 reserve_bootmem(INITRD_START
, INITRD_SIZE
);
953 initrd_start
= INITRD_START
? INITRD_START
+ PAGE_OFFSET
: 0;
954 initrd_end
= initrd_start
+ INITRD_SIZE
;
958 "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n"
959 "disabling initrd\n",
960 INITRD_START
+ INITRD_SIZE
,
961 low_top_pfn
<< PAGE_SHIFT
);
967 } /* end setup_linux_memory() */
970 /*****************************************************************************/
972 * set up the memory map for uClinux
975 static void __init
setup_uclinux_memory(void)
977 #ifdef CONFIG_PROTECT_KERNEL
983 kend
= (unsigned long) &__kernel_image_end
;
984 kend
= (kend
+ PAGE_SIZE
- 1) & PAGE_MASK
;
986 /* give all the memory to the bootmap allocator, tell it to put the
987 * boot mem_map immediately following the kernel image
989 bootmap_size
= init_bootmem_node(NODE_DATA(0),
990 kend
>> PAGE_SHIFT
, /* map addr */
991 memory_start
>> PAGE_SHIFT
, /* start of RAM */
992 memory_end
>> PAGE_SHIFT
/* end of RAM */
995 /* free all the usable memory */
996 free_bootmem(memory_start
, memory_end
- memory_start
);
998 high_memory
= (void *) (memory_end
& PAGE_MASK
);
999 max_mapnr
= num_physpages
= ((unsigned long) high_memory
- PAGE_OFFSET
) >> PAGE_SHIFT
;
1001 min_low_pfn
= memory_start
>> PAGE_SHIFT
;
1002 max_low_pfn
= memory_end
>> PAGE_SHIFT
;
1003 max_pfn
= max_low_pfn
;
1005 /* now take back the bits the core kernel is occupying */
1006 #ifndef CONFIG_PROTECT_KERNEL
1007 reserve_bootmem(kend
, bootmap_size
);
1008 reserve_bootmem((unsigned long) &__kernel_image_start
,
1009 kend
- (unsigned long) &__kernel_image_start
);
1012 dampr
= __get_DAMPR(0);
1014 dampr
= (dampr
>> 4) + 17;
1017 reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN
, dampr
);
1020 /* reserve some memory to do uncached DMA through if requested */
1021 #ifdef CONFIG_RESERVE_DMA_COHERENT
1022 if (dma_coherent_mem_start
)
1023 reserve_bootmem(dma_coherent_mem_start
,
1024 dma_coherent_mem_end
- dma_coherent_mem_start
);
1027 } /* end setup_uclinux_memory() */
1030 /*****************************************************************************/
1032 * get CPU information for use by procfs
1034 static int show_cpuinfo(struct seq_file
*m
, void *v
)
1036 const char *gr
, *fr
, *fm
, *fp
, *cm
, *nem
, *ble
;
1041 gr
= cpu_hsr0_all
& HSR0_GRHE
? "gr0-63" : "gr0-31";
1042 fr
= cpu_hsr0_all
& HSR0_FRHE
? "fr0-63" : "fr0-31";
1043 fm
= cpu_psr_all
& PSR_EM
? ", Media" : "";
1044 fp
= cpu_psr_all
& PSR_EF
? ", FPU" : "";
1045 cm
= cpu_psr_all
& PSR_CM
? ", CCCR" : "";
1046 nem
= cpu_psr_all
& PSR_NEM
? ", NE" : "";
1047 ble
= cpu_psr_all
& PSR_BE
? "BE" : "LE";
1051 "CPU-Core:\t%s, %s, %s%s%s\n"
1054 "FP-Media:\t%s%s%s\n"
1057 cpu_core
, gr
, ble
, cm
, nem
,
1064 seq_printf(m
, ", %s", cpu_board1
);
1067 seq_printf(m
, ", %s", cpu_board2
);
1069 seq_printf(m
, "\n");
1072 seq_printf(m
, "PM-Controls:");
1075 if (clock_bits_settable
& CLOCK_BIT_CMODE
) {
1076 seq_printf(m
, "%scmode=0x%04hx", sep
, clock_cmodes_permitted
);
1080 if (clock_bits_settable
& CLOCK_BIT_CM
) {
1081 seq_printf(m
, "%scm=0x%lx", sep
, clock_bits_settable
& CLOCK_BIT_CM
);
1085 if (clock_bits_settable
& CLOCK_BIT_P0
) {
1086 seq_printf(m
, "%sp0=0x3", sep
);
1090 seq_printf(m
, "%ssuspend=0x22\n", sep
);
1094 "PM-Status:\tcmode=%d, cm=%d, p0=%d\n",
1095 clock_cmode_current
, clock_cm_current
, clock_p0_current
);
1097 #define print_clk(TAG, VAR) \
1098 seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100)
1100 print_clk("In", __clkin_clock_speed_HZ
);
1101 print_clk("Core", __core_clock_speed_HZ
);
1102 print_clk("SDRAM", __sdram_clock_speed_HZ
);
1103 print_clk("CBus", __core_bus_clock_speed_HZ
);
1104 print_clk("Res", __res_bus_clock_speed_HZ
);
1105 print_clk("Ext", __ext_bus_clock_speed_HZ
);
1106 print_clk("DSU", __dsu_clock_speed_HZ
);
1109 "BogoMips:\t%lu.%02lu\n",
1110 (loops_per_jiffy
* HZ
) / 500000, ((loops_per_jiffy
* HZ
) / 5000) % 100);
1113 } /* end show_cpuinfo() */
1115 static void *c_start(struct seq_file
*m
, loff_t
*pos
)
1117 return *pos
< NR_CPUS
? (void *) 0x12345678 : NULL
;
1120 static void *c_next(struct seq_file
*m
, void *v
, loff_t
*pos
)
1123 return c_start(m
, pos
);
1126 static void c_stop(struct seq_file
*m
, void *v
)
1130 struct seq_operations cpuinfo_op
= {
1134 .show
= show_cpuinfo
,
1137 void arch_gettod(int *year
, int *mon
, int *day
, int *hour
,
1140 *year
= *mon
= *day
= *hour
= *min
= *sec
= 0;
1143 /*****************************************************************************/
1147 #ifdef CONFIG_MB93090_MB00
1148 static void __init
mb93090_sendlcdcmd(uint32_t cmd
)
1150 unsigned long base
= __addr_LCD();
1153 /* request reading of the busy flag */
1154 __set_LCD(base
, LCD_CMD_READ_BUSY
);
1155 __set_LCD(base
, LCD_CMD_READ_BUSY
& ~LCD_E
);
1157 /* wait for the busy flag to become clear */
1158 for (loop
= 10000; loop
> 0; loop
--)
1159 if (!(__get_LCD(base
) & 0x80))
1162 /* send the command */
1163 __set_LCD(base
, cmd
);
1164 __set_LCD(base
, cmd
& ~LCD_E
);
1166 } /* end mb93090_sendlcdcmd() */
1168 /*****************************************************************************/
1170 * write to the MB93090 LEDs and LCD
1172 static void __init
mb93090_display(void)
1178 /* set up the LCD */
1179 mb93090_sendlcdcmd(LCD_CMD_CLEAR
);
1180 mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0));
1181 mb93090_sendlcdcmd(LCD_CMD_ON(0,0));
1182 mb93090_sendlcdcmd(LCD_CMD_HOME
);
1184 mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0));
1185 for (p
= mb93090_banner
; *p
; p
++)
1186 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p
));
1188 mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64));
1189 for (p
= mb93090_version
; *p
; p
++)
1190 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p
));
1192 } /* end mb93090_display() */
1194 #endif // CONFIG_MB93090_MB00