[ARM] pxa: fix pxa27x_udc default pullup GPIO
[linux-2.6/mini2440.git] / arch / arm / mm / fault-armv.c
blobbc0099d5ae85c022d12a051062915fa1bae6aefb
1 /*
2 * linux/arch/arm/mm/fault-armv.c
4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2002 Russell King
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/mm.h>
15 #include <linux/bitops.h>
16 #include <linux/vmalloc.h>
17 #include <linux/init.h>
18 #include <linux/pagemap.h>
20 #include <asm/bugs.h>
21 #include <asm/cacheflush.h>
22 #include <asm/cachetype.h>
23 #include <asm/pgtable.h>
24 #include <asm/tlbflush.h>
26 static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
29 * We take the easy way out of this problem - we make the
30 * PTE uncacheable. However, we leave the write buffer on.
32 * Note that the pte lock held when calling update_mmu_cache must also
33 * guard the pte (somewhere else in the same mm) that we modify here.
34 * Therefore those configurations which might call adjust_pte (those
35 * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
37 static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
39 pgd_t *pgd;
40 pmd_t *pmd;
41 pte_t *pte, entry;
42 int ret;
44 pgd = pgd_offset(vma->vm_mm, address);
45 if (pgd_none(*pgd))
46 goto no_pgd;
47 if (pgd_bad(*pgd))
48 goto bad_pgd;
50 pmd = pmd_offset(pgd, address);
51 if (pmd_none(*pmd))
52 goto no_pmd;
53 if (pmd_bad(*pmd))
54 goto bad_pmd;
56 pte = pte_offset_map(pmd, address);
57 entry = *pte;
60 * If this page is present, it's actually being shared.
62 ret = pte_present(entry);
65 * If this page isn't present, or is already setup to
66 * fault (ie, is old), we can safely ignore any issues.
68 if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
69 unsigned long pfn = pte_pfn(entry);
70 flush_cache_page(vma, address, pfn);
71 outer_flush_range((pfn << PAGE_SHIFT),
72 (pfn << PAGE_SHIFT) + PAGE_SIZE);
73 pte_val(entry) &= ~L_PTE_MT_MASK;
74 pte_val(entry) |= shared_pte_mask;
75 set_pte_at(vma->vm_mm, address, pte, entry);
76 flush_tlb_page(vma, address);
78 pte_unmap(pte);
79 return ret;
81 bad_pgd:
82 pgd_ERROR(*pgd);
83 pgd_clear(pgd);
84 no_pgd:
85 return 0;
87 bad_pmd:
88 pmd_ERROR(*pmd);
89 pmd_clear(pmd);
90 no_pmd:
91 return 0;
94 static void
95 make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
97 struct mm_struct *mm = vma->vm_mm;
98 struct vm_area_struct *mpnt;
99 struct prio_tree_iter iter;
100 unsigned long offset;
101 pgoff_t pgoff;
102 int aliases = 0;
104 pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
107 * If we have any shared mappings that are in the same mm
108 * space, then we need to handle them specially to maintain
109 * cache coherency.
111 flush_dcache_mmap_lock(mapping);
112 vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
114 * If this VMA is not in our MM, we can ignore it.
115 * Note that we intentionally mask out the VMA
116 * that we are fixing up.
118 if (mpnt->vm_mm != mm || mpnt == vma)
119 continue;
120 if (!(mpnt->vm_flags & VM_MAYSHARE))
121 continue;
122 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
123 aliases += adjust_pte(mpnt, mpnt->vm_start + offset);
125 flush_dcache_mmap_unlock(mapping);
126 if (aliases)
127 adjust_pte(vma, addr);
128 else
129 flush_cache_page(vma, addr, pfn);
133 * Take care of architecture specific things when placing a new PTE into
134 * a page table, or changing an existing PTE. Basically, there are two
135 * things that we need to take care of:
137 * 1. If PG_dcache_dirty is set for the page, we need to ensure
138 * that any cache entries for the kernels virtual memory
139 * range are written back to the page.
140 * 2. If we have multiple shared mappings of the same space in
141 * an object, we need to deal with the cache aliasing issues.
143 * Note that the pte lock will be held.
145 void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
147 unsigned long pfn = pte_pfn(pte);
148 struct address_space *mapping;
149 struct page *page;
151 if (!pfn_valid(pfn))
152 return;
154 page = pfn_to_page(pfn);
155 mapping = page_mapping(page);
156 if (mapping) {
157 #ifndef CONFIG_SMP
158 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
160 if (dirty)
161 __flush_dcache_page(mapping, page);
162 #endif
164 if (cache_is_vivt())
165 make_coherent(mapping, vma, addr, pfn);
166 else if (vma->vm_flags & VM_EXEC)
167 __flush_icache_all();
172 * Check whether the write buffer has physical address aliasing
173 * issues. If it has, we need to avoid them for the case where
174 * we have several shared mappings of the same object in user
175 * space.
177 static int __init check_writebuffer(unsigned long *p1, unsigned long *p2)
179 register unsigned long zero = 0, one = 1, val;
181 local_irq_disable();
182 mb();
183 *p1 = one;
184 mb();
185 *p2 = zero;
186 mb();
187 val = *p1;
188 mb();
189 local_irq_enable();
190 return val != zero;
193 void __init check_writebuffer_bugs(void)
195 struct page *page;
196 const char *reason;
197 unsigned long v = 1;
199 printk(KERN_INFO "CPU: Testing write buffer coherency: ");
201 page = alloc_page(GFP_KERNEL);
202 if (page) {
203 unsigned long *p1, *p2;
204 pgprot_t prot = __pgprot(L_PTE_PRESENT|L_PTE_YOUNG|
205 L_PTE_DIRTY|L_PTE_WRITE|
206 L_PTE_MT_BUFFERABLE);
208 p1 = vmap(&page, 1, VM_IOREMAP, prot);
209 p2 = vmap(&page, 1, VM_IOREMAP, prot);
211 if (p1 && p2) {
212 v = check_writebuffer(p1, p2);
213 reason = "enabling work-around";
214 } else {
215 reason = "unable to map memory\n";
218 vunmap(p1);
219 vunmap(p2);
220 put_page(page);
221 } else {
222 reason = "unable to grab page\n";
225 if (v) {
226 printk("failed, %s\n", reason);
227 shared_pte_mask = L_PTE_MT_UNCACHED;
228 } else {
229 printk("ok\n");