2 * linux/arch/arm/mm/alignment.c
4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2001 Russell King
6 * Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
7 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
8 * Copyright (C) 1996, Cygnus Software Technologies Ltd.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/compiler.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/proc_fs.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/uaccess.h>
23 #include <asm/unaligned.h>
28 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
29 * /proc/sys/debug/alignment, modified and integrated into
30 * Linux 2.1 by Russell King
32 * Speed optimisations and better fault handling by Russell King.
35 * This code is not portable to processors with late data abort handling.
37 #define CODING_BITS(i) (i & 0x0e000000)
39 #define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
40 #define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
41 #define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */
42 #define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */
43 #define LDST_L_BIT(i) (i & (1 << 20)) /* Load */
45 #define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
47 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
48 #define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */
50 #define RN_BITS(i) ((i >> 16) & 15) /* Rn */
51 #define RD_BITS(i) ((i >> 12) & 15) /* Rd */
52 #define RM_BITS(i) (i & 15) /* Rm */
54 #define REGMASK_BITS(i) (i & 0xffff)
55 #define OFFSET_BITS(i) (i & 0x0fff)
57 #define IS_SHIFT(i) (i & 0x0ff0)
58 #define SHIFT_BITS(i) ((i >> 7) & 0x1f)
59 #define SHIFT_TYPE(i) (i & 0x60)
60 #define SHIFT_LSL 0x00
61 #define SHIFT_LSR 0x20
62 #define SHIFT_ASR 0x40
63 #define SHIFT_RORRRX 0x60
65 static unsigned long ai_user
;
66 static unsigned long ai_sys
;
67 static unsigned long ai_skipped
;
68 static unsigned long ai_half
;
69 static unsigned long ai_word
;
70 static unsigned long ai_dword
;
71 static unsigned long ai_multi
;
72 static int ai_usermode
;
74 #define UM_WARN (1 << 0)
75 #define UM_FIXUP (1 << 1)
76 #define UM_SIGNAL (1 << 2)
79 static const char *usermode_action
[] = {
89 proc_alignment_read(char *page
, char **start
, off_t off
, int count
, int *eof
,
95 p
+= sprintf(p
, "User:\t\t%lu\n", ai_user
);
96 p
+= sprintf(p
, "System:\t\t%lu\n", ai_sys
);
97 p
+= sprintf(p
, "Skipped:\t%lu\n", ai_skipped
);
98 p
+= sprintf(p
, "Half:\t\t%lu\n", ai_half
);
99 p
+= sprintf(p
, "Word:\t\t%lu\n", ai_word
);
100 if (cpu_architecture() >= CPU_ARCH_ARMv5TE
)
101 p
+= sprintf(p
, "DWord:\t\t%lu\n", ai_dword
);
102 p
+= sprintf(p
, "Multi:\t\t%lu\n", ai_multi
);
103 p
+= sprintf(p
, "User faults:\t%i (%s)\n", ai_usermode
,
104 usermode_action
[ai_usermode
]);
106 len
= (p
- page
) - off
;
110 *eof
= (len
<= count
) ? 1 : 0;
116 static int proc_alignment_write(struct file
*file
, const char __user
*buffer
,
117 unsigned long count
, void *data
)
122 if (get_user(mode
, buffer
))
124 if (mode
>= '0' && mode
<= '5')
125 ai_usermode
= mode
- '0';
130 #endif /* CONFIG_PROC_FS */
144 #define FIRST_BYTE_16 "mov %1, %1, ror #8\n"
145 #define FIRST_BYTE_32 "mov %1, %1, ror #24\n"
146 #define NEXT_BYTE "ror #24"
149 #define FIRST_BYTE_16
150 #define FIRST_BYTE_32
151 #define NEXT_BYTE "lsr #8"
154 #define __get8_unaligned_check(ins,val,addr,err) \
156 "1: "ins" %1, [%2], #1\n" \
158 " .section .fixup,\"ax\"\n" \
163 " .section __ex_table,\"a\"\n" \
167 : "=r" (err), "=&r" (val), "=r" (addr) \
168 : "0" (err), "2" (addr))
170 #define __get16_unaligned_check(ins,val,addr) \
172 unsigned int err = 0, v, a = addr; \
173 __get8_unaligned_check(ins,v,a,err); \
174 val = v << ((BE) ? 8 : 0); \
175 __get8_unaligned_check(ins,v,a,err); \
176 val |= v << ((BE) ? 0 : 8); \
181 #define get16_unaligned_check(val,addr) \
182 __get16_unaligned_check("ldrb",val,addr)
184 #define get16t_unaligned_check(val,addr) \
185 __get16_unaligned_check("ldrbt",val,addr)
187 #define __get32_unaligned_check(ins,val,addr) \
189 unsigned int err = 0, v, a = addr; \
190 __get8_unaligned_check(ins,v,a,err); \
191 val = v << ((BE) ? 24 : 0); \
192 __get8_unaligned_check(ins,v,a,err); \
193 val |= v << ((BE) ? 16 : 8); \
194 __get8_unaligned_check(ins,v,a,err); \
195 val |= v << ((BE) ? 8 : 16); \
196 __get8_unaligned_check(ins,v,a,err); \
197 val |= v << ((BE) ? 0 : 24); \
202 #define get32_unaligned_check(val,addr) \
203 __get32_unaligned_check("ldrb",val,addr)
205 #define get32t_unaligned_check(val,addr) \
206 __get32_unaligned_check("ldrbt",val,addr)
208 #define __put16_unaligned_check(ins,val,addr) \
210 unsigned int err = 0, v = val, a = addr; \
211 __asm__( FIRST_BYTE_16 \
212 "1: "ins" %1, [%2], #1\n" \
213 " mov %1, %1, "NEXT_BYTE"\n" \
214 "2: "ins" %1, [%2]\n" \
216 " .section .fixup,\"ax\"\n" \
221 " .section __ex_table,\"a\"\n" \
226 : "=r" (err), "=&r" (v), "=&r" (a) \
227 : "0" (err), "1" (v), "2" (a)); \
232 #define put16_unaligned_check(val,addr) \
233 __put16_unaligned_check("strb",val,addr)
235 #define put16t_unaligned_check(val,addr) \
236 __put16_unaligned_check("strbt",val,addr)
238 #define __put32_unaligned_check(ins,val,addr) \
240 unsigned int err = 0, v = val, a = addr; \
241 __asm__( FIRST_BYTE_32 \
242 "1: "ins" %1, [%2], #1\n" \
243 " mov %1, %1, "NEXT_BYTE"\n" \
244 "2: "ins" %1, [%2], #1\n" \
245 " mov %1, %1, "NEXT_BYTE"\n" \
246 "3: "ins" %1, [%2], #1\n" \
247 " mov %1, %1, "NEXT_BYTE"\n" \
248 "4: "ins" %1, [%2]\n" \
250 " .section .fixup,\"ax\"\n" \
255 " .section __ex_table,\"a\"\n" \
262 : "=r" (err), "=&r" (v), "=&r" (a) \
263 : "0" (err), "1" (v), "2" (a)); \
268 #define put32_unaligned_check(val,addr) \
269 __put32_unaligned_check("strb", val, addr)
271 #define put32t_unaligned_check(val,addr) \
272 __put32_unaligned_check("strbt", val, addr)
275 do_alignment_finish_ldst(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
, union offset_union offset
)
277 if (!LDST_U_BIT(instr
))
278 offset
.un
= -offset
.un
;
280 if (!LDST_P_BIT(instr
))
283 if (!LDST_P_BIT(instr
) || LDST_W_BIT(instr
))
284 regs
->uregs
[RN_BITS(instr
)] = addr
;
288 do_alignment_ldrhstrh(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
)
290 unsigned int rd
= RD_BITS(instr
);
297 if (LDST_L_BIT(instr
)) {
299 get16_unaligned_check(val
, addr
);
301 /* signed half-word? */
303 val
= (signed long)((signed short) val
);
305 regs
->uregs
[rd
] = val
;
307 put16_unaligned_check(regs
->uregs
[rd
], addr
);
312 if (LDST_L_BIT(instr
)) {
314 get16t_unaligned_check(val
, addr
);
316 /* signed half-word? */
318 val
= (signed long)((signed short) val
);
320 regs
->uregs
[rd
] = val
;
322 put16t_unaligned_check(regs
->uregs
[rd
], addr
);
331 do_alignment_ldrdstrd(unsigned long addr
, unsigned long instr
,
332 struct pt_regs
*regs
)
334 unsigned int rd
= RD_BITS(instr
);
336 if (((rd
& 1) == 1) || (rd
== 14))
344 if ((instr
& 0xf0) == 0xd0) {
346 get32_unaligned_check(val
, addr
);
347 regs
->uregs
[rd
] = val
;
348 get32_unaligned_check(val
, addr
+ 4);
349 regs
->uregs
[rd
+ 1] = val
;
351 put32_unaligned_check(regs
->uregs
[rd
], addr
);
352 put32_unaligned_check(regs
->uregs
[rd
+ 1], addr
+ 4);
358 if ((instr
& 0xf0) == 0xd0) {
360 get32t_unaligned_check(val
, addr
);
361 regs
->uregs
[rd
] = val
;
362 get32t_unaligned_check(val
, addr
+ 4);
363 regs
->uregs
[rd
+ 1] = val
;
365 put32t_unaligned_check(regs
->uregs
[rd
], addr
);
366 put32t_unaligned_check(regs
->uregs
[rd
+ 1], addr
+ 4);
377 do_alignment_ldrstr(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
)
379 unsigned int rd
= RD_BITS(instr
);
383 if ((!LDST_P_BIT(instr
) && LDST_W_BIT(instr
)) || user_mode(regs
))
386 if (LDST_L_BIT(instr
)) {
388 get32_unaligned_check(val
, addr
);
389 regs
->uregs
[rd
] = val
;
391 put32_unaligned_check(regs
->uregs
[rd
], addr
);
395 if (LDST_L_BIT(instr
)) {
397 get32t_unaligned_check(val
, addr
);
398 regs
->uregs
[rd
] = val
;
400 put32t_unaligned_check(regs
->uregs
[rd
], addr
);
408 * LDM/STM alignment handler.
410 * There are 4 variants of this instruction:
412 * B = rn pointer before instruction, A = rn pointer after instruction
413 * ------ increasing address ----->
414 * | | r0 | r1 | ... | rx | |
421 do_alignment_ldmstm(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
)
423 unsigned int rd
, rn
, correction
, nr_regs
, regbits
;
424 unsigned long eaddr
, newaddr
;
426 if (LDM_S_BIT(instr
))
429 correction
= 4; /* processor implementation defined */
430 regs
->ARM_pc
+= correction
;
434 /* count the number of registers in the mask to be transferred */
435 nr_regs
= hweight16(REGMASK_BITS(instr
)) * 4;
438 newaddr
= eaddr
= regs
->uregs
[rn
];
440 if (!LDST_U_BIT(instr
))
443 if (!LDST_U_BIT(instr
))
446 if (LDST_P_EQ_U(instr
)) /* U = P */
450 * For alignment faults on the ARM922T/ARM920T the MMU makes
451 * the FSR (and hence addr) equal to the updated base address
452 * of the multiple access rather than the restored value.
453 * Switch this message off if we've got a ARM92[02], otherwise
454 * [ls]dm alignment faults are noisy!
456 #if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T)
458 * This is a "hint" - we already have eaddr worked out by the
462 printk(KERN_ERR
"LDMSTM: PC = %08lx, instr = %08lx, "
463 "addr = %08lx, eaddr = %08lx\n",
464 instruction_pointer(regs
), instr
, addr
, eaddr
);
469 if (user_mode(regs
)) {
470 for (regbits
= REGMASK_BITS(instr
), rd
= 0; regbits
;
471 regbits
>>= 1, rd
+= 1)
473 if (LDST_L_BIT(instr
)) {
475 get32t_unaligned_check(val
, eaddr
);
476 regs
->uregs
[rd
] = val
;
478 put32t_unaligned_check(regs
->uregs
[rd
], eaddr
);
482 for (regbits
= REGMASK_BITS(instr
), rd
= 0; regbits
;
483 regbits
>>= 1, rd
+= 1)
485 if (LDST_L_BIT(instr
)) {
487 get32_unaligned_check(val
, eaddr
);
488 regs
->uregs
[rd
] = val
;
490 put32_unaligned_check(regs
->uregs
[rd
], eaddr
);
495 if (LDST_W_BIT(instr
))
496 regs
->uregs
[rn
] = newaddr
;
497 if (!LDST_L_BIT(instr
) || !(REGMASK_BITS(instr
) & (1 << 15)))
498 regs
->ARM_pc
-= correction
;
502 regs
->ARM_pc
-= correction
;
506 printk(KERN_ERR
"Alignment trap: not handling ldm with s-bit set\n");
511 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
512 * we can reuse ARM userland alignment fault fixups for Thumb.
514 * This implementation was initially based on the algorithm found in
515 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
516 * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
519 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
520 * 2. If for some reason we're passed an non-ld/st Thumb instruction to
521 * decode, we return 0xdeadc0de. This should never happen under normal
522 * circumstances but if it does, we've got other problems to deal with
523 * elsewhere and we obviously can't fix those problems here.
527 thumb2arm(u16 tinstr
)
529 u32 L
= (tinstr
& (1<<11)) >> 11;
531 switch ((tinstr
& 0xf800) >> 11) {
532 /* 6.5.1 Format 1: */
533 case 0x6000 >> 11: /* 7.1.52 STR(1) */
534 case 0x6800 >> 11: /* 7.1.26 LDR(1) */
535 case 0x7000 >> 11: /* 7.1.55 STRB(1) */
536 case 0x7800 >> 11: /* 7.1.30 LDRB(1) */
538 ((tinstr
& (1<<12)) << (22-12)) | /* fixup */
539 (L
<<20) | /* L==1? */
540 ((tinstr
& (7<<0)) << (12-0)) | /* Rd */
541 ((tinstr
& (7<<3)) << (16-3)) | /* Rn */
542 ((tinstr
& (31<<6)) >> /* immed_5 */
543 (6 - ((tinstr
& (1<<12)) ? 0 : 2)));
544 case 0x8000 >> 11: /* 7.1.57 STRH(1) */
545 case 0x8800 >> 11: /* 7.1.32 LDRH(1) */
547 (L
<<20) | /* L==1? */
548 ((tinstr
& (7<<0)) << (12-0)) | /* Rd */
549 ((tinstr
& (7<<3)) << (16-3)) | /* Rn */
550 ((tinstr
& (7<<6)) >> (6-1)) | /* immed_5[2:0] */
551 ((tinstr
& (3<<9)) >> (9-8)); /* immed_5[4:3] */
553 /* 6.5.1 Format 2: */
557 static const u32 subset
[8] = {
558 0xe7800000, /* 7.1.53 STR(2) */
559 0xe18000b0, /* 7.1.58 STRH(2) */
560 0xe7c00000, /* 7.1.56 STRB(2) */
561 0xe19000d0, /* 7.1.34 LDRSB */
562 0xe7900000, /* 7.1.27 LDR(2) */
563 0xe19000b0, /* 7.1.33 LDRH(2) */
564 0xe7d00000, /* 7.1.31 LDRB(2) */
565 0xe19000f0 /* 7.1.35 LDRSH */
567 return subset
[(tinstr
& (7<<9)) >> 9] |
568 ((tinstr
& (7<<0)) << (12-0)) | /* Rd */
569 ((tinstr
& (7<<3)) << (16-3)) | /* Rn */
570 ((tinstr
& (7<<6)) >> (6-0)); /* Rm */
573 /* 6.5.1 Format 3: */
574 case 0x4800 >> 11: /* 7.1.28 LDR(3) */
575 /* NOTE: This case is not technically possible. We're
576 * loading 32-bit memory data via PC relative
577 * addressing mode. So we can and should eliminate
578 * this case. But I'll leave it here for now.
581 ((tinstr
& (7<<8)) << (12-8)) | /* Rd */
582 ((tinstr
& 255) << (2-0)); /* immed_8 */
584 /* 6.5.1 Format 4: */
585 case 0x9000 >> 11: /* 7.1.54 STR(3) */
586 case 0x9800 >> 11: /* 7.1.29 LDR(4) */
588 (L
<<20) | /* L==1? */
589 ((tinstr
& (7<<8)) << (12-8)) | /* Rd */
590 ((tinstr
& 255) << 2); /* immed_8 */
592 /* 6.6.1 Format 1: */
593 case 0xc000 >> 11: /* 7.1.51 STMIA */
594 case 0xc800 >> 11: /* 7.1.25 LDMIA */
596 u32 Rn
= (tinstr
& (7<<8)) >> 8;
597 u32 W
= ((L
<<Rn
) & (tinstr
&255)) ? 0 : 1<<21;
599 return 0xe8800000 | W
| (L
<<20) | (Rn
<<16) |
603 /* 6.6.1 Format 2: */
604 case 0xb000 >> 11: /* 7.1.48 PUSH */
605 case 0xb800 >> 11: /* 7.1.47 POP */
606 if ((tinstr
& (3 << 9)) == 0x0400) {
607 static const u32 subset
[4] = {
608 0xe92d0000, /* STMDB sp!,{registers} */
609 0xe92d4000, /* STMDB sp!,{registers,lr} */
610 0xe8bd0000, /* LDMIA sp!,{registers} */
611 0xe8bd8000 /* LDMIA sp!,{registers,pc} */
613 return subset
[(L
<<1) | ((tinstr
& (1<<8)) >> 8)] |
614 (tinstr
& 255); /* register_list */
616 /* Else fall through for illegal instruction case */
624 do_alignment(unsigned long addr
, unsigned int fsr
, struct pt_regs
*regs
)
626 union offset_union offset
;
627 unsigned long instr
= 0, instrptr
;
628 int (*handler
)(unsigned long addr
, unsigned long instr
, struct pt_regs
*regs
);
634 instrptr
= instruction_pointer(regs
);
638 if (thumb_mode(regs
)) {
639 fault
= __get_user(tinstr
, (u16
*)(instrptr
& ~1));
641 instr
= thumb2arm(tinstr
);
643 fault
= __get_user(instr
, (u32
*)instrptr
);
658 regs
->ARM_pc
+= thumb_mode(regs
) ? 2 : 4;
660 switch (CODING_BITS(instr
)) {
661 case 0x00000000: /* 3.13.4 load/store instruction extensions */
662 if (LDSTHD_I_BIT(instr
))
663 offset
.un
= (instr
& 0xf00) >> 4 | (instr
& 15);
665 offset
.un
= regs
->uregs
[RM_BITS(instr
)];
667 if ((instr
& 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
668 (instr
& 0x001000f0) == 0x001000f0) /* LDRSH */
669 handler
= do_alignment_ldrhstrh
;
670 else if ((instr
& 0x001000f0) == 0x000000d0 || /* LDRD */
671 (instr
& 0x001000f0) == 0x000000f0) /* STRD */
672 handler
= do_alignment_ldrdstrd
;
673 else if ((instr
& 0x01f00ff0) == 0x01000090) /* SWP */
679 case 0x04000000: /* ldr or str immediate */
680 offset
.un
= OFFSET_BITS(instr
);
681 handler
= do_alignment_ldrstr
;
684 case 0x06000000: /* ldr or str register */
685 offset
.un
= regs
->uregs
[RM_BITS(instr
)];
687 if (IS_SHIFT(instr
)) {
688 unsigned int shiftval
= SHIFT_BITS(instr
);
690 switch(SHIFT_TYPE(instr
)) {
692 offset
.un
<<= shiftval
;
696 offset
.un
>>= shiftval
;
700 offset
.sn
>>= shiftval
;
706 if (regs
->ARM_cpsr
& PSR_C_BIT
)
707 offset
.un
|= 1 << 31;
709 offset
.un
= offset
.un
>> shiftval
|
710 offset
.un
<< (32 - shiftval
);
714 handler
= do_alignment_ldrstr
;
717 case 0x08000000: /* ldm or stm */
718 handler
= do_alignment_ldmstm
;
725 type
= handler(addr
, instr
, regs
);
727 if (type
== TYPE_ERROR
|| type
== TYPE_FAULT
)
730 if (type
== TYPE_LDST
)
731 do_alignment_finish_ldst(addr
, instr
, regs
, offset
);
736 if (type
== TYPE_ERROR
)
738 regs
->ARM_pc
-= thumb_mode(regs
) ? 2 : 4;
740 * We got a fault - fix it up, or die.
742 do_bad_area(addr
, fsr
, regs
);
746 printk(KERN_ERR
"Alignment trap: not handling swp instruction\n");
750 * Oops, we didn't handle the instruction.
752 printk(KERN_ERR
"Alignment trap: not handling instruction "
753 "%0*lx at [<%08lx>]\n",
754 thumb_mode(regs
) ? 4 : 8,
755 thumb_mode(regs
) ? tinstr
: instr
, instrptr
);
762 if (ai_usermode
& UM_WARN
)
763 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
764 "Address=0x%08lx FSR 0x%03x\n", current
->comm
,
765 task_pid_nr(current
), instrptr
,
766 thumb_mode(regs
) ? 4 : 8,
767 thumb_mode(regs
) ? tinstr
: instr
,
770 if (ai_usermode
& UM_FIXUP
)
773 if (ai_usermode
& UM_SIGNAL
)
774 force_sig(SIGBUS
, current
);
776 set_cr(cr_no_alignment
);
782 * This needs to be done after sysctl_init, otherwise sys/ will be
783 * overwritten. Actually, this shouldn't be in sys/ at all since
784 * it isn't a sysctl, and it doesn't contain sysctl information.
785 * We now locate it in /proc/cpu/alignment instead.
787 static int __init
alignment_init(void)
789 #ifdef CONFIG_PROC_FS
790 struct proc_dir_entry
*res
;
792 res
= proc_mkdir("cpu", NULL
);
796 res
= create_proc_entry("alignment", S_IWUSR
| S_IRUGO
, res
);
800 res
->read_proc
= proc_alignment_read
;
801 res
->write_proc
= proc_alignment_write
;
805 * ARMv6 and later CPUs can perform unaligned accesses for
806 * most single load and store instructions up to word size.
807 * LDM, STM, LDRD and STRD still need to be handled.
809 * Ignoring the alignment fault is not an option on these
810 * CPUs since we spin re-faulting the instruction without
811 * making any progress.
813 if (cpu_architecture() >= CPU_ARCH_ARMv6
&& (cr_alignment
& CR_U
)) {
814 cr_alignment
&= ~CR_A
;
815 cr_no_alignment
&= ~CR_A
;
816 set_cr(cr_alignment
);
817 ai_usermode
= UM_FIXUP
;
820 hook_fault_code(1, do_alignment
, SIGILL
, "alignment exception");
821 hook_fault_code(3, do_alignment
, SIGILL
, "alignment exception");
826 fs_initcall(alignment_init
);