arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c

   1 /*
   2  * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
   3  * M (part of the Centrino chipset).
   4  *
   5  * Despite the "SpeedStep" in the name, this is almost entirely unlike
   6  * traditional SpeedStep.
   7  *
   8  * Modelled on speedstep.c
   9  *
  10  * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
  11  *
  12  * WARNING WARNING WARNING
  13  *
  14  * This driver manipulates the PERF_CTL MSR, which is only somewhat
  15  * documented.  While it seems to work on my laptop, it has not been
  16  * tested anywhere else, and it may not work for you, do strange
  17  * things or simply crash.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/cpufreq.h>
  24 #include <linux/config.h>
  25 #include <linux/delay.h>
  26 #include <linux/compiler.h>
  27
  28 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
  29 #include <linux/acpi.h>
  30 #include <acpi/processor.h>
  31 #endif
  32
  33 #include <asm/msr.h>
  34 #include <asm/processor.h>
  35 #include <asm/cpufeature.h>
  36
  37 #include "speedstep-est-common.h"
  38
  39 #define PFX             "speedstep-centrino: "
  40 #define MAINTAINER      "Jeremy Fitzhardinge <jeremy@goop.org>"
  41
  42 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
  43
  44
  45 struct cpu_id
  46 {
  47         __u8    x86;            /* CPU family */
  48         __u8    x86_model;      /* model */
  49         __u8    x86_mask;       /* stepping */
  50 };
  51
  52 enum {
  53         CPU_BANIAS,
  54         CPU_DOTHAN_A1,
  55         CPU_DOTHAN_A2,
  56         CPU_DOTHAN_B0,
  57         CPU_MP4HT_D0,
  58         CPU_MP4HT_E0,
  59 };
  60
  61 static const struct cpu_id cpu_ids[] = {
  62         [CPU_BANIAS]    = { 6,  9, 5 },
  63         [CPU_DOTHAN_A1] = { 6, 13, 1 },
  64         [CPU_DOTHAN_A2] = { 6, 13, 2 },
  65         [CPU_DOTHAN_B0] = { 6, 13, 6 },
  66         [CPU_MP4HT_D0]  = {15,  3, 4 },
  67         [CPU_MP4HT_E0]  = {15,  4, 1 },
  68 };
  69 #define N_IDS   (sizeof(cpu_ids)/sizeof(cpu_ids[0]))
  70
  71 struct cpu_model
  72 {
  73         const struct cpu_id *cpu_id;
  74         const char      *model_name;
  75         unsigned        max_freq; /* max clock in kHz */
  76
  77         struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
  78 };
  79 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
  80
  81 /* Operating points for current CPU */
  82 static struct cpu_model *centrino_model[NR_CPUS];
  83 static const struct cpu_id *centrino_cpu[NR_CPUS];
  84
  85 static struct cpufreq_driver centrino_driver;
  86
  87 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
  88
  89 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
  90    frequency/voltage operating point; frequency in MHz, volts in mV.
  91    This is stored as "index" in the structure. */
  92 #define OP(mhz, mv)                                                     \
  93         {                                                               \
  94                 .frequency = (mhz) * 1000,                              \
  95                 .index = (((mhz)/100) << 8) | ((mv - 700) / 16)         \
  96         }
  97
  98 /*
  99  * These voltage tables were derived from the Intel Pentium M
 100  * datasheet, document 25261202.pdf, Table 5.  I have verified they
 101  * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
 102  * M.
 103  */
 104
 105 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
 106 static struct cpufreq_frequency_table banias_900[] =
 107 {
 108         OP(600,  844),
 109         OP(800,  988),
 110         OP(900, 1004),
 111         { .frequency = CPUFREQ_TABLE_END }
 112 };
 113
 114 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
 115 static struct cpufreq_frequency_table banias_1000[] =
 116 {
 117         OP(600,   844),
 118         OP(800,   972),
 119         OP(900,   988),
 120         OP(1000, 1004),
 121         { .frequency = CPUFREQ_TABLE_END }
 122 };
 123
 124 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
 125 static struct cpufreq_frequency_table banias_1100[] =
 126 {
 127         OP( 600,  956),
 128         OP( 800, 1020),
 129         OP( 900, 1100),
 130         OP(1000, 1164),
 131         OP(1100, 1180),
 132         { .frequency = CPUFREQ_TABLE_END }
 133 };
 134
 135
 136 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
 137 static struct cpufreq_frequency_table banias_1200[] =
 138 {
 139         OP( 600,  956),
 140         OP( 800, 1004),
 141         OP( 900, 1020),
 142         OP(1000, 1100),
 143         OP(1100, 1164),
 144         OP(1200, 1180),
 145         { .frequency = CPUFREQ_TABLE_END }
 146 };
 147
 148 /* Intel Pentium M processor 1.30GHz (Banias) */
 149 static struct cpufreq_frequency_table banias_1300[] =
 150 {
 151         OP( 600,  956),
 152         OP( 800, 1260),
 153         OP(1000, 1292),
 154         OP(1200, 1356),
 155         OP(1300, 1388),
 156         { .frequency = CPUFREQ_TABLE_END }
 157 };
 158
 159 /* Intel Pentium M processor 1.40GHz (Banias) */
 160 static struct cpufreq_frequency_table banias_1400[] =
 161 {
 162         OP( 600,  956),
 163         OP( 800, 1180),
 164         OP(1000, 1308),
 165         OP(1200, 1436),
 166         OP(1400, 1484),
 167         { .frequency = CPUFREQ_TABLE_END }
 168 };
 169
 170 /* Intel Pentium M processor 1.50GHz (Banias) */
 171 static struct cpufreq_frequency_table banias_1500[] =
 172 {
 173         OP( 600,  956),
 174         OP( 800, 1116),
 175         OP(1000, 1228),
 176         OP(1200, 1356),
 177         OP(1400, 1452),
 178         OP(1500, 1484),
 179         { .frequency = CPUFREQ_TABLE_END }
 180 };
 181
 182 /* Intel Pentium M processor 1.60GHz (Banias) */
 183 static struct cpufreq_frequency_table banias_1600[] =
 184 {
 185         OP( 600,  956),
 186         OP( 800, 1036),
 187         OP(1000, 1164),
 188         OP(1200, 1276),
 189         OP(1400, 1420),
 190         OP(1600, 1484),
 191         { .frequency = CPUFREQ_TABLE_END }
 192 };
 193
 194 /* Intel Pentium M processor 1.70GHz (Banias) */
 195 static struct cpufreq_frequency_table banias_1700[] =
 196 {
 197         OP( 600,  956),
 198         OP( 800, 1004),
 199         OP(1000, 1116),
 200         OP(1200, 1228),
 201         OP(1400, 1308),
 202         OP(1700, 1484),
 203         { .frequency = CPUFREQ_TABLE_END }
 204 };
 205 #undef OP
 206
 207 #define _BANIAS(cpuid, max, name)       \
 208 {       .cpu_id         = cpuid,        \
 209         .model_name     = "Intel(R) Pentium(R) M processor " name "MHz", \
 210         .max_freq       = (max)*1000,   \
 211         .op_points      = banias_##max, \
 212 }
 213 #define BANIAS(max)     _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
 214
 215 /* CPU models, their operating frequency range, and freq/voltage
 216    operating points */
 217 static struct cpu_model models[] =
 218 {
 219         _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
 220         BANIAS(1000),
 221         BANIAS(1100),
 222         BANIAS(1200),
 223         BANIAS(1300),
 224         BANIAS(1400),
 225         BANIAS(1500),
 226         BANIAS(1600),
 227         BANIAS(1700),
 228
 229         /* NULL model_name is a wildcard */
 230         { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
 231         { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
 232         { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
 233         { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
 234         { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
 235
 236         { NULL, }
 237 };
 238 #undef _BANIAS
 239 #undef BANIAS
 240
 241 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
 242 {
 243         struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
 244         struct cpu_model *model;
 245
 246         for(model = models; model->cpu_id != NULL; model++)
 247                 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
 248                     (model->model_name == NULL ||
 249                      strcmp(cpu->x86_model_id, model->model_name) == 0))
 250                         break;
 251
 252         if (model->cpu_id == NULL) {
 253                 /* No match at all */
 254                 dprintk(KERN_INFO PFX "no support for CPU model \"%s\": "
 255                        "send /proc/cpuinfo to " MAINTAINER "\n",
 256                        cpu->x86_model_id);
 257                 return -ENOENT;
 258         }
 259
 260         if (model->op_points == NULL) {
 261                 /* Matched a non-match */
 262                 dprintk(KERN_INFO PFX "no table support for CPU model \"%s\": \n",
 263                        cpu->x86_model_id);
 264 #ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 265                 dprintk(KERN_INFO PFX "try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
 266 #endif
 267                 return -ENOENT;
 268         }
 269
 270         centrino_model[policy->cpu] = model;
 271
 272         dprintk("found \"%s\": max frequency: %dkHz\n",
 273                model->model_name, model->max_freq);
 274
 275         return 0;
 276 }
 277
 278 #else
 279 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
 280 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
 281
 282 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
 283 {
 284         if ((c->x86 == x->x86) &&
 285             (c->x86_model == x->x86_model) &&
 286             (c->x86_mask == x->x86_mask))
 287                 return 1;
 288         return 0;
 289 }
 290
 291 /* To be called only after centrino_model is initialized */
 292 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
 293 {
 294         int i;
 295
 296         /*
 297          * Extract clock in kHz from PERF_CTL value
 298          * for centrino, as some DSDTs are buggy.
 299          * Ideally, this can be done using the acpi_data structure.
 300          */
 301         if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
 302             (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
 303             (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
 304                 msr = (msr >> 8) & 0xff;
 305                 return msr * 100000;
 306         }
 307
 308         if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points))
 309                 return 0;
 310
 311         msr &= 0xffff;
 312         for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
 313                 if (msr == centrino_model[cpu]->op_points[i].index)
 314                         return centrino_model[cpu]->op_points[i].frequency;
 315         }
 316         if (failsafe)
 317                 return centrino_model[cpu]->op_points[i-1].frequency;
 318         else
 319                 return 0;
 320 }
 321
 322 /* Return the current CPU frequency in kHz */
 323 static unsigned int get_cur_freq(unsigned int cpu)
 324 {
 325         unsigned l, h;
 326         unsigned clock_freq;
 327         cpumask_t saved_mask;
 328
 329         saved_mask = current->cpus_allowed;
 330         set_cpus_allowed(current, cpumask_of_cpu(cpu));
 331         if (smp_processor_id() != cpu)
 332                 return 0;
 333
 334         rdmsr(MSR_IA32_PERF_STATUS, l, h);
 335         clock_freq = extract_clock(l, cpu, 0);
 336
 337         if (unlikely(clock_freq == 0)) {
 338                 /*
 339                  * On some CPUs, we can see transient MSR values (which are
 340                  * not present in _PSS), while CPU is doing some automatic
 341                  * P-state transition (like TM2). Get the last freq set
 342                  * in PERF_CTL.
 343                  */
 344                 rdmsr(MSR_IA32_PERF_CTL, l, h);
 345                 clock_freq = extract_clock(l, cpu, 1);
 346         }
 347
 348         set_cpus_allowed(current, saved_mask);
 349         return clock_freq;
 350 }
 351
 352
 353 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 354
 355 static struct acpi_processor_performance p;
 356
 357 /*
 358  * centrino_cpu_init_acpi - register with ACPI P-States library
 359  *
 360  * Register with the ACPI P-States library (part of drivers/acpi/processor.c)
 361  * in order to determine correct frequency and voltage pairings by reading
 362  * the _PSS of the ACPI DSDT or SSDT tables.
 363  */
 364 static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
 365 {
 366         union acpi_object               arg0 = {ACPI_TYPE_BUFFER};
 367         u32                             arg0_buf[3];
 368         struct acpi_object_list         arg_list = {1, &arg0};
 369         unsigned long                   cur_freq;
 370         int                             result = 0, i;
 371         unsigned int                    cpu = policy->cpu;
 372
 373         /* _PDC settings */
 374         arg0.buffer.length = 12;
 375         arg0.buffer.pointer = (u8 *) arg0_buf;
 376         arg0_buf[0] = ACPI_PDC_REVISION_ID;
 377         arg0_buf[1] = 1;
 378         arg0_buf[2] = ACPI_PDC_EST_CAPABILITY_SMP_MSR;
 379
 380         p.pdc = &arg_list;
 381
 382         /* register with ACPI core */
 383         if (acpi_processor_register_performance(&p, cpu)) {
 384                 dprintk(KERN_INFO PFX "obtaining ACPI data failed\n");
 385                 return -EIO;
 386         }
 387
 388         /* verify the acpi_data */
 389         if (p.state_count <= 1) {
 390                 dprintk("No P-States\n");
 391                 result = -ENODEV;
 392                 goto err_unreg;
 393         }
 394
 395         if ((p.control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
 396             (p.status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
 397                 dprintk("Invalid control/status registers (%x - %x)\n",
 398                         p.control_register.space_id, p.status_register.space_id);
 399                 result = -EIO;
 400                 goto err_unreg;
 401         }
 402
 403         for (i=0; i<p.state_count; i++) {
 404                 if (p.states[i].control != p.states[i].status) {
 405                         dprintk("Different control (%llu) and status values (%llu)\n",
 406                                 p.states[i].control, p.states[i].status);
 407                         result = -EINVAL;
 408                         goto err_unreg;
 409                 }
 410
 411                 if (!p.states[i].core_frequency) {
 412                         dprintk("Zero core frequency for state %u\n", i);
 413                         result = -EINVAL;
 414                         goto err_unreg;
 415                 }
 416
 417                 if (p.states[i].core_frequency > p.states[0].core_frequency) {
 418                         dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i,
 419                                 p.states[i].core_frequency, p.states[0].core_frequency);
 420                         p.states[i].core_frequency = 0;
 421                         continue;
 422                 }
 423         }
 424
 425         centrino_model[cpu] = kmalloc(sizeof(struct cpu_model), GFP_KERNEL);
 426         if (!centrino_model[cpu]) {
 427                 result = -ENOMEM;
 428                 goto err_unreg;
 429         }
 430         memset(centrino_model[cpu], 0, sizeof(struct cpu_model));
 431
 432         centrino_model[cpu]->model_name=NULL;
 433         centrino_model[cpu]->max_freq = p.states[0].core_frequency * 1000;
 434         centrino_model[cpu]->op_points =  kmalloc(sizeof(struct cpufreq_frequency_table) *
 435                                              (p.state_count + 1), GFP_KERNEL);
 436         if (!centrino_model[cpu]->op_points) {
 437                 result = -ENOMEM;
 438                 goto err_kfree;
 439         }
 440
 441         for (i=0; i<p.state_count; i++) {
 442                 centrino_model[cpu]->op_points[i].index = p.states[i].control;
 443                 centrino_model[cpu]->op_points[i].frequency = p.states[i].core_frequency * 1000;
 444                 dprintk("adding state %i with frequency %u and control value %04x\n",
 445                         i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index);
 446         }
 447         centrino_model[cpu]->op_points[p.state_count].frequency = CPUFREQ_TABLE_END;
 448
 449         cur_freq = get_cur_freq(cpu);
 450
 451         for (i=0; i<p.state_count; i++) {
 452                 if (!p.states[i].core_frequency) {
 453                         dprintk("skipping state %u\n", i);
 454                         centrino_model[cpu]->op_points[i].frequency = CPUFREQ_ENTRY_INVALID;
 455                         continue;
 456                 }
 457
 458                 if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) !=
 459                     (centrino_model[cpu]->op_points[i].frequency)) {
 460                         dprintk("Invalid encoded frequency (%u vs. %u)\n",
 461                                 extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0),
 462                                 centrino_model[cpu]->op_points[i].frequency);
 463                         result = -EINVAL;
 464                         goto err_kfree_all;
 465                 }
 466
 467                 if (cur_freq == centrino_model[cpu]->op_points[i].frequency)
 468                         p.state = i;
 469         }
 470
 471         /* notify BIOS that we exist */
 472         acpi_processor_notify_smm(THIS_MODULE);
 473
 474         return 0;
 475
 476  err_kfree_all:
 477         kfree(centrino_model[cpu]->op_points);
 478  err_kfree:
 479         kfree(centrino_model[cpu]);
 480  err_unreg:
 481         acpi_processor_unregister_performance(&p, cpu);
 482         dprintk(KERN_INFO PFX "invalid ACPI data\n");
 483         return (result);
 484 }
 485 #else
 486 static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; }
 487 #endif
 488
 489 static int centrino_cpu_init(struct cpufreq_policy *policy)
 490 {
 491         struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
 492         unsigned freq;
 493         unsigned l, h;
 494         int ret;
 495         int i;
 496
 497         /* Only Intel makes Enhanced Speedstep-capable CPUs */
 498         if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
 499                 return -ENODEV;
 500
 501         if (is_const_loops_cpu(policy->cpu)) {
 502                 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
 503         }
 504
 505         if (centrino_cpu_init_acpi(policy)) {
 506                 if (policy->cpu != 0)
 507                         return -ENODEV;
 508
 509                 for (i = 0; i < N_IDS; i++)
 510                         if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
 511                                 break;
 512
 513                 if (i != N_IDS)
 514                         centrino_cpu[policy->cpu] = &cpu_ids[i];
 515
 516                 if (!centrino_cpu[policy->cpu]) {
 517                         dprintk(KERN_INFO PFX "found unsupported CPU with "
 518                         "Enhanced SpeedStep: send /proc/cpuinfo to "
 519                         MAINTAINER "\n");
 520                         return -ENODEV;
 521                 }
 522
 523                 if (centrino_cpu_init_table(policy)) {
 524                         return -ENODEV;
 525                 }
 526         }
 527
 528         /* Check to see if Enhanced SpeedStep is enabled, and try to
 529            enable it if not. */
 530         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 531
 532         if (!(l & (1<<16))) {
 533                 l |= (1<<16);
 534                 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
 535                 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
 536
 537                 /* check to see if it stuck */
 538                 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
 539                 if (!(l & (1<<16))) {
 540                         printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
 541                         return -ENODEV;
 542                 }
 543         }
 544
 545         freq = get_cur_freq(policy->cpu);
 546
 547         policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 548         policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
 549         policy->cur = freq;
 550
 551         dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
 552
 553         ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
 554         if (ret)
 555                 return (ret);
 556
 557         cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);
 558
 559         return 0;
 560 }
 561
 562 static int centrino_cpu_exit(struct cpufreq_policy *policy)
 563 {
 564         unsigned int cpu = policy->cpu;
 565
 566         if (!centrino_model[cpu])
 567                 return -ENODEV;
 568
 569         cpufreq_frequency_table_put_attr(cpu);
 570
 571 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
 572         if (!centrino_model[cpu]->model_name) {
 573                 dprintk("unregistering and freeing ACPI data\n");
 574                 acpi_processor_unregister_performance(&p, cpu);
 575                 kfree(centrino_model[cpu]->op_points);
 576                 kfree(centrino_model[cpu]);
 577         }
 578 #endif
 579
 580         centrino_model[cpu] = NULL;
 581
 582         return 0;
 583 }
 584
 585 /**
 586  * centrino_verify - verifies a new CPUFreq policy
 587  * @policy: new policy
 588  *
 589  * Limit must be within this model's frequency range at least one
 590  * border included.
 591  */
 592 static int centrino_verify (struct cpufreq_policy *policy)
 593 {
 594         return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
 595 }
 596
 597 /**
 598  * centrino_setpolicy - set a new CPUFreq policy
 599  * @policy: new policy
 600  * @target_freq: the target frequency
 601  * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
 602  *
 603  * Sets a new CPUFreq policy.
 604  */
 605 static int centrino_target (struct cpufreq_policy *policy,
 606                             unsigned int target_freq,
 607                             unsigned int relation)
 608 {
 609         unsigned int    newstate = 0;
 610         unsigned int    msr, oldmsr, h, cpu = policy->cpu;
 611         struct cpufreq_freqs    freqs;
 612         cpumask_t               saved_mask;
 613         int                     retval;
 614
 615         if (centrino_model[cpu] == NULL)
 616                 return -ENODEV;
 617
 618         /*
 619          * Support for SMP systems.
 620          * Make sure we are running on the CPU that wants to change frequency
 621          */
 622         saved_mask = current->cpus_allowed;
 623         set_cpus_allowed(current, policy->cpus);
 624         if (!cpu_isset(smp_processor_id(), policy->cpus)) {
 625                 dprintk("couldn't limit to CPUs in this domain\n");
 626                 return(-EAGAIN);
 627         }
 628
 629         if (cpufreq_frequency_table_target(policy, centrino_model[cpu]->op_points, target_freq,
 630                                            relation, &newstate)) {
 631                 retval = -EINVAL;
 632                 goto migrate_end;
 633         }
 634
 635         msr = centrino_model[cpu]->op_points[newstate].index;
 636         rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 637
 638         if (msr == (oldmsr & 0xffff)) {
 639                 retval = 0;
 640                 dprintk("no change needed - msr was and needs to be %x\n", oldmsr);
 641                 goto migrate_end;
 642         }
 643
 644         freqs.cpu = cpu;
 645         freqs.old = extract_clock(oldmsr, cpu, 0);
 646         freqs.new = extract_clock(msr, cpu, 0);
 647
 648         dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
 649                 target_freq, freqs.old, freqs.new, msr);
 650
 651         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 652
 653         /* all but 16 LSB are "reserved", so treat them with
 654            care */
 655         oldmsr &= ~0xffff;
 656         msr &= 0xffff;
 657         oldmsr |= msr;
 658
 659         wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
 660
 661         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 662
 663         retval = 0;
 664 migrate_end:
 665         set_cpus_allowed(current, saved_mask);
 666         return (retval);
 667 }
 668
 669 static struct freq_attr* centrino_attr[] = {
 670         &cpufreq_freq_attr_scaling_available_freqs,
 671         NULL,
 672 };
 673
 674 static struct cpufreq_driver centrino_driver = {
 675         .name           = "centrino", /* should be speedstep-centrino,
 676                                          but there's a 16 char limit */
 677         .init           = centrino_cpu_init,
 678         .exit           = centrino_cpu_exit,
 679         .verify         = centrino_verify,
 680         .target         = centrino_target,
 681         .get            = get_cur_freq,
 682         .attr           = centrino_attr,
 683         .owner          = THIS_MODULE,
 684 };
 685
 686
 687 /**
 688  * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
 689  *
 690  * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
 691  * unsupported devices, -ENOENT if there's no voltage table for this
 692  * particular CPU model, -EINVAL on problems during initiatization,
 693  * and zero on success.
 694  *
 695  * This is quite picky.  Not only does the CPU have to advertise the
 696  * "est" flag in the cpuid capability flags, we look for a specific
 697  * CPU model and stepping, and we need to have the exact model name in
 698  * our voltage tables.  That is, be paranoid about not releasing
 699  * someone's valuable magic smoke.
 700  */
 701 static int __init centrino_init(void)
 702 {
 703         struct cpuinfo_x86 *cpu = cpu_data;
 704
 705         if (!cpu_has(cpu, X86_FEATURE_EST))
 706                 return -ENODEV;
 707
 708         return cpufreq_register_driver(&centrino_driver);
 709 }
 710
 711 static void __exit centrino_exit(void)
 712 {
 713         cpufreq_unregister_driver(&centrino_driver);
 714 }
 715
 716 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
 717 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
 718 MODULE_LICENSE ("GPL");
 719
 720 late_initcall(centrino_init);
 721 module_exit(centrino_exit);