[PATCH] vmi: cpu cycles fix
[linux-2.6/mini2440.git] / arch / i386 / kernel / tsc.c
blob59222a04234b929cb98b086caaad46f021b259df
1 /*
2 * This code largely moved from arch/i386/kernel/timer/timer_tsc.c
3 * which was originally moved from arch/i386/kernel/time.c.
4 * See comments there for proper credits.
5 */
7 #include <linux/clocksource.h>
8 #include <linux/workqueue.h>
9 #include <linux/cpufreq.h>
10 #include <linux/jiffies.h>
11 #include <linux/init.h>
12 #include <linux/dmi.h>
14 #include <asm/delay.h>
15 #include <asm/tsc.h>
16 #include <asm/io.h>
17 #include <asm/timer.h>
19 #include "mach_timer.h"
22 * On some systems the TSC frequency does not
23 * change with the cpu frequency. So we need
24 * an extra value to store the TSC freq
26 unsigned int tsc_khz;
27 unsigned long long (*custom_sched_clock)(void);
29 int tsc_disable;
31 #ifdef CONFIG_X86_TSC
32 static int __init tsc_setup(char *str)
34 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
35 "cannot disable TSC.\n");
36 return 1;
38 #else
40 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
41 * in cpu/common.c
43 static int __init tsc_setup(char *str)
45 tsc_disable = 1;
47 return 1;
49 #endif
51 __setup("notsc", tsc_setup);
54 * code to mark and check if the TSC is unstable
55 * due to cpufreq or due to unsynced TSCs
57 static int tsc_unstable;
59 static inline int check_tsc_unstable(void)
61 return tsc_unstable;
64 /* Accellerators for sched_clock()
65 * convert from cycles(64bits) => nanoseconds (64bits)
66 * basic equation:
67 * ns = cycles / (freq / ns_per_sec)
68 * ns = cycles * (ns_per_sec / freq)
69 * ns = cycles * (10^9 / (cpu_khz * 10^3))
70 * ns = cycles * (10^6 / cpu_khz)
72 * Then we use scaling math (suggested by george@mvista.com) to get:
73 * ns = cycles * (10^6 * SC / cpu_khz) / SC
74 * ns = cycles * cyc2ns_scale / SC
76 * And since SC is a constant power of two, we can convert the div
77 * into a shift.
79 * We can use khz divisor instead of mhz to keep a better percision, since
80 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
81 * (mathieu.desnoyers@polymtl.ca)
83 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
85 static unsigned long cyc2ns_scale __read_mostly;
87 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
89 static inline void set_cyc2ns_scale(unsigned long cpu_khz)
91 cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
94 static inline unsigned long long cycles_2_ns(unsigned long long cyc)
96 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
100 * Scheduler clock - returns current time in nanosec units.
102 unsigned long long sched_clock(void)
104 unsigned long long this_offset;
107 * Fall back to jiffies if there's no TSC available:
109 if (unlikely(tsc_disable))
110 /* No locking but a rare wrong value is not a big deal: */
111 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
113 /* read the Time Stamp Counter: */
114 get_scheduled_cycles(this_offset);
116 /* return the value in ns */
117 return cycles_2_ns(this_offset);
120 unsigned long native_calculate_cpu_khz(void)
122 unsigned long long start, end;
123 unsigned long count;
124 u64 delta64;
125 int i;
126 unsigned long flags;
128 local_irq_save(flags);
130 /* run 3 times to ensure the cache is warm */
131 for (i = 0; i < 3; i++) {
132 mach_prepare_counter();
133 rdtscll(start);
134 mach_countup(&count);
135 rdtscll(end);
138 * Error: ECTCNEVERSET
139 * The CTC wasn't reliable: we got a hit on the very first read,
140 * or the CPU was so fast/slow that the quotient wouldn't fit in
141 * 32 bits..
143 if (count <= 1)
144 goto err;
146 delta64 = end - start;
148 /* cpu freq too fast: */
149 if (delta64 > (1ULL<<32))
150 goto err;
152 /* cpu freq too slow: */
153 if (delta64 <= CALIBRATE_TIME_MSEC)
154 goto err;
156 delta64 += CALIBRATE_TIME_MSEC/2; /* round for do_div */
157 do_div(delta64,CALIBRATE_TIME_MSEC);
159 local_irq_restore(flags);
160 return (unsigned long)delta64;
161 err:
162 local_irq_restore(flags);
163 return 0;
166 int recalibrate_cpu_khz(void)
168 #ifndef CONFIG_SMP
169 unsigned long cpu_khz_old = cpu_khz;
171 if (cpu_has_tsc) {
172 cpu_khz = calculate_cpu_khz();
173 tsc_khz = cpu_khz;
174 cpu_data[0].loops_per_jiffy =
175 cpufreq_scale(cpu_data[0].loops_per_jiffy,
176 cpu_khz_old, cpu_khz);
177 return 0;
178 } else
179 return -ENODEV;
180 #else
181 return -ENODEV;
182 #endif
185 EXPORT_SYMBOL(recalibrate_cpu_khz);
187 void __init tsc_init(void)
189 if (!cpu_has_tsc || tsc_disable)
190 goto out_no_tsc;
192 cpu_khz = calculate_cpu_khz();
193 tsc_khz = cpu_khz;
195 if (!cpu_khz)
196 goto out_no_tsc;
198 printk("Detected %lu.%03lu MHz processor.\n",
199 (unsigned long)cpu_khz / 1000,
200 (unsigned long)cpu_khz % 1000);
202 set_cyc2ns_scale(cpu_khz);
203 use_tsc_delay();
204 return;
206 out_no_tsc:
208 * Set the tsc_disable flag if there's no TSC support, this
209 * makes it a fast flag for the kernel to see whether it
210 * should be using the TSC.
212 tsc_disable = 1;
215 #ifdef CONFIG_CPU_FREQ
218 * if the CPU frequency is scaled, TSC-based delays will need a different
219 * loops_per_jiffy value to function properly.
221 static unsigned int ref_freq = 0;
222 static unsigned long loops_per_jiffy_ref = 0;
223 static unsigned long cpu_khz_ref = 0;
225 static int
226 time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
228 struct cpufreq_freqs *freq = data;
230 if (val != CPUFREQ_RESUMECHANGE && val != CPUFREQ_SUSPENDCHANGE)
231 write_seqlock_irq(&xtime_lock);
233 if (!ref_freq) {
234 if (!freq->old){
235 ref_freq = freq->new;
236 goto end;
238 ref_freq = freq->old;
239 loops_per_jiffy_ref = cpu_data[freq->cpu].loops_per_jiffy;
240 cpu_khz_ref = cpu_khz;
243 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
244 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
245 (val == CPUFREQ_RESUMECHANGE)) {
246 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
247 cpu_data[freq->cpu].loops_per_jiffy =
248 cpufreq_scale(loops_per_jiffy_ref,
249 ref_freq, freq->new);
251 if (cpu_khz) {
253 if (num_online_cpus() == 1)
254 cpu_khz = cpufreq_scale(cpu_khz_ref,
255 ref_freq, freq->new);
256 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) {
257 tsc_khz = cpu_khz;
258 set_cyc2ns_scale(cpu_khz);
260 * TSC based sched_clock turns
261 * to junk w/ cpufreq
263 mark_tsc_unstable();
267 end:
268 if (val != CPUFREQ_RESUMECHANGE && val != CPUFREQ_SUSPENDCHANGE)
269 write_sequnlock_irq(&xtime_lock);
271 return 0;
274 static struct notifier_block time_cpufreq_notifier_block = {
275 .notifier_call = time_cpufreq_notifier
278 static int __init cpufreq_tsc(void)
280 return cpufreq_register_notifier(&time_cpufreq_notifier_block,
281 CPUFREQ_TRANSITION_NOTIFIER);
283 core_initcall(cpufreq_tsc);
285 #endif
287 /* clock source code */
289 static unsigned long current_tsc_khz = 0;
291 static cycle_t read_tsc(void)
293 cycle_t ret;
295 rdtscll(ret);
297 return ret;
300 static struct clocksource clocksource_tsc = {
301 .name = "tsc",
302 .rating = 300,
303 .read = read_tsc,
304 .mask = CLOCKSOURCE_MASK(64),
305 .mult = 0, /* to be set */
306 .shift = 22,
307 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
308 CLOCK_SOURCE_MUST_VERIFY,
311 void mark_tsc_unstable(void)
313 if (!tsc_unstable) {
314 tsc_unstable = 1;
315 /* Can be called before registration */
316 if (clocksource_tsc.mult)
317 clocksource_change_rating(&clocksource_tsc, 0);
318 else
319 clocksource_tsc.rating = 0;
322 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
324 static int __init dmi_mark_tsc_unstable(struct dmi_system_id *d)
326 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
327 d->ident);
328 tsc_unstable = 1;
329 return 0;
332 /* List of systems that have known TSC problems */
333 static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
335 .callback = dmi_mark_tsc_unstable,
336 .ident = "IBM Thinkpad 380XD",
337 .matches = {
338 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
339 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
346 * Make an educated guess if the TSC is trustworthy and synchronized
347 * over all CPUs.
349 __cpuinit int unsynchronized_tsc(void)
351 if (!cpu_has_tsc || tsc_unstable)
352 return 1;
354 * Intel systems are normally all synchronized.
355 * Exceptions must mark TSC as unstable:
357 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
358 /* assume multi socket systems are not synchronized: */
359 if (num_possible_cpus() > 1)
360 tsc_unstable = 1;
362 return tsc_unstable;
366 * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
368 #ifdef CONFIG_MGEODE_LX
369 /* RTSC counts during suspend */
370 #define RTSC_SUSP 0x100
372 static void __init check_geode_tsc_reliable(void)
374 unsigned long val;
376 rdmsrl(MSR_GEODE_BUSCONT_CONF0, val);
377 if ((val & RTSC_SUSP))
378 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
380 #else
381 static inline void check_geode_tsc_reliable(void) { }
382 #endif
384 static int __init init_tsc_clocksource(void)
387 if (cpu_has_tsc && tsc_khz && !tsc_disable) {
388 /* check blacklist */
389 dmi_check_system(bad_tsc_dmi_table);
391 unsynchronized_tsc();
392 check_geode_tsc_reliable();
393 current_tsc_khz = tsc_khz;
394 clocksource_tsc.mult = clocksource_khz2mult(current_tsc_khz,
395 clocksource_tsc.shift);
396 /* lower the rating if we already know its unstable: */
397 if (check_tsc_unstable()) {
398 clocksource_tsc.rating = 0;
399 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
402 return clocksource_register(&clocksource_tsc);
405 return 0;
408 module_init(init_tsc_clocksource);