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AMD IOMMU: add stats counter for map_single requests
[linux-2.6/mini2440.git] / arch / x86 / kernel / amd_iommu.c
blobef377865eb7637e923abfb725a7658256fea32ec
1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/iommu-helper.h>
26 #ifdef CONFIG_IOMMU_API
27 #include <linux/iommu.h>
28 #endif
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
31 #include <asm/gart.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
34
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36
37 #define EXIT_LOOP_COUNT 10000000
38
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44
45 #ifdef CONFIG_IOMMU_API
46 static struct iommu_ops amd_iommu_ops;
47 #endif
48
49 /*
50 * general struct to manage commands send to an IOMMU
51 */
52 struct iommu_cmd {
53 u32 data[4];
54 };
55
56 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
57 struct unity_map_entry *e);
58 static struct dma_ops_domain *find_protection_domain(u16 devid);
59
60
61 #ifdef CONFIG_AMD_IOMMU_STATS
62
63 /*
64 * Initialization code for statistics collection
65 */
66
67 DECLARE_STATS_COUNTER(compl_wait);
68 DECLARE_STATS_COUNTER(cnt_map_single);
69
70 static struct dentry *stats_dir;
71 static struct dentry *de_isolate;
72 static struct dentry *de_fflush;
73
74 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
75 {
76 if (stats_dir == NULL)
77 return;
78
79 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
80 &cnt->value);
81 }
82
83 static void amd_iommu_stats_init(void)
84 {
85 stats_dir = debugfs_create_dir("amd-iommu", NULL);
86 if (stats_dir == NULL)
87 return;
88
89 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
90 (u32 *)&amd_iommu_isolate);
91
92 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
93 (u32 *)&amd_iommu_unmap_flush);
94
95 amd_iommu_stats_add(&compl_wait);
96 amd_iommu_stats_add(&cnt_map_single);
97 }
98
99 #endif
100
101 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
102 static int iommu_has_npcache(struct amd_iommu *iommu)
103 {
104 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
105 }
106
107 /****************************************************************************
108 *
109 * Interrupt handling functions
110 *
111 ****************************************************************************/
112
113 static void iommu_print_event(void *__evt)
114 {
115 u32 *event = __evt;
116 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
117 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
118 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
119 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
120 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
121
122 printk(KERN_ERR "AMD IOMMU: Event logged [");
123
124 switch (type) {
125 case EVENT_TYPE_ILL_DEV:
126 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
127 "address=0x%016llx flags=0x%04x]\n",
128 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
129 address, flags);
130 break;
131 case EVENT_TYPE_IO_FAULT:
132 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
133 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
134 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
135 domid, address, flags);
136 break;
137 case EVENT_TYPE_DEV_TAB_ERR:
138 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
139 "address=0x%016llx flags=0x%04x]\n",
140 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
141 address, flags);
142 break;
143 case EVENT_TYPE_PAGE_TAB_ERR:
144 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
145 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
146 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
147 domid, address, flags);
148 break;
149 case EVENT_TYPE_ILL_CMD:
150 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
151 break;
152 case EVENT_TYPE_CMD_HARD_ERR:
153 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
154 "flags=0x%04x]\n", address, flags);
155 break;
156 case EVENT_TYPE_IOTLB_INV_TO:
157 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
158 "address=0x%016llx]\n",
159 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
160 address);
161 break;
162 case EVENT_TYPE_INV_DEV_REQ:
163 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
164 "address=0x%016llx flags=0x%04x]\n",
165 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
166 address, flags);
167 break;
168 default:
169 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
170 }
171 }
172
173 static void iommu_poll_events(struct amd_iommu *iommu)
174 {
175 u32 head, tail;
176 unsigned long flags;
177
178 spin_lock_irqsave(&iommu->lock, flags);
179
180 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
181 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
182
183 while (head != tail) {
184 iommu_print_event(iommu->evt_buf + head);
185 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
186 }
187
188 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
189
190 spin_unlock_irqrestore(&iommu->lock, flags);
191 }
192
193 irqreturn_t amd_iommu_int_handler(int irq, void *data)
194 {
195 struct amd_iommu *iommu;
196
197 list_for_each_entry(iommu, &amd_iommu_list, list)
198 iommu_poll_events(iommu);
199
200 return IRQ_HANDLED;
201 }
202
203 /****************************************************************************
204 *
205 * IOMMU command queuing functions
206 *
207 ****************************************************************************/
208
209 /*
210 * Writes the command to the IOMMUs command buffer and informs the
211 * hardware about the new command. Must be called with iommu->lock held.
212 */
213 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
214 {
215 u32 tail, head;
216 u8 *target;
217
218 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
219 target = iommu->cmd_buf + tail;
220 memcpy_toio(target, cmd, sizeof(*cmd));
221 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
222 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
223 if (tail == head)
224 return -ENOMEM;
225 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
226
227 return 0;
228 }
229
230 /*
231 * General queuing function for commands. Takes iommu->lock and calls
232 * __iommu_queue_command().
233 */
234 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
235 {
236 unsigned long flags;
237 int ret;
238
239 spin_lock_irqsave(&iommu->lock, flags);
240 ret = __iommu_queue_command(iommu, cmd);
241 if (!ret)
242 iommu->need_sync = true;
243 spin_unlock_irqrestore(&iommu->lock, flags);
244
245 return ret;
246 }
247
248 /*
249 * This function waits until an IOMMU has completed a completion
250 * wait command
251 */
252 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
253 {
254 int ready = 0;
255 unsigned status = 0;
256 unsigned long i = 0;
257
258 INC_STATS_COUNTER(compl_wait);
259
260 while (!ready && (i < EXIT_LOOP_COUNT)) {
261 ++i;
262 /* wait for the bit to become one */
263 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
264 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
265 }
266
267 /* set bit back to zero */
268 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
269 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
270
271 if (unlikely(i == EXIT_LOOP_COUNT))
272 panic("AMD IOMMU: Completion wait loop failed\n");
273 }
274
275 /*
276 * This function queues a completion wait command into the command
277 * buffer of an IOMMU
278 */
279 static int __iommu_completion_wait(struct amd_iommu *iommu)
280 {
281 struct iommu_cmd cmd;
282
283 memset(&cmd, 0, sizeof(cmd));
284 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
285 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
286
287 return __iommu_queue_command(iommu, &cmd);
288 }
289
290 /*
291 * This function is called whenever we need to ensure that the IOMMU has
292 * completed execution of all commands we sent. It sends a
293 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
294 * us about that by writing a value to a physical address we pass with
295 * the command.
296 */
297 static int iommu_completion_wait(struct amd_iommu *iommu)
298 {
299 int ret = 0;
300 unsigned long flags;
301
302 spin_lock_irqsave(&iommu->lock, flags);
303
304 if (!iommu->need_sync)
305 goto out;
306
307 ret = __iommu_completion_wait(iommu);
308
309 iommu->need_sync = false;
310
311 if (ret)
312 goto out;
313
314 __iommu_wait_for_completion(iommu);
315
316 out:
317 spin_unlock_irqrestore(&iommu->lock, flags);
318
319 return 0;
320 }
321
322 /*
323 * Command send function for invalidating a device table entry
324 */
325 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
326 {
327 struct iommu_cmd cmd;
328 int ret;
329
330 BUG_ON(iommu == NULL);
331
332 memset(&cmd, 0, sizeof(cmd));
333 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
334 cmd.data[0] = devid;
335
336 ret = iommu_queue_command(iommu, &cmd);
337
338 return ret;
339 }
340
341 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
342 u16 domid, int pde, int s)
343 {
344 memset(cmd, 0, sizeof(*cmd));
345 address &= PAGE_MASK;
346 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
347 cmd->data[1] |= domid;
348 cmd->data[2] = lower_32_bits(address);
349 cmd->data[3] = upper_32_bits(address);
350 if (s) /* size bit - we flush more than one 4kb page */
351 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
352 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
353 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
354 }
355
356 /*
357 * Generic command send function for invalidaing TLB entries
358 */
359 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
360 u64 address, u16 domid, int pde, int s)
361 {
362 struct iommu_cmd cmd;
363 int ret;
364
365 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
366
367 ret = iommu_queue_command(iommu, &cmd);
368
369 return ret;
370 }
371
372 /*
373 * TLB invalidation function which is called from the mapping functions.
374 * It invalidates a single PTE if the range to flush is within a single
375 * page. Otherwise it flushes the whole TLB of the IOMMU.
376 */
377 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
378 u64 address, size_t size)
379 {
380 int s = 0;
381 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
382
383 address &= PAGE_MASK;
384
385 if (pages > 1) {
386 /*
387 * If we have to flush more than one page, flush all
388 * TLB entries for this domain
389 */
390 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
391 s = 1;
392 }
393
394 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
395
396 return 0;
397 }
398
399 /* Flush the whole IO/TLB for a given protection domain */
400 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
401 {
402 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
403
404 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
405 }
406
407 #ifdef CONFIG_IOMMU_API
408 /*
409 * This function is used to flush the IO/TLB for a given protection domain
410 * on every IOMMU in the system
411 */
412 static void iommu_flush_domain(u16 domid)
413 {
414 unsigned long flags;
415 struct amd_iommu *iommu;
416 struct iommu_cmd cmd;
417
418 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
419 domid, 1, 1);
420
421 list_for_each_entry(iommu, &amd_iommu_list, list) {
422 spin_lock_irqsave(&iommu->lock, flags);
423 __iommu_queue_command(iommu, &cmd);
424 __iommu_completion_wait(iommu);
425 __iommu_wait_for_completion(iommu);
426 spin_unlock_irqrestore(&iommu->lock, flags);
427 }
428 }
429 #endif
430
431 /****************************************************************************
432 *
433 * The functions below are used the create the page table mappings for
434 * unity mapped regions.
435 *
436 ****************************************************************************/
437
438 /*
439 * Generic mapping functions. It maps a physical address into a DMA
440 * address space. It allocates the page table pages if necessary.
441 * In the future it can be extended to a generic mapping function
442 * supporting all features of AMD IOMMU page tables like level skipping
443 * and full 64 bit address spaces.
444 */
445 static int iommu_map_page(struct protection_domain *dom,
446 unsigned long bus_addr,
447 unsigned long phys_addr,
448 int prot)
449 {
450 u64 __pte, *pte, *page;
451
452 bus_addr = PAGE_ALIGN(bus_addr);
453 phys_addr = PAGE_ALIGN(phys_addr);
454
455 /* only support 512GB address spaces for now */
456 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
457 return -EINVAL;
458
459 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
460
461 if (!IOMMU_PTE_PRESENT(*pte)) {
462 page = (u64 *)get_zeroed_page(GFP_KERNEL);
463 if (!page)
464 return -ENOMEM;
465 *pte = IOMMU_L2_PDE(virt_to_phys(page));
466 }
467
468 pte = IOMMU_PTE_PAGE(*pte);
469 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
470
471 if (!IOMMU_PTE_PRESENT(*pte)) {
472 page = (u64 *)get_zeroed_page(GFP_KERNEL);
473 if (!page)
474 return -ENOMEM;
475 *pte = IOMMU_L1_PDE(virt_to_phys(page));
476 }
477
478 pte = IOMMU_PTE_PAGE(*pte);
479 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
480
481 if (IOMMU_PTE_PRESENT(*pte))
482 return -EBUSY;
483
484 __pte = phys_addr | IOMMU_PTE_P;
485 if (prot & IOMMU_PROT_IR)
486 __pte |= IOMMU_PTE_IR;
487 if (prot & IOMMU_PROT_IW)
488 __pte |= IOMMU_PTE_IW;
489
490 *pte = __pte;
491
492 return 0;
493 }
494
495 #ifdef CONFIG_IOMMU_API
496 static void iommu_unmap_page(struct protection_domain *dom,
497 unsigned long bus_addr)
498 {
499 u64 *pte;
500
501 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
502
503 if (!IOMMU_PTE_PRESENT(*pte))
504 return;
505
506 pte = IOMMU_PTE_PAGE(*pte);
507 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
508
509 if (!IOMMU_PTE_PRESENT(*pte))
510 return;
511
512 pte = IOMMU_PTE_PAGE(*pte);
513 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
514
515 *pte = 0;
516 }
517 #endif
518
519 /*
520 * This function checks if a specific unity mapping entry is needed for
521 * this specific IOMMU.
522 */
523 static int iommu_for_unity_map(struct amd_iommu *iommu,
524 struct unity_map_entry *entry)
525 {
526 u16 bdf, i;
527
528 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
529 bdf = amd_iommu_alias_table[i];
530 if (amd_iommu_rlookup_table[bdf] == iommu)
531 return 1;
532 }
533
534 return 0;
535 }
536
537 /*
538 * Init the unity mappings for a specific IOMMU in the system
539 *
540 * Basically iterates over all unity mapping entries and applies them to
541 * the default domain DMA of that IOMMU if necessary.
542 */
543 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
544 {
545 struct unity_map_entry *entry;
546 int ret;
547
548 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
549 if (!iommu_for_unity_map(iommu, entry))
550 continue;
551 ret = dma_ops_unity_map(iommu->default_dom, entry);
552 if (ret)
553 return ret;
554 }
555
556 return 0;
557 }
558
559 /*
560 * This function actually applies the mapping to the page table of the
561 * dma_ops domain.
562 */
563 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
564 struct unity_map_entry *e)
565 {
566 u64 addr;
567 int ret;
568
569 for (addr = e->address_start; addr < e->address_end;
570 addr += PAGE_SIZE) {
571 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
572 if (ret)
573 return ret;
574 /*
575 * if unity mapping is in aperture range mark the page
576 * as allocated in the aperture
577 */
578 if (addr < dma_dom->aperture_size)
579 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
580 }
581
582 return 0;
583 }
584
585 /*
586 * Inits the unity mappings required for a specific device
587 */
588 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
589 u16 devid)
590 {
591 struct unity_map_entry *e;
592 int ret;
593
594 list_for_each_entry(e, &amd_iommu_unity_map, list) {
595 if (!(devid >= e->devid_start && devid <= e->devid_end))
596 continue;
597 ret = dma_ops_unity_map(dma_dom, e);
598 if (ret)
599 return ret;
600 }
601
602 return 0;
603 }
604
605 /****************************************************************************
606 *
607 * The next functions belong to the address allocator for the dma_ops
608 * interface functions. They work like the allocators in the other IOMMU
609 * drivers. Its basically a bitmap which marks the allocated pages in
610 * the aperture. Maybe it could be enhanced in the future to a more
611 * efficient allocator.
612 *
613 ****************************************************************************/
614
615 /*
616 * The address allocator core function.
617 *
618 * called with domain->lock held
619 */
620 static unsigned long dma_ops_alloc_addresses(struct device *dev,
621 struct dma_ops_domain *dom,
622 unsigned int pages,
623 unsigned long align_mask,
624 u64 dma_mask)
625 {
626 unsigned long limit;
627 unsigned long address;
628 unsigned long boundary_size;
629
630 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
631 PAGE_SIZE) >> PAGE_SHIFT;
632 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
633 dma_mask >> PAGE_SHIFT);
634
635 if (dom->next_bit >= limit) {
636 dom->next_bit = 0;
637 dom->need_flush = true;
638 }
639
640 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
641 0 , boundary_size, align_mask);
642 if (address == -1) {
643 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
644 0, boundary_size, align_mask);
645 dom->need_flush = true;
646 }
647
648 if (likely(address != -1)) {
649 dom->next_bit = address + pages;
650 address <<= PAGE_SHIFT;
651 } else
652 address = bad_dma_address;
653
654 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
655
656 return address;
657 }
658
659 /*
660 * The address free function.
661 *
662 * called with domain->lock held
663 */
664 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
665 unsigned long address,
666 unsigned int pages)
667 {
668 address >>= PAGE_SHIFT;
669 iommu_area_free(dom->bitmap, address, pages);
670
671 if (address >= dom->next_bit)
672 dom->need_flush = true;
673 }
674
675 /****************************************************************************
676 *
677 * The next functions belong to the domain allocation. A domain is
678 * allocated for every IOMMU as the default domain. If device isolation
679 * is enabled, every device get its own domain. The most important thing
680 * about domains is the page table mapping the DMA address space they
681 * contain.
682 *
683 ****************************************************************************/
684
685 static u16 domain_id_alloc(void)
686 {
687 unsigned long flags;
688 int id;
689
690 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
691 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
692 BUG_ON(id == 0);
693 if (id > 0 && id < MAX_DOMAIN_ID)
694 __set_bit(id, amd_iommu_pd_alloc_bitmap);
695 else
696 id = 0;
697 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
698
699 return id;
700 }
701
702 #ifdef CONFIG_IOMMU_API
703 static void domain_id_free(int id)
704 {
705 unsigned long flags;
706
707 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
708 if (id > 0 && id < MAX_DOMAIN_ID)
709 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
710 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
711 }
712 #endif
713
714 /*
715 * Used to reserve address ranges in the aperture (e.g. for exclusion
716 * ranges.
717 */
718 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
719 unsigned long start_page,
720 unsigned int pages)
721 {
722 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
723
724 if (start_page + pages > last_page)
725 pages = last_page - start_page;
726
727 iommu_area_reserve(dom->bitmap, start_page, pages);
728 }
729
730 static void free_pagetable(struct protection_domain *domain)
731 {
732 int i, j;
733 u64 *p1, *p2, *p3;
734
735 p1 = domain->pt_root;
736
737 if (!p1)
738 return;
739
740 for (i = 0; i < 512; ++i) {
741 if (!IOMMU_PTE_PRESENT(p1[i]))
742 continue;
743
744 p2 = IOMMU_PTE_PAGE(p1[i]);
745 for (j = 0; j < 512; ++j) {
746 if (!IOMMU_PTE_PRESENT(p2[j]))
747 continue;
748 p3 = IOMMU_PTE_PAGE(p2[j]);
749 free_page((unsigned long)p3);
750 }
751
752 free_page((unsigned long)p2);
753 }
754
755 free_page((unsigned long)p1);
756
757 domain->pt_root = NULL;
758 }
759
760 /*
761 * Free a domain, only used if something went wrong in the
762 * allocation path and we need to free an already allocated page table
763 */
764 static void dma_ops_domain_free(struct dma_ops_domain *dom)
765 {
766 if (!dom)
767 return;
768
769 free_pagetable(&dom->domain);
770
771 kfree(dom->pte_pages);
772
773 kfree(dom->bitmap);
774
775 kfree(dom);
776 }
777
778 /*
779 * Allocates a new protection domain usable for the dma_ops functions.
780 * It also intializes the page table and the address allocator data
781 * structures required for the dma_ops interface
782 */
783 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
784 unsigned order)
785 {
786 struct dma_ops_domain *dma_dom;
787 unsigned i, num_pte_pages;
788 u64 *l2_pde;
789 u64 address;
790
791 /*
792 * Currently the DMA aperture must be between 32 MB and 1GB in size
793 */
794 if ((order < 25) || (order > 30))
795 return NULL;
796
797 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
798 if (!dma_dom)
799 return NULL;
800
801 spin_lock_init(&dma_dom->domain.lock);
802
803 dma_dom->domain.id = domain_id_alloc();
804 if (dma_dom->domain.id == 0)
805 goto free_dma_dom;
806 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
807 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
808 dma_dom->domain.flags = PD_DMA_OPS_MASK;
809 dma_dom->domain.priv = dma_dom;
810 if (!dma_dom->domain.pt_root)
811 goto free_dma_dom;
812 dma_dom->aperture_size = (1ULL << order);
813 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
814 GFP_KERNEL);
815 if (!dma_dom->bitmap)
816 goto free_dma_dom;
817 /*
818 * mark the first page as allocated so we never return 0 as
819 * a valid dma-address. So we can use 0 as error value
820 */
821 dma_dom->bitmap[0] = 1;
822 dma_dom->next_bit = 0;
823
824 dma_dom->need_flush = false;
825 dma_dom->target_dev = 0xffff;
826
827 /* Intialize the exclusion range if necessary */
828 if (iommu->exclusion_start &&
829 iommu->exclusion_start < dma_dom->aperture_size) {
830 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
831 int pages = iommu_num_pages(iommu->exclusion_start,
832 iommu->exclusion_length,
833 PAGE_SIZE);
834 dma_ops_reserve_addresses(dma_dom, startpage, pages);
835 }
836
837 /*
838 * At the last step, build the page tables so we don't need to
839 * allocate page table pages in the dma_ops mapping/unmapping
840 * path.
841 */
842 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
843 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
844 GFP_KERNEL);
845 if (!dma_dom->pte_pages)
846 goto free_dma_dom;
847
848 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
849 if (l2_pde == NULL)
850 goto free_dma_dom;
851
852 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
853
854 for (i = 0; i < num_pte_pages; ++i) {
855 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
856 if (!dma_dom->pte_pages[i])
857 goto free_dma_dom;
858 address = virt_to_phys(dma_dom->pte_pages[i]);
859 l2_pde[i] = IOMMU_L1_PDE(address);
860 }
861
862 return dma_dom;
863
864 free_dma_dom:
865 dma_ops_domain_free(dma_dom);
866
867 return NULL;
868 }
869
870 /*
871 * little helper function to check whether a given protection domain is a
872 * dma_ops domain
873 */
874 static bool dma_ops_domain(struct protection_domain *domain)
875 {
876 return domain->flags & PD_DMA_OPS_MASK;
877 }
878
879 /*
880 * Find out the protection domain structure for a given PCI device. This
881 * will give us the pointer to the page table root for example.
882 */
883 static struct protection_domain *domain_for_device(u16 devid)
884 {
885 struct protection_domain *dom;
886 unsigned long flags;
887
888 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
889 dom = amd_iommu_pd_table[devid];
890 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
891
892 return dom;
893 }
894
895 /*
896 * If a device is not yet associated with a domain, this function does
897 * assigns it visible for the hardware
898 */
899 static void attach_device(struct amd_iommu *iommu,
900 struct protection_domain *domain,
901 u16 devid)
902 {
903 unsigned long flags;
904 u64 pte_root = virt_to_phys(domain->pt_root);
905
906 domain->dev_cnt += 1;
907
908 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
909 << DEV_ENTRY_MODE_SHIFT;
910 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
911
912 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
913 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
914 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
915 amd_iommu_dev_table[devid].data[2] = domain->id;
916
917 amd_iommu_pd_table[devid] = domain;
918 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
919
920 iommu_queue_inv_dev_entry(iommu, devid);
921 }
922
923 /*
924 * Removes a device from a protection domain (unlocked)
925 */
926 static void __detach_device(struct protection_domain *domain, u16 devid)
927 {
928
929 /* lock domain */
930 spin_lock(&domain->lock);
931
932 /* remove domain from the lookup table */
933 amd_iommu_pd_table[devid] = NULL;
934
935 /* remove entry from the device table seen by the hardware */
936 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
937 amd_iommu_dev_table[devid].data[1] = 0;
938 amd_iommu_dev_table[devid].data[2] = 0;
939
940 /* decrease reference counter */
941 domain->dev_cnt -= 1;
942
943 /* ready */
944 spin_unlock(&domain->lock);
945 }
946
947 /*
948 * Removes a device from a protection domain (with devtable_lock held)
949 */
950 static void detach_device(struct protection_domain *domain, u16 devid)
951 {
952 unsigned long flags;
953
954 /* lock device table */
955 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
956 __detach_device(domain, devid);
957 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
958 }
959
960 static int device_change_notifier(struct notifier_block *nb,
961 unsigned long action, void *data)
962 {
963 struct device *dev = data;
964 struct pci_dev *pdev = to_pci_dev(dev);
965 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
966 struct protection_domain *domain;
967 struct dma_ops_domain *dma_domain;
968 struct amd_iommu *iommu;
969 int order = amd_iommu_aperture_order;
970 unsigned long flags;
971
972 if (devid > amd_iommu_last_bdf)
973 goto out;
974
975 devid = amd_iommu_alias_table[devid];
976
977 iommu = amd_iommu_rlookup_table[devid];
978 if (iommu == NULL)
979 goto out;
980
981 domain = domain_for_device(devid);
982
983 if (domain && !dma_ops_domain(domain))
984 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
985 "to a non-dma-ops domain\n", dev_name(dev));
986
987 switch (action) {
988 case BUS_NOTIFY_BOUND_DRIVER:
989 if (domain)
990 goto out;
991 dma_domain = find_protection_domain(devid);
992 if (!dma_domain)
993 dma_domain = iommu->default_dom;
994 attach_device(iommu, &dma_domain->domain, devid);
995 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
996 "device %s\n", dma_domain->domain.id, dev_name(dev));
997 break;
998 case BUS_NOTIFY_UNBIND_DRIVER:
999 if (!domain)
1000 goto out;
1001 detach_device(domain, devid);
1002 break;
1003 case BUS_NOTIFY_ADD_DEVICE:
1004 /* allocate a protection domain if a device is added */
1005 dma_domain = find_protection_domain(devid);
1006 if (dma_domain)
1007 goto out;
1008 dma_domain = dma_ops_domain_alloc(iommu, order);
1009 if (!dma_domain)
1010 goto out;
1011 dma_domain->target_dev = devid;
1012
1013 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1014 list_add_tail(&dma_domain->list, &iommu_pd_list);
1015 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1016
1017 break;
1018 default:
1019 goto out;
1020 }
1021
1022 iommu_queue_inv_dev_entry(iommu, devid);
1023 iommu_completion_wait(iommu);
1024
1025 out:
1026 return 0;
1027 }
1028
1029 struct notifier_block device_nb = {
1030 .notifier_call = device_change_notifier,
1031 };
1032
1033 /*****************************************************************************
1034 *
1035 * The next functions belong to the dma_ops mapping/unmapping code.
1036 *
1037 *****************************************************************************/
1038
1039 /*
1040 * This function checks if the driver got a valid device from the caller to
1041 * avoid dereferencing invalid pointers.
1042 */
1043 static bool check_device(struct device *dev)
1044 {
1045 if (!dev || !dev->dma_mask)
1046 return false;
1047
1048 return true;
1049 }
1050
1051 /*
1052 * In this function the list of preallocated protection domains is traversed to
1053 * find the domain for a specific device
1054 */
1055 static struct dma_ops_domain *find_protection_domain(u16 devid)
1056 {
1057 struct dma_ops_domain *entry, *ret = NULL;
1058 unsigned long flags;
1059
1060 if (list_empty(&iommu_pd_list))
1061 return NULL;
1062
1063 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1064
1065 list_for_each_entry(entry, &iommu_pd_list, list) {
1066 if (entry->target_dev == devid) {
1067 ret = entry;
1068 break;
1069 }
1070 }
1071
1072 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1073
1074 return ret;
1075 }
1076
1077 /*
1078 * In the dma_ops path we only have the struct device. This function
1079 * finds the corresponding IOMMU, the protection domain and the
1080 * requestor id for a given device.
1081 * If the device is not yet associated with a domain this is also done
1082 * in this function.
1083 */
1084 static int get_device_resources(struct device *dev,
1085 struct amd_iommu **iommu,
1086 struct protection_domain **domain,
1087 u16 *bdf)
1088 {
1089 struct dma_ops_domain *dma_dom;
1090 struct pci_dev *pcidev;
1091 u16 _bdf;
1092
1093 *iommu = NULL;
1094 *domain = NULL;
1095 *bdf = 0xffff;
1096
1097 if (dev->bus != &pci_bus_type)
1098 return 0;
1099
1100 pcidev = to_pci_dev(dev);
1101 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1102
1103 /* device not translated by any IOMMU in the system? */
1104 if (_bdf > amd_iommu_last_bdf)
1105 return 0;
1106
1107 *bdf = amd_iommu_alias_table[_bdf];
1108
1109 *iommu = amd_iommu_rlookup_table[*bdf];
1110 if (*iommu == NULL)
1111 return 0;
1112 *domain = domain_for_device(*bdf);
1113 if (*domain == NULL) {
1114 dma_dom = find_protection_domain(*bdf);
1115 if (!dma_dom)
1116 dma_dom = (*iommu)->default_dom;
1117 *domain = &dma_dom->domain;
1118 attach_device(*iommu, *domain, *bdf);
1119 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1120 "device %s\n", (*domain)->id, dev_name(dev));
1121 }
1122
1123 if (domain_for_device(_bdf) == NULL)
1124 attach_device(*iommu, *domain, _bdf);
1125
1126 return 1;
1127 }
1128
1129 /*
1130 * This is the generic map function. It maps one 4kb page at paddr to
1131 * the given address in the DMA address space for the domain.
1132 */
1133 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1134 struct dma_ops_domain *dom,
1135 unsigned long address,
1136 phys_addr_t paddr,
1137 int direction)
1138 {
1139 u64 *pte, __pte;
1140
1141 WARN_ON(address > dom->aperture_size);
1142
1143 paddr &= PAGE_MASK;
1144
1145 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1146 pte += IOMMU_PTE_L0_INDEX(address);
1147
1148 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1149
1150 if (direction == DMA_TO_DEVICE)
1151 __pte |= IOMMU_PTE_IR;
1152 else if (direction == DMA_FROM_DEVICE)
1153 __pte |= IOMMU_PTE_IW;
1154 else if (direction == DMA_BIDIRECTIONAL)
1155 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1156
1157 WARN_ON(*pte);
1158
1159 *pte = __pte;
1160
1161 return (dma_addr_t)address;
1162 }
1163
1164 /*
1165 * The generic unmapping function for on page in the DMA address space.
1166 */
1167 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1168 struct dma_ops_domain *dom,
1169 unsigned long address)
1170 {
1171 u64 *pte;
1172
1173 if (address >= dom->aperture_size)
1174 return;
1175
1176 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1177
1178 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1179 pte += IOMMU_PTE_L0_INDEX(address);
1180
1181 WARN_ON(!*pte);
1182
1183 *pte = 0ULL;
1184 }
1185
1186 /*
1187 * This function contains common code for mapping of a physically
1188 * contiguous memory region into DMA address space. It is used by all
1189 * mapping functions provided with this IOMMU driver.
1190 * Must be called with the domain lock held.
1191 */
1192 static dma_addr_t __map_single(struct device *dev,
1193 struct amd_iommu *iommu,
1194 struct dma_ops_domain *dma_dom,
1195 phys_addr_t paddr,
1196 size_t size,
1197 int dir,
1198 bool align,
1199 u64 dma_mask)
1200 {
1201 dma_addr_t offset = paddr & ~PAGE_MASK;
1202 dma_addr_t address, start;
1203 unsigned int pages;
1204 unsigned long align_mask = 0;
1205 int i;
1206
1207 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1208 paddr &= PAGE_MASK;
1209
1210 if (align)
1211 align_mask = (1UL << get_order(size)) - 1;
1212
1213 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1214 dma_mask);
1215 if (unlikely(address == bad_dma_address))
1216 goto out;
1217
1218 start = address;
1219 for (i = 0; i < pages; ++i) {
1220 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1221 paddr += PAGE_SIZE;
1222 start += PAGE_SIZE;
1223 }
1224 address += offset;
1225
1226 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1227 iommu_flush_tlb(iommu, dma_dom->domain.id);
1228 dma_dom->need_flush = false;
1229 } else if (unlikely(iommu_has_npcache(iommu)))
1230 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1231
1232 out:
1233 return address;
1234 }
1235
1236 /*
1237 * Does the reverse of the __map_single function. Must be called with
1238 * the domain lock held too
1239 */
1240 static void __unmap_single(struct amd_iommu *iommu,
1241 struct dma_ops_domain *dma_dom,
1242 dma_addr_t dma_addr,
1243 size_t size,
1244 int dir)
1245 {
1246 dma_addr_t i, start;
1247 unsigned int pages;
1248
1249 if ((dma_addr == bad_dma_address) ||
1250 (dma_addr + size > dma_dom->aperture_size))
1251 return;
1252
1253 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1254 dma_addr &= PAGE_MASK;
1255 start = dma_addr;
1256
1257 for (i = 0; i < pages; ++i) {
1258 dma_ops_domain_unmap(iommu, dma_dom, start);
1259 start += PAGE_SIZE;
1260 }
1261
1262 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1263
1264 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1265 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1266 dma_dom->need_flush = false;
1267 }
1268 }
1269
1270 /*
1271 * The exported map_single function for dma_ops.
1272 */
1273 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1274 size_t size, int dir)
1275 {
1276 unsigned long flags;
1277 struct amd_iommu *iommu;
1278 struct protection_domain *domain;
1279 u16 devid;
1280 dma_addr_t addr;
1281 u64 dma_mask;
1282
1283 INC_STATS_COUNTER(cnt_map_single);
1284
1285 if (!check_device(dev))
1286 return bad_dma_address;
1287
1288 dma_mask = *dev->dma_mask;
1289
1290 get_device_resources(dev, &iommu, &domain, &devid);
1291
1292 if (iommu == NULL || domain == NULL)
1293 /* device not handled by any AMD IOMMU */
1294 return (dma_addr_t)paddr;
1295
1296 if (!dma_ops_domain(domain))
1297 return bad_dma_address;
1298
1299 spin_lock_irqsave(&domain->lock, flags);
1300 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1301 dma_mask);
1302 if (addr == bad_dma_address)
1303 goto out;
1304
1305 iommu_completion_wait(iommu);
1306
1307 out:
1308 spin_unlock_irqrestore(&domain->lock, flags);
1309
1310 return addr;
1311 }
1312
1313 /*
1314 * The exported unmap_single function for dma_ops.
1315 */
1316 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1317 size_t size, int dir)
1318 {
1319 unsigned long flags;
1320 struct amd_iommu *iommu;
1321 struct protection_domain *domain;
1322 u16 devid;
1323
1324 if (!check_device(dev) ||
1325 !get_device_resources(dev, &iommu, &domain, &devid))
1326 /* device not handled by any AMD IOMMU */
1327 return;
1328
1329 if (!dma_ops_domain(domain))
1330 return;
1331
1332 spin_lock_irqsave(&domain->lock, flags);
1333
1334 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1335
1336 iommu_completion_wait(iommu);
1337
1338 spin_unlock_irqrestore(&domain->lock, flags);
1339 }
1340
1341 /*
1342 * This is a special map_sg function which is used if we should map a
1343 * device which is not handled by an AMD IOMMU in the system.
1344 */
1345 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1346 int nelems, int dir)
1347 {
1348 struct scatterlist *s;
1349 int i;
1350
1351 for_each_sg(sglist, s, nelems, i) {
1352 s->dma_address = (dma_addr_t)sg_phys(s);
1353 s->dma_length = s->length;
1354 }
1355
1356 return nelems;
1357 }
1358
1359 /*
1360 * The exported map_sg function for dma_ops (handles scatter-gather
1361 * lists).
1362 */
1363 static int map_sg(struct device *dev, struct scatterlist *sglist,
1364 int nelems, int dir)
1365 {
1366 unsigned long flags;
1367 struct amd_iommu *iommu;
1368 struct protection_domain *domain;
1369 u16 devid;
1370 int i;
1371 struct scatterlist *s;
1372 phys_addr_t paddr;
1373 int mapped_elems = 0;
1374 u64 dma_mask;
1375
1376 if (!check_device(dev))
1377 return 0;
1378
1379 dma_mask = *dev->dma_mask;
1380
1381 get_device_resources(dev, &iommu, &domain, &devid);
1382
1383 if (!iommu || !domain)
1384 return map_sg_no_iommu(dev, sglist, nelems, dir);
1385
1386 if (!dma_ops_domain(domain))
1387 return 0;
1388
1389 spin_lock_irqsave(&domain->lock, flags);
1390
1391 for_each_sg(sglist, s, nelems, i) {
1392 paddr = sg_phys(s);
1393
1394 s->dma_address = __map_single(dev, iommu, domain->priv,
1395 paddr, s->length, dir, false,
1396 dma_mask);
1397
1398 if (s->dma_address) {
1399 s->dma_length = s->length;
1400 mapped_elems++;
1401 } else
1402 goto unmap;
1403 }
1404
1405 iommu_completion_wait(iommu);
1406
1407 out:
1408 spin_unlock_irqrestore(&domain->lock, flags);
1409
1410 return mapped_elems;
1411 unmap:
1412 for_each_sg(sglist, s, mapped_elems, i) {
1413 if (s->dma_address)
1414 __unmap_single(iommu, domain->priv, s->dma_address,
1415 s->dma_length, dir);
1416 s->dma_address = s->dma_length = 0;
1417 }
1418
1419 mapped_elems = 0;
1420
1421 goto out;
1422 }
1423
1424 /*
1425 * The exported map_sg function for dma_ops (handles scatter-gather
1426 * lists).
1427 */
1428 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1429 int nelems, int dir)
1430 {
1431 unsigned long flags;
1432 struct amd_iommu *iommu;
1433 struct protection_domain *domain;
1434 struct scatterlist *s;
1435 u16 devid;
1436 int i;
1437
1438 if (!check_device(dev) ||
1439 !get_device_resources(dev, &iommu, &domain, &devid))
1440 return;
1441
1442 if (!dma_ops_domain(domain))
1443 return;
1444
1445 spin_lock_irqsave(&domain->lock, flags);
1446
1447 for_each_sg(sglist, s, nelems, i) {
1448 __unmap_single(iommu, domain->priv, s->dma_address,
1449 s->dma_length, dir);
1450 s->dma_address = s->dma_length = 0;
1451 }
1452
1453 iommu_completion_wait(iommu);
1454
1455 spin_unlock_irqrestore(&domain->lock, flags);
1456 }
1457
1458 /*
1459 * The exported alloc_coherent function for dma_ops.
1460 */
1461 static void *alloc_coherent(struct device *dev, size_t size,
1462 dma_addr_t *dma_addr, gfp_t flag)
1463 {
1464 unsigned long flags;
1465 void *virt_addr;
1466 struct amd_iommu *iommu;
1467 struct protection_domain *domain;
1468 u16 devid;
1469 phys_addr_t paddr;
1470 u64 dma_mask = dev->coherent_dma_mask;
1471
1472 if (!check_device(dev))
1473 return NULL;
1474
1475 if (!get_device_resources(dev, &iommu, &domain, &devid))
1476 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1477
1478 flag |= __GFP_ZERO;
1479 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1480 if (!virt_addr)
1481 return 0;
1482
1483 paddr = virt_to_phys(virt_addr);
1484
1485 if (!iommu || !domain) {
1486 *dma_addr = (dma_addr_t)paddr;
1487 return virt_addr;
1488 }
1489
1490 if (!dma_ops_domain(domain))
1491 goto out_free;
1492
1493 if (!dma_mask)
1494 dma_mask = *dev->dma_mask;
1495
1496 spin_lock_irqsave(&domain->lock, flags);
1497
1498 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1499 size, DMA_BIDIRECTIONAL, true, dma_mask);
1500
1501 if (*dma_addr == bad_dma_address)
1502 goto out_free;
1503
1504 iommu_completion_wait(iommu);
1505
1506 spin_unlock_irqrestore(&domain->lock, flags);
1507
1508 return virt_addr;
1509
1510 out_free:
1511
1512 free_pages((unsigned long)virt_addr, get_order(size));
1513
1514 return NULL;
1515 }
1516
1517 /*
1518 * The exported free_coherent function for dma_ops.
1519 */
1520 static void free_coherent(struct device *dev, size_t size,
1521 void *virt_addr, dma_addr_t dma_addr)
1522 {
1523 unsigned long flags;
1524 struct amd_iommu *iommu;
1525 struct protection_domain *domain;
1526 u16 devid;
1527
1528 if (!check_device(dev))
1529 return;
1530
1531 get_device_resources(dev, &iommu, &domain, &devid);
1532
1533 if (!iommu || !domain)
1534 goto free_mem;
1535
1536 if (!dma_ops_domain(domain))
1537 goto free_mem;
1538
1539 spin_lock_irqsave(&domain->lock, flags);
1540
1541 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1542
1543 iommu_completion_wait(iommu);
1544
1545 spin_unlock_irqrestore(&domain->lock, flags);
1546
1547 free_mem:
1548 free_pages((unsigned long)virt_addr, get_order(size));
1549 }
1550
1551 /*
1552 * This function is called by the DMA layer to find out if we can handle a
1553 * particular device. It is part of the dma_ops.
1554 */
1555 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1556 {
1557 u16 bdf;
1558 struct pci_dev *pcidev;
1559
1560 /* No device or no PCI device */
1561 if (!dev || dev->bus != &pci_bus_type)
1562 return 0;
1563
1564 pcidev = to_pci_dev(dev);
1565
1566 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1567
1568 /* Out of our scope? */
1569 if (bdf > amd_iommu_last_bdf)
1570 return 0;
1571
1572 return 1;
1573 }
1574
1575 /*
1576 * The function for pre-allocating protection domains.
1577 *
1578 * If the driver core informs the DMA layer if a driver grabs a device
1579 * we don't need to preallocate the protection domains anymore.
1580 * For now we have to.
1581 */
1582 void prealloc_protection_domains(void)
1583 {
1584 struct pci_dev *dev = NULL;
1585 struct dma_ops_domain *dma_dom;
1586 struct amd_iommu *iommu;
1587 int order = amd_iommu_aperture_order;
1588 u16 devid;
1589
1590 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1591 devid = calc_devid(dev->bus->number, dev->devfn);
1592 if (devid > amd_iommu_last_bdf)
1593 continue;
1594 devid = amd_iommu_alias_table[devid];
1595 if (domain_for_device(devid))
1596 continue;
1597 iommu = amd_iommu_rlookup_table[devid];
1598 if (!iommu)
1599 continue;
1600 dma_dom = dma_ops_domain_alloc(iommu, order);
1601 if (!dma_dom)
1602 continue;
1603 init_unity_mappings_for_device(dma_dom, devid);
1604 dma_dom->target_dev = devid;
1605
1606 list_add_tail(&dma_dom->list, &iommu_pd_list);
1607 }
1608 }
1609
1610 static struct dma_mapping_ops amd_iommu_dma_ops = {
1611 .alloc_coherent = alloc_coherent,
1612 .free_coherent = free_coherent,
1613 .map_single = map_single,
1614 .unmap_single = unmap_single,
1615 .map_sg = map_sg,
1616 .unmap_sg = unmap_sg,
1617 .dma_supported = amd_iommu_dma_supported,
1618 };
1619
1620 /*
1621 * The function which clues the AMD IOMMU driver into dma_ops.
1622 */
1623 int __init amd_iommu_init_dma_ops(void)
1624 {
1625 struct amd_iommu *iommu;
1626 int order = amd_iommu_aperture_order;
1627 int ret;
1628
1629 /*
1630 * first allocate a default protection domain for every IOMMU we
1631 * found in the system. Devices not assigned to any other
1632 * protection domain will be assigned to the default one.
1633 */
1634 list_for_each_entry(iommu, &amd_iommu_list, list) {
1635 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1636 if (iommu->default_dom == NULL)
1637 return -ENOMEM;
1638 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1639 ret = iommu_init_unity_mappings(iommu);
1640 if (ret)
1641 goto free_domains;
1642 }
1643
1644 /*
1645 * If device isolation is enabled, pre-allocate the protection
1646 * domains for each device.
1647 */
1648 if (amd_iommu_isolate)
1649 prealloc_protection_domains();
1650
1651 iommu_detected = 1;
1652 force_iommu = 1;
1653 bad_dma_address = 0;
1654 #ifdef CONFIG_GART_IOMMU
1655 gart_iommu_aperture_disabled = 1;
1656 gart_iommu_aperture = 0;
1657 #endif
1658
1659 /* Make the driver finally visible to the drivers */
1660 dma_ops = &amd_iommu_dma_ops;
1661
1662 #ifdef CONFIG_IOMMU_API
1663 register_iommu(&amd_iommu_ops);
1664 #endif
1665
1666 bus_register_notifier(&pci_bus_type, &device_nb);
1667
1668 amd_iommu_stats_init();
1669
1670 return 0;
1671
1672 free_domains:
1673
1674 list_for_each_entry(iommu, &amd_iommu_list, list) {
1675 if (iommu->default_dom)
1676 dma_ops_domain_free(iommu->default_dom);
1677 }
1678
1679 return ret;
1680 }
1681
1682 /*****************************************************************************
1683 *
1684 * The following functions belong to the exported interface of AMD IOMMU
1685 *
1686 * This interface allows access to lower level functions of the IOMMU
1687 * like protection domain handling and assignement of devices to domains
1688 * which is not possible with the dma_ops interface.
1689 *
1690 *****************************************************************************/
1691
1692 #ifdef CONFIG_IOMMU_API
1693
1694 static void cleanup_domain(struct protection_domain *domain)
1695 {
1696 unsigned long flags;
1697 u16 devid;
1698
1699 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1700
1701 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1702 if (amd_iommu_pd_table[devid] == domain)
1703 __detach_device(domain, devid);
1704
1705 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1706 }
1707
1708 static int amd_iommu_domain_init(struct iommu_domain *dom)
1709 {
1710 struct protection_domain *domain;
1711
1712 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1713 if (!domain)
1714 return -ENOMEM;
1715
1716 spin_lock_init(&domain->lock);
1717 domain->mode = PAGE_MODE_3_LEVEL;
1718 domain->id = domain_id_alloc();
1719 if (!domain->id)
1720 goto out_free;
1721 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1722 if (!domain->pt_root)
1723 goto out_free;
1724
1725 dom->priv = domain;
1726
1727 return 0;
1728
1729 out_free:
1730 kfree(domain);
1731
1732 return -ENOMEM;
1733 }
1734
1735 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1736 {
1737 struct protection_domain *domain = dom->priv;
1738
1739 if (!domain)
1740 return;
1741
1742 if (domain->dev_cnt > 0)
1743 cleanup_domain(domain);
1744
1745 BUG_ON(domain->dev_cnt != 0);
1746
1747 free_pagetable(domain);
1748
1749 domain_id_free(domain->id);
1750
1751 kfree(domain);
1752
1753 dom->priv = NULL;
1754 }
1755
1756 static void amd_iommu_detach_device(struct iommu_domain *dom,
1757 struct device *dev)
1758 {
1759 struct protection_domain *domain = dom->priv;
1760 struct amd_iommu *iommu;
1761 struct pci_dev *pdev;
1762 u16 devid;
1763
1764 if (dev->bus != &pci_bus_type)
1765 return;
1766
1767 pdev = to_pci_dev(dev);
1768
1769 devid = calc_devid(pdev->bus->number, pdev->devfn);
1770
1771 if (devid > 0)
1772 detach_device(domain, devid);
1773
1774 iommu = amd_iommu_rlookup_table[devid];
1775 if (!iommu)
1776 return;
1777
1778 iommu_queue_inv_dev_entry(iommu, devid);
1779 iommu_completion_wait(iommu);
1780 }
1781
1782 static int amd_iommu_attach_device(struct iommu_domain *dom,
1783 struct device *dev)
1784 {
1785 struct protection_domain *domain = dom->priv;
1786 struct protection_domain *old_domain;
1787 struct amd_iommu *iommu;
1788 struct pci_dev *pdev;
1789 u16 devid;
1790
1791 if (dev->bus != &pci_bus_type)
1792 return -EINVAL;
1793
1794 pdev = to_pci_dev(dev);
1795
1796 devid = calc_devid(pdev->bus->number, pdev->devfn);
1797
1798 if (devid >= amd_iommu_last_bdf ||
1799 devid != amd_iommu_alias_table[devid])
1800 return -EINVAL;
1801
1802 iommu = amd_iommu_rlookup_table[devid];
1803 if (!iommu)
1804 return -EINVAL;
1805
1806 old_domain = domain_for_device(devid);
1807 if (old_domain)
1808 return -EBUSY;
1809
1810 attach_device(iommu, domain, devid);
1811
1812 iommu_completion_wait(iommu);
1813
1814 return 0;
1815 }
1816
1817 static int amd_iommu_map_range(struct iommu_domain *dom,
1818 unsigned long iova, phys_addr_t paddr,
1819 size_t size, int iommu_prot)
1820 {
1821 struct protection_domain *domain = dom->priv;
1822 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1823 int prot = 0;
1824 int ret;
1825
1826 if (iommu_prot & IOMMU_READ)
1827 prot |= IOMMU_PROT_IR;
1828 if (iommu_prot & IOMMU_WRITE)
1829 prot |= IOMMU_PROT_IW;
1830
1831 iova &= PAGE_MASK;
1832 paddr &= PAGE_MASK;
1833
1834 for (i = 0; i < npages; ++i) {
1835 ret = iommu_map_page(domain, iova, paddr, prot);
1836 if (ret)
1837 return ret;
1838
1839 iova += PAGE_SIZE;
1840 paddr += PAGE_SIZE;
1841 }
1842
1843 return 0;
1844 }
1845
1846 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1847 unsigned long iova, size_t size)
1848 {
1849
1850 struct protection_domain *domain = dom->priv;
1851 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1852
1853 iova &= PAGE_MASK;
1854
1855 for (i = 0; i < npages; ++i) {
1856 iommu_unmap_page(domain, iova);
1857 iova += PAGE_SIZE;
1858 }
1859
1860 iommu_flush_domain(domain->id);
1861 }
1862
1863 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1864 unsigned long iova)
1865 {
1866 struct protection_domain *domain = dom->priv;
1867 unsigned long offset = iova & ~PAGE_MASK;
1868 phys_addr_t paddr;
1869 u64 *pte;
1870
1871 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1872
1873 if (!IOMMU_PTE_PRESENT(*pte))
1874 return 0;
1875
1876 pte = IOMMU_PTE_PAGE(*pte);
1877 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1878
1879 if (!IOMMU_PTE_PRESENT(*pte))
1880 return 0;
1881
1882 pte = IOMMU_PTE_PAGE(*pte);
1883 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1884
1885 if (!IOMMU_PTE_PRESENT(*pte))
1886 return 0;
1887
1888 paddr = *pte & IOMMU_PAGE_MASK;
1889 paddr |= offset;
1890
1891 return paddr;
1892 }
1893
1894 static struct iommu_ops amd_iommu_ops = {
1895 .domain_init = amd_iommu_domain_init,
1896 .domain_destroy = amd_iommu_domain_destroy,
1897 .attach_dev = amd_iommu_attach_device,
1898 .detach_dev = amd_iommu_detach_device,
1899 .map = amd_iommu_map_range,
1900 .unmap = amd_iommu_unmap_range,
1901 .iova_to_phys = amd_iommu_iova_to_phys,
1902 };
1903
1904 #endif
Support for the Chinese Samsung S3C2440 based development boards