2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.23"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define TX_RING_SIZE 512
68 #define TX_DEF_PENDING 128
69 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
72 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
73 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
74 #define TX_WATCHDOG (5 * HZ)
75 #define NAPI_WEIGHT 64
76 #define PHY_RETRIES 1000
78 #define SKY2_EEPROM_MAGIC 0x9955aabb
81 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83 static const u32 default_msg
=
84 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
85 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
88 static int debug
= -1; /* defaults above */
89 module_param(debug
, int, 0);
90 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
92 static int copybreak __read_mostly
= 128;
93 module_param(copybreak
, int, 0);
94 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
96 static int disable_msi
= 0;
97 module_param(disable_msi
, int, 0);
98 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
100 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table
) = {
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4354) }, /* 88E8040 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4355) }, /* 88E8040T */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4370) }, /* 88E8075 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4380) }, /* 88E8057 */
143 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
147 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
148 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
150 static void sky2_set_multicast(struct net_device
*dev
);
152 /* Access to PHY via serial interconnect */
153 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
157 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
158 gma_write16(hw
, port
, GM_SMI_CTRL
,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
161 for (i
= 0; i
< PHY_RETRIES
; i
++) {
162 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
166 if (!(ctrl
& GM_SMI_CT_BUSY
))
172 dev_warn(&hw
->pdev
->dev
,"%s: phy write timeout\n", hw
->dev
[port
]->name
);
176 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
180 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
184 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
185 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
187 for (i
= 0; i
< PHY_RETRIES
; i
++) {
188 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
192 if (ctrl
& GM_SMI_CT_RD_VAL
) {
193 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
200 dev_warn(&hw
->pdev
->dev
, "%s: phy read timeout\n", hw
->dev
[port
]->name
);
203 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
207 static inline u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
210 __gm_phy_read(hw
, port
, reg
, &v
);
215 static void sky2_power_on(struct sky2_hw
*hw
)
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw
, B0_POWER_CTRL
,
219 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
221 /* disable Core Clock Division, */
222 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
224 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
225 /* enable bits are inverted */
226 sky2_write8(hw
, B2_Y2_CLK_GATE
,
227 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
228 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
229 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
231 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
233 if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
) {
236 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
238 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg
&= P_ASPM_CONTROL_MSK
;
241 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
243 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
244 /* set all bits to 0 except bits 28 & 27 */
245 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
246 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
248 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg
= sky2_read32(hw
, B2_GP_IO
);
252 reg
|= GLB_GPIO_STAT_RACE_DIS
;
253 sky2_write32(hw
, B2_GP_IO
, reg
);
255 sky2_read32(hw
, B2_GP_IO
);
259 static void sky2_power_aux(struct sky2_hw
*hw
)
261 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
262 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
264 /* enable bits are inverted */
265 sky2_write8(hw
, B2_Y2_CLK_GATE
,
266 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
267 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
268 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
270 /* switch power to VAUX */
271 if (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
)
272 sky2_write8(hw
, B0_POWER_CTRL
,
273 (PC_VAUX_ENA
| PC_VCC_ENA
|
274 PC_VAUX_ON
| PC_VCC_OFF
));
277 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
284 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
285 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
286 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
287 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
289 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
290 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
291 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
294 /* flow control to advertise bits */
295 static const u16 copper_fc_adv
[] = {
297 [FC_TX
] = PHY_M_AN_ASP
,
298 [FC_RX
] = PHY_M_AN_PC
,
299 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
302 /* flow control to advertise bits when using 1000BaseX */
303 static const u16 fiber_fc_adv
[] = {
304 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
305 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
306 [FC_RX
] = PHY_M_P_SYM_MD_X
,
307 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
310 /* flow control to GMA disable bits */
311 static const u16 gm_fc_disable
[] = {
312 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
313 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
314 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
319 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
321 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
322 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
324 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) &&
325 !(hw
->flags
& SKY2_HW_NEWER_PHY
)) {
326 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
328 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
330 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
333 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
334 /* set downshift counter to 3x and enable downshift */
335 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
337 /* set master & slave downshift counter to 1x */
338 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
340 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
343 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
344 if (sky2_is_copper(hw
)) {
345 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
346 /* enable automatic crossover */
347 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
349 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
350 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
353 /* Enable Class A driver for FE+ A0 */
354 spec
= gm_phy_read(hw
, port
, PHY_MARV_FE_SPEC_2
);
355 spec
|= PHY_M_FESC_SEL_CL_A
;
356 gm_phy_write(hw
, port
, PHY_MARV_FE_SPEC_2
, spec
);
359 /* disable energy detect */
360 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
362 /* enable automatic crossover */
363 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
365 /* downshift on PHY 88E1112 and 88E1149 is changed */
366 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
367 && (hw
->flags
& SKY2_HW_NEWER_PHY
)) {
368 /* set downshift counter to 3x and enable downshift */
369 ctrl
&= ~PHY_M_PC_DSC_MSK
;
370 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
377 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
380 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
382 /* special setup for PHY 88E1112 Fiber */
383 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& (hw
->flags
& SKY2_HW_FIBRE_PHY
)) {
384 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
388 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
389 ctrl
&= ~PHY_M_MAC_MD_MSK
;
390 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
391 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
393 if (hw
->pmd_type
== 'P') {
394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
399 ctrl
|= PHY_M_FIB_SIGD_POL
;
400 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
403 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
411 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) {
412 if (sky2_is_copper(hw
)) {
413 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
414 ct1000
|= PHY_M_1000C_AFD
;
415 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
416 ct1000
|= PHY_M_1000C_AHD
;
417 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
418 adv
|= PHY_M_AN_100_FD
;
419 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
420 adv
|= PHY_M_AN_100_HD
;
421 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
422 adv
|= PHY_M_AN_10_FD
;
423 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
424 adv
|= PHY_M_AN_10_HD
;
426 } else { /* special defines for FIBER (88E1040S only) */
427 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
428 adv
|= PHY_M_AN_1000X_AFD
;
429 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
430 adv
|= PHY_M_AN_1000X_AHD
;
433 /* Restart Auto-negotiation */
434 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
436 /* forced speed/duplex settings */
437 ct1000
= PHY_M_1000C_MSE
;
439 /* Disable auto update for duplex flow control and duplex */
440 reg
|= GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_SPD_DIS
;
442 switch (sky2
->speed
) {
444 ctrl
|= PHY_CT_SP1000
;
445 reg
|= GM_GPCR_SPEED_1000
;
448 ctrl
|= PHY_CT_SP100
;
449 reg
|= GM_GPCR_SPEED_100
;
453 if (sky2
->duplex
== DUPLEX_FULL
) {
454 reg
|= GM_GPCR_DUP_FULL
;
455 ctrl
|= PHY_CT_DUP_MD
;
456 } else if (sky2
->speed
< SPEED_1000
)
457 sky2
->flow_mode
= FC_NONE
;
460 if (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
) {
461 if (sky2_is_copper(hw
))
462 adv
|= copper_fc_adv
[sky2
->flow_mode
];
464 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
466 reg
|= GM_GPCR_AU_FCT_DIS
;
467 reg
|= gm_fc_disable
[sky2
->flow_mode
];
469 /* Forward pause packets to GMAC? */
470 if (sky2
->flow_mode
& FC_RX
)
471 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
473 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
476 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
478 if (hw
->flags
& SKY2_HW_GIGABIT
)
479 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
481 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
482 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
484 /* Setup Phy LED's */
485 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
488 switch (hw
->chip_id
) {
489 case CHIP_ID_YUKON_FE
:
490 /* on 88E3082 these bits are at 11..9 (shifted left) */
491 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
493 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
495 /* delete ACT LED control bits */
496 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
497 /* change ACT LED control to blink mode */
498 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
499 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
502 case CHIP_ID_YUKON_FE_P
:
503 /* Enable Link Partner Next Page */
504 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
505 ctrl
|= PHY_M_PC_ENA_LIP_NP
;
507 /* disable Energy Detect and enable scrambler */
508 ctrl
&= ~(PHY_M_PC_ENA_ENE_DT
| PHY_M_PC_DIS_SCRAMB
);
509 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
511 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
512 ctrl
= PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL
) |
513 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK
) |
514 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED
);
516 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
519 case CHIP_ID_YUKON_XL
:
520 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
522 /* select page 3 to access LED control register */
523 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
525 /* set LED Function Control register */
526 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
527 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
528 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
529 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
530 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
532 /* set Polarity Control register */
533 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
534 (PHY_M_POLC_LS1_P_MIX(4) |
535 PHY_M_POLC_IS0_P_MIX(4) |
536 PHY_M_POLC_LOS_CTRL(2) |
537 PHY_M_POLC_INIT_CTRL(2) |
538 PHY_M_POLC_STA1_CTRL(2) |
539 PHY_M_POLC_STA0_CTRL(2)));
541 /* restore page register */
542 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
545 case CHIP_ID_YUKON_EC_U
:
546 case CHIP_ID_YUKON_EX
:
547 case CHIP_ID_YUKON_SUPR
:
548 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
550 /* select page 3 to access LED control register */
551 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
553 /* set LED Function Control register */
554 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
555 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
556 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
557 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
558 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
560 /* set Blink Rate in LED Timer Control Register */
561 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
562 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
563 /* restore page register */
564 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
568 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
569 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
571 /* turn off the Rx LED (LED_RX) */
572 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
575 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_UL_2
) {
576 /* apply fixes in PHY AFE */
577 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
579 /* increase differential signal amplitude in 10BASE-T */
580 gm_phy_write(hw
, port
, 0x18, 0xaa99);
581 gm_phy_write(hw
, port
, 0x17, 0x2011);
583 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
584 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
585 gm_phy_write(hw
, port
, 0x18, 0xa204);
586 gm_phy_write(hw
, port
, 0x17, 0x2002);
589 /* set page register to 0 */
590 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
591 } else if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
592 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
593 /* apply workaround for integrated resistors calibration */
594 gm_phy_write(hw
, port
, PHY_MARV_PAGE_ADDR
, 17);
595 gm_phy_write(hw
, port
, PHY_MARV_PAGE_DATA
, 0x3f60);
596 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
&&
597 hw
->chip_id
< CHIP_ID_YUKON_SUPR
) {
598 /* no effect on Yukon-XL */
599 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
601 if ( !(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
602 || sky2
->speed
== SPEED_100
) {
603 /* turn on 100 Mbps LED (LED_LINK100) */
604 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
608 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
612 /* Enable phy interrupt on auto-negotiation complete (or link up) */
613 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
614 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
616 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
619 static const u32 phy_power
[] = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
620 static const u32 coma_mode
[] = { PCI_Y2_PHY1_COMA
, PCI_Y2_PHY2_COMA
};
622 static void sky2_phy_power_up(struct sky2_hw
*hw
, unsigned port
)
626 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
627 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
628 reg1
&= ~phy_power
[port
];
630 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
631 reg1
|= coma_mode
[port
];
633 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
634 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
635 sky2_pci_read32(hw
, PCI_DEV_REG1
);
637 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
638 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_ANE
);
639 else if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
)
640 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
643 static void sky2_phy_power_down(struct sky2_hw
*hw
, unsigned port
)
648 /* release GPHY Control reset */
649 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
651 /* release GMAC reset */
652 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
654 if (hw
->flags
& SKY2_HW_NEWER_PHY
) {
655 /* select page 2 to access MAC control register */
656 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
658 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
659 /* allow GMII Power Down */
660 ctrl
&= ~PHY_M_MAC_GMIF_PUP
;
661 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
663 /* set page register back to 0 */
664 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
667 /* setup General Purpose Control Register */
668 gma_write16(hw
, port
, GM_GP_CTRL
,
669 GM_GPCR_FL_PASS
| GM_GPCR_SPEED_100
|
670 GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_FCT_DIS
|
673 if (hw
->chip_id
!= CHIP_ID_YUKON_EC
) {
674 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
675 /* select page 2 to access MAC control register */
676 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
678 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
679 /* enable Power Down */
680 ctrl
|= PHY_M_PC_POW_D_ENA
;
681 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
683 /* set page register back to 0 */
684 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
687 /* set IEEE compatible Power Down Mode (dev. #4.99) */
688 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_PDOWN
);
691 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
692 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
693 reg1
|= phy_power
[port
]; /* set PHY to PowerDown/COMA Mode */
694 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
695 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
698 /* Force a renegotiation */
699 static void sky2_phy_reinit(struct sky2_port
*sky2
)
701 spin_lock_bh(&sky2
->phy_lock
);
702 sky2_phy_init(sky2
->hw
, sky2
->port
);
703 spin_unlock_bh(&sky2
->phy_lock
);
706 /* Put device in state to listen for Wake On Lan */
707 static void sky2_wol_init(struct sky2_port
*sky2
)
709 struct sky2_hw
*hw
= sky2
->hw
;
710 unsigned port
= sky2
->port
;
711 enum flow_control save_mode
;
715 /* Bring hardware out of reset */
716 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
717 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
719 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
720 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
723 * sky2_reset will re-enable on resume
725 save_mode
= sky2
->flow_mode
;
726 ctrl
= sky2
->advertising
;
728 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
729 sky2
->flow_mode
= FC_NONE
;
731 spin_lock_bh(&sky2
->phy_lock
);
732 sky2_phy_power_up(hw
, port
);
733 sky2_phy_init(hw
, port
);
734 spin_unlock_bh(&sky2
->phy_lock
);
736 sky2
->flow_mode
= save_mode
;
737 sky2
->advertising
= ctrl
;
739 /* Set GMAC to no flow control and auto update for speed/duplex */
740 gma_write16(hw
, port
, GM_GP_CTRL
,
741 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
742 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
744 /* Set WOL address */
745 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
746 sky2
->netdev
->dev_addr
, ETH_ALEN
);
748 /* Turn on appropriate WOL control bits */
749 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
751 if (sky2
->wol
& WAKE_PHY
)
752 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
754 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
756 if (sky2
->wol
& WAKE_MAGIC
)
757 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
759 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;;
761 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
762 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
764 /* Turn on legacy PCI-Express PME mode */
765 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
766 reg1
|= PCI_Y2_PME_LEGACY
;
767 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
770 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
774 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
776 struct net_device
*dev
= hw
->dev
[port
];
778 if ( (hw
->chip_id
== CHIP_ID_YUKON_EX
&&
779 hw
->chip_rev
!= CHIP_REV_YU_EX_A0
) ||
780 hw
->chip_id
== CHIP_ID_YUKON_FE_P
||
781 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
782 /* Yukon-Extreme B0 and further Extreme devices */
783 /* enable Store & Forward mode for TX */
785 if (dev
->mtu
<= ETH_DATA_LEN
)
786 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
787 TX_JUMBO_DIS
| TX_STFW_ENA
);
790 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
791 TX_JUMBO_ENA
| TX_STFW_ENA
);
793 if (dev
->mtu
<= ETH_DATA_LEN
)
794 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_ENA
);
796 /* set Tx GMAC FIFO Almost Empty Threshold */
797 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
798 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
800 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
802 /* Can't do offload because of lack of store/forward */
803 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_SG
| NETIF_F_ALL_CSUM
);
808 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
810 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
814 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
816 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
817 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
819 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
821 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
822 /* WA DEV_472 -- looks like crossed wires on port 2 */
823 /* clear GMAC 1 Control reset */
824 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
826 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
827 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
828 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
829 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
830 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
833 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
835 /* Enable Transmit FIFO Underrun */
836 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
838 spin_lock_bh(&sky2
->phy_lock
);
839 sky2_phy_power_up(hw
, port
);
840 sky2_phy_init(hw
, port
);
841 spin_unlock_bh(&sky2
->phy_lock
);
844 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
845 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
847 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
848 gma_read16(hw
, port
, i
);
849 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
851 /* transmit control */
852 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
854 /* receive control reg: unicast + multicast + no FCS */
855 gma_write16(hw
, port
, GM_RX_CTRL
,
856 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
858 /* transmit flow control */
859 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
861 /* transmit parameter */
862 gma_write16(hw
, port
, GM_TX_PARAM
,
863 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
864 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
865 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
866 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
868 /* serial mode register */
869 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
870 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
872 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
873 reg
|= GM_SMOD_JUMBO_ENA
;
875 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
877 /* virtual address for data */
878 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
880 /* physical address: used for pause frames */
881 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
883 /* ignore counter overflows */
884 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
885 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
886 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
888 /* Configure Rx MAC FIFO */
889 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
890 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
891 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
892 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
893 rx_reg
|= GMF_RX_OVER_ON
;
895 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
897 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
898 /* Hardware errata - clear flush mask */
899 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), 0);
901 /* Flush Rx MAC FIFO on any flow control or error */
902 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
905 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
906 reg
= RX_GMF_FL_THR_DEF
+ 1;
907 /* Another magic mystery workaround from sk98lin */
908 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
909 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
911 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), reg
);
913 /* Configure Tx MAC FIFO */
914 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
915 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
917 /* On chips without ram buffer, pause is controled by MAC level */
918 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
)) {
919 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
920 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
922 sky2_set_tx_stfwd(hw
, port
);
925 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
926 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
927 /* disable dynamic watermark */
928 reg
= sky2_read16(hw
, SK_REG(port
, TX_GMF_EA
));
929 reg
&= ~TX_DYN_WM_ENA
;
930 sky2_write16(hw
, SK_REG(port
, TX_GMF_EA
), reg
);
934 /* Assign Ram Buffer allocation to queue */
935 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
939 /* convert from K bytes to qwords used for hw register */
942 end
= start
+ space
- 1;
944 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
945 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
946 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
947 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
948 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
950 if (q
== Q_R1
|| q
== Q_R2
) {
951 u32 tp
= space
- space
/4;
953 /* On receive queue's set the thresholds
954 * give receiver priority when > 3/4 full
955 * send pause when down to 2K
957 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
958 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
961 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
962 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
964 /* Enable store & forward on Tx queue's because
965 * Tx FIFO is only 1K on Yukon
967 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
970 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
971 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
974 /* Setup Bus Memory Interface */
975 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
977 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
978 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
979 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
980 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
983 /* Setup prefetch unit registers. This is the interface between
984 * hardware and driver list elements
986 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
989 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
990 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
991 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
992 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
993 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
994 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
996 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
999 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
, u16
*slot
)
1001 struct sky2_tx_le
*le
= sky2
->tx_le
+ *slot
;
1003 *slot
= RING_NEXT(*slot
, TX_RING_SIZE
);
1008 static void tx_init(struct sky2_port
*sky2
)
1010 struct sky2_tx_le
*le
;
1012 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1013 sky2
->tx_tcpsum
= 0;
1014 sky2
->tx_last_mss
= 0;
1016 le
= get_tx_le(sky2
, &sky2
->tx_prod
);
1018 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1021 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
1022 struct sky2_tx_le
*le
)
1024 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
1027 /* Update chip's next pointer */
1028 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
1030 /* Make sure write' to descriptors are complete before we tell hardware */
1032 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
1034 /* Synchronize I/O on since next processor may write to tail */
1039 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
1041 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
1042 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
1047 /* Build description to hardware for one receive segment */
1048 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
1049 dma_addr_t map
, unsigned len
)
1051 struct sky2_rx_le
*le
;
1053 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1054 le
= sky2_next_rx(sky2
);
1055 le
->addr
= cpu_to_le32(upper_32_bits(map
));
1056 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1059 le
= sky2_next_rx(sky2
);
1060 le
->addr
= cpu_to_le32((u32
) map
);
1061 le
->length
= cpu_to_le16(len
);
1062 le
->opcode
= op
| HW_OWNER
;
1065 /* Build description to hardware for one possibly fragmented skb */
1066 static void sky2_rx_submit(struct sky2_port
*sky2
,
1067 const struct rx_ring_info
*re
)
1071 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
1073 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
1074 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
1078 static int sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
1081 struct sk_buff
*skb
= re
->skb
;
1084 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
1085 if (unlikely(pci_dma_mapping_error(pdev
, re
->data_addr
)))
1088 pci_unmap_len_set(re
, data_size
, size
);
1090 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1091 re
->frag_addr
[i
] = pci_map_page(pdev
,
1092 skb_shinfo(skb
)->frags
[i
].page
,
1093 skb_shinfo(skb
)->frags
[i
].page_offset
,
1094 skb_shinfo(skb
)->frags
[i
].size
,
1095 PCI_DMA_FROMDEVICE
);
1099 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
1101 struct sk_buff
*skb
= re
->skb
;
1104 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
1105 PCI_DMA_FROMDEVICE
);
1107 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1108 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1109 skb_shinfo(skb
)->frags
[i
].size
,
1110 PCI_DMA_FROMDEVICE
);
1113 /* Tell chip where to start receive checksum.
1114 * Actually has two checksums, but set both same to avoid possible byte
1117 static void rx_set_checksum(struct sky2_port
*sky2
)
1119 struct sky2_rx_le
*le
= sky2_next_rx(sky2
);
1121 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
1123 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
1125 sky2_write32(sky2
->hw
,
1126 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1127 (sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
)
1128 ? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
1132 * The RX Stop command will not work for Yukon-2 if the BMU does not
1133 * reach the end of packet and since we can't make sure that we have
1134 * incoming data, we must reset the BMU while it is not doing a DMA
1135 * transfer. Since it is possible that the RX path is still active,
1136 * the RX RAM buffer will be stopped first, so any possible incoming
1137 * data will not trigger a DMA. After the RAM buffer is stopped, the
1138 * BMU is polled until any DMA in progress is ended and only then it
1141 static void sky2_rx_stop(struct sky2_port
*sky2
)
1143 struct sky2_hw
*hw
= sky2
->hw
;
1144 unsigned rxq
= rxqaddr
[sky2
->port
];
1147 /* disable the RAM Buffer receive queue */
1148 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1150 for (i
= 0; i
< 0xffff; i
++)
1151 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1152 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1155 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
1156 sky2
->netdev
->name
);
1158 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1160 /* reset the Rx prefetch unit */
1161 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1165 /* Clean out receive buffer area, assumes receiver hardware stopped */
1166 static void sky2_rx_clean(struct sky2_port
*sky2
)
1170 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1171 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1172 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1175 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1180 skb_queue_purge(&sky2
->rx_recycle
);
1183 /* Basic MII support */
1184 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1186 struct mii_ioctl_data
*data
= if_mii(ifr
);
1187 struct sky2_port
*sky2
= netdev_priv(dev
);
1188 struct sky2_hw
*hw
= sky2
->hw
;
1189 int err
= -EOPNOTSUPP
;
1191 if (!netif_running(dev
))
1192 return -ENODEV
; /* Phy still in reset */
1196 data
->phy_id
= PHY_ADDR_MARV
;
1202 spin_lock_bh(&sky2
->phy_lock
);
1203 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1204 spin_unlock_bh(&sky2
->phy_lock
);
1206 data
->val_out
= val
;
1211 if (!capable(CAP_NET_ADMIN
))
1214 spin_lock_bh(&sky2
->phy_lock
);
1215 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1217 spin_unlock_bh(&sky2
->phy_lock
);
1223 #ifdef SKY2_VLAN_TAG_USED
1224 static void sky2_set_vlan_mode(struct sky2_hw
*hw
, u16 port
, bool onoff
)
1227 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1229 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1232 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1234 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1239 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1241 struct sky2_port
*sky2
= netdev_priv(dev
);
1242 struct sky2_hw
*hw
= sky2
->hw
;
1243 u16 port
= sky2
->port
;
1245 netif_tx_lock_bh(dev
);
1246 napi_disable(&hw
->napi
);
1249 sky2_set_vlan_mode(hw
, port
, grp
!= NULL
);
1251 sky2_read32(hw
, B0_Y2_SP_LISR
);
1252 napi_enable(&hw
->napi
);
1253 netif_tx_unlock_bh(dev
);
1257 /* Amount of required worst case padding in rx buffer */
1258 static inline unsigned sky2_rx_pad(const struct sky2_hw
*hw
)
1260 return (hw
->flags
& SKY2_HW_RAM_BUFFER
) ? 8 : 2;
1264 * Allocate an skb for receiving. If the MTU is large enough
1265 * make the skb non-linear with a fragment list of pages.
1267 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1269 struct sk_buff
*skb
;
1272 skb
= __skb_dequeue(&sky2
->rx_recycle
);
1274 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
1275 + sky2_rx_pad(sky2
->hw
));
1279 if (sky2
->hw
->flags
& SKY2_HW_RAM_BUFFER
) {
1280 unsigned char *start
;
1282 * Workaround for a bug in FIFO that cause hang
1283 * if the FIFO if the receive buffer is not 64 byte aligned.
1284 * The buffer returned from netdev_alloc_skb is
1285 * aligned except if slab debugging is enabled.
1287 start
= PTR_ALIGN(skb
->data
, 8);
1288 skb_reserve(skb
, start
- skb
->data
);
1290 skb_reserve(skb
, NET_IP_ALIGN
);
1292 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1293 struct page
*page
= alloc_page(GFP_ATOMIC
);
1297 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1307 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1309 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1313 * Allocate and setup receiver buffer pool.
1314 * Normal case this ends up creating one list element for skb
1315 * in the receive ring. Worst case if using large MTU and each
1316 * allocation falls on a different 64 bit region, that results
1317 * in 6 list elements per ring entry.
1318 * One element is used for checksum enable/disable, and one
1319 * extra to avoid wrap.
1321 static int sky2_rx_start(struct sky2_port
*sky2
)
1323 struct sky2_hw
*hw
= sky2
->hw
;
1324 struct rx_ring_info
*re
;
1325 unsigned rxq
= rxqaddr
[sky2
->port
];
1326 unsigned i
, size
, thresh
;
1328 sky2
->rx_put
= sky2
->rx_next
= 0;
1331 /* On PCI express lowering the watermark gives better performance */
1332 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1333 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1335 /* These chips have no ram buffer?
1336 * MAC Rx RAM Read is controlled by hardware */
1337 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1338 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1339 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1340 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1342 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1344 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1345 rx_set_checksum(sky2
);
1347 /* Space needed for frame data + headers rounded up */
1348 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1350 /* Stopping point for hardware truncation */
1351 thresh
= (size
- 8) / sizeof(u32
);
1353 sky2
->rx_nfrags
= size
>> PAGE_SHIFT
;
1354 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1356 /* Compute residue after pages */
1357 size
-= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1359 /* Optimize to handle small packets and headers */
1360 if (size
< copybreak
)
1362 if (size
< ETH_HLEN
)
1365 sky2
->rx_data_size
= size
;
1367 skb_queue_head_init(&sky2
->rx_recycle
);
1370 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1371 re
= sky2
->rx_ring
+ i
;
1373 re
->skb
= sky2_rx_alloc(sky2
);
1377 if (sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
)) {
1378 dev_kfree_skb(re
->skb
);
1383 sky2_rx_submit(sky2
, re
);
1387 * The receiver hangs if it receives frames larger than the
1388 * packet buffer. As a workaround, truncate oversize frames, but
1389 * the register is limited to 9 bits, so if you do frames > 2052
1390 * you better get the MTU right!
1393 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1395 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1396 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1399 /* Tell chip about available buffers */
1400 sky2_rx_update(sky2
, rxq
);
1403 sky2_rx_clean(sky2
);
1407 /* Bring up network interface. */
1408 static int sky2_up(struct net_device
*dev
)
1410 struct sky2_port
*sky2
= netdev_priv(dev
);
1411 struct sky2_hw
*hw
= sky2
->hw
;
1412 unsigned port
= sky2
->port
;
1414 int cap
, err
= -ENOMEM
;
1415 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1418 * On dual port PCI-X card, there is an problem where status
1419 * can be received out of order due to split transactions
1421 if (otherdev
&& netif_running(otherdev
) &&
1422 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1425 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1426 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1427 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1431 netif_carrier_off(dev
);
1433 /* must be power of 2 */
1434 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1436 sizeof(struct sky2_tx_le
),
1441 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1448 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1452 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1454 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1459 sky2_mac_init(hw
, port
);
1461 /* Register is number of 4K blocks on internal RAM buffer. */
1462 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1466 hw
->flags
|= SKY2_HW_RAM_BUFFER
;
1467 pr_debug(PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1469 rxspace
= ramsize
/ 2;
1471 rxspace
= 8 + (2*(ramsize
- 16))/3;
1473 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1474 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1476 /* Make sure SyncQ is disabled */
1477 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1481 sky2_qset(hw
, txqaddr
[port
]);
1483 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1484 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1485 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1487 /* Set almost empty threshold */
1488 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1489 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1490 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1492 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1495 #ifdef SKY2_VLAN_TAG_USED
1496 sky2_set_vlan_mode(hw
, port
, sky2
->vlgrp
!= NULL
);
1499 sky2
->restarting
= 0;
1501 err
= sky2_rx_start(sky2
);
1505 /* Enable interrupts from phy/mac for port */
1506 imask
= sky2_read32(hw
, B0_IMSK
);
1507 imask
|= portirq_msk
[port
];
1508 sky2_write32(hw
, B0_IMSK
, imask
);
1509 sky2_read32(hw
, B0_IMSK
);
1511 /* wake queue incase we are restarting */
1512 netif_wake_queue(dev
);
1514 if (netif_msg_ifup(sky2
))
1515 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1521 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1522 sky2
->rx_le
, sky2
->rx_le_map
);
1526 pci_free_consistent(hw
->pdev
,
1527 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1528 sky2
->tx_le
, sky2
->tx_le_map
);
1531 kfree(sky2
->tx_ring
);
1532 kfree(sky2
->rx_ring
);
1534 sky2
->tx_ring
= NULL
;
1535 sky2
->rx_ring
= NULL
;
1539 /* Modular subtraction in ring */
1540 static inline int tx_dist(unsigned tail
, unsigned head
)
1542 return (head
- tail
) & (TX_RING_SIZE
- 1);
1545 /* Number of list elements available for next tx */
1546 static inline int tx_avail(const struct sky2_port
*sky2
)
1548 if (unlikely(sky2
->restarting
))
1550 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1553 /* Estimate of number of transmit list elements required */
1554 static unsigned tx_le_req(const struct sk_buff
*skb
)
1558 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1559 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1561 if (skb_is_gso(skb
))
1564 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1571 * Put one packet in ring for transmit.
1572 * A single packet can generate multiple list elements, and
1573 * the number of ring elements will probably be less than the number
1574 * of list elements used.
1576 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1578 struct sky2_port
*sky2
= netdev_priv(dev
);
1579 struct sky2_hw
*hw
= sky2
->hw
;
1580 struct sky2_tx_le
*le
= NULL
;
1581 struct tx_ring_info
*re
;
1588 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1589 return NETDEV_TX_BUSY
;
1591 len
= skb_headlen(skb
);
1592 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1594 if (pci_dma_mapping_error(hw
->pdev
, mapping
))
1597 slot
= sky2
->tx_prod
;
1598 if (unlikely(netif_msg_tx_queued(sky2
)))
1599 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1600 dev
->name
, slot
, skb
->len
);
1602 /* Send high bits if needed */
1603 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1604 le
= get_tx_le(sky2
, &slot
);
1605 le
->addr
= cpu_to_le32(upper_32_bits(mapping
));
1606 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1609 /* Check for TCP Segmentation Offload */
1610 mss
= skb_shinfo(skb
)->gso_size
;
1613 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1614 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1616 if (mss
!= sky2
->tx_last_mss
) {
1617 le
= get_tx_le(sky2
, &slot
);
1618 le
->addr
= cpu_to_le32(mss
);
1620 if (hw
->flags
& SKY2_HW_NEW_LE
)
1621 le
->opcode
= OP_MSS
| HW_OWNER
;
1623 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1624 sky2
->tx_last_mss
= mss
;
1629 #ifdef SKY2_VLAN_TAG_USED
1630 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1631 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1633 le
= get_tx_le(sky2
, &slot
);
1635 le
->opcode
= OP_VLAN
|HW_OWNER
;
1637 le
->opcode
|= OP_VLAN
;
1638 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1643 /* Handle TCP checksum offload */
1644 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1645 /* On Yukon EX (some versions) encoding change. */
1646 if (hw
->flags
& SKY2_HW_AUTO_TX_SUM
)
1647 ctrl
|= CALSUM
; /* auto checksum */
1649 const unsigned offset
= skb_transport_offset(skb
);
1652 tcpsum
= offset
<< 16; /* sum start */
1653 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1655 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1656 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1659 if (tcpsum
!= sky2
->tx_tcpsum
) {
1660 sky2
->tx_tcpsum
= tcpsum
;
1662 le
= get_tx_le(sky2
, &slot
);
1663 le
->addr
= cpu_to_le32(tcpsum
);
1664 le
->length
= 0; /* initial checksum value */
1665 le
->ctrl
= 1; /* one packet */
1666 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1671 le
= get_tx_le(sky2
, &slot
);
1672 le
->addr
= cpu_to_le32((u32
) mapping
);
1673 le
->length
= cpu_to_le16(len
);
1675 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1677 re
= tx_le_re(sky2
, le
);
1679 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1680 pci_unmap_len_set(re
, maplen
, len
);
1682 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1683 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1685 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1686 frag
->size
, PCI_DMA_TODEVICE
);
1688 if (pci_dma_mapping_error(hw
->pdev
, mapping
))
1689 goto mapping_unwind
;
1691 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1692 le
= get_tx_le(sky2
, &slot
);
1693 le
->addr
= cpu_to_le32(upper_32_bits(mapping
));
1695 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1698 le
= get_tx_le(sky2
, &slot
);
1699 le
->addr
= cpu_to_le32((u32
) mapping
);
1700 le
->length
= cpu_to_le16(frag
->size
);
1702 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1704 re
= tx_le_re(sky2
, le
);
1706 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1707 pci_unmap_len_set(re
, maplen
, frag
->size
);
1712 sky2
->tx_prod
= slot
;
1714 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1715 netif_stop_queue(dev
);
1717 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1719 return NETDEV_TX_OK
;
1722 for (i
= sky2
->tx_prod
; i
!= slot
; i
= RING_NEXT(i
, TX_RING_SIZE
)) {
1723 le
= sky2
->tx_le
+ i
;
1724 re
= sky2
->tx_ring
+ i
;
1726 switch(le
->opcode
& ~HW_OWNER
) {
1729 pci_unmap_single(hw
->pdev
,
1730 pci_unmap_addr(re
, mapaddr
),
1731 pci_unmap_len(re
, maplen
),
1735 pci_unmap_page(hw
->pdev
, pci_unmap_addr(re
, mapaddr
),
1736 pci_unmap_len(re
, maplen
),
1743 if (net_ratelimit())
1744 dev_warn(&hw
->pdev
->dev
, "%s: tx mapping error\n", dev
->name
);
1746 return NETDEV_TX_OK
;
1750 * Free ring elements from starting at tx_cons until "done"
1753 * 1. The hardware will tell us about partial completion of multi-part
1754 * buffers so make sure not to free skb to early.
1755 * 2. This may run in parallel start_xmit because the it only
1756 * looks at the tail of the queue of FIFO (tx_cons), not
1757 * the head (tx_prod)
1759 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1761 struct net_device
*dev
= sky2
->netdev
;
1762 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1765 BUG_ON(done
>= TX_RING_SIZE
);
1767 for (idx
= sky2
->tx_cons
; idx
!= done
;
1768 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1769 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1770 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1772 switch(le
->opcode
& ~HW_OWNER
) {
1775 pci_unmap_single(pdev
,
1776 pci_unmap_addr(re
, mapaddr
),
1777 pci_unmap_len(re
, maplen
),
1781 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1782 pci_unmap_len(re
, maplen
),
1787 if (le
->ctrl
& EOP
) {
1788 struct sk_buff
*skb
= re
->skb
;
1790 if (unlikely(netif_msg_tx_done(sky2
)))
1791 printk(KERN_DEBUG
"%s: tx done %u\n",
1794 dev
->stats
.tx_packets
++;
1795 dev
->stats
.tx_bytes
+= skb
->len
;
1797 if (skb_queue_len(&sky2
->rx_recycle
) < sky2
->rx_pending
1798 && skb_recycle_check(skb
, sky2
->rx_data_size
1799 + sky2_rx_pad(sky2
->hw
)))
1800 __skb_queue_head(&sky2
->rx_recycle
, skb
);
1802 dev_kfree_skb_any(skb
);
1804 sky2
->tx_next
= RING_NEXT(idx
, TX_RING_SIZE
);
1808 sky2
->tx_cons
= idx
;
1811 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1812 netif_wake_queue(dev
);
1815 static void sky2_tx_reset(struct sky2_hw
*hw
, unsigned port
)
1817 /* Disable Force Sync bit and Enable Alloc bit */
1818 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1819 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1821 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1822 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1823 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1825 /* Reset the PCI FIFO of the async Tx queue */
1826 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1827 BMU_RST_SET
| BMU_FIFO_RST
);
1829 /* Reset the Tx prefetch units */
1830 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1833 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1834 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1837 /* Network shutdown */
1838 static int sky2_down(struct net_device
*dev
)
1840 struct sky2_port
*sky2
= netdev_priv(dev
);
1841 struct sky2_hw
*hw
= sky2
->hw
;
1842 unsigned port
= sky2
->port
;
1846 /* Never really got started! */
1850 if (netif_msg_ifdown(sky2
))
1851 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1853 /* explicitly shut off tx incase we're restarting */
1854 sky2
->restarting
= 1;
1855 netif_tx_disable(dev
);
1857 /* Force flow control off */
1858 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1860 /* Stop transmitter */
1861 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1862 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1864 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1865 RB_RST_SET
| RB_DIS_OP_MD
);
1867 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1868 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1869 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1871 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1873 /* Workaround shared GMAC reset */
1874 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1875 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1876 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1878 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1880 /* Force any delayed status interrrupt and NAPI */
1881 sky2_write32(hw
, STAT_LEV_TIMER_CNT
, 0);
1882 sky2_write32(hw
, STAT_TX_TIMER_CNT
, 0);
1883 sky2_write32(hw
, STAT_ISR_TIMER_CNT
, 0);
1884 sky2_read8(hw
, STAT_ISR_TIMER_CTRL
);
1888 /* Disable port IRQ */
1889 imask
= sky2_read32(hw
, B0_IMSK
);
1890 imask
&= ~portirq_msk
[port
];
1891 sky2_write32(hw
, B0_IMSK
, imask
);
1892 sky2_read32(hw
, B0_IMSK
);
1894 synchronize_irq(hw
->pdev
->irq
);
1895 napi_synchronize(&hw
->napi
);
1897 spin_lock_bh(&sky2
->phy_lock
);
1898 sky2_phy_power_down(hw
, port
);
1899 spin_unlock_bh(&sky2
->phy_lock
);
1901 /* turn off LED's */
1902 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1904 sky2_tx_reset(hw
, port
);
1906 /* Free any pending frames stuck in HW queue */
1907 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1909 sky2_rx_clean(sky2
);
1911 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1912 sky2
->rx_le
, sky2
->rx_le_map
);
1913 kfree(sky2
->rx_ring
);
1915 pci_free_consistent(hw
->pdev
,
1916 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1917 sky2
->tx_le
, sky2
->tx_le_map
);
1918 kfree(sky2
->tx_ring
);
1923 sky2
->rx_ring
= NULL
;
1924 sky2
->tx_ring
= NULL
;
1929 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1931 if (hw
->flags
& SKY2_HW_FIBRE_PHY
)
1934 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
1935 if (aux
& PHY_M_PS_SPEED_100
)
1941 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1942 case PHY_M_PS_SPEED_1000
:
1944 case PHY_M_PS_SPEED_100
:
1951 static void sky2_link_up(struct sky2_port
*sky2
)
1953 struct sky2_hw
*hw
= sky2
->hw
;
1954 unsigned port
= sky2
->port
;
1956 static const char *fc_name
[] = {
1964 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1965 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1966 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1968 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1970 netif_carrier_on(sky2
->netdev
);
1972 mod_timer(&hw
->watchdog_timer
, jiffies
+ 1);
1974 /* Turn on link LED */
1975 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1976 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1978 if (netif_msg_link(sky2
))
1979 printk(KERN_INFO PFX
1980 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1981 sky2
->netdev
->name
, sky2
->speed
,
1982 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1983 fc_name
[sky2
->flow_status
]);
1986 static void sky2_link_down(struct sky2_port
*sky2
)
1988 struct sky2_hw
*hw
= sky2
->hw
;
1989 unsigned port
= sky2
->port
;
1992 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1994 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1995 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1996 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1998 netif_carrier_off(sky2
->netdev
);
2000 /* Turn on link LED */
2001 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
2003 if (netif_msg_link(sky2
))
2004 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
2006 sky2_phy_init(hw
, port
);
2009 static enum flow_control
sky2_flow(int rx
, int tx
)
2012 return tx
? FC_BOTH
: FC_RX
;
2014 return tx
? FC_TX
: FC_NONE
;
2017 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
2019 struct sky2_hw
*hw
= sky2
->hw
;
2020 unsigned port
= sky2
->port
;
2023 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
2024 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
2025 if (lpa
& PHY_M_AN_RF
) {
2026 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
2030 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
2031 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
2032 sky2
->netdev
->name
);
2036 sky2
->speed
= sky2_phy_speed(hw
, aux
);
2037 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2039 /* Since the pause result bits seem to in different positions on
2040 * different chips. look at registers.
2042 if (hw
->flags
& SKY2_HW_FIBRE_PHY
) {
2043 /* Shift for bits in fiber PHY */
2044 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
2045 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
2047 if (advert
& ADVERTISE_1000XPAUSE
)
2048 advert
|= ADVERTISE_PAUSE_CAP
;
2049 if (advert
& ADVERTISE_1000XPSE_ASYM
)
2050 advert
|= ADVERTISE_PAUSE_ASYM
;
2051 if (lpa
& LPA_1000XPAUSE
)
2052 lpa
|= LPA_PAUSE_CAP
;
2053 if (lpa
& LPA_1000XPAUSE_ASYM
)
2054 lpa
|= LPA_PAUSE_ASYM
;
2057 sky2
->flow_status
= FC_NONE
;
2058 if (advert
& ADVERTISE_PAUSE_CAP
) {
2059 if (lpa
& LPA_PAUSE_CAP
)
2060 sky2
->flow_status
= FC_BOTH
;
2061 else if (advert
& ADVERTISE_PAUSE_ASYM
)
2062 sky2
->flow_status
= FC_RX
;
2063 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
2064 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
2065 sky2
->flow_status
= FC_TX
;
2068 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
2069 && !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
2070 sky2
->flow_status
= FC_NONE
;
2072 if (sky2
->flow_status
& FC_TX
)
2073 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
2075 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2080 /* Interrupt from PHY */
2081 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
2083 struct net_device
*dev
= hw
->dev
[port
];
2084 struct sky2_port
*sky2
= netdev_priv(dev
);
2085 u16 istatus
, phystat
;
2087 if (!netif_running(dev
))
2090 spin_lock(&sky2
->phy_lock
);
2091 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
2092 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2094 if (netif_msg_intr(sky2
))
2095 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
2096 sky2
->netdev
->name
, istatus
, phystat
);
2098 if (istatus
& PHY_M_IS_AN_COMPL
) {
2099 if (sky2_autoneg_done(sky2
, phystat
) == 0)
2104 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2105 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
2107 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2109 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2111 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2112 if (phystat
& PHY_M_PS_LINK_UP
)
2115 sky2_link_down(sky2
);
2118 spin_unlock(&sky2
->phy_lock
);
2121 /* Transmit timeout is only called if we are running, carrier is up
2122 * and tx queue is full (stopped).
2124 static void sky2_tx_timeout(struct net_device
*dev
)
2126 struct sky2_port
*sky2
= netdev_priv(dev
);
2127 struct sky2_hw
*hw
= sky2
->hw
;
2129 if (netif_msg_timer(sky2
))
2130 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
2132 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
2133 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
2134 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
2135 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
2137 /* can't restart safely under softirq */
2138 schedule_work(&hw
->restart_work
);
2141 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
2143 struct sky2_port
*sky2
= netdev_priv(dev
);
2144 struct sky2_hw
*hw
= sky2
->hw
;
2145 unsigned port
= sky2
->port
;
2150 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2153 if (new_mtu
> ETH_DATA_LEN
&&
2154 (hw
->chip_id
== CHIP_ID_YUKON_FE
||
2155 hw
->chip_id
== CHIP_ID_YUKON_FE_P
))
2158 if (!netif_running(dev
)) {
2163 imask
= sky2_read32(hw
, B0_IMSK
);
2164 sky2_write32(hw
, B0_IMSK
, 0);
2166 dev
->trans_start
= jiffies
; /* prevent tx timeout */
2167 netif_stop_queue(dev
);
2168 napi_disable(&hw
->napi
);
2170 synchronize_irq(hw
->pdev
->irq
);
2172 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
))
2173 sky2_set_tx_stfwd(hw
, port
);
2175 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2176 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
2178 sky2_rx_clean(sky2
);
2182 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
2183 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
2185 if (dev
->mtu
> ETH_DATA_LEN
)
2186 mode
|= GM_SMOD_JUMBO_ENA
;
2188 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
2190 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
2192 err
= sky2_rx_start(sky2
);
2193 sky2_write32(hw
, B0_IMSK
, imask
);
2195 sky2_read32(hw
, B0_Y2_SP_LISR
);
2196 napi_enable(&hw
->napi
);
2201 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
2203 netif_wake_queue(dev
);
2209 /* For small just reuse existing skb for next receive */
2210 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2211 const struct rx_ring_info
*re
,
2214 struct sk_buff
*skb
;
2216 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
2218 skb_reserve(skb
, 2);
2219 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2220 length
, PCI_DMA_FROMDEVICE
);
2221 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2222 skb
->ip_summed
= re
->skb
->ip_summed
;
2223 skb
->csum
= re
->skb
->csum
;
2224 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2225 length
, PCI_DMA_FROMDEVICE
);
2226 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2227 skb_put(skb
, length
);
2232 /* Adjust length of skb with fragments to match received data */
2233 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2234 unsigned int length
)
2239 /* put header into skb */
2240 size
= min(length
, hdr_space
);
2245 num_frags
= skb_shinfo(skb
)->nr_frags
;
2246 for (i
= 0; i
< num_frags
; i
++) {
2247 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2250 /* don't need this page */
2251 __free_page(frag
->page
);
2252 --skb_shinfo(skb
)->nr_frags
;
2254 size
= min(length
, (unsigned) PAGE_SIZE
);
2257 skb
->data_len
+= size
;
2258 skb
->truesize
+= size
;
2265 /* Normal packet - take skb from ring element and put in a new one */
2266 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2267 struct rx_ring_info
*re
,
2268 unsigned int length
)
2270 struct sk_buff
*skb
, *nskb
;
2271 unsigned hdr_space
= sky2
->rx_data_size
;
2273 /* Don't be tricky about reusing pages (yet) */
2274 nskb
= sky2_rx_alloc(sky2
);
2275 if (unlikely(!nskb
))
2279 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2281 prefetch(skb
->data
);
2283 if (sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
)) {
2284 dev_kfree_skb(nskb
);
2289 if (skb_shinfo(skb
)->nr_frags
)
2290 skb_put_frags(skb
, hdr_space
, length
);
2292 skb_put(skb
, length
);
2297 * Receive one packet.
2298 * For larger packets, get new buffer.
2300 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2301 u16 length
, u32 status
)
2303 struct sky2_port
*sky2
= netdev_priv(dev
);
2304 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2305 struct sk_buff
*skb
= NULL
;
2306 u16 count
= (status
& GMR_FS_LEN
) >> 16;
2308 #ifdef SKY2_VLAN_TAG_USED
2309 /* Account for vlan tag */
2310 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
))
2314 if (unlikely(netif_msg_rx_status(sky2
)))
2315 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2316 dev
->name
, sky2
->rx_next
, status
, length
);
2318 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2319 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2321 /* This chip has hardware problems that generates bogus status.
2322 * So do only marginal checking and expect higher level protocols
2323 * to handle crap frames.
2325 if (sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
2326 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
&&
2330 if (status
& GMR_FS_ANY_ERR
)
2333 if (!(status
& GMR_FS_RX_OK
))
2336 /* if length reported by DMA does not match PHY, packet was truncated */
2337 if (length
!= count
)
2341 if (length
< copybreak
)
2342 skb
= receive_copy(sky2
, re
, length
);
2344 skb
= receive_new(sky2
, re
, length
);
2346 sky2_rx_submit(sky2
, re
);
2351 /* Truncation of overlength packets
2352 causes PHY length to not match MAC length */
2353 ++dev
->stats
.rx_length_errors
;
2354 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2355 pr_info(PFX
"%s: rx length error: status %#x length %d\n",
2356 dev
->name
, status
, length
);
2360 ++dev
->stats
.rx_errors
;
2361 if (status
& GMR_FS_RX_FF_OV
) {
2362 dev
->stats
.rx_over_errors
++;
2366 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2367 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2368 dev
->name
, status
, length
);
2370 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2371 dev
->stats
.rx_length_errors
++;
2372 if (status
& GMR_FS_FRAGMENT
)
2373 dev
->stats
.rx_frame_errors
++;
2374 if (status
& GMR_FS_CRC_ERR
)
2375 dev
->stats
.rx_crc_errors
++;
2380 /* Transmit complete */
2381 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2383 struct sky2_port
*sky2
= netdev_priv(dev
);
2385 if (likely(netif_running(dev
) && !sky2
->restarting
))
2386 sky2_tx_complete(sky2
, last
);
2389 static inline void sky2_skb_rx(const struct sky2_port
*sky2
,
2390 u32 status
, struct sk_buff
*skb
)
2392 #ifdef SKY2_VLAN_TAG_USED
2393 u16 vlan_tag
= be16_to_cpu(sky2
->rx_tag
);
2394 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2395 if (skb
->ip_summed
== CHECKSUM_NONE
)
2396 vlan_hwaccel_receive_skb(skb
, sky2
->vlgrp
, vlan_tag
);
2398 vlan_gro_receive(&sky2
->hw
->napi
, sky2
->vlgrp
,
2403 if (skb
->ip_summed
== CHECKSUM_NONE
)
2404 netif_receive_skb(skb
);
2406 napi_gro_receive(&sky2
->hw
->napi
, skb
);
2409 static inline void sky2_rx_done(struct sky2_hw
*hw
, unsigned port
,
2410 unsigned packets
, unsigned bytes
)
2413 struct net_device
*dev
= hw
->dev
[port
];
2415 dev
->stats
.rx_packets
+= packets
;
2416 dev
->stats
.rx_bytes
+= bytes
;
2417 dev
->last_rx
= jiffies
;
2418 sky2_rx_update(netdev_priv(dev
), rxqaddr
[port
]);
2422 /* Process status response ring */
2423 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
, u16 idx
)
2426 unsigned int total_bytes
[2] = { 0 };
2427 unsigned int total_packets
[2] = { 0 };
2431 struct sky2_port
*sky2
;
2432 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2434 struct net_device
*dev
;
2435 struct sk_buff
*skb
;
2438 u8 opcode
= le
->opcode
;
2440 if (!(opcode
& HW_OWNER
))
2443 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2445 port
= le
->css
& CSS_LINK_BIT
;
2446 dev
= hw
->dev
[port
];
2447 sky2
= netdev_priv(dev
);
2448 length
= le16_to_cpu(le
->length
);
2449 status
= le32_to_cpu(le
->status
);
2452 switch (opcode
& ~HW_OWNER
) {
2454 total_packets
[port
]++;
2455 total_bytes
[port
] += length
;
2456 skb
= sky2_receive(dev
, length
, status
);
2457 if (unlikely(!skb
)) {
2458 dev
->stats
.rx_dropped
++;
2462 /* This chip reports checksum status differently */
2463 if (hw
->flags
& SKY2_HW_NEW_LE
) {
2464 if ((sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
) &&
2465 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2466 (le
->css
& CSS_TCPUDPCSOK
))
2467 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2469 skb
->ip_summed
= CHECKSUM_NONE
;
2472 skb
->protocol
= eth_type_trans(skb
, dev
);
2474 sky2_skb_rx(sky2
, status
, skb
);
2476 /* Stop after net poll weight */
2477 if (++work_done
>= to_do
)
2481 #ifdef SKY2_VLAN_TAG_USED
2483 sky2
->rx_tag
= length
;
2487 sky2
->rx_tag
= length
;
2491 if (!(sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
))
2494 /* If this happens then driver assuming wrong format */
2495 if (unlikely(hw
->flags
& SKY2_HW_NEW_LE
)) {
2496 if (net_ratelimit())
2497 printk(KERN_NOTICE
"%s: unexpected"
2498 " checksum status\n",
2503 /* Both checksum counters are programmed to start at
2504 * the same offset, so unless there is a problem they
2505 * should match. This failure is an early indication that
2506 * hardware receive checksumming won't work.
2508 if (likely(status
>> 16 == (status
& 0xffff))) {
2509 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2510 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2511 skb
->csum
= le16_to_cpu(status
);
2513 printk(KERN_NOTICE PFX
"%s: hardware receive "
2514 "checksum problem (status = %#x)\n",
2516 sky2
->flags
&= ~SKY2_FLAG_RX_CHECKSUM
;
2518 sky2_write32(sky2
->hw
,
2519 Q_ADDR(rxqaddr
[port
], Q_CSR
),
2525 /* TX index reports status for both ports */
2526 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2527 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2529 sky2_tx_done(hw
->dev
[1],
2530 ((status
>> 24) & 0xff)
2531 | (u16
)(length
& 0xf) << 8);
2535 if (net_ratelimit())
2536 printk(KERN_WARNING PFX
2537 "unknown status opcode 0x%x\n", opcode
);
2539 } while (hw
->st_idx
!= idx
);
2541 /* Fully processed status ring so clear irq */
2542 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2545 sky2_rx_done(hw
, 0, total_packets
[0], total_bytes
[0]);
2546 sky2_rx_done(hw
, 1, total_packets
[1], total_bytes
[1]);
2551 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2553 struct net_device
*dev
= hw
->dev
[port
];
2555 if (net_ratelimit())
2556 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2559 if (status
& Y2_IS_PAR_RD1
) {
2560 if (net_ratelimit())
2561 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2564 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2567 if (status
& Y2_IS_PAR_WR1
) {
2568 if (net_ratelimit())
2569 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2572 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2575 if (status
& Y2_IS_PAR_MAC1
) {
2576 if (net_ratelimit())
2577 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2578 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2581 if (status
& Y2_IS_PAR_RX1
) {
2582 if (net_ratelimit())
2583 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2584 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2587 if (status
& Y2_IS_TCP_TXA1
) {
2588 if (net_ratelimit())
2589 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2591 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2595 static void sky2_hw_intr(struct sky2_hw
*hw
)
2597 struct pci_dev
*pdev
= hw
->pdev
;
2598 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2599 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2603 if (status
& Y2_IS_TIST_OV
)
2604 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2606 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2609 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2610 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2611 if (net_ratelimit())
2612 dev_err(&pdev
->dev
, "PCI hardware error (0x%x)\n",
2615 sky2_pci_write16(hw
, PCI_STATUS
,
2616 pci_err
| PCI_STATUS_ERROR_BITS
);
2617 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2620 if (status
& Y2_IS_PCI_EXP
) {
2621 /* PCI-Express uncorrectable Error occurred */
2624 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2625 err
= sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2626 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2628 if (net_ratelimit())
2629 dev_err(&pdev
->dev
, "PCI Express error (0x%x)\n", err
);
2631 sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2632 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2635 if (status
& Y2_HWE_L1_MASK
)
2636 sky2_hw_error(hw
, 0, status
);
2638 if (status
& Y2_HWE_L1_MASK
)
2639 sky2_hw_error(hw
, 1, status
);
2642 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2644 struct net_device
*dev
= hw
->dev
[port
];
2645 struct sky2_port
*sky2
= netdev_priv(dev
);
2646 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2648 if (netif_msg_intr(sky2
))
2649 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2652 if (status
& GM_IS_RX_CO_OV
)
2653 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2655 if (status
& GM_IS_TX_CO_OV
)
2656 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2658 if (status
& GM_IS_RX_FF_OR
) {
2659 ++dev
->stats
.rx_fifo_errors
;
2660 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2663 if (status
& GM_IS_TX_FF_UR
) {
2664 ++dev
->stats
.tx_fifo_errors
;
2665 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2669 /* This should never happen it is a bug. */
2670 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
,
2671 u16 q
, unsigned ring_size
)
2673 struct net_device
*dev
= hw
->dev
[port
];
2674 struct sky2_port
*sky2
= netdev_priv(dev
);
2676 const u64
*le
= (q
== Q_R1
|| q
== Q_R2
)
2677 ? (u64
*) sky2
->rx_le
: (u64
*) sky2
->tx_le
;
2679 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2680 printk(KERN_ERR PFX
"%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2681 dev
->name
, (unsigned) q
, idx
, (unsigned long long) le
[idx
],
2682 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2684 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2687 static int sky2_rx_hung(struct net_device
*dev
)
2689 struct sky2_port
*sky2
= netdev_priv(dev
);
2690 struct sky2_hw
*hw
= sky2
->hw
;
2691 unsigned port
= sky2
->port
;
2692 unsigned rxq
= rxqaddr
[port
];
2693 u32 mac_rp
= sky2_read32(hw
, SK_REG(port
, RX_GMF_RP
));
2694 u8 mac_lev
= sky2_read8(hw
, SK_REG(port
, RX_GMF_RLEV
));
2695 u8 fifo_rp
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RP
));
2696 u8 fifo_lev
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RL
));
2698 /* If idle and MAC or PCI is stuck */
2699 if (sky2
->check
.last
== dev
->last_rx
&&
2700 ((mac_rp
== sky2
->check
.mac_rp
&&
2701 mac_lev
!= 0 && mac_lev
>= sky2
->check
.mac_lev
) ||
2702 /* Check if the PCI RX hang */
2703 (fifo_rp
== sky2
->check
.fifo_rp
&&
2704 fifo_lev
!= 0 && fifo_lev
>= sky2
->check
.fifo_lev
))) {
2705 printk(KERN_DEBUG PFX
"%s: hung mac %d:%d fifo %d (%d:%d)\n",
2706 dev
->name
, mac_lev
, mac_rp
, fifo_lev
, fifo_rp
,
2707 sky2_read8(hw
, Q_ADDR(rxq
, Q_WP
)));
2710 sky2
->check
.last
= dev
->last_rx
;
2711 sky2
->check
.mac_rp
= mac_rp
;
2712 sky2
->check
.mac_lev
= mac_lev
;
2713 sky2
->check
.fifo_rp
= fifo_rp
;
2714 sky2
->check
.fifo_lev
= fifo_lev
;
2719 static void sky2_watchdog(unsigned long arg
)
2721 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2723 /* Check for lost IRQ once a second */
2724 if (sky2_read32(hw
, B0_ISRC
)) {
2725 napi_schedule(&hw
->napi
);
2729 for (i
= 0; i
< hw
->ports
; i
++) {
2730 struct net_device
*dev
= hw
->dev
[i
];
2731 if (!netif_running(dev
))
2735 /* For chips with Rx FIFO, check if stuck */
2736 if ((hw
->flags
& SKY2_HW_RAM_BUFFER
) &&
2737 sky2_rx_hung(dev
)) {
2738 pr_info(PFX
"%s: receiver hang detected\n",
2740 schedule_work(&hw
->restart_work
);
2749 mod_timer(&hw
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
2752 /* Hardware/software error handling */
2753 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2755 if (net_ratelimit())
2756 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2758 if (status
& Y2_IS_HW_ERR
)
2761 if (status
& Y2_IS_IRQ_MAC1
)
2762 sky2_mac_intr(hw
, 0);
2764 if (status
& Y2_IS_IRQ_MAC2
)
2765 sky2_mac_intr(hw
, 1);
2767 if (status
& Y2_IS_CHK_RX1
)
2768 sky2_le_error(hw
, 0, Q_R1
, RX_LE_SIZE
);
2770 if (status
& Y2_IS_CHK_RX2
)
2771 sky2_le_error(hw
, 1, Q_R2
, RX_LE_SIZE
);
2773 if (status
& Y2_IS_CHK_TXA1
)
2774 sky2_le_error(hw
, 0, Q_XA1
, TX_RING_SIZE
);
2776 if (status
& Y2_IS_CHK_TXA2
)
2777 sky2_le_error(hw
, 1, Q_XA2
, TX_RING_SIZE
);
2780 static int sky2_poll(struct napi_struct
*napi
, int work_limit
)
2782 struct sky2_hw
*hw
= container_of(napi
, struct sky2_hw
, napi
);
2783 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2787 if (unlikely(status
& Y2_IS_ERROR
))
2788 sky2_err_intr(hw
, status
);
2790 if (status
& Y2_IS_IRQ_PHY1
)
2791 sky2_phy_intr(hw
, 0);
2793 if (status
& Y2_IS_IRQ_PHY2
)
2794 sky2_phy_intr(hw
, 1);
2796 while ((idx
= sky2_read16(hw
, STAT_PUT_IDX
)) != hw
->st_idx
) {
2797 work_done
+= sky2_status_intr(hw
, work_limit
- work_done
, idx
);
2799 if (work_done
>= work_limit
)
2803 napi_complete(napi
);
2804 sky2_read32(hw
, B0_Y2_SP_LISR
);
2810 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2812 struct sky2_hw
*hw
= dev_id
;
2815 /* Reading this mask interrupts as side effect */
2816 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2817 if (status
== 0 || status
== ~0)
2820 prefetch(&hw
->st_le
[hw
->st_idx
]);
2822 napi_schedule(&hw
->napi
);
2827 #ifdef CONFIG_NET_POLL_CONTROLLER
2828 static void sky2_netpoll(struct net_device
*dev
)
2830 struct sky2_port
*sky2
= netdev_priv(dev
);
2832 napi_schedule(&sky2
->hw
->napi
);
2836 /* Chip internal frequency for clock calculations */
2837 static u32
sky2_mhz(const struct sky2_hw
*hw
)
2839 switch (hw
->chip_id
) {
2840 case CHIP_ID_YUKON_EC
:
2841 case CHIP_ID_YUKON_EC_U
:
2842 case CHIP_ID_YUKON_EX
:
2843 case CHIP_ID_YUKON_SUPR
:
2844 case CHIP_ID_YUKON_UL_2
:
2847 case CHIP_ID_YUKON_FE
:
2850 case CHIP_ID_YUKON_FE_P
:
2853 case CHIP_ID_YUKON_XL
:
2861 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2863 return sky2_mhz(hw
) * us
;
2866 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2868 return clk
/ sky2_mhz(hw
);
2872 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2876 /* Enable all clocks and check for bad PCI access */
2877 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2879 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2881 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2882 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2884 switch(hw
->chip_id
) {
2885 case CHIP_ID_YUKON_XL
:
2886 hw
->flags
= SKY2_HW_GIGABIT
| SKY2_HW_NEWER_PHY
;
2889 case CHIP_ID_YUKON_EC_U
:
2890 hw
->flags
= SKY2_HW_GIGABIT
2892 | SKY2_HW_ADV_POWER_CTL
;
2895 case CHIP_ID_YUKON_EX
:
2896 hw
->flags
= SKY2_HW_GIGABIT
2899 | SKY2_HW_ADV_POWER_CTL
;
2901 /* New transmit checksum */
2902 if (hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
2903 hw
->flags
|= SKY2_HW_AUTO_TX_SUM
;
2906 case CHIP_ID_YUKON_EC
:
2907 /* This rev is really old, and requires untested workarounds */
2908 if (hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2909 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-EC rev A1\n");
2912 hw
->flags
= SKY2_HW_GIGABIT
;
2915 case CHIP_ID_YUKON_FE
:
2918 case CHIP_ID_YUKON_FE_P
:
2919 hw
->flags
= SKY2_HW_NEWER_PHY
2921 | SKY2_HW_AUTO_TX_SUM
2922 | SKY2_HW_ADV_POWER_CTL
;
2925 case CHIP_ID_YUKON_SUPR
:
2926 hw
->flags
= SKY2_HW_GIGABIT
2929 | SKY2_HW_AUTO_TX_SUM
2930 | SKY2_HW_ADV_POWER_CTL
;
2933 case CHIP_ID_YUKON_UL_2
:
2934 hw
->flags
= SKY2_HW_GIGABIT
2935 | SKY2_HW_ADV_POWER_CTL
;
2939 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2944 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2945 if (hw
->pmd_type
== 'L' || hw
->pmd_type
== 'S' || hw
->pmd_type
== 'P')
2946 hw
->flags
|= SKY2_HW_FIBRE_PHY
;
2949 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2950 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2951 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2958 static void sky2_reset(struct sky2_hw
*hw
)
2960 struct pci_dev
*pdev
= hw
->pdev
;
2963 u32 hwe_mask
= Y2_HWE_ALL_MASK
;
2966 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
2967 status
= sky2_read16(hw
, HCU_CCSR
);
2968 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
2969 HCU_CCSR_UC_STATE_MSK
);
2970 sky2_write16(hw
, HCU_CCSR
, status
);
2972 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2973 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2976 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2977 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2979 /* allow writes to PCI config */
2980 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2982 /* clear PCI errors, if any */
2983 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2984 status
|= PCI_STATUS_ERROR_BITS
;
2985 sky2_pci_write16(hw
, PCI_STATUS
, status
);
2987 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2989 cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
2991 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2994 /* If error bit is stuck on ignore it */
2995 if (sky2_read32(hw
, B0_HWE_ISRC
) & Y2_IS_PCI_EXP
)
2996 dev_info(&pdev
->dev
, "ignoring stuck error report bit\n");
2998 hwe_mask
|= Y2_IS_PCI_EXP
;
3002 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3004 for (i
= 0; i
< hw
->ports
; i
++) {
3005 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
3006 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
3008 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
3009 hw
->chip_id
== CHIP_ID_YUKON_SUPR
)
3010 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
3011 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
3015 /* Clear I2C IRQ noise */
3016 sky2_write32(hw
, B2_I2C_IRQ
, 1);
3018 /* turn off hardware timer (unused) */
3019 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
3020 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
3022 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
3024 /* Turn off descriptor polling */
3025 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
3027 /* Turn off receive timestamp */
3028 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
3029 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
3031 /* enable the Tx Arbiters */
3032 for (i
= 0; i
< hw
->ports
; i
++)
3033 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
3035 /* Initialize ram interface */
3036 for (i
= 0; i
< hw
->ports
; i
++) {
3037 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
3039 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
3040 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
3041 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
3042 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
3043 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
3044 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
3045 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
3046 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
3047 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
3048 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
3049 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
3050 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
3053 sky2_write32(hw
, B0_HWE_IMSK
, hwe_mask
);
3055 for (i
= 0; i
< hw
->ports
; i
++)
3056 sky2_gmac_reset(hw
, i
);
3058 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
3061 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
3062 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
3064 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
3065 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
3067 /* Set the list last index */
3068 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
3070 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
3071 sky2_write8(hw
, STAT_FIFO_WM
, 16);
3073 /* set Status-FIFO ISR watermark */
3074 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
3075 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
3077 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
3079 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
3080 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
3081 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
3083 /* enable status unit */
3084 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
3086 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3087 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3088 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3091 /* Take device down (offline).
3092 * Equivalent to doing dev_stop() but this does not
3093 * inform upper layers of the transistion.
3095 static void sky2_detach(struct net_device
*dev
)
3097 if (netif_running(dev
)) {
3098 netif_device_detach(dev
); /* stop txq */
3103 /* Bring device back after doing sky2_detach */
3104 static int sky2_reattach(struct net_device
*dev
)
3108 if (netif_running(dev
)) {
3111 printk(KERN_INFO PFX
"%s: could not restart %d\n",
3115 netif_device_attach(dev
);
3116 sky2_set_multicast(dev
);
3123 static void sky2_restart(struct work_struct
*work
)
3125 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
3129 for (i
= 0; i
< hw
->ports
; i
++)
3130 sky2_detach(hw
->dev
[i
]);
3132 napi_disable(&hw
->napi
);
3133 sky2_write32(hw
, B0_IMSK
, 0);
3135 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3136 napi_enable(&hw
->napi
);
3138 for (i
= 0; i
< hw
->ports
; i
++)
3139 sky2_reattach(hw
->dev
[i
]);
3144 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
3146 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
3149 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3151 const struct sky2_port
*sky2
= netdev_priv(dev
);
3153 wol
->supported
= sky2_wol_supported(sky2
->hw
);
3154 wol
->wolopts
= sky2
->wol
;
3157 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3159 struct sky2_port
*sky2
= netdev_priv(dev
);
3160 struct sky2_hw
*hw
= sky2
->hw
;
3162 if ((wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
))
3163 || !device_can_wakeup(&hw
->pdev
->dev
))
3166 sky2
->wol
= wol
->wolopts
;
3168 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3169 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3170 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
3171 sky2_write32(hw
, B0_CTST
, sky2
->wol
3172 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
3174 device_set_wakeup_enable(&hw
->pdev
->dev
, sky2
->wol
);
3176 if (!netif_running(dev
))
3177 sky2_wol_init(sky2
);
3181 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
3183 if (sky2_is_copper(hw
)) {
3184 u32 modes
= SUPPORTED_10baseT_Half
3185 | SUPPORTED_10baseT_Full
3186 | SUPPORTED_100baseT_Half
3187 | SUPPORTED_100baseT_Full
3188 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
3190 if (hw
->flags
& SKY2_HW_GIGABIT
)
3191 modes
|= SUPPORTED_1000baseT_Half
3192 | SUPPORTED_1000baseT_Full
;
3195 return SUPPORTED_1000baseT_Half
3196 | SUPPORTED_1000baseT_Full
3201 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3203 struct sky2_port
*sky2
= netdev_priv(dev
);
3204 struct sky2_hw
*hw
= sky2
->hw
;
3206 ecmd
->transceiver
= XCVR_INTERNAL
;
3207 ecmd
->supported
= sky2_supported_modes(hw
);
3208 ecmd
->phy_address
= PHY_ADDR_MARV
;
3209 if (sky2_is_copper(hw
)) {
3210 ecmd
->port
= PORT_TP
;
3211 ecmd
->speed
= sky2
->speed
;
3213 ecmd
->speed
= SPEED_1000
;
3214 ecmd
->port
= PORT_FIBRE
;
3217 ecmd
->advertising
= sky2
->advertising
;
3218 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
3219 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3220 ecmd
->duplex
= sky2
->duplex
;
3224 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3226 struct sky2_port
*sky2
= netdev_priv(dev
);
3227 const struct sky2_hw
*hw
= sky2
->hw
;
3228 u32 supported
= sky2_supported_modes(hw
);
3230 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3231 sky2
->flags
|= SKY2_FLAG_AUTO_SPEED
;
3232 ecmd
->advertising
= supported
;
3238 switch (ecmd
->speed
) {
3240 if (ecmd
->duplex
== DUPLEX_FULL
)
3241 setting
= SUPPORTED_1000baseT_Full
;
3242 else if (ecmd
->duplex
== DUPLEX_HALF
)
3243 setting
= SUPPORTED_1000baseT_Half
;
3248 if (ecmd
->duplex
== DUPLEX_FULL
)
3249 setting
= SUPPORTED_100baseT_Full
;
3250 else if (ecmd
->duplex
== DUPLEX_HALF
)
3251 setting
= SUPPORTED_100baseT_Half
;
3257 if (ecmd
->duplex
== DUPLEX_FULL
)
3258 setting
= SUPPORTED_10baseT_Full
;
3259 else if (ecmd
->duplex
== DUPLEX_HALF
)
3260 setting
= SUPPORTED_10baseT_Half
;
3268 if ((setting
& supported
) == 0)
3271 sky2
->speed
= ecmd
->speed
;
3272 sky2
->duplex
= ecmd
->duplex
;
3273 sky2
->flags
&= ~SKY2_FLAG_AUTO_SPEED
;
3276 sky2
->advertising
= ecmd
->advertising
;
3278 if (netif_running(dev
)) {
3279 sky2_phy_reinit(sky2
);
3280 sky2_set_multicast(dev
);
3286 static void sky2_get_drvinfo(struct net_device
*dev
,
3287 struct ethtool_drvinfo
*info
)
3289 struct sky2_port
*sky2
= netdev_priv(dev
);
3291 strcpy(info
->driver
, DRV_NAME
);
3292 strcpy(info
->version
, DRV_VERSION
);
3293 strcpy(info
->fw_version
, "N/A");
3294 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
3297 static const struct sky2_stat
{
3298 char name
[ETH_GSTRING_LEN
];
3301 { "tx_bytes", GM_TXO_OK_HI
},
3302 { "rx_bytes", GM_RXO_OK_HI
},
3303 { "tx_broadcast", GM_TXF_BC_OK
},
3304 { "rx_broadcast", GM_RXF_BC_OK
},
3305 { "tx_multicast", GM_TXF_MC_OK
},
3306 { "rx_multicast", GM_RXF_MC_OK
},
3307 { "tx_unicast", GM_TXF_UC_OK
},
3308 { "rx_unicast", GM_RXF_UC_OK
},
3309 { "tx_mac_pause", GM_TXF_MPAUSE
},
3310 { "rx_mac_pause", GM_RXF_MPAUSE
},
3311 { "collisions", GM_TXF_COL
},
3312 { "late_collision",GM_TXF_LAT_COL
},
3313 { "aborted", GM_TXF_ABO_COL
},
3314 { "single_collisions", GM_TXF_SNG_COL
},
3315 { "multi_collisions", GM_TXF_MUL_COL
},
3317 { "rx_short", GM_RXF_SHT
},
3318 { "rx_runt", GM_RXE_FRAG
},
3319 { "rx_64_byte_packets", GM_RXF_64B
},
3320 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
3321 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
3322 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
3323 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
3324 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
3325 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
3326 { "rx_too_long", GM_RXF_LNG_ERR
},
3327 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
3328 { "rx_jabber", GM_RXF_JAB_PKT
},
3329 { "rx_fcs_error", GM_RXF_FCS_ERR
},
3331 { "tx_64_byte_packets", GM_TXF_64B
},
3332 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
3333 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
3334 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
3335 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
3336 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
3337 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
3338 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
3341 static u32
sky2_get_rx_csum(struct net_device
*dev
)
3343 struct sky2_port
*sky2
= netdev_priv(dev
);
3345 return !!(sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
);
3348 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
3350 struct sky2_port
*sky2
= netdev_priv(dev
);
3353 sky2
->flags
|= SKY2_FLAG_RX_CHECKSUM
;
3355 sky2
->flags
&= ~SKY2_FLAG_RX_CHECKSUM
;
3357 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
3358 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
3363 static u32
sky2_get_msglevel(struct net_device
*netdev
)
3365 struct sky2_port
*sky2
= netdev_priv(netdev
);
3366 return sky2
->msg_enable
;
3369 static int sky2_nway_reset(struct net_device
*dev
)
3371 struct sky2_port
*sky2
= netdev_priv(dev
);
3373 if (!netif_running(dev
) || !(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
))
3376 sky2_phy_reinit(sky2
);
3377 sky2_set_multicast(dev
);
3382 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
3384 struct sky2_hw
*hw
= sky2
->hw
;
3385 unsigned port
= sky2
->port
;
3388 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
3389 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
3390 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
3391 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
3393 for (i
= 2; i
< count
; i
++)
3394 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
3397 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3399 struct sky2_port
*sky2
= netdev_priv(netdev
);
3400 sky2
->msg_enable
= value
;
3403 static int sky2_get_sset_count(struct net_device
*dev
, int sset
)
3407 return ARRAY_SIZE(sky2_stats
);
3413 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3414 struct ethtool_stats
*stats
, u64
* data
)
3416 struct sky2_port
*sky2
= netdev_priv(dev
);
3418 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3421 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3425 switch (stringset
) {
3427 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3428 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3429 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3434 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3436 struct sky2_port
*sky2
= netdev_priv(dev
);
3437 struct sky2_hw
*hw
= sky2
->hw
;
3438 unsigned port
= sky2
->port
;
3439 const struct sockaddr
*addr
= p
;
3441 if (!is_valid_ether_addr(addr
->sa_data
))
3442 return -EADDRNOTAVAIL
;
3444 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3445 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3446 dev
->dev_addr
, ETH_ALEN
);
3447 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3448 dev
->dev_addr
, ETH_ALEN
);
3450 /* virtual address for data */
3451 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3453 /* physical address: used for pause frames */
3454 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3459 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3463 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3464 filter
[bit
>> 3] |= 1 << (bit
& 7);
3467 static void sky2_set_multicast(struct net_device
*dev
)
3469 struct sky2_port
*sky2
= netdev_priv(dev
);
3470 struct sky2_hw
*hw
= sky2
->hw
;
3471 unsigned port
= sky2
->port
;
3472 struct dev_mc_list
*list
= dev
->mc_list
;
3476 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3478 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3479 memset(filter
, 0, sizeof(filter
));
3481 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3482 reg
|= GM_RXCR_UCF_ENA
;
3484 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3485 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3486 else if (dev
->flags
& IFF_ALLMULTI
)
3487 memset(filter
, 0xff, sizeof(filter
));
3488 else if (dev
->mc_count
== 0 && !rx_pause
)
3489 reg
&= ~GM_RXCR_MCF_ENA
;
3492 reg
|= GM_RXCR_MCF_ENA
;
3495 sky2_add_filter(filter
, pause_mc_addr
);
3497 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3498 sky2_add_filter(filter
, list
->dmi_addr
);
3501 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3502 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3503 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3504 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3505 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3506 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3507 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3508 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3510 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3513 /* Can have one global because blinking is controlled by
3514 * ethtool and that is always under RTNL mutex
3516 static void sky2_led(struct sky2_port
*sky2
, enum led_mode mode
)
3518 struct sky2_hw
*hw
= sky2
->hw
;
3519 unsigned port
= sky2
->port
;
3521 spin_lock_bh(&sky2
->phy_lock
);
3522 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3523 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3524 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
3526 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3527 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3531 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3532 PHY_M_LEDC_LOS_CTRL(8) |
3533 PHY_M_LEDC_INIT_CTRL(8) |
3534 PHY_M_LEDC_STA1_CTRL(8) |
3535 PHY_M_LEDC_STA0_CTRL(8));
3538 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3539 PHY_M_LEDC_LOS_CTRL(9) |
3540 PHY_M_LEDC_INIT_CTRL(9) |
3541 PHY_M_LEDC_STA1_CTRL(9) |
3542 PHY_M_LEDC_STA0_CTRL(9));
3545 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3546 PHY_M_LEDC_LOS_CTRL(0xa) |
3547 PHY_M_LEDC_INIT_CTRL(0xa) |
3548 PHY_M_LEDC_STA1_CTRL(0xa) |
3549 PHY_M_LEDC_STA0_CTRL(0xa));
3552 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3553 PHY_M_LEDC_LOS_CTRL(1) |
3554 PHY_M_LEDC_INIT_CTRL(8) |
3555 PHY_M_LEDC_STA1_CTRL(7) |
3556 PHY_M_LEDC_STA0_CTRL(7));
3559 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3561 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3562 PHY_M_LED_MO_DUP(mode
) |
3563 PHY_M_LED_MO_10(mode
) |
3564 PHY_M_LED_MO_100(mode
) |
3565 PHY_M_LED_MO_1000(mode
) |
3566 PHY_M_LED_MO_RX(mode
) |
3567 PHY_M_LED_MO_TX(mode
));
3569 spin_unlock_bh(&sky2
->phy_lock
);
3572 /* blink LED's for finding board */
3573 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3575 struct sky2_port
*sky2
= netdev_priv(dev
);
3581 for (i
= 0; i
< data
; i
++) {
3582 sky2_led(sky2
, MO_LED_ON
);
3583 if (msleep_interruptible(500))
3585 sky2_led(sky2
, MO_LED_OFF
);
3586 if (msleep_interruptible(500))
3589 sky2_led(sky2
, MO_LED_NORM
);
3594 static void sky2_get_pauseparam(struct net_device
*dev
,
3595 struct ethtool_pauseparam
*ecmd
)
3597 struct sky2_port
*sky2
= netdev_priv(dev
);
3599 switch (sky2
->flow_mode
) {
3601 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3604 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3607 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3610 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3613 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
)
3614 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3617 static int sky2_set_pauseparam(struct net_device
*dev
,
3618 struct ethtool_pauseparam
*ecmd
)
3620 struct sky2_port
*sky2
= netdev_priv(dev
);
3622 if (ecmd
->autoneg
== AUTONEG_ENABLE
)
3623 sky2
->flags
|= SKY2_FLAG_AUTO_PAUSE
;
3625 sky2
->flags
&= ~SKY2_FLAG_AUTO_PAUSE
;
3627 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3629 if (netif_running(dev
))
3630 sky2_phy_reinit(sky2
);
3635 static int sky2_get_coalesce(struct net_device
*dev
,
3636 struct ethtool_coalesce
*ecmd
)
3638 struct sky2_port
*sky2
= netdev_priv(dev
);
3639 struct sky2_hw
*hw
= sky2
->hw
;
3641 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3642 ecmd
->tx_coalesce_usecs
= 0;
3644 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3645 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3647 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3649 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3650 ecmd
->rx_coalesce_usecs
= 0;
3652 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3653 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3655 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3657 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3658 ecmd
->rx_coalesce_usecs_irq
= 0;
3660 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3661 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3664 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3669 /* Note: this affect both ports */
3670 static int sky2_set_coalesce(struct net_device
*dev
,
3671 struct ethtool_coalesce
*ecmd
)
3673 struct sky2_port
*sky2
= netdev_priv(dev
);
3674 struct sky2_hw
*hw
= sky2
->hw
;
3675 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3677 if (ecmd
->tx_coalesce_usecs
> tmax
||
3678 ecmd
->rx_coalesce_usecs
> tmax
||
3679 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3682 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3684 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3686 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3689 if (ecmd
->tx_coalesce_usecs
== 0)
3690 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3692 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3693 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3694 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3696 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3698 if (ecmd
->rx_coalesce_usecs
== 0)
3699 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3701 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3702 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3703 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3705 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3707 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3708 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3710 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3711 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3712 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3714 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3718 static void sky2_get_ringparam(struct net_device
*dev
,
3719 struct ethtool_ringparam
*ering
)
3721 struct sky2_port
*sky2
= netdev_priv(dev
);
3723 ering
->rx_max_pending
= RX_MAX_PENDING
;
3724 ering
->rx_mini_max_pending
= 0;
3725 ering
->rx_jumbo_max_pending
= 0;
3726 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3728 ering
->rx_pending
= sky2
->rx_pending
;
3729 ering
->rx_mini_pending
= 0;
3730 ering
->rx_jumbo_pending
= 0;
3731 ering
->tx_pending
= sky2
->tx_pending
;
3734 static int sky2_set_ringparam(struct net_device
*dev
,
3735 struct ethtool_ringparam
*ering
)
3737 struct sky2_port
*sky2
= netdev_priv(dev
);
3739 if (ering
->rx_pending
> RX_MAX_PENDING
||
3740 ering
->rx_pending
< 8 ||
3741 ering
->tx_pending
< MAX_SKB_TX_LE
||
3742 ering
->tx_pending
> TX_RING_SIZE
- 1)
3747 sky2
->rx_pending
= ering
->rx_pending
;
3748 sky2
->tx_pending
= ering
->tx_pending
;
3750 return sky2_reattach(dev
);
3753 static int sky2_get_regs_len(struct net_device
*dev
)
3759 * Returns copy of control register region
3760 * Note: ethtool_get_regs always provides full size (16k) buffer
3762 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3765 const struct sky2_port
*sky2
= netdev_priv(dev
);
3766 const void __iomem
*io
= sky2
->hw
->regs
;
3771 for (b
= 0; b
< 128; b
++) {
3772 /* This complicated switch statement is to make sure and
3773 * only access regions that are unreserved.
3774 * Some blocks are only valid on dual port cards.
3775 * and block 3 has some special diagnostic registers that
3780 /* skip diagnostic ram region */
3781 memcpy_fromio(p
+ 0x10, io
+ 0x10, 128 - 0x10);
3784 /* dual port cards only */
3785 case 5: /* Tx Arbiter 2 */
3787 case 14 ... 15: /* TX2 */
3788 case 17: case 19: /* Ram Buffer 2 */
3789 case 22 ... 23: /* Tx Ram Buffer 2 */
3790 case 25: /* Rx MAC Fifo 1 */
3791 case 27: /* Tx MAC Fifo 2 */
3792 case 31: /* GPHY 2 */
3793 case 40 ... 47: /* Pattern Ram 2 */
3794 case 52: case 54: /* TCP Segmentation 2 */
3795 case 112 ... 116: /* GMAC 2 */
3796 if (sky2
->hw
->ports
== 1)
3799 case 0: /* Control */
3800 case 2: /* Mac address */
3801 case 4: /* Tx Arbiter 1 */
3802 case 7: /* PCI express reg */
3804 case 12 ... 13: /* TX1 */
3805 case 16: case 18:/* Rx Ram Buffer 1 */
3806 case 20 ... 21: /* Tx Ram Buffer 1 */
3807 case 24: /* Rx MAC Fifo 1 */
3808 case 26: /* Tx MAC Fifo 1 */
3809 case 28 ... 29: /* Descriptor and status unit */
3810 case 30: /* GPHY 1*/
3811 case 32 ... 39: /* Pattern Ram 1 */
3812 case 48: case 50: /* TCP Segmentation 1 */
3813 case 56 ... 60: /* PCI space */
3814 case 80 ... 84: /* GMAC 1 */
3815 memcpy_fromio(p
, io
, 128);
3827 /* In order to do Jumbo packets on these chips, need to turn off the
3828 * transmit store/forward. Therefore checksum offload won't work.
3830 static int no_tx_offload(struct net_device
*dev
)
3832 const struct sky2_port
*sky2
= netdev_priv(dev
);
3833 const struct sky2_hw
*hw
= sky2
->hw
;
3835 return dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
;
3838 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3840 if (data
&& no_tx_offload(dev
))
3843 return ethtool_op_set_tx_csum(dev
, data
);
3847 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3849 if (data
&& no_tx_offload(dev
))
3852 return ethtool_op_set_tso(dev
, data
);
3855 static int sky2_get_eeprom_len(struct net_device
*dev
)
3857 struct sky2_port
*sky2
= netdev_priv(dev
);
3858 struct sky2_hw
*hw
= sky2
->hw
;
3861 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
3862 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
3865 static int sky2_vpd_wait(const struct sky2_hw
*hw
, int cap
, u16 busy
)
3867 unsigned long start
= jiffies
;
3869 while ( (sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
) == busy
) {
3870 /* Can take up to 10.6 ms for write */
3871 if (time_after(jiffies
, start
+ HZ
/4)) {
3872 dev_err(&hw
->pdev
->dev
, PFX
"VPD cycle timed out");
3881 static int sky2_vpd_read(struct sky2_hw
*hw
, int cap
, void *data
,
3882 u16 offset
, size_t length
)
3886 while (length
> 0) {
3889 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
3890 rc
= sky2_vpd_wait(hw
, cap
, 0);
3894 val
= sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
3896 memcpy(data
, &val
, min(sizeof(val
), length
));
3897 offset
+= sizeof(u32
);
3898 data
+= sizeof(u32
);
3899 length
-= sizeof(u32
);
3905 static int sky2_vpd_write(struct sky2_hw
*hw
, int cap
, const void *data
,
3906 u16 offset
, unsigned int length
)
3911 for (i
= 0; i
< length
; i
+= sizeof(u32
)) {
3912 u32 val
= *(u32
*)(data
+ i
);
3914 sky2_pci_write32(hw
, cap
+ PCI_VPD_DATA
, val
);
3915 sky2_pci_write32(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
3917 rc
= sky2_vpd_wait(hw
, cap
, PCI_VPD_ADDR_F
);
3924 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3927 struct sky2_port
*sky2
= netdev_priv(dev
);
3928 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3933 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
3935 return sky2_vpd_read(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
3938 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
3941 struct sky2_port
*sky2
= netdev_priv(dev
);
3942 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
3947 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
3950 /* Partial writes not supported */
3951 if ((eeprom
->offset
& 3) || (eeprom
->len
& 3))
3954 return sky2_vpd_write(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
3958 static const struct ethtool_ops sky2_ethtool_ops
= {
3959 .get_settings
= sky2_get_settings
,
3960 .set_settings
= sky2_set_settings
,
3961 .get_drvinfo
= sky2_get_drvinfo
,
3962 .get_wol
= sky2_get_wol
,
3963 .set_wol
= sky2_set_wol
,
3964 .get_msglevel
= sky2_get_msglevel
,
3965 .set_msglevel
= sky2_set_msglevel
,
3966 .nway_reset
= sky2_nway_reset
,
3967 .get_regs_len
= sky2_get_regs_len
,
3968 .get_regs
= sky2_get_regs
,
3969 .get_link
= ethtool_op_get_link
,
3970 .get_eeprom_len
= sky2_get_eeprom_len
,
3971 .get_eeprom
= sky2_get_eeprom
,
3972 .set_eeprom
= sky2_set_eeprom
,
3973 .set_sg
= ethtool_op_set_sg
,
3974 .set_tx_csum
= sky2_set_tx_csum
,
3975 .set_tso
= sky2_set_tso
,
3976 .get_rx_csum
= sky2_get_rx_csum
,
3977 .set_rx_csum
= sky2_set_rx_csum
,
3978 .get_strings
= sky2_get_strings
,
3979 .get_coalesce
= sky2_get_coalesce
,
3980 .set_coalesce
= sky2_set_coalesce
,
3981 .get_ringparam
= sky2_get_ringparam
,
3982 .set_ringparam
= sky2_set_ringparam
,
3983 .get_pauseparam
= sky2_get_pauseparam
,
3984 .set_pauseparam
= sky2_set_pauseparam
,
3985 .phys_id
= sky2_phys_id
,
3986 .get_sset_count
= sky2_get_sset_count
,
3987 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3990 #ifdef CONFIG_SKY2_DEBUG
3992 static struct dentry
*sky2_debug
;
3996 * Read and parse the first part of Vital Product Data
3998 #define VPD_SIZE 128
3999 #define VPD_MAGIC 0x82
4001 static const struct vpd_tag
{
4005 { "PN", "Part Number" },
4006 { "EC", "Engineering Level" },
4007 { "MN", "Manufacturer" },
4008 { "SN", "Serial Number" },
4009 { "YA", "Asset Tag" },
4010 { "VL", "First Error Log Message" },
4011 { "VF", "Second Error Log Message" },
4012 { "VB", "Boot Agent ROM Configuration" },
4013 { "VE", "EFI UNDI Configuration" },
4016 static void sky2_show_vpd(struct seq_file
*seq
, struct sky2_hw
*hw
)
4024 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
4025 vpd_size
= 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
4027 seq_printf(seq
, "%s Product Data\n", pci_name(hw
->pdev
));
4028 buf
= kmalloc(vpd_size
, GFP_KERNEL
);
4030 seq_puts(seq
, "no memory!\n");
4034 if (pci_read_vpd(hw
->pdev
, 0, vpd_size
, buf
) < 0) {
4035 seq_puts(seq
, "VPD read failed\n");
4039 if (buf
[0] != VPD_MAGIC
) {
4040 seq_printf(seq
, "VPD tag mismatch: %#x\n", buf
[0]);
4044 if (len
== 0 || len
> vpd_size
- 4) {
4045 seq_printf(seq
, "Invalid id length: %d\n", len
);
4049 seq_printf(seq
, "%.*s\n", len
, buf
+ 3);
4052 while (offs
< vpd_size
- 4) {
4055 if (!memcmp("RW", buf
+ offs
, 2)) /* end marker */
4057 len
= buf
[offs
+ 2];
4058 if (offs
+ len
+ 3 >= vpd_size
)
4061 for (i
= 0; i
< ARRAY_SIZE(vpd_tags
); i
++) {
4062 if (!memcmp(vpd_tags
[i
].tag
, buf
+ offs
, 2)) {
4063 seq_printf(seq
, " %s: %.*s\n",
4064 vpd_tags
[i
].label
, len
, buf
+ offs
+ 3);
4074 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
4076 struct net_device
*dev
= seq
->private;
4077 const struct sky2_port
*sky2
= netdev_priv(dev
);
4078 struct sky2_hw
*hw
= sky2
->hw
;
4079 unsigned port
= sky2
->port
;
4083 sky2_show_vpd(seq
, hw
);
4085 seq_printf(seq
, "\nIRQ src=%x mask=%x control=%x\n",
4086 sky2_read32(hw
, B0_ISRC
),
4087 sky2_read32(hw
, B0_IMSK
),
4088 sky2_read32(hw
, B0_Y2_SP_ICR
));
4090 if (!netif_running(dev
)) {
4091 seq_printf(seq
, "network not running\n");
4095 napi_disable(&hw
->napi
);
4096 last
= sky2_read16(hw
, STAT_PUT_IDX
);
4098 if (hw
->st_idx
== last
)
4099 seq_puts(seq
, "Status ring (empty)\n");
4101 seq_puts(seq
, "Status ring\n");
4102 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< STATUS_RING_SIZE
;
4103 idx
= RING_NEXT(idx
, STATUS_RING_SIZE
)) {
4104 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
4105 seq_printf(seq
, "[%d] %#x %d %#x\n",
4106 idx
, le
->opcode
, le
->length
, le
->status
);
4108 seq_puts(seq
, "\n");
4111 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
4112 sky2
->tx_cons
, sky2
->tx_prod
,
4113 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
4114 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
4116 /* Dump contents of tx ring */
4118 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< TX_RING_SIZE
;
4119 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
4120 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
4121 u32 a
= le32_to_cpu(le
->addr
);
4124 seq_printf(seq
, "%u:", idx
);
4127 switch(le
->opcode
& ~HW_OWNER
) {
4129 seq_printf(seq
, " %#x:", a
);
4132 seq_printf(seq
, " mtu=%d", a
);
4135 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
4138 seq_printf(seq
, " csum=%#x", a
);
4141 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
4144 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
4147 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
4150 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
4151 a
, le16_to_cpu(le
->length
));
4154 if (le
->ctrl
& EOP
) {
4155 seq_putc(seq
, '\n');
4160 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
4161 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
4162 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
4163 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
4165 sky2_read32(hw
, B0_Y2_SP_LISR
);
4166 napi_enable(&hw
->napi
);
4170 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
4172 return single_open(file
, sky2_debug_show
, inode
->i_private
);
4175 static const struct file_operations sky2_debug_fops
= {
4176 .owner
= THIS_MODULE
,
4177 .open
= sky2_debug_open
,
4179 .llseek
= seq_lseek
,
4180 .release
= single_release
,
4184 * Use network device events to create/remove/rename
4185 * debugfs file entries
4187 static int sky2_device_event(struct notifier_block
*unused
,
4188 unsigned long event
, void *ptr
)
4190 struct net_device
*dev
= ptr
;
4191 struct sky2_port
*sky2
= netdev_priv(dev
);
4193 if (dev
->netdev_ops
->ndo_open
!= sky2_up
|| !sky2_debug
)
4197 case NETDEV_CHANGENAME
:
4198 if (sky2
->debugfs
) {
4199 sky2
->debugfs
= debugfs_rename(sky2_debug
, sky2
->debugfs
,
4200 sky2_debug
, dev
->name
);
4204 case NETDEV_GOING_DOWN
:
4205 if (sky2
->debugfs
) {
4206 printk(KERN_DEBUG PFX
"%s: remove debugfs\n",
4208 debugfs_remove(sky2
->debugfs
);
4209 sky2
->debugfs
= NULL
;
4214 sky2
->debugfs
= debugfs_create_file(dev
->name
, S_IRUGO
,
4217 if (IS_ERR(sky2
->debugfs
))
4218 sky2
->debugfs
= NULL
;
4224 static struct notifier_block sky2_notifier
= {
4225 .notifier_call
= sky2_device_event
,
4229 static __init
void sky2_debug_init(void)
4233 ent
= debugfs_create_dir("sky2", NULL
);
4234 if (!ent
|| IS_ERR(ent
))
4238 register_netdevice_notifier(&sky2_notifier
);
4241 static __exit
void sky2_debug_cleanup(void)
4244 unregister_netdevice_notifier(&sky2_notifier
);
4245 debugfs_remove(sky2_debug
);
4251 #define sky2_debug_init()
4252 #define sky2_debug_cleanup()
4255 /* Two copies of network device operations to handle special case of
4256 not allowing netpoll on second port */
4257 static const struct net_device_ops sky2_netdev_ops
[2] = {
4259 .ndo_open
= sky2_up
,
4260 .ndo_stop
= sky2_down
,
4261 .ndo_start_xmit
= sky2_xmit_frame
,
4262 .ndo_do_ioctl
= sky2_ioctl
,
4263 .ndo_validate_addr
= eth_validate_addr
,
4264 .ndo_set_mac_address
= sky2_set_mac_address
,
4265 .ndo_set_multicast_list
= sky2_set_multicast
,
4266 .ndo_change_mtu
= sky2_change_mtu
,
4267 .ndo_tx_timeout
= sky2_tx_timeout
,
4268 #ifdef SKY2_VLAN_TAG_USED
4269 .ndo_vlan_rx_register
= sky2_vlan_rx_register
,
4271 #ifdef CONFIG_NET_POLL_CONTROLLER
4272 .ndo_poll_controller
= sky2_netpoll
,
4276 .ndo_open
= sky2_up
,
4277 .ndo_stop
= sky2_down
,
4278 .ndo_start_xmit
= sky2_xmit_frame
,
4279 .ndo_do_ioctl
= sky2_ioctl
,
4280 .ndo_validate_addr
= eth_validate_addr
,
4281 .ndo_set_mac_address
= sky2_set_mac_address
,
4282 .ndo_set_multicast_list
= sky2_set_multicast
,
4283 .ndo_change_mtu
= sky2_change_mtu
,
4284 .ndo_tx_timeout
= sky2_tx_timeout
,
4285 #ifdef SKY2_VLAN_TAG_USED
4286 .ndo_vlan_rx_register
= sky2_vlan_rx_register
,
4291 /* Initialize network device */
4292 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
4294 int highmem
, int wol
)
4296 struct sky2_port
*sky2
;
4297 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
4300 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed\n");
4304 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
4305 dev
->irq
= hw
->pdev
->irq
;
4306 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
4307 dev
->watchdog_timeo
= TX_WATCHDOG
;
4308 dev
->netdev_ops
= &sky2_netdev_ops
[port
];
4310 sky2
= netdev_priv(dev
);
4313 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
4315 /* Auto speed and flow control */
4316 sky2
->flags
= SKY2_FLAG_AUTO_SPEED
| SKY2_FLAG_AUTO_PAUSE
;
4317 if (hw
->chip_id
!= CHIP_ID_YUKON_XL
)
4318 sky2
->flags
|= SKY2_FLAG_RX_CHECKSUM
;
4320 sky2
->flow_mode
= FC_BOTH
;
4324 sky2
->advertising
= sky2_supported_modes(hw
);
4327 spin_lock_init(&sky2
->phy_lock
);
4328 sky2
->tx_pending
= TX_DEF_PENDING
;
4329 sky2
->rx_pending
= RX_DEF_PENDING
;
4330 sky2
->restarting
= 0;
4332 hw
->dev
[port
] = dev
;
4336 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
4338 dev
->features
|= NETIF_F_HIGHDMA
;
4340 #ifdef SKY2_VLAN_TAG_USED
4341 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4342 if (!(sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
4343 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)) {
4344 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4348 /* read the mac address */
4349 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
4350 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4355 static void __devinit
sky2_show_addr(struct net_device
*dev
)
4357 const struct sky2_port
*sky2
= netdev_priv(dev
);
4359 if (netif_msg_probe(sky2
))
4360 printk(KERN_INFO PFX
"%s: addr %pM\n",
4361 dev
->name
, dev
->dev_addr
);
4364 /* Handle software interrupt used during MSI test */
4365 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
4367 struct sky2_hw
*hw
= dev_id
;
4368 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
4373 if (status
& Y2_IS_IRQ_SW
) {
4374 hw
->flags
|= SKY2_HW_USE_MSI
;
4375 wake_up(&hw
->msi_wait
);
4376 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4378 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
4383 /* Test interrupt path by forcing a a software IRQ */
4384 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
4386 struct pci_dev
*pdev
= hw
->pdev
;
4389 init_waitqueue_head (&hw
->msi_wait
);
4391 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
4393 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
4395 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4399 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
4400 sky2_read8(hw
, B0_CTST
);
4402 wait_event_timeout(hw
->msi_wait
, (hw
->flags
& SKY2_HW_USE_MSI
), HZ
/10);
4404 if (!(hw
->flags
& SKY2_HW_USE_MSI
)) {
4405 /* MSI test failed, go back to INTx mode */
4406 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
4407 "switching to INTx mode.\n");
4410 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4413 sky2_write32(hw
, B0_IMSK
, 0);
4414 sky2_read32(hw
, B0_IMSK
);
4416 free_irq(pdev
->irq
, hw
);
4421 /* This driver supports yukon2 chipset only */
4422 static const char *sky2_name(u8 chipid
, char *buf
, int sz
)
4424 const char *name
[] = {
4426 "EC Ultra", /* 0xb4 */
4427 "Extreme", /* 0xb5 */
4431 "Supreme", /* 0xb9 */
4435 if (chipid
>= CHIP_ID_YUKON_XL
&& chipid
< CHIP_ID_YUKON_UL_2
)
4436 strncpy(buf
, name
[chipid
- CHIP_ID_YUKON_XL
], sz
);
4438 snprintf(buf
, sz
, "(chip %#x)", chipid
);
4442 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
4443 const struct pci_device_id
*ent
)
4445 struct net_device
*dev
;
4447 int err
, using_dac
= 0, wol_default
;
4451 err
= pci_enable_device(pdev
);
4453 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
4457 /* Get configuration information
4458 * Note: only regular PCI config access once to test for HW issues
4459 * other PCI access through shared memory for speed and to
4460 * avoid MMCONFIG problems.
4462 err
= pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
4464 dev_err(&pdev
->dev
, "PCI read config failed\n");
4469 dev_err(&pdev
->dev
, "PCI configuration read error\n");
4473 err
= pci_request_regions(pdev
, DRV_NAME
);
4475 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
4476 goto err_out_disable
;
4479 pci_set_master(pdev
);
4481 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
4482 !(err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)))) {
4484 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
4486 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
4487 "for consistent allocations\n");
4488 goto err_out_free_regions
;
4491 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
4493 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
4494 goto err_out_free_regions
;
4500 /* The sk98lin vendor driver uses hardware byte swapping but
4501 * this driver uses software swapping.
4503 reg
&= ~PCI_REV_DESC
;
4504 err
= pci_write_config_dword(pdev
,PCI_DEV_REG2
, reg
);
4506 dev_err(&pdev
->dev
, "PCI write config failed\n");
4507 goto err_out_free_regions
;
4511 wol_default
= device_may_wakeup(&pdev
->dev
) ? WAKE_MAGIC
: 0;
4514 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
4516 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
4517 goto err_out_free_regions
;
4522 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
4524 dev_err(&pdev
->dev
, "cannot map device registers\n");
4525 goto err_out_free_hw
;
4528 /* ring for status responses */
4529 hw
->st_le
= pci_alloc_consistent(pdev
, STATUS_LE_BYTES
, &hw
->st_dma
);
4531 goto err_out_iounmap
;
4533 err
= sky2_init(hw
);
4535 goto err_out_iounmap
;
4537 dev_info(&pdev
->dev
, "Yukon-2 %s chip revision %d\n",
4538 sky2_name(hw
->chip_id
, buf1
, sizeof(buf1
)), hw
->chip_rev
);
4542 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
4545 goto err_out_free_pci
;
4548 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
4549 err
= sky2_test_msi(hw
);
4550 if (err
== -EOPNOTSUPP
)
4551 pci_disable_msi(pdev
);
4553 goto err_out_free_netdev
;
4556 err
= register_netdev(dev
);
4558 dev_err(&pdev
->dev
, "cannot register net device\n");
4559 goto err_out_free_netdev
;
4562 netif_napi_add(dev
, &hw
->napi
, sky2_poll
, NAPI_WEIGHT
);
4564 err
= request_irq(pdev
->irq
, sky2_intr
,
4565 (hw
->flags
& SKY2_HW_USE_MSI
) ? 0 : IRQF_SHARED
,
4568 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4569 goto err_out_unregister
;
4571 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4572 napi_enable(&hw
->napi
);
4574 sky2_show_addr(dev
);
4576 if (hw
->ports
> 1) {
4577 struct net_device
*dev1
;
4579 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
4581 dev_warn(&pdev
->dev
, "allocation for second device failed\n");
4582 else if ((err
= register_netdev(dev1
))) {
4583 dev_warn(&pdev
->dev
,
4584 "register of second port failed (%d)\n", err
);
4588 sky2_show_addr(dev1
);
4591 setup_timer(&hw
->watchdog_timer
, sky2_watchdog
, (unsigned long) hw
);
4592 INIT_WORK(&hw
->restart_work
, sky2_restart
);
4594 pci_set_drvdata(pdev
, hw
);
4599 if (hw
->flags
& SKY2_HW_USE_MSI
)
4600 pci_disable_msi(pdev
);
4601 unregister_netdev(dev
);
4602 err_out_free_netdev
:
4605 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4606 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4611 err_out_free_regions
:
4612 pci_release_regions(pdev
);
4614 pci_disable_device(pdev
);
4616 pci_set_drvdata(pdev
, NULL
);
4620 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
4622 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4628 del_timer_sync(&hw
->watchdog_timer
);
4629 cancel_work_sync(&hw
->restart_work
);
4631 for (i
= hw
->ports
-1; i
>= 0; --i
)
4632 unregister_netdev(hw
->dev
[i
]);
4634 sky2_write32(hw
, B0_IMSK
, 0);
4638 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
4639 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4640 sky2_read8(hw
, B0_CTST
);
4642 free_irq(pdev
->irq
, hw
);
4643 if (hw
->flags
& SKY2_HW_USE_MSI
)
4644 pci_disable_msi(pdev
);
4645 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4646 pci_release_regions(pdev
);
4647 pci_disable_device(pdev
);
4649 for (i
= hw
->ports
-1; i
>= 0; --i
)
4650 free_netdev(hw
->dev
[i
]);
4655 pci_set_drvdata(pdev
, NULL
);
4659 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4661 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4667 del_timer_sync(&hw
->watchdog_timer
);
4668 cancel_work_sync(&hw
->restart_work
);
4671 for (i
= 0; i
< hw
->ports
; i
++) {
4672 struct net_device
*dev
= hw
->dev
[i
];
4673 struct sky2_port
*sky2
= netdev_priv(dev
);
4678 sky2_wol_init(sky2
);
4683 sky2_write32(hw
, B0_IMSK
, 0);
4684 napi_disable(&hw
->napi
);
4688 pci_save_state(pdev
);
4689 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
4690 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
4695 static int sky2_resume(struct pci_dev
*pdev
)
4697 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4703 err
= pci_set_power_state(pdev
, PCI_D0
);
4707 err
= pci_restore_state(pdev
);
4711 pci_enable_wake(pdev
, PCI_D0
, 0);
4713 /* Re-enable all clocks */
4714 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
4715 hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
4716 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
4717 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
4720 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4721 napi_enable(&hw
->napi
);
4724 for (i
= 0; i
< hw
->ports
; i
++) {
4725 err
= sky2_reattach(hw
->dev
[i
]);
4735 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
4736 pci_disable_device(pdev
);
4741 static void sky2_shutdown(struct pci_dev
*pdev
)
4743 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4750 del_timer_sync(&hw
->watchdog_timer
);
4752 for (i
= 0; i
< hw
->ports
; i
++) {
4753 struct net_device
*dev
= hw
->dev
[i
];
4754 struct sky2_port
*sky2
= netdev_priv(dev
);
4758 sky2_wol_init(sky2
);
4766 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
4767 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
4769 pci_disable_device(pdev
);
4770 pci_set_power_state(pdev
, PCI_D3hot
);
4773 static struct pci_driver sky2_driver
= {
4775 .id_table
= sky2_id_table
,
4776 .probe
= sky2_probe
,
4777 .remove
= __devexit_p(sky2_remove
),
4779 .suspend
= sky2_suspend
,
4780 .resume
= sky2_resume
,
4782 .shutdown
= sky2_shutdown
,
4785 static int __init
sky2_init_module(void)
4787 pr_info(PFX
"driver version " DRV_VERSION
"\n");
4790 return pci_register_driver(&sky2_driver
);
4793 static void __exit
sky2_cleanup_module(void)
4795 pci_unregister_driver(&sky2_driver
);
4796 sky2_debug_cleanup();
4799 module_init(sky2_init_module
);
4800 module_exit(sky2_cleanup_module
);
4802 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4803 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4804 MODULE_LICENSE("GPL");
4805 MODULE_VERSION(DRV_VERSION
);