drivers/ata/sata_sis.c

   1 /*
   2  *  sata_sis.c - Silicon Integrated Systems SATA
   3  *
   4  *  Maintained by:  Uwe Koziolek
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2004 Uwe Koziolek
   9  *
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; see the file COPYING.  If not, write to
  23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  *
  26  *  libata documentation is available via 'make {ps|pdf}docs',
  27  *  as Documentation/DocBook/libata.*
  28  *
  29  *  Hardware documentation available under NDA.
  30  *
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/pci.h>
  36 #include <linux/init.h>
  37 #include <linux/blkdev.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/device.h>
  41 #include <scsi/scsi_host.h>
  42 #include <linux/libata.h>
  43 #include "libata.h"
  44
  45 #undef DRV_NAME         /* already defined in libata.h, for libata-core */
  46 #define DRV_NAME        "sata_sis"
  47 #define DRV_VERSION     "0.7"
  48
  49 enum {
  50         sis_180                 = 0,
  51         SIS_SCR_PCI_BAR         = 5,
  52
  53         /* PCI configuration registers */
  54         SIS_GENCTL              = 0x54, /* IDE General Control register */
  55         SIS_SCR_BASE            = 0xc0, /* sata0 phy SCR registers */
  56         SIS180_SATA1_OFS        = 0x10, /* offset from sata0->sata1 phy regs */
  57         SIS182_SATA1_OFS        = 0x20, /* offset from sata0->sata1 phy regs */
  58         SIS_PMR                 = 0x90, /* port mapping register */
  59         SIS_PMR_COMBINED        = 0x30,
  60
  61         /* random bits */
  62         SIS_FLAG_CFGSCR         = (1 << 30), /* host flag: SCRs via PCI cfg */
  63
  64         GENCTL_IOMAPPED_SCR     = (1 << 26), /* if set, SCRs are in IO space */
  65 };
  66
  67 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  68 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
  69 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
  70
  71 static const struct pci_device_id sis_pci_tbl[] = {
  72         { PCI_VDEVICE(SI, 0x0180), sis_180 },           /* SiS 964/180 */
  73         { PCI_VDEVICE(SI, 0x0181), sis_180 },           /* SiS 964/180 */
  74         { PCI_VDEVICE(SI, 0x0182), sis_180 },           /* SiS 965/965L */
  75         { PCI_VDEVICE(SI, 0x0183), sis_180 },           /* SiS 965/965L */
  76         { PCI_VDEVICE(SI, 0x1182), sis_180 },           /* SiS 966/966L */
  77         { PCI_VDEVICE(SI, 0x1183), sis_180 },           /* SiS 966/966L */
  78
  79         { }     /* terminate list */
  80 };
  81
  82 static struct pci_driver sis_pci_driver = {
  83         .name                   = DRV_NAME,
  84         .id_table               = sis_pci_tbl,
  85         .probe                  = sis_init_one,
  86         .remove                 = ata_pci_remove_one,
  87 };
  88
  89 static struct scsi_host_template sis_sht = {
  90         .module                 = THIS_MODULE,
  91         .name                   = DRV_NAME,
  92         .ioctl                  = ata_scsi_ioctl,
  93         .queuecommand           = ata_scsi_queuecmd,
  94         .can_queue              = ATA_DEF_QUEUE,
  95         .this_id                = ATA_SHT_THIS_ID,
  96         .sg_tablesize           = ATA_MAX_PRD,
  97         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
  98         .emulated               = ATA_SHT_EMULATED,
  99         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 100         .proc_name              = DRV_NAME,
 101         .dma_boundary           = ATA_DMA_BOUNDARY,
 102         .slave_configure        = ata_scsi_slave_config,
 103         .slave_destroy          = ata_scsi_slave_destroy,
 104         .bios_param             = ata_std_bios_param,
 105 };
 106
 107 static const struct ata_port_operations sis_ops = {
 108         .port_disable           = ata_port_disable,
 109         .tf_load                = ata_tf_load,
 110         .tf_read                = ata_tf_read,
 111         .check_status           = ata_check_status,
 112         .exec_command           = ata_exec_command,
 113         .dev_select             = ata_std_dev_select,
 114         .bmdma_setup            = ata_bmdma_setup,
 115         .bmdma_start            = ata_bmdma_start,
 116         .bmdma_stop             = ata_bmdma_stop,
 117         .bmdma_status           = ata_bmdma_status,
 118         .qc_prep                = ata_qc_prep,
 119         .qc_issue               = ata_qc_issue_prot,
 120         .data_xfer              = ata_data_xfer,
 121         .freeze                 = ata_bmdma_freeze,
 122         .thaw                   = ata_bmdma_thaw,
 123         .error_handler          = ata_bmdma_error_handler,
 124         .post_internal_cmd      = ata_bmdma_post_internal_cmd,
 125         .irq_handler            = ata_interrupt,
 126         .irq_clear              = ata_bmdma_irq_clear,
 127         .scr_read               = sis_scr_read,
 128         .scr_write              = sis_scr_write,
 129         .port_start             = ata_port_start,
 130 };
 131
 132 static struct ata_port_info sis_port_info = {
 133         .sht            = &sis_sht,
 134         .flags          = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
 135         .pio_mask       = 0x1f,
 136         .mwdma_mask     = 0x7,
 137         .udma_mask      = 0x7f,
 138         .port_ops       = &sis_ops,
 139 };
 140
 141 MODULE_AUTHOR("Uwe Koziolek");
 142 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
 143 MODULE_LICENSE("GPL");
 144 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
 145 MODULE_VERSION(DRV_VERSION);
 146
 147 static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
 148 {
 149         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 150         unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
 151         u8 pmr;
 152
 153         if (ap->port_no)  {
 154                 switch (pdev->device) {
 155                         case 0x0180:
 156                         case 0x0181:
 157                                 pci_read_config_byte(pdev, SIS_PMR, &pmr);
 158                                 if ((pmr & SIS_PMR_COMBINED) == 0)
 159                                         addr += SIS180_SATA1_OFS;
 160                                 break;
 161
 162                         case 0x0182:
 163                         case 0x0183:
 164                         case 0x1182:
 165                         case 0x1183:
 166                                 addr += SIS182_SATA1_OFS;
 167                                 break;
 168                 }
 169         }
 170         return addr;
 171 }
 172
 173 static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
 174 {
 175         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 176         unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
 177         u32 val, val2 = 0;
 178         u8 pmr;
 179
 180         if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
 181                 return 0xffffffff;
 182
 183         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 184
 185         pci_read_config_dword(pdev, cfg_addr, &val);
 186
 187         if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
 188             (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
 189                 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
 190
 191         return (val|val2) &  0xfffffffb; /* avoid problems with powerdowned ports */
 192 }
 193
 194 static void sis_scr_cfg_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
 195 {
 196         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 197         unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
 198         u8 pmr;
 199
 200         if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
 201                 return;
 202
 203         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 204
 205         pci_write_config_dword(pdev, cfg_addr, val);
 206
 207         if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
 208             (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
 209                 pci_write_config_dword(pdev, cfg_addr+0x10, val);
 210 }
 211
 212 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
 213 {
 214         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 215         u32 val, val2 = 0;
 216         u8 pmr;
 217
 218         if (sc_reg > SCR_CONTROL)
 219                 return 0xffffffffU;
 220
 221         if (ap->flags & SIS_FLAG_CFGSCR)
 222                 return sis_scr_cfg_read(ap, sc_reg);
 223
 224         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 225
 226         val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
 227
 228         if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
 229             (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
 230                 val2 = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
 231
 232         return (val | val2) &  0xfffffffb;
 233 }
 234
 235 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
 236 {
 237         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 238         u8 pmr;
 239
 240         if (sc_reg > SCR_CONTROL)
 241                 return;
 242
 243         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 244
 245         if (ap->flags & SIS_FLAG_CFGSCR)
 246                 sis_scr_cfg_write(ap, sc_reg, val);
 247         else {
 248                 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
 249                 if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
 250                     (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
 251                         iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
 252         }
 253 }
 254
 255 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 256 {
 257         static int printed_version;
 258         struct ata_probe_ent *probe_ent = NULL;
 259         int rc;
 260         u32 genctl, val;
 261         struct ata_port_info pi = sis_port_info, *ppi[2] = { &pi, &pi };
 262         u8 pmr;
 263         u8 port2_start = 0x20;
 264
 265         if (!printed_version++)
 266                 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
 267
 268         rc = pcim_enable_device(pdev);
 269         if (rc)
 270                 return rc;
 271
 272         rc = pci_request_regions(pdev, DRV_NAME);
 273         if (rc) {
 274                 pcim_pin_device(pdev);
 275                 return rc;
 276         }
 277
 278         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
 279         if (rc)
 280                 return rc;
 281         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
 282         if (rc)
 283                 return rc;
 284
 285         /* check and see if the SCRs are in IO space or PCI cfg space */
 286         pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
 287         if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
 288                 pi.flags |= SIS_FLAG_CFGSCR;
 289
 290         /* if hardware thinks SCRs are in IO space, but there are
 291          * no IO resources assigned, change to PCI cfg space.
 292          */
 293         if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
 294             ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
 295              (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
 296                 genctl &= ~GENCTL_IOMAPPED_SCR;
 297                 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
 298                 pi.flags |= SIS_FLAG_CFGSCR;
 299         }
 300
 301         pci_read_config_byte(pdev, SIS_PMR, &pmr);
 302         switch (ent->device) {
 303         case 0x0180:
 304         case 0x0181:
 305
 306                 /* The PATA-handling is provided by pata_sis */
 307                 switch (pmr & 0x30) {
 308                 case 0x10:
 309                         ppi[1] = &sis_info133;
 310                         break;
 311
 312                 case 0x30:
 313                         ppi[0] = &sis_info133;
 314                         break;
 315                 }
 316                 if ((pmr & SIS_PMR_COMBINED) == 0) {
 317                         dev_printk(KERN_INFO, &pdev->dev,
 318                                    "Detected SiS 180/181/964 chipset in SATA mode\n");
 319                         port2_start = 64;
 320                 } else {
 321                         dev_printk(KERN_INFO, &pdev->dev,
 322                                    "Detected SiS 180/181 chipset in combined mode\n");
 323                         port2_start=0;
 324                         pi.flags |= ATA_FLAG_SLAVE_POSS;
 325                 }
 326                 break;
 327
 328         case 0x0182:
 329         case 0x0183:
 330                 pci_read_config_dword ( pdev, 0x6C, &val);
 331                 if (val & (1L << 31)) {
 332                         dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n");
 333                         pi.flags |= ATA_FLAG_SLAVE_POSS;
 334                 } else {
 335                         dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n");
 336                 }
 337                 break;
 338
 339         case 0x1182:
 340         case 0x1183:
 341                 pci_read_config_dword(pdev, 0x64, &val);
 342                 if (val & 0x10000000) {
 343                         dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966L SATA controller\n");
 344                 } else {
 345                         dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966 SATA controller\n");
 346                         pi.flags |= ATA_FLAG_SLAVE_POSS;
 347                 }
 348                 break;
 349         }
 350
 351         probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
 352         if (!probe_ent)
 353                 return -ENOMEM;
 354
 355         if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) {
 356                 void *mmio;
 357
 358                 mmio = pcim_iomap(pdev, SIS_SCR_PCI_BAR, 0);
 359                 if (!mmio)
 360                         return -ENOMEM;
 361
 362                 probe_ent->port[0].scr_addr = mmio;
 363                 probe_ent->port[1].scr_addr = mmio + port2_start;
 364         }
 365
 366         pci_set_master(pdev);
 367         pci_intx(pdev, 1);
 368
 369         if (!ata_device_add(probe_ent))
 370                 return -EIO;
 371
 372         devm_kfree(&pdev->dev, probe_ent);
 373         return 0;
 374
 375 }
 376
 377 static int __init sis_init(void)
 378 {
 379         return pci_register_driver(&sis_pci_driver);
 380 }
 381
 382 static void __exit sis_exit(void)
 383 {
 384         pci_unregister_driver(&sis_pci_driver);
 385 }
 386
 387 module_init(sis_init);
 388 module_exit(sis_exit);