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libata: convert to iomap
[linux-2.6/mini2440.git] / drivers / ata / pata_amd.c
blobed0e4f6fc715150b7bd5172e81550df3426efa4f
1 /*
2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based on pata-sil680. Errata information is taken from data sheets
7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
8 * claimed by sata-nv.c.
9 *
10 * TODO:
11 * Variable system clock when/if it makes sense
12 * Power management on ports
13 *
14 *
15 * Documentation publically available.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <scsi/scsi_host.h>
25 #include <linux/libata.h>
26
27 #define DRV_NAME "pata_amd"
28 #define DRV_VERSION "0.2.7"
29
30 /**
31 * timing_setup - shared timing computation and load
32 * @ap: ATA port being set up
33 * @adev: drive being configured
34 * @offset: port offset
35 * @speed: target speed
36 * @clock: clock multiplier (number of times 33MHz for this part)
37 *
38 * Perform the actual timing set up for Nvidia or AMD PATA devices.
39 * The actual devices vary so they all call into this helper function
40 * providing the clock multipler and offset (because AMD and Nvidia put
41 * the ports at different locations).
42 */
43
44 static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
45 {
46 static const unsigned char amd_cyc2udma[] = {
47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
48 };
49
50 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
51 struct ata_device *peer = ata_dev_pair(adev);
52 int dn = ap->port_no * 2 + adev->devno;
53 struct ata_timing at, apeer;
54 int T, UT;
55 const int amd_clock = 33333; /* KHz. */
56 u8 t;
57
58 T = 1000000000 / amd_clock;
59 UT = T / min_t(int, max_t(int, clock, 1), 2);
60
61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
62 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
63 return;
64 }
65
66 if (peer) {
67 /* This may be over conservative */
68 if (peer->dma_mode) {
69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
71 }
72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
74 }
75
76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
78
79 /*
80 * Now do the setup work
81 */
82
83 /* Configure the address set up timing */
84 pci_read_config_byte(pdev, offset + 0x0C, &t);
85 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
86 pci_write_config_byte(pdev, offset + 0x0C , t);
87
88 /* Configure the 8bit I/O timing */
89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
90 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1));
91
92 /* Drive timing */
93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
94 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1));
95
96 switch (clock) {
97 case 1:
98 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03;
99 break;
100
101 case 2:
102 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
103 break;
104
105 case 3:
106 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
107 break;
108
109 case 4:
110 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
111 break;
112
113 default:
114 return;
115 }
116
117 /* UDMA timing */
118 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
119 }
120
121 /**
122 * amd_probe_init - cable detection
123 * @ap: ATA port
124 *
125 * Perform cable detection. The BIOS stores this in PCI config
126 * space for us.
127 */
128
129 static int amd_pre_reset(struct ata_port *ap)
130 {
131 static const u32 bitmask[2] = {0x03, 0xC0};
132 static const struct pci_bits amd_enable_bits[] = {
133 { 0x40, 1, 0x02, 0x02 },
134 { 0x40, 1, 0x01, 0x01 }
135 };
136
137 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
138 u8 ata66;
139
140 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
141 return -ENOENT;
142
143 pci_read_config_byte(pdev, 0x42, &ata66);
144 if (ata66 & bitmask[ap->port_no])
145 ap->cbl = ATA_CBL_PATA80;
146 else
147 ap->cbl = ATA_CBL_PATA40;
148 return ata_std_prereset(ap);
149
150 }
151
152 static void amd_error_handler(struct ata_port *ap)
153 {
154 return ata_bmdma_drive_eh(ap, amd_pre_reset,
155 ata_std_softreset, NULL,
156 ata_std_postreset);
157 }
158
159 static int amd_early_pre_reset(struct ata_port *ap)
160 {
161 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
162 static struct pci_bits amd_enable_bits[] = {
163 { 0x40, 1, 0x02, 0x02 },
164 { 0x40, 1, 0x01, 0x01 }
165 };
166
167 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
168 return -ENOENT;
169
170 /* No host side cable detection */
171 ap->cbl = ATA_CBL_PATA80;
172 return ata_std_prereset(ap);
173
174 }
175
176 static void amd_early_error_handler(struct ata_port *ap)
177 {
178 ata_bmdma_drive_eh(ap, amd_early_pre_reset,
179 ata_std_softreset, NULL,
180 ata_std_postreset);
181 }
182
183 /**
184 * amd33_set_piomode - set initial PIO mode data
185 * @ap: ATA interface
186 * @adev: ATA device
187 *
188 * Program the AMD registers for PIO mode.
189 */
190
191 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
192 {
193 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
194 }
195
196 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
197 {
198 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
199 }
200
201 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
202 {
203 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
204 }
205
206 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
207 {
208 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
209 }
210
211 /**
212 * amd33_set_dmamode - set initial DMA mode data
213 * @ap: ATA interface
214 * @adev: ATA device
215 *
216 * Program the MWDMA/UDMA modes for the AMD and Nvidia
217 * chipset.
218 */
219
220 static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
221 {
222 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
223 }
224
225 static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
226 {
227 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
228 }
229
230 static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
231 {
232 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
233 }
234
235 static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
236 {
237 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
238 }
239
240
241 /**
242 * nv_probe_init - cable detection
243 * @ap: ATA port
244 *
245 * Perform cable detection. The BIOS stores this in PCI config
246 * space for us.
247 */
248
249 static int nv_pre_reset(struct ata_port *ap) {
250 static const u8 bitmask[2] = {0x03, 0xC0};
251 static const struct pci_bits nv_enable_bits[] = {
252 { 0x50, 1, 0x02, 0x02 },
253 { 0x50, 1, 0x01, 0x01 }
254 };
255
256 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
257 u8 ata66;
258 u16 udma;
259
260 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
261 return -ENOENT;
262
263 pci_read_config_byte(pdev, 0x52, &ata66);
264 if (ata66 & bitmask[ap->port_no])
265 ap->cbl = ATA_CBL_PATA80;
266 else
267 ap->cbl = ATA_CBL_PATA40;
268
269 /* We now have to double check because the Nvidia boxes BIOS
270 doesn't always set the cable bits but does set mode bits */
271
272 pci_read_config_word(pdev, 0x62 - 2 * ap->port_no, &udma);
273 if ((udma & 0xC4) == 0xC4 || (udma & 0xC400) == 0xC400)
274 ap->cbl = ATA_CBL_PATA80;
275 return ata_std_prereset(ap);
276 }
277
278 static void nv_error_handler(struct ata_port *ap)
279 {
280 ata_bmdma_drive_eh(ap, nv_pre_reset,
281 ata_std_softreset, NULL,
282 ata_std_postreset);
283 }
284 /**
285 * nv100_set_piomode - set initial PIO mode data
286 * @ap: ATA interface
287 * @adev: ATA device
288 *
289 * Program the AMD registers for PIO mode.
290 */
291
292 static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
293 {
294 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
295 }
296
297 static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
298 {
299 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
300 }
301
302 /**
303 * nv100_set_dmamode - set initial DMA mode data
304 * @ap: ATA interface
305 * @adev: ATA device
306 *
307 * Program the MWDMA/UDMA modes for the AMD and Nvidia
308 * chipset.
309 */
310
311 static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
312 {
313 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
314 }
315
316 static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
317 {
318 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
319 }
320
321 static struct scsi_host_template amd_sht = {
322 .module = THIS_MODULE,
323 .name = DRV_NAME,
324 .ioctl = ata_scsi_ioctl,
325 .queuecommand = ata_scsi_queuecmd,
326 .can_queue = ATA_DEF_QUEUE,
327 .this_id = ATA_SHT_THIS_ID,
328 .sg_tablesize = LIBATA_MAX_PRD,
329 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
330 .emulated = ATA_SHT_EMULATED,
331 .use_clustering = ATA_SHT_USE_CLUSTERING,
332 .proc_name = DRV_NAME,
333 .dma_boundary = ATA_DMA_BOUNDARY,
334 .slave_configure = ata_scsi_slave_config,
335 .slave_destroy = ata_scsi_slave_destroy,
336 .bios_param = ata_std_bios_param,
337 .resume = ata_scsi_device_resume,
338 .suspend = ata_scsi_device_suspend,
339 };
340
341 static struct ata_port_operations amd33_port_ops = {
342 .port_disable = ata_port_disable,
343 .set_piomode = amd33_set_piomode,
344 .set_dmamode = amd33_set_dmamode,
345 .mode_filter = ata_pci_default_filter,
346 .tf_load = ata_tf_load,
347 .tf_read = ata_tf_read,
348 .check_status = ata_check_status,
349 .exec_command = ata_exec_command,
350 .dev_select = ata_std_dev_select,
351
352 .freeze = ata_bmdma_freeze,
353 .thaw = ata_bmdma_thaw,
354 .error_handler = amd_early_error_handler,
355 .post_internal_cmd = ata_bmdma_post_internal_cmd,
356
357 .bmdma_setup = ata_bmdma_setup,
358 .bmdma_start = ata_bmdma_start,
359 .bmdma_stop = ata_bmdma_stop,
360 .bmdma_status = ata_bmdma_status,
361
362 .qc_prep = ata_qc_prep,
363 .qc_issue = ata_qc_issue_prot,
364
365 .data_xfer = ata_data_xfer,
366
367 .irq_handler = ata_interrupt,
368 .irq_clear = ata_bmdma_irq_clear,
369
370 .port_start = ata_port_start,
371 };
372
373 static struct ata_port_operations amd66_port_ops = {
374 .port_disable = ata_port_disable,
375 .set_piomode = amd66_set_piomode,
376 .set_dmamode = amd66_set_dmamode,
377 .mode_filter = ata_pci_default_filter,
378 .tf_load = ata_tf_load,
379 .tf_read = ata_tf_read,
380 .check_status = ata_check_status,
381 .exec_command = ata_exec_command,
382 .dev_select = ata_std_dev_select,
383
384 .freeze = ata_bmdma_freeze,
385 .thaw = ata_bmdma_thaw,
386 .error_handler = amd_early_error_handler,
387 .post_internal_cmd = ata_bmdma_post_internal_cmd,
388
389 .bmdma_setup = ata_bmdma_setup,
390 .bmdma_start = ata_bmdma_start,
391 .bmdma_stop = ata_bmdma_stop,
392 .bmdma_status = ata_bmdma_status,
393
394 .qc_prep = ata_qc_prep,
395 .qc_issue = ata_qc_issue_prot,
396
397 .data_xfer = ata_data_xfer,
398
399 .irq_handler = ata_interrupt,
400 .irq_clear = ata_bmdma_irq_clear,
401
402 .port_start = ata_port_start,
403 };
404
405 static struct ata_port_operations amd100_port_ops = {
406 .port_disable = ata_port_disable,
407 .set_piomode = amd100_set_piomode,
408 .set_dmamode = amd100_set_dmamode,
409 .mode_filter = ata_pci_default_filter,
410 .tf_load = ata_tf_load,
411 .tf_read = ata_tf_read,
412 .check_status = ata_check_status,
413 .exec_command = ata_exec_command,
414 .dev_select = ata_std_dev_select,
415
416 .freeze = ata_bmdma_freeze,
417 .thaw = ata_bmdma_thaw,
418 .error_handler = amd_error_handler,
419 .post_internal_cmd = ata_bmdma_post_internal_cmd,
420
421 .bmdma_setup = ata_bmdma_setup,
422 .bmdma_start = ata_bmdma_start,
423 .bmdma_stop = ata_bmdma_stop,
424 .bmdma_status = ata_bmdma_status,
425
426 .qc_prep = ata_qc_prep,
427 .qc_issue = ata_qc_issue_prot,
428
429 .data_xfer = ata_data_xfer,
430
431 .irq_handler = ata_interrupt,
432 .irq_clear = ata_bmdma_irq_clear,
433
434 .port_start = ata_port_start,
435 };
436
437 static struct ata_port_operations amd133_port_ops = {
438 .port_disable = ata_port_disable,
439 .set_piomode = amd133_set_piomode,
440 .set_dmamode = amd133_set_dmamode,
441 .mode_filter = ata_pci_default_filter,
442 .tf_load = ata_tf_load,
443 .tf_read = ata_tf_read,
444 .check_status = ata_check_status,
445 .exec_command = ata_exec_command,
446 .dev_select = ata_std_dev_select,
447
448 .freeze = ata_bmdma_freeze,
449 .thaw = ata_bmdma_thaw,
450 .error_handler = amd_error_handler,
451 .post_internal_cmd = ata_bmdma_post_internal_cmd,
452
453 .bmdma_setup = ata_bmdma_setup,
454 .bmdma_start = ata_bmdma_start,
455 .bmdma_stop = ata_bmdma_stop,
456 .bmdma_status = ata_bmdma_status,
457
458 .qc_prep = ata_qc_prep,
459 .qc_issue = ata_qc_issue_prot,
460
461 .data_xfer = ata_data_xfer,
462
463 .irq_handler = ata_interrupt,
464 .irq_clear = ata_bmdma_irq_clear,
465
466 .port_start = ata_port_start,
467 };
468
469 static struct ata_port_operations nv100_port_ops = {
470 .port_disable = ata_port_disable,
471 .set_piomode = nv100_set_piomode,
472 .set_dmamode = nv100_set_dmamode,
473 .mode_filter = ata_pci_default_filter,
474 .tf_load = ata_tf_load,
475 .tf_read = ata_tf_read,
476 .check_status = ata_check_status,
477 .exec_command = ata_exec_command,
478 .dev_select = ata_std_dev_select,
479
480 .freeze = ata_bmdma_freeze,
481 .thaw = ata_bmdma_thaw,
482 .error_handler = nv_error_handler,
483 .post_internal_cmd = ata_bmdma_post_internal_cmd,
484
485 .bmdma_setup = ata_bmdma_setup,
486 .bmdma_start = ata_bmdma_start,
487 .bmdma_stop = ata_bmdma_stop,
488 .bmdma_status = ata_bmdma_status,
489
490 .qc_prep = ata_qc_prep,
491 .qc_issue = ata_qc_issue_prot,
492
493 .data_xfer = ata_data_xfer,
494
495 .irq_handler = ata_interrupt,
496 .irq_clear = ata_bmdma_irq_clear,
497
498 .port_start = ata_port_start,
499 };
500
501 static struct ata_port_operations nv133_port_ops = {
502 .port_disable = ata_port_disable,
503 .set_piomode = nv133_set_piomode,
504 .set_dmamode = nv133_set_dmamode,
505 .mode_filter = ata_pci_default_filter,
506 .tf_load = ata_tf_load,
507 .tf_read = ata_tf_read,
508 .check_status = ata_check_status,
509 .exec_command = ata_exec_command,
510 .dev_select = ata_std_dev_select,
511
512 .freeze = ata_bmdma_freeze,
513 .thaw = ata_bmdma_thaw,
514 .error_handler = nv_error_handler,
515 .post_internal_cmd = ata_bmdma_post_internal_cmd,
516
517 .bmdma_setup = ata_bmdma_setup,
518 .bmdma_start = ata_bmdma_start,
519 .bmdma_stop = ata_bmdma_stop,
520 .bmdma_status = ata_bmdma_status,
521
522 .qc_prep = ata_qc_prep,
523 .qc_issue = ata_qc_issue_prot,
524
525 .data_xfer = ata_data_xfer,
526
527 .irq_handler = ata_interrupt,
528 .irq_clear = ata_bmdma_irq_clear,
529
530 .port_start = ata_port_start,
531 };
532
533 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
534 {
535 static struct ata_port_info info[10] = {
536 { /* 0: AMD 7401 */
537 .sht = &amd_sht,
538 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
539 .pio_mask = 0x1f,
540 .mwdma_mask = 0x07, /* No SWDMA */
541 .udma_mask = 0x07, /* UDMA 33 */
542 .port_ops = &amd33_port_ops
543 },
544 { /* 1: Early AMD7409 - no swdma */
545 .sht = &amd_sht,
546 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
547 .pio_mask = 0x1f,
548 .mwdma_mask = 0x07,
549 .udma_mask = 0x1f, /* UDMA 66 */
550 .port_ops = &amd66_port_ops
551 },
552 { /* 2: AMD 7409, no swdma errata */
553 .sht = &amd_sht,
554 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
555 .pio_mask = 0x1f,
556 .mwdma_mask = 0x07,
557 .udma_mask = 0x1f, /* UDMA 66 */
558 .port_ops = &amd66_port_ops
559 },
560 { /* 3: AMD 7411 */
561 .sht = &amd_sht,
562 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
563 .pio_mask = 0x1f,
564 .mwdma_mask = 0x07,
565 .udma_mask = 0x3f, /* UDMA 100 */
566 .port_ops = &amd100_port_ops
567 },
568 { /* 4: AMD 7441 */
569 .sht = &amd_sht,
570 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
571 .pio_mask = 0x1f,
572 .mwdma_mask = 0x07,
573 .udma_mask = 0x3f, /* UDMA 100 */
574 .port_ops = &amd100_port_ops
575 },
576 { /* 5: AMD 8111*/
577 .sht = &amd_sht,
578 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
579 .pio_mask = 0x1f,
580 .mwdma_mask = 0x07,
581 .udma_mask = 0x7f, /* UDMA 133, no swdma */
582 .port_ops = &amd133_port_ops
583 },
584 { /* 6: AMD 8111 UDMA 100 (Serenade) */
585 .sht = &amd_sht,
586 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
587 .pio_mask = 0x1f,
588 .mwdma_mask = 0x07,
589 .udma_mask = 0x3f, /* UDMA 100, no swdma */
590 .port_ops = &amd133_port_ops
591 },
592 { /* 7: Nvidia Nforce */
593 .sht = &amd_sht,
594 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
595 .pio_mask = 0x1f,
596 .mwdma_mask = 0x07,
597 .udma_mask = 0x3f, /* UDMA 100 */
598 .port_ops = &nv100_port_ops
599 },
600 { /* 8: Nvidia Nforce2 and later */
601 .sht = &amd_sht,
602 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
603 .pio_mask = 0x1f,
604 .mwdma_mask = 0x07,
605 .udma_mask = 0x7f, /* UDMA 133, no swdma */
606 .port_ops = &nv133_port_ops
607 },
608 { /* 9: AMD CS5536 (Geode companion) */
609 .sht = &amd_sht,
610 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
611 .pio_mask = 0x1f,
612 .mwdma_mask = 0x07,
613 .udma_mask = 0x3f, /* UDMA 100 */
614 .port_ops = &amd100_port_ops
615 }
616 };
617 static struct ata_port_info *port_info[2];
618 static int printed_version;
619 int type = id->driver_data;
620 u8 rev;
621 u8 fifo;
622
623 if (!printed_version++)
624 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
625
626 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
627 pci_read_config_byte(pdev, 0x41, &fifo);
628
629 /* Check for AMD7409 without swdma errata and if found adjust type */
630 if (type == 1 && rev > 0x7)
631 type = 2;
632
633 /* Check for AMD7411 */
634 if (type == 3)
635 /* FIFO is broken */
636 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
637 else
638 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
639
640 /* Serenade ? */
641 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
642 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
643 type = 6; /* UDMA 100 only */
644
645 if (type < 3)
646 ata_pci_clear_simplex(pdev);
647
648 /* And fire it up */
649
650 port_info[0] = port_info[1] = &info[type];
651 return ata_pci_init_one(pdev, port_info, 2);
652 }
653
654 static int amd_reinit_one(struct pci_dev *pdev)
655 {
656 if (pdev->vendor == PCI_VENDOR_ID_AMD) {
657 u8 fifo;
658 pci_read_config_byte(pdev, 0x41, &fifo);
659 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
660 /* FIFO is broken */
661 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
662 else
663 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
664 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
665 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
666 ata_pci_clear_simplex(pdev);
667 }
668 return ata_pci_device_resume(pdev);
669 }
670
671 static const struct pci_device_id amd[] = {
672 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
673 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
674 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
675 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
676 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
677 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
678 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
679 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
680 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
681 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
682 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
683 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
684 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
685 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
686 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
687 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
688 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
689 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
690
691 { },
692 };
693
694 static struct pci_driver amd_pci_driver = {
695 .name = DRV_NAME,
696 .id_table = amd,
697 .probe = amd_init_one,
698 .remove = ata_pci_remove_one,
699 .suspend = ata_pci_device_suspend,
700 .resume = amd_reinit_one,
701 };
702
703 static int __init amd_init(void)
704 {
705 return pci_register_driver(&amd_pci_driver);
706 }
707
708 static void __exit amd_exit(void)
709 {
710 pci_unregister_driver(&amd_pci_driver);
711 }
712
713 MODULE_AUTHOR("Alan Cox");
714 MODULE_DESCRIPTION("low-level driver for AMD PATA IDE");
715 MODULE_LICENSE("GPL");
716 MODULE_DEVICE_TABLE(pci, amd);
717 MODULE_VERSION(DRV_VERSION);
718
719 module_init(amd_init);
720 module_exit(amd_exit);
Support for the Chinese Samsung S3C2440 based development boards