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libata: convert to iomap
[linux-2.6/mini2440.git] / drivers / ata / ahci.c
blob6d664849cc095a2a8a382285baf9cf91ec9c2fda
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "2.0"
51
52
53 enum {
54 AHCI_PCI_BAR = 5,
55 AHCI_MAX_PORTS = 32,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_MAX_CMDS = 32,
60 AHCI_CMD_SZ = 32,
61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_RX_FIS_SZ = 256,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
79
80 board_ahci = 0,
81 board_ahci_pi = 1,
82 board_ahci_vt8251 = 2,
83 board_ahci_ign_iferr = 3,
84
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
101 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
102 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
103
104 /* registers for each SATA port */
105 PORT_LST_ADDR = 0x00, /* command list DMA addr */
106 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
107 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
108 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
109 PORT_IRQ_STAT = 0x10, /* interrupt status */
110 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
111 PORT_CMD = 0x18, /* port command */
112 PORT_TFDATA = 0x20, /* taskfile data */
113 PORT_SIG = 0x24, /* device TF signature */
114 PORT_CMD_ISSUE = 0x38, /* command issue */
115 PORT_SCR = 0x28, /* SATA phy register block */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
120
121 /* PORT_IRQ_{STAT,MASK} bits */
122 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
123 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
124 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
125 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
126 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
127 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
128 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
129 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
130
131 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
132 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
133 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
134 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
135 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
136 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
137 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
138 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
139 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
140
141 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
142 PORT_IRQ_IF_ERR |
143 PORT_IRQ_CONNECT |
144 PORT_IRQ_PHYRDY |
145 PORT_IRQ_UNK_FIS,
146 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
147 PORT_IRQ_TF_ERR |
148 PORT_IRQ_HBUS_DATA_ERR,
149 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
150 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
151 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
152
153 /* PORT_CMD bits */
154 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
155 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
156 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
157 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
158 PORT_CMD_CLO = (1 << 3), /* Command list override */
159 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
160 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
161 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
162
163 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
164 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
165 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
166 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
167
168 /* ap->flags bits */
169 AHCI_FLAG_NO_NCQ = (1 << 24),
170 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
171 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
172 };
173
174 struct ahci_cmd_hdr {
175 u32 opts;
176 u32 status;
177 u32 tbl_addr;
178 u32 tbl_addr_hi;
179 u32 reserved[4];
180 };
181
182 struct ahci_sg {
183 u32 addr;
184 u32 addr_hi;
185 u32 reserved;
186 u32 flags_size;
187 };
188
189 struct ahci_host_priv {
190 u32 cap; /* cache of HOST_CAP register */
191 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
192 };
193
194 struct ahci_port_priv {
195 struct ahci_cmd_hdr *cmd_slot;
196 dma_addr_t cmd_slot_dma;
197 void *cmd_tbl;
198 dma_addr_t cmd_tbl_dma;
199 void *rx_fis;
200 dma_addr_t rx_fis_dma;
201 /* for NCQ spurious interrupt analysis */
202 int ncq_saw_spurious_sdb_cnt;
203 unsigned int ncq_saw_d2h:1;
204 unsigned int ncq_saw_dmas:1;
205 };
206
207 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
208 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
209 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
210 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
211 static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
212 static void ahci_irq_clear(struct ata_port *ap);
213 static int ahci_port_start(struct ata_port *ap);
214 static void ahci_port_stop(struct ata_port *ap);
215 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
216 static void ahci_qc_prep(struct ata_queued_cmd *qc);
217 static u8 ahci_check_status(struct ata_port *ap);
218 static void ahci_freeze(struct ata_port *ap);
219 static void ahci_thaw(struct ata_port *ap);
220 static void ahci_error_handler(struct ata_port *ap);
221 static void ahci_vt8251_error_handler(struct ata_port *ap);
222 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
223 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
224 static int ahci_port_resume(struct ata_port *ap);
225 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
226 static int ahci_pci_device_resume(struct pci_dev *pdev);
227
228 static struct scsi_host_template ahci_sht = {
229 .module = THIS_MODULE,
230 .name = DRV_NAME,
231 .ioctl = ata_scsi_ioctl,
232 .queuecommand = ata_scsi_queuecmd,
233 .change_queue_depth = ata_scsi_change_queue_depth,
234 .can_queue = AHCI_MAX_CMDS - 1,
235 .this_id = ATA_SHT_THIS_ID,
236 .sg_tablesize = AHCI_MAX_SG,
237 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
238 .emulated = ATA_SHT_EMULATED,
239 .use_clustering = AHCI_USE_CLUSTERING,
240 .proc_name = DRV_NAME,
241 .dma_boundary = AHCI_DMA_BOUNDARY,
242 .slave_configure = ata_scsi_slave_config,
243 .slave_destroy = ata_scsi_slave_destroy,
244 .bios_param = ata_std_bios_param,
245 .suspend = ata_scsi_device_suspend,
246 .resume = ata_scsi_device_resume,
247 };
248
249 static const struct ata_port_operations ahci_ops = {
250 .port_disable = ata_port_disable,
251
252 .check_status = ahci_check_status,
253 .check_altstatus = ahci_check_status,
254 .dev_select = ata_noop_dev_select,
255
256 .tf_read = ahci_tf_read,
257
258 .qc_prep = ahci_qc_prep,
259 .qc_issue = ahci_qc_issue,
260
261 .irq_handler = ahci_interrupt,
262 .irq_clear = ahci_irq_clear,
263
264 .scr_read = ahci_scr_read,
265 .scr_write = ahci_scr_write,
266
267 .freeze = ahci_freeze,
268 .thaw = ahci_thaw,
269
270 .error_handler = ahci_error_handler,
271 .post_internal_cmd = ahci_post_internal_cmd,
272
273 .port_suspend = ahci_port_suspend,
274 .port_resume = ahci_port_resume,
275
276 .port_start = ahci_port_start,
277 .port_stop = ahci_port_stop,
278 };
279
280 static const struct ata_port_operations ahci_vt8251_ops = {
281 .port_disable = ata_port_disable,
282
283 .check_status = ahci_check_status,
284 .check_altstatus = ahci_check_status,
285 .dev_select = ata_noop_dev_select,
286
287 .tf_read = ahci_tf_read,
288
289 .qc_prep = ahci_qc_prep,
290 .qc_issue = ahci_qc_issue,
291
292 .irq_handler = ahci_interrupt,
293 .irq_clear = ahci_irq_clear,
294
295 .scr_read = ahci_scr_read,
296 .scr_write = ahci_scr_write,
297
298 .freeze = ahci_freeze,
299 .thaw = ahci_thaw,
300
301 .error_handler = ahci_vt8251_error_handler,
302 .post_internal_cmd = ahci_post_internal_cmd,
303
304 .port_suspend = ahci_port_suspend,
305 .port_resume = ahci_port_resume,
306
307 .port_start = ahci_port_start,
308 .port_stop = ahci_port_stop,
309 };
310
311 static const struct ata_port_info ahci_port_info[] = {
312 /* board_ahci */
313 {
314 .sht = &ahci_sht,
315 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
316 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
317 ATA_FLAG_SKIP_D2H_BSY,
318 .pio_mask = 0x1f, /* pio0-4 */
319 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
320 .port_ops = &ahci_ops,
321 },
322 /* board_ahci_pi */
323 {
324 .sht = &ahci_sht,
325 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
326 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
327 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
328 .pio_mask = 0x1f, /* pio0-4 */
329 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
330 .port_ops = &ahci_ops,
331 },
332 /* board_ahci_vt8251 */
333 {
334 .sht = &ahci_sht,
335 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
336 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
337 ATA_FLAG_SKIP_D2H_BSY |
338 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
339 .pio_mask = 0x1f, /* pio0-4 */
340 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
341 .port_ops = &ahci_vt8251_ops,
342 },
343 /* board_ahci_ign_iferr */
344 {
345 .sht = &ahci_sht,
346 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
347 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
348 ATA_FLAG_SKIP_D2H_BSY |
349 AHCI_FLAG_IGN_IRQ_IF_ERR,
350 .pio_mask = 0x1f, /* pio0-4 */
351 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
352 .port_ops = &ahci_ops,
353 },
354 };
355
356 static const struct pci_device_id ahci_pci_tbl[] = {
357 /* Intel */
358 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
359 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
360 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
361 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
362 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
363 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
364 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
365 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
366 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
367 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
368 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
369 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
370 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
371 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
372 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
373 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
374 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
375 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
376 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
377 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
378 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
379 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
380 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
381 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
382 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
383 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
384
385 /* JMicron */
386 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */
387 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */
388 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */
389 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */
390 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */
391
392 /* ATI */
393 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
394 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
395
396 /* VIA */
397 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
398
399 /* NVIDIA */
400 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
401 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
402 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
403 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
404 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
405 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
406 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
407 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
408 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
409 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
410 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
411 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
412 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
413 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
414 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
415 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
416 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
417 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
419 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
420
421 /* SiS */
422 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
423 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
424 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
425
426 /* Generic, PCI class code for AHCI */
427 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
428 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
429
430 { } /* terminate list */
431 };
432
433
434 static struct pci_driver ahci_pci_driver = {
435 .name = DRV_NAME,
436 .id_table = ahci_pci_tbl,
437 .probe = ahci_init_one,
438 .remove = ata_pci_remove_one,
439 .suspend = ahci_pci_device_suspend,
440 .resume = ahci_pci_device_resume,
441 };
442
443
444 static inline int ahci_nr_ports(u32 cap)
445 {
446 return (cap & 0x1f) + 1;
447 }
448
449 static inline void __iomem *ahci_port_base(void __iomem *base,
450 unsigned int port)
451 {
452 return base + 0x100 + (port * 0x80);
453 }
454
455 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
456 {
457 unsigned int sc_reg;
458
459 switch (sc_reg_in) {
460 case SCR_STATUS: sc_reg = 0; break;
461 case SCR_CONTROL: sc_reg = 1; break;
462 case SCR_ERROR: sc_reg = 2; break;
463 case SCR_ACTIVE: sc_reg = 3; break;
464 default:
465 return 0xffffffffU;
466 }
467
468 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
469 }
470
471
472 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
473 u32 val)
474 {
475 unsigned int sc_reg;
476
477 switch (sc_reg_in) {
478 case SCR_STATUS: sc_reg = 0; break;
479 case SCR_CONTROL: sc_reg = 1; break;
480 case SCR_ERROR: sc_reg = 2; break;
481 case SCR_ACTIVE: sc_reg = 3; break;
482 default:
483 return;
484 }
485
486 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
487 }
488
489 static void ahci_start_engine(void __iomem *port_mmio)
490 {
491 u32 tmp;
492
493 /* start DMA */
494 tmp = readl(port_mmio + PORT_CMD);
495 tmp |= PORT_CMD_START;
496 writel(tmp, port_mmio + PORT_CMD);
497 readl(port_mmio + PORT_CMD); /* flush */
498 }
499
500 static int ahci_stop_engine(void __iomem *port_mmio)
501 {
502 u32 tmp;
503
504 tmp = readl(port_mmio + PORT_CMD);
505
506 /* check if the HBA is idle */
507 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
508 return 0;
509
510 /* setting HBA to idle */
511 tmp &= ~PORT_CMD_START;
512 writel(tmp, port_mmio + PORT_CMD);
513
514 /* wait for engine to stop. This could be as long as 500 msec */
515 tmp = ata_wait_register(port_mmio + PORT_CMD,
516 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
517 if (tmp & PORT_CMD_LIST_ON)
518 return -EIO;
519
520 return 0;
521 }
522
523 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
524 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
525 {
526 u32 tmp;
527
528 /* set FIS registers */
529 if (cap & HOST_CAP_64)
530 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
531 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
532
533 if (cap & HOST_CAP_64)
534 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
535 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
536
537 /* enable FIS reception */
538 tmp = readl(port_mmio + PORT_CMD);
539 tmp |= PORT_CMD_FIS_RX;
540 writel(tmp, port_mmio + PORT_CMD);
541
542 /* flush */
543 readl(port_mmio + PORT_CMD);
544 }
545
546 static int ahci_stop_fis_rx(void __iomem *port_mmio)
547 {
548 u32 tmp;
549
550 /* disable FIS reception */
551 tmp = readl(port_mmio + PORT_CMD);
552 tmp &= ~PORT_CMD_FIS_RX;
553 writel(tmp, port_mmio + PORT_CMD);
554
555 /* wait for completion, spec says 500ms, give it 1000 */
556 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
557 PORT_CMD_FIS_ON, 10, 1000);
558 if (tmp & PORT_CMD_FIS_ON)
559 return -EBUSY;
560
561 return 0;
562 }
563
564 static void ahci_power_up(void __iomem *port_mmio, u32 cap)
565 {
566 u32 cmd;
567
568 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
569
570 /* spin up device */
571 if (cap & HOST_CAP_SSS) {
572 cmd |= PORT_CMD_SPIN_UP;
573 writel(cmd, port_mmio + PORT_CMD);
574 }
575
576 /* wake up link */
577 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
578 }
579
580 static void ahci_power_down(void __iomem *port_mmio, u32 cap)
581 {
582 u32 cmd, scontrol;
583
584 if (!(cap & HOST_CAP_SSS))
585 return;
586
587 /* put device into listen mode, first set PxSCTL.DET to 0 */
588 scontrol = readl(port_mmio + PORT_SCR_CTL);
589 scontrol &= ~0xf;
590 writel(scontrol, port_mmio + PORT_SCR_CTL);
591
592 /* then set PxCMD.SUD to 0 */
593 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
594 cmd &= ~PORT_CMD_SPIN_UP;
595 writel(cmd, port_mmio + PORT_CMD);
596 }
597
598 static void ahci_init_port(void __iomem *port_mmio, u32 cap,
599 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
600 {
601 /* enable FIS reception */
602 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
603
604 /* enable DMA */
605 ahci_start_engine(port_mmio);
606 }
607
608 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
609 {
610 int rc;
611
612 /* disable DMA */
613 rc = ahci_stop_engine(port_mmio);
614 if (rc) {
615 *emsg = "failed to stop engine";
616 return rc;
617 }
618
619 /* disable FIS reception */
620 rc = ahci_stop_fis_rx(port_mmio);
621 if (rc) {
622 *emsg = "failed stop FIS RX";
623 return rc;
624 }
625
626 return 0;
627 }
628
629 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
630 {
631 u32 cap_save, impl_save, tmp;
632
633 cap_save = readl(mmio + HOST_CAP);
634 impl_save = readl(mmio + HOST_PORTS_IMPL);
635
636 /* global controller reset */
637 tmp = readl(mmio + HOST_CTL);
638 if ((tmp & HOST_RESET) == 0) {
639 writel(tmp | HOST_RESET, mmio + HOST_CTL);
640 readl(mmio + HOST_CTL); /* flush */
641 }
642
643 /* reset must complete within 1 second, or
644 * the hardware should be considered fried.
645 */
646 ssleep(1);
647
648 tmp = readl(mmio + HOST_CTL);
649 if (tmp & HOST_RESET) {
650 dev_printk(KERN_ERR, &pdev->dev,
651 "controller reset failed (0x%x)\n", tmp);
652 return -EIO;
653 }
654
655 /* turn on AHCI mode */
656 writel(HOST_AHCI_EN, mmio + HOST_CTL);
657 (void) readl(mmio + HOST_CTL); /* flush */
658
659 /* These write-once registers are normally cleared on reset.
660 * Restore BIOS values... which we HOPE were present before
661 * reset.
662 */
663 if (!impl_save) {
664 impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
665 dev_printk(KERN_WARNING, &pdev->dev,
666 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
667 }
668 writel(cap_save, mmio + HOST_CAP);
669 writel(impl_save, mmio + HOST_PORTS_IMPL);
670 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
671
672 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
673 u16 tmp16;
674
675 /* configure PCS */
676 pci_read_config_word(pdev, 0x92, &tmp16);
677 tmp16 |= 0xf;
678 pci_write_config_word(pdev, 0x92, tmp16);
679 }
680
681 return 0;
682 }
683
684 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
685 int n_ports, unsigned int port_flags,
686 struct ahci_host_priv *hpriv)
687 {
688 int i, rc;
689 u32 tmp;
690
691 for (i = 0; i < n_ports; i++) {
692 void __iomem *port_mmio = ahci_port_base(mmio, i);
693 const char *emsg = NULL;
694
695 if ((port_flags & AHCI_FLAG_HONOR_PI) &&
696 !(hpriv->port_map & (1 << i)))
697 continue;
698
699 /* make sure port is not active */
700 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
701 if (rc)
702 dev_printk(KERN_WARNING, &pdev->dev,
703 "%s (%d)\n", emsg, rc);
704
705 /* clear SError */
706 tmp = readl(port_mmio + PORT_SCR_ERR);
707 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
708 writel(tmp, port_mmio + PORT_SCR_ERR);
709
710 /* clear port IRQ */
711 tmp = readl(port_mmio + PORT_IRQ_STAT);
712 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
713 if (tmp)
714 writel(tmp, port_mmio + PORT_IRQ_STAT);
715
716 writel(1 << i, mmio + HOST_IRQ_STAT);
717 }
718
719 tmp = readl(mmio + HOST_CTL);
720 VPRINTK("HOST_CTL 0x%x\n", tmp);
721 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
722 tmp = readl(mmio + HOST_CTL);
723 VPRINTK("HOST_CTL 0x%x\n", tmp);
724 }
725
726 static unsigned int ahci_dev_classify(struct ata_port *ap)
727 {
728 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
729 struct ata_taskfile tf;
730 u32 tmp;
731
732 tmp = readl(port_mmio + PORT_SIG);
733 tf.lbah = (tmp >> 24) & 0xff;
734 tf.lbam = (tmp >> 16) & 0xff;
735 tf.lbal = (tmp >> 8) & 0xff;
736 tf.nsect = (tmp) & 0xff;
737
738 return ata_dev_classify(&tf);
739 }
740
741 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
742 u32 opts)
743 {
744 dma_addr_t cmd_tbl_dma;
745
746 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
747
748 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
749 pp->cmd_slot[tag].status = 0;
750 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
751 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
752 }
753
754 static int ahci_clo(struct ata_port *ap)
755 {
756 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
757 struct ahci_host_priv *hpriv = ap->host->private_data;
758 u32 tmp;
759
760 if (!(hpriv->cap & HOST_CAP_CLO))
761 return -EOPNOTSUPP;
762
763 tmp = readl(port_mmio + PORT_CMD);
764 tmp |= PORT_CMD_CLO;
765 writel(tmp, port_mmio + PORT_CMD);
766
767 tmp = ata_wait_register(port_mmio + PORT_CMD,
768 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
769 if (tmp & PORT_CMD_CLO)
770 return -EIO;
771
772 return 0;
773 }
774
775 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
776 {
777 struct ahci_port_priv *pp = ap->private_data;
778 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
779 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
780 const u32 cmd_fis_len = 5; /* five dwords */
781 const char *reason = NULL;
782 struct ata_taskfile tf;
783 u32 tmp;
784 u8 *fis;
785 int rc;
786
787 DPRINTK("ENTER\n");
788
789 if (ata_port_offline(ap)) {
790 DPRINTK("PHY reports no device\n");
791 *class = ATA_DEV_NONE;
792 return 0;
793 }
794
795 /* prepare for SRST (AHCI-1.1 10.4.1) */
796 rc = ahci_stop_engine(port_mmio);
797 if (rc) {
798 reason = "failed to stop engine";
799 goto fail_restart;
800 }
801
802 /* check BUSY/DRQ, perform Command List Override if necessary */
803 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
804 rc = ahci_clo(ap);
805
806 if (rc == -EOPNOTSUPP) {
807 reason = "port busy but CLO unavailable";
808 goto fail_restart;
809 } else if (rc) {
810 reason = "port busy but CLO failed";
811 goto fail_restart;
812 }
813 }
814
815 /* restart engine */
816 ahci_start_engine(port_mmio);
817
818 ata_tf_init(ap->device, &tf);
819 fis = pp->cmd_tbl;
820
821 /* issue the first D2H Register FIS */
822 ahci_fill_cmd_slot(pp, 0,
823 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
824
825 tf.ctl |= ATA_SRST;
826 ata_tf_to_fis(&tf, fis, 0);
827 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
828
829 writel(1, port_mmio + PORT_CMD_ISSUE);
830
831 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
832 if (tmp & 0x1) {
833 rc = -EIO;
834 reason = "1st FIS failed";
835 goto fail;
836 }
837
838 /* spec says at least 5us, but be generous and sleep for 1ms */
839 msleep(1);
840
841 /* issue the second D2H Register FIS */
842 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
843
844 tf.ctl &= ~ATA_SRST;
845 ata_tf_to_fis(&tf, fis, 0);
846 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
847
848 writel(1, port_mmio + PORT_CMD_ISSUE);
849 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
850
851 /* spec mandates ">= 2ms" before checking status.
852 * We wait 150ms, because that was the magic delay used for
853 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
854 * between when the ATA command register is written, and then
855 * status is checked. Because waiting for "a while" before
856 * checking status is fine, post SRST, we perform this magic
857 * delay here as well.
858 */
859 msleep(150);
860
861 *class = ATA_DEV_NONE;
862 if (ata_port_online(ap)) {
863 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
864 rc = -EIO;
865 reason = "device not ready";
866 goto fail;
867 }
868 *class = ahci_dev_classify(ap);
869 }
870
871 DPRINTK("EXIT, class=%u\n", *class);
872 return 0;
873
874 fail_restart:
875 ahci_start_engine(port_mmio);
876 fail:
877 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
878 return rc;
879 }
880
881 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
882 {
883 struct ahci_port_priv *pp = ap->private_data;
884 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
885 struct ata_taskfile tf;
886 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
887 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
888 int rc;
889
890 DPRINTK("ENTER\n");
891
892 ahci_stop_engine(port_mmio);
893
894 /* clear D2H reception area to properly wait for D2H FIS */
895 ata_tf_init(ap->device, &tf);
896 tf.command = 0x80;
897 ata_tf_to_fis(&tf, d2h_fis, 0);
898
899 rc = sata_std_hardreset(ap, class);
900
901 ahci_start_engine(port_mmio);
902
903 if (rc == 0 && ata_port_online(ap))
904 *class = ahci_dev_classify(ap);
905 if (*class == ATA_DEV_UNKNOWN)
906 *class = ATA_DEV_NONE;
907
908 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
909 return rc;
910 }
911
912 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
913 {
914 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
915 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
916 int rc;
917
918 DPRINTK("ENTER\n");
919
920 ahci_stop_engine(port_mmio);
921
922 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
923
924 /* vt8251 needs SError cleared for the port to operate */
925 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
926
927 ahci_start_engine(port_mmio);
928
929 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
930
931 /* vt8251 doesn't clear BSY on signature FIS reception,
932 * request follow-up softreset.
933 */
934 return rc ?: -EAGAIN;
935 }
936
937 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
938 {
939 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
940 u32 new_tmp, tmp;
941
942 ata_std_postreset(ap, class);
943
944 /* Make sure port's ATAPI bit is set appropriately */
945 new_tmp = tmp = readl(port_mmio + PORT_CMD);
946 if (*class == ATA_DEV_ATAPI)
947 new_tmp |= PORT_CMD_ATAPI;
948 else
949 new_tmp &= ~PORT_CMD_ATAPI;
950 if (new_tmp != tmp) {
951 writel(new_tmp, port_mmio + PORT_CMD);
952 readl(port_mmio + PORT_CMD); /* flush */
953 }
954 }
955
956 static u8 ahci_check_status(struct ata_port *ap)
957 {
958 void __iomem *mmio = ap->ioaddr.cmd_addr;
959
960 return readl(mmio + PORT_TFDATA) & 0xFF;
961 }
962
963 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
964 {
965 struct ahci_port_priv *pp = ap->private_data;
966 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
967
968 ata_tf_from_fis(d2h_fis, tf);
969 }
970
971 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
972 {
973 struct scatterlist *sg;
974 struct ahci_sg *ahci_sg;
975 unsigned int n_sg = 0;
976
977 VPRINTK("ENTER\n");
978
979 /*
980 * Next, the S/G list.
981 */
982 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
983 ata_for_each_sg(sg, qc) {
984 dma_addr_t addr = sg_dma_address(sg);
985 u32 sg_len = sg_dma_len(sg);
986
987 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
988 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
989 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
990
991 ahci_sg++;
992 n_sg++;
993 }
994
995 return n_sg;
996 }
997
998 static void ahci_qc_prep(struct ata_queued_cmd *qc)
999 {
1000 struct ata_port *ap = qc->ap;
1001 struct ahci_port_priv *pp = ap->private_data;
1002 int is_atapi = is_atapi_taskfile(&qc->tf);
1003 void *cmd_tbl;
1004 u32 opts;
1005 const u32 cmd_fis_len = 5; /* five dwords */
1006 unsigned int n_elem;
1007
1008 /*
1009 * Fill in command table information. First, the header,
1010 * a SATA Register - Host to Device command FIS.
1011 */
1012 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1013
1014 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
1015 if (is_atapi) {
1016 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1017 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1018 }
1019
1020 n_elem = 0;
1021 if (qc->flags & ATA_QCFLAG_DMAMAP)
1022 n_elem = ahci_fill_sg(qc, cmd_tbl);
1023
1024 /*
1025 * Fill in command slot information.
1026 */
1027 opts = cmd_fis_len | n_elem << 16;
1028 if (qc->tf.flags & ATA_TFLAG_WRITE)
1029 opts |= AHCI_CMD_WRITE;
1030 if (is_atapi)
1031 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1032
1033 ahci_fill_cmd_slot(pp, qc->tag, opts);
1034 }
1035
1036 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1037 {
1038 struct ahci_port_priv *pp = ap->private_data;
1039 struct ata_eh_info *ehi = &ap->eh_info;
1040 unsigned int err_mask = 0, action = 0;
1041 struct ata_queued_cmd *qc;
1042 u32 serror;
1043
1044 ata_ehi_clear_desc(ehi);
1045
1046 /* AHCI needs SError cleared; otherwise, it might lock up */
1047 serror = ahci_scr_read(ap, SCR_ERROR);
1048 ahci_scr_write(ap, SCR_ERROR, serror);
1049
1050 /* analyze @irq_stat */
1051 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1052
1053 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1054 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1055 irq_stat &= ~PORT_IRQ_IF_ERR;
1056
1057 if (irq_stat & PORT_IRQ_TF_ERR)
1058 err_mask |= AC_ERR_DEV;
1059
1060 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1061 err_mask |= AC_ERR_HOST_BUS;
1062 action |= ATA_EH_SOFTRESET;
1063 }
1064
1065 if (irq_stat & PORT_IRQ_IF_ERR) {
1066 err_mask |= AC_ERR_ATA_BUS;
1067 action |= ATA_EH_SOFTRESET;
1068 ata_ehi_push_desc(ehi, ", interface fatal error");
1069 }
1070
1071 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1072 ata_ehi_hotplugged(ehi);
1073 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1074 "connection status changed" : "PHY RDY changed");
1075 }
1076
1077 if (irq_stat & PORT_IRQ_UNK_FIS) {
1078 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1079
1080 err_mask |= AC_ERR_HSM;
1081 action |= ATA_EH_SOFTRESET;
1082 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1083 unk[0], unk[1], unk[2], unk[3]);
1084 }
1085
1086 /* okay, let's hand over to EH */
1087 ehi->serror |= serror;
1088 ehi->action |= action;
1089
1090 qc = ata_qc_from_tag(ap, ap->active_tag);
1091 if (qc)
1092 qc->err_mask |= err_mask;
1093 else
1094 ehi->err_mask |= err_mask;
1095
1096 if (irq_stat & PORT_IRQ_FREEZE)
1097 ata_port_freeze(ap);
1098 else
1099 ata_port_abort(ap);
1100 }
1101
1102 static void ahci_host_intr(struct ata_port *ap)
1103 {
1104 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1105 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1106 struct ata_eh_info *ehi = &ap->eh_info;
1107 struct ahci_port_priv *pp = ap->private_data;
1108 u32 status, qc_active;
1109 int rc, known_irq = 0;
1110
1111 status = readl(port_mmio + PORT_IRQ_STAT);
1112 writel(status, port_mmio + PORT_IRQ_STAT);
1113
1114 if (unlikely(status & PORT_IRQ_ERROR)) {
1115 ahci_error_intr(ap, status);
1116 return;
1117 }
1118
1119 if (ap->sactive)
1120 qc_active = readl(port_mmio + PORT_SCR_ACT);
1121 else
1122 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1123
1124 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1125 if (rc > 0)
1126 return;
1127 if (rc < 0) {
1128 ehi->err_mask |= AC_ERR_HSM;
1129 ehi->action |= ATA_EH_SOFTRESET;
1130 ata_port_freeze(ap);
1131 return;
1132 }
1133
1134 /* hmmm... a spurious interupt */
1135
1136 /* if !NCQ, ignore. No modern ATA device has broken HSM
1137 * implementation for non-NCQ commands.
1138 */
1139 if (!ap->sactive)
1140 return;
1141
1142 if (status & PORT_IRQ_D2H_REG_FIS) {
1143 if (!pp->ncq_saw_d2h)
1144 ata_port_printk(ap, KERN_INFO,
1145 "D2H reg with I during NCQ, "
1146 "this message won't be printed again\n");
1147 pp->ncq_saw_d2h = 1;
1148 known_irq = 1;
1149 }
1150
1151 if (status & PORT_IRQ_DMAS_FIS) {
1152 if (!pp->ncq_saw_dmas)
1153 ata_port_printk(ap, KERN_INFO,
1154 "DMAS FIS during NCQ, "
1155 "this message won't be printed again\n");
1156 pp->ncq_saw_dmas = 1;
1157 known_irq = 1;
1158 }
1159
1160 if (status & PORT_IRQ_SDB_FIS &&
1161 pp->ncq_saw_spurious_sdb_cnt < 10) {
1162 /* SDB FIS containing spurious completions might be
1163 * dangerous, we need to know more about them. Print
1164 * more of it.
1165 */
1166 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1167
1168 ata_port_printk(ap, KERN_INFO, "Spurious SDB FIS during NCQ "
1169 "issue=0x%x SAct=0x%x FIS=%08x:%08x%s\n",
1170 readl(port_mmio + PORT_CMD_ISSUE),
1171 readl(port_mmio + PORT_SCR_ACT),
1172 le32_to_cpu(f[0]), le32_to_cpu(f[1]),
1173 pp->ncq_saw_spurious_sdb_cnt < 10 ?
1174 "" : ", shutting up");
1175
1176 pp->ncq_saw_spurious_sdb_cnt++;
1177 known_irq = 1;
1178 }
1179
1180 if (!known_irq)
1181 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1182 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1183 status, ap->active_tag, ap->sactive);
1184 }
1185
1186 static void ahci_irq_clear(struct ata_port *ap)
1187 {
1188 /* TODO */
1189 }
1190
1191 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1192 {
1193 struct ata_host *host = dev_instance;
1194 struct ahci_host_priv *hpriv;
1195 unsigned int i, handled = 0;
1196 void __iomem *mmio;
1197 u32 irq_stat, irq_ack = 0;
1198
1199 VPRINTK("ENTER\n");
1200
1201 hpriv = host->private_data;
1202 mmio = host->iomap[AHCI_PCI_BAR];
1203
1204 /* sigh. 0xffffffff is a valid return from h/w */
1205 irq_stat = readl(mmio + HOST_IRQ_STAT);
1206 irq_stat &= hpriv->port_map;
1207 if (!irq_stat)
1208 return IRQ_NONE;
1209
1210 spin_lock(&host->lock);
1211
1212 for (i = 0; i < host->n_ports; i++) {
1213 struct ata_port *ap;
1214
1215 if (!(irq_stat & (1 << i)))
1216 continue;
1217
1218 ap = host->ports[i];
1219 if (ap) {
1220 ahci_host_intr(ap);
1221 VPRINTK("port %u\n", i);
1222 } else {
1223 VPRINTK("port %u (no irq)\n", i);
1224 if (ata_ratelimit())
1225 dev_printk(KERN_WARNING, host->dev,
1226 "interrupt on disabled port %u\n", i);
1227 }
1228
1229 irq_ack |= (1 << i);
1230 }
1231
1232 if (irq_ack) {
1233 writel(irq_ack, mmio + HOST_IRQ_STAT);
1234 handled = 1;
1235 }
1236
1237 spin_unlock(&host->lock);
1238
1239 VPRINTK("EXIT\n");
1240
1241 return IRQ_RETVAL(handled);
1242 }
1243
1244 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1245 {
1246 struct ata_port *ap = qc->ap;
1247 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1248
1249 if (qc->tf.protocol == ATA_PROT_NCQ)
1250 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1251 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1252 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1253
1254 return 0;
1255 }
1256
1257 static void ahci_freeze(struct ata_port *ap)
1258 {
1259 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1260 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1261
1262 /* turn IRQ off */
1263 writel(0, port_mmio + PORT_IRQ_MASK);
1264 }
1265
1266 static void ahci_thaw(struct ata_port *ap)
1267 {
1268 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1269 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1270 u32 tmp;
1271
1272 /* clear IRQ */
1273 tmp = readl(port_mmio + PORT_IRQ_STAT);
1274 writel(tmp, port_mmio + PORT_IRQ_STAT);
1275 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1276
1277 /* turn IRQ back on */
1278 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1279 }
1280
1281 static void ahci_error_handler(struct ata_port *ap)
1282 {
1283 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1284 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1285
1286 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1287 /* restart engine */
1288 ahci_stop_engine(port_mmio);
1289 ahci_start_engine(port_mmio);
1290 }
1291
1292 /* perform recovery */
1293 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1294 ahci_postreset);
1295 }
1296
1297 static void ahci_vt8251_error_handler(struct ata_port *ap)
1298 {
1299 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1300 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1301
1302 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1303 /* restart engine */
1304 ahci_stop_engine(port_mmio);
1305 ahci_start_engine(port_mmio);
1306 }
1307
1308 /* perform recovery */
1309 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1310 ahci_postreset);
1311 }
1312
1313 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1314 {
1315 struct ata_port *ap = qc->ap;
1316 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1317 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1318
1319 if (qc->flags & ATA_QCFLAG_FAILED)
1320 qc->err_mask |= AC_ERR_OTHER;
1321
1322 if (qc->err_mask) {
1323 /* make DMA engine forget about the failed command */
1324 ahci_stop_engine(port_mmio);
1325 ahci_start_engine(port_mmio);
1326 }
1327 }
1328
1329 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1330 {
1331 struct ahci_host_priv *hpriv = ap->host->private_data;
1332 struct ahci_port_priv *pp = ap->private_data;
1333 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1334 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1335 const char *emsg = NULL;
1336 int rc;
1337
1338 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1339 if (rc == 0)
1340 ahci_power_down(port_mmio, hpriv->cap);
1341 else {
1342 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1343 ahci_init_port(port_mmio, hpriv->cap,
1344 pp->cmd_slot_dma, pp->rx_fis_dma);
1345 }
1346
1347 return rc;
1348 }
1349
1350 static int ahci_port_resume(struct ata_port *ap)
1351 {
1352 struct ahci_port_priv *pp = ap->private_data;
1353 struct ahci_host_priv *hpriv = ap->host->private_data;
1354 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1355 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1356
1357 ahci_power_up(port_mmio, hpriv->cap);
1358 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1359
1360 return 0;
1361 }
1362
1363 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1364 {
1365 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1366 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1367 u32 ctl;
1368
1369 if (mesg.event == PM_EVENT_SUSPEND) {
1370 /* AHCI spec rev1.1 section 8.3.3:
1371 * Software must disable interrupts prior to requesting a
1372 * transition of the HBA to D3 state.
1373 */
1374 ctl = readl(mmio + HOST_CTL);
1375 ctl &= ~HOST_IRQ_EN;
1376 writel(ctl, mmio + HOST_CTL);
1377 readl(mmio + HOST_CTL); /* flush */
1378 }
1379
1380 return ata_pci_device_suspend(pdev, mesg);
1381 }
1382
1383 static int ahci_pci_device_resume(struct pci_dev *pdev)
1384 {
1385 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1386 struct ahci_host_priv *hpriv = host->private_data;
1387 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1388 int rc;
1389
1390 rc = ata_pci_device_do_resume(pdev);
1391 if (rc)
1392 return rc;
1393
1394 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1395 rc = ahci_reset_controller(mmio, pdev);
1396 if (rc)
1397 return rc;
1398
1399 ahci_init_controller(mmio, pdev, host->n_ports,
1400 host->ports[0]->flags, hpriv);
1401 }
1402
1403 ata_host_resume(host);
1404
1405 return 0;
1406 }
1407
1408 static int ahci_port_start(struct ata_port *ap)
1409 {
1410 struct device *dev = ap->host->dev;
1411 struct ahci_host_priv *hpriv = ap->host->private_data;
1412 struct ahci_port_priv *pp;
1413 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1414 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1415 void *mem;
1416 dma_addr_t mem_dma;
1417 int rc;
1418
1419 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1420 if (!pp)
1421 return -ENOMEM;
1422
1423 rc = ata_pad_alloc(ap, dev);
1424 if (rc)
1425 return rc;
1426
1427 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1428 GFP_KERNEL);
1429 if (!mem)
1430 return -ENOMEM;
1431 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1432
1433 /*
1434 * First item in chunk of DMA memory: 32-slot command table,
1435 * 32 bytes each in size
1436 */
1437 pp->cmd_slot = mem;
1438 pp->cmd_slot_dma = mem_dma;
1439
1440 mem += AHCI_CMD_SLOT_SZ;
1441 mem_dma += AHCI_CMD_SLOT_SZ;
1442
1443 /*
1444 * Second item: Received-FIS area
1445 */
1446 pp->rx_fis = mem;
1447 pp->rx_fis_dma = mem_dma;
1448
1449 mem += AHCI_RX_FIS_SZ;
1450 mem_dma += AHCI_RX_FIS_SZ;
1451
1452 /*
1453 * Third item: data area for storing a single command
1454 * and its scatter-gather table
1455 */
1456 pp->cmd_tbl = mem;
1457 pp->cmd_tbl_dma = mem_dma;
1458
1459 ap->private_data = pp;
1460
1461 /* power up port */
1462 ahci_power_up(port_mmio, hpriv->cap);
1463
1464 /* initialize port */
1465 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1466
1467 return 0;
1468 }
1469
1470 static void ahci_port_stop(struct ata_port *ap)
1471 {
1472 struct ahci_host_priv *hpriv = ap->host->private_data;
1473 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1474 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1475 const char *emsg = NULL;
1476 int rc;
1477
1478 /* de-initialize port */
1479 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1480 if (rc)
1481 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1482 }
1483
1484 static void ahci_setup_port(struct ata_ioports *port, void __iomem *base,
1485 unsigned int port_idx)
1486 {
1487 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1488 base = ahci_port_base(base, port_idx);
1489 VPRINTK("base now==0x%lx\n", base);
1490
1491 port->cmd_addr = base;
1492 port->scr_addr = base + PORT_SCR;
1493
1494 VPRINTK("EXIT\n");
1495 }
1496
1497 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1498 {
1499 struct ahci_host_priv *hpriv = probe_ent->private_data;
1500 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1501 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
1502 unsigned int i, cap_n_ports, using_dac;
1503 int rc;
1504
1505 rc = ahci_reset_controller(mmio, pdev);
1506 if (rc)
1507 return rc;
1508
1509 hpriv->cap = readl(mmio + HOST_CAP);
1510 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1511 cap_n_ports = ahci_nr_ports(hpriv->cap);
1512
1513 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1514 hpriv->cap, hpriv->port_map, cap_n_ports);
1515
1516 if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) {
1517 unsigned int n_ports = cap_n_ports;
1518 u32 port_map = hpriv->port_map;
1519 int max_port = 0;
1520
1521 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
1522 if (port_map & (1 << i)) {
1523 n_ports--;
1524 port_map &= ~(1 << i);
1525 max_port = i;
1526 } else
1527 probe_ent->dummy_port_mask |= 1 << i;
1528 }
1529
1530 if (n_ports || port_map)
1531 dev_printk(KERN_WARNING, &pdev->dev,
1532 "nr_ports (%u) and implemented port map "
1533 "(0x%x) don't match\n",
1534 cap_n_ports, hpriv->port_map);
1535
1536 probe_ent->n_ports = max_port + 1;
1537 } else
1538 probe_ent->n_ports = cap_n_ports;
1539
1540 using_dac = hpriv->cap & HOST_CAP_64;
1541 if (using_dac &&
1542 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1543 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1544 if (rc) {
1545 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1546 if (rc) {
1547 dev_printk(KERN_ERR, &pdev->dev,
1548 "64-bit DMA enable failed\n");
1549 return rc;
1550 }
1551 }
1552 } else {
1553 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1554 if (rc) {
1555 dev_printk(KERN_ERR, &pdev->dev,
1556 "32-bit DMA enable failed\n");
1557 return rc;
1558 }
1559 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1560 if (rc) {
1561 dev_printk(KERN_ERR, &pdev->dev,
1562 "32-bit consistent DMA enable failed\n");
1563 return rc;
1564 }
1565 }
1566
1567 for (i = 0; i < probe_ent->n_ports; i++)
1568 ahci_setup_port(&probe_ent->port[i], mmio, i);
1569
1570 ahci_init_controller(mmio, pdev, probe_ent->n_ports,
1571 probe_ent->port_flags, hpriv);
1572
1573 pci_set_master(pdev);
1574
1575 return 0;
1576 }
1577
1578 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1579 {
1580 struct ahci_host_priv *hpriv = probe_ent->private_data;
1581 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1582 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
1583 u32 vers, cap, impl, speed;
1584 const char *speed_s;
1585 u16 cc;
1586 const char *scc_s;
1587
1588 vers = readl(mmio + HOST_VERSION);
1589 cap = hpriv->cap;
1590 impl = hpriv->port_map;
1591
1592 speed = (cap >> 20) & 0xf;
1593 if (speed == 1)
1594 speed_s = "1.5";
1595 else if (speed == 2)
1596 speed_s = "3";
1597 else
1598 speed_s = "?";
1599
1600 pci_read_config_word(pdev, 0x0a, &cc);
1601 if (cc == PCI_CLASS_STORAGE_IDE)
1602 scc_s = "IDE";
1603 else if (cc == PCI_CLASS_STORAGE_SATA)
1604 scc_s = "SATA";
1605 else if (cc == PCI_CLASS_STORAGE_RAID)
1606 scc_s = "RAID";
1607 else
1608 scc_s = "unknown";
1609
1610 dev_printk(KERN_INFO, &pdev->dev,
1611 "AHCI %02x%02x.%02x%02x "
1612 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1613 ,
1614
1615 (vers >> 24) & 0xff,
1616 (vers >> 16) & 0xff,
1617 (vers >> 8) & 0xff,
1618 vers & 0xff,
1619
1620 ((cap >> 8) & 0x1f) + 1,
1621 (cap & 0x1f) + 1,
1622 speed_s,
1623 impl,
1624 scc_s);
1625
1626 dev_printk(KERN_INFO, &pdev->dev,
1627 "flags: "
1628 "%s%s%s%s%s%s"
1629 "%s%s%s%s%s%s%s\n"
1630 ,
1631
1632 cap & (1 << 31) ? "64bit " : "",
1633 cap & (1 << 30) ? "ncq " : "",
1634 cap & (1 << 28) ? "ilck " : "",
1635 cap & (1 << 27) ? "stag " : "",
1636 cap & (1 << 26) ? "pm " : "",
1637 cap & (1 << 25) ? "led " : "",
1638
1639 cap & (1 << 24) ? "clo " : "",
1640 cap & (1 << 19) ? "nz " : "",
1641 cap & (1 << 18) ? "only " : "",
1642 cap & (1 << 17) ? "pmp " : "",
1643 cap & (1 << 15) ? "pio " : "",
1644 cap & (1 << 14) ? "slum " : "",
1645 cap & (1 << 13) ? "part " : ""
1646 );
1647 }
1648
1649 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1650 {
1651 static int printed_version;
1652 unsigned int board_idx = (unsigned int) ent->driver_data;
1653 struct device *dev = &pdev->dev;
1654 struct ata_probe_ent *probe_ent;
1655 struct ahci_host_priv *hpriv;
1656 int rc;
1657
1658 VPRINTK("ENTER\n");
1659
1660 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1661
1662 if (!printed_version++)
1663 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1664
1665 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1666 /* Function 1 is the PATA controller except on the 368, where
1667 we are not AHCI anyway */
1668 if (PCI_FUNC(pdev->devfn))
1669 return -ENODEV;
1670 }
1671
1672 rc = pcim_enable_device(pdev);
1673 if (rc)
1674 return rc;
1675
1676 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1677 if (rc == -EBUSY)
1678 pcim_pin_device(pdev);
1679 if (rc)
1680 return rc;
1681
1682 if (pci_enable_msi(pdev))
1683 pci_intx(pdev, 1);
1684
1685 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
1686 if (probe_ent == NULL)
1687 return -ENOMEM;
1688
1689 probe_ent->dev = pci_dev_to_dev(pdev);
1690 INIT_LIST_HEAD(&probe_ent->node);
1691
1692 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1693 if (!hpriv)
1694 return -ENOMEM;
1695
1696 probe_ent->sht = ahci_port_info[board_idx].sht;
1697 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1698 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1699 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1700 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1701
1702 probe_ent->irq = pdev->irq;
1703 probe_ent->irq_flags = IRQF_SHARED;
1704 probe_ent->iomap = pcim_iomap_table(pdev);
1705 probe_ent->private_data = hpriv;
1706
1707 /* initialize adapter */
1708 rc = ahci_host_init(probe_ent);
1709 if (rc)
1710 return rc;
1711
1712 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
1713 (hpriv->cap & HOST_CAP_NCQ))
1714 probe_ent->port_flags |= ATA_FLAG_NCQ;
1715
1716 ahci_print_info(probe_ent);
1717
1718 if (!ata_device_add(probe_ent))
1719 return -ENODEV;
1720
1721 devm_kfree(dev, probe_ent);
1722 return 0;
1723 }
1724
1725 static int __init ahci_init(void)
1726 {
1727 return pci_register_driver(&ahci_pci_driver);
1728 }
1729
1730 static void __exit ahci_exit(void)
1731 {
1732 pci_unregister_driver(&ahci_pci_driver);
1733 }
1734
1735
1736 MODULE_AUTHOR("Jeff Garzik");
1737 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1738 MODULE_LICENSE("GPL");
1739 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1740 MODULE_VERSION(DRV_VERSION);
1741
1742 module_init(ahci_init);
1743 module_exit(ahci_exit);
Support for the Chinese Samsung S3C2440 based development boards