2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/interrupt.h>
18 #include <linux/ptrace.h>
19 #include <linux/sysdev.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
23 #include <asm/hardware.h>
25 #include <asm/arch/irqs.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/mach/irq.h>
32 * OMAP1510 GPIO registers
34 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43 #define OMAP1510_IH_GPIO_BASE 64
46 * OMAP1610 specific GPIO registers
48 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
49 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
50 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
51 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
71 * OMAP730 specific GPIO registers
73 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
74 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
75 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
76 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
77 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
78 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
87 * omap24xx specific GPIO registers
89 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
90 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
91 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
92 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
93 #define OMAP24XX_GPIO_REVISION 0x0000
94 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
95 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
96 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
97 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
98 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
99 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
100 #define OMAP24XX_GPIO_CTRL 0x0030
101 #define OMAP24XX_GPIO_OE 0x0034
102 #define OMAP24XX_GPIO_DATAIN 0x0038
103 #define OMAP24XX_GPIO_DATAOUT 0x003c
104 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
105 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
106 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
107 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
108 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
109 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
110 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
111 #define OMAP24XX_GPIO_SETWKUENA 0x0084
112 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
113 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
118 u16 virtual_irq_start
;
126 #define METHOD_MPUIO 0
127 #define METHOD_GPIO_1510 1
128 #define METHOD_GPIO_1610 2
129 #define METHOD_GPIO_730 3
130 #define METHOD_GPIO_24XX 4
132 #ifdef CONFIG_ARCH_OMAP16XX
133 static struct gpio_bank gpio_bank_1610
[5] = {
134 { OMAP_MPUIO_BASE
, INT_MPUIO
, IH_MPUIO_BASE
, METHOD_MPUIO
},
135 { OMAP1610_GPIO1_BASE
, INT_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_1610
},
136 { OMAP1610_GPIO2_BASE
, INT_1610_GPIO_BANK2
, IH_GPIO_BASE
+ 16, METHOD_GPIO_1610
},
137 { OMAP1610_GPIO3_BASE
, INT_1610_GPIO_BANK3
, IH_GPIO_BASE
+ 32, METHOD_GPIO_1610
},
138 { OMAP1610_GPIO4_BASE
, INT_1610_GPIO_BANK4
, IH_GPIO_BASE
+ 48, METHOD_GPIO_1610
},
142 #ifdef CONFIG_ARCH_OMAP15XX
143 static struct gpio_bank gpio_bank_1510
[2] = {
144 { OMAP_MPUIO_BASE
, INT_MPUIO
, IH_MPUIO_BASE
, METHOD_MPUIO
},
145 { OMAP1510_GPIO_BASE
, INT_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_1510
}
149 #ifdef CONFIG_ARCH_OMAP730
150 static struct gpio_bank gpio_bank_730
[7] = {
151 { OMAP_MPUIO_BASE
, INT_730_MPUIO
, IH_MPUIO_BASE
, METHOD_MPUIO
},
152 { OMAP730_GPIO1_BASE
, INT_730_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_730
},
153 { OMAP730_GPIO2_BASE
, INT_730_GPIO_BANK2
, IH_GPIO_BASE
+ 32, METHOD_GPIO_730
},
154 { OMAP730_GPIO3_BASE
, INT_730_GPIO_BANK3
, IH_GPIO_BASE
+ 64, METHOD_GPIO_730
},
155 { OMAP730_GPIO4_BASE
, INT_730_GPIO_BANK4
, IH_GPIO_BASE
+ 96, METHOD_GPIO_730
},
156 { OMAP730_GPIO5_BASE
, INT_730_GPIO_BANK5
, IH_GPIO_BASE
+ 128, METHOD_GPIO_730
},
157 { OMAP730_GPIO6_BASE
, INT_730_GPIO_BANK6
, IH_GPIO_BASE
+ 160, METHOD_GPIO_730
},
161 #ifdef CONFIG_ARCH_OMAP24XX
162 static struct gpio_bank gpio_bank_24xx
[4] = {
163 { OMAP24XX_GPIO1_BASE
, INT_24XX_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_24XX
},
164 { OMAP24XX_GPIO2_BASE
, INT_24XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32, METHOD_GPIO_24XX
},
165 { OMAP24XX_GPIO3_BASE
, INT_24XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64, METHOD_GPIO_24XX
},
166 { OMAP24XX_GPIO4_BASE
, INT_24XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96, METHOD_GPIO_24XX
},
170 static struct gpio_bank
*gpio_bank
;
171 static int gpio_bank_count
;
173 static inline struct gpio_bank
*get_gpio_bank(int gpio
)
175 #ifdef CONFIG_ARCH_OMAP15XX
176 if (cpu_is_omap15xx()) {
177 if (OMAP_GPIO_IS_MPUIO(gpio
))
178 return &gpio_bank
[0];
179 return &gpio_bank
[1];
182 #if defined(CONFIG_ARCH_OMAP16XX)
183 if (cpu_is_omap16xx()) {
184 if (OMAP_GPIO_IS_MPUIO(gpio
))
185 return &gpio_bank
[0];
186 return &gpio_bank
[1 + (gpio
>> 4)];
189 #ifdef CONFIG_ARCH_OMAP730
190 if (cpu_is_omap730()) {
191 if (OMAP_GPIO_IS_MPUIO(gpio
))
192 return &gpio_bank
[0];
193 return &gpio_bank
[1 + (gpio
>> 5)];
196 #ifdef CONFIG_ARCH_OMAP24XX
197 if (cpu_is_omap24xx())
198 return &gpio_bank
[gpio
>> 5];
202 static inline int get_gpio_index(int gpio
)
204 #ifdef CONFIG_ARCH_OMAP730
205 if (cpu_is_omap730())
208 #ifdef CONFIG_ARCH_OMAP24XX
209 if (cpu_is_omap24xx())
215 static inline int gpio_valid(int gpio
)
219 #ifndef CONFIG_ARCH_OMAP24XX
220 if (OMAP_GPIO_IS_MPUIO(gpio
)) {
221 if (gpio
>= OMAP_MAX_GPIO_LINES
+ 16)
226 #ifdef CONFIG_ARCH_OMAP15XX
227 if (cpu_is_omap15xx() && gpio
< 16)
230 #if defined(CONFIG_ARCH_OMAP16XX)
231 if ((cpu_is_omap16xx()) && gpio
< 64)
234 #ifdef CONFIG_ARCH_OMAP730
235 if (cpu_is_omap730() && gpio
< 192)
238 #ifdef CONFIG_ARCH_OMAP24XX
239 if (cpu_is_omap24xx() && gpio
< 128)
245 static int check_gpio(int gpio
)
247 if (unlikely(gpio_valid(gpio
)) < 0) {
248 printk(KERN_ERR
"omap-gpio: invalid GPIO %d\n", gpio
);
255 static void _set_gpio_direction(struct gpio_bank
*bank
, int gpio
, int is_input
)
257 void __iomem
*reg
= bank
->base
;
260 switch (bank
->method
) {
262 reg
+= OMAP_MPUIO_IO_CNTL
;
264 case METHOD_GPIO_1510
:
265 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
267 case METHOD_GPIO_1610
:
268 reg
+= OMAP1610_GPIO_DIRECTION
;
270 case METHOD_GPIO_730
:
271 reg
+= OMAP730_GPIO_DIR_CONTROL
;
273 case METHOD_GPIO_24XX
:
274 reg
+= OMAP24XX_GPIO_OE
;
277 l
= __raw_readl(reg
);
282 __raw_writel(l
, reg
);
285 void omap_set_gpio_direction(int gpio
, int is_input
)
287 struct gpio_bank
*bank
;
289 if (check_gpio(gpio
) < 0)
291 bank
= get_gpio_bank(gpio
);
292 spin_lock(&bank
->lock
);
293 _set_gpio_direction(bank
, get_gpio_index(gpio
), is_input
);
294 spin_unlock(&bank
->lock
);
297 static void _set_gpio_dataout(struct gpio_bank
*bank
, int gpio
, int enable
)
299 void __iomem
*reg
= bank
->base
;
302 switch (bank
->method
) {
304 reg
+= OMAP_MPUIO_OUTPUT
;
305 l
= __raw_readl(reg
);
311 case METHOD_GPIO_1510
:
312 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
313 l
= __raw_readl(reg
);
319 case METHOD_GPIO_1610
:
321 reg
+= OMAP1610_GPIO_SET_DATAOUT
;
323 reg
+= OMAP1610_GPIO_CLEAR_DATAOUT
;
326 case METHOD_GPIO_730
:
327 reg
+= OMAP730_GPIO_DATA_OUTPUT
;
328 l
= __raw_readl(reg
);
334 case METHOD_GPIO_24XX
:
336 reg
+= OMAP24XX_GPIO_SETDATAOUT
;
338 reg
+= OMAP24XX_GPIO_CLEARDATAOUT
;
345 __raw_writel(l
, reg
);
348 void omap_set_gpio_dataout(int gpio
, int enable
)
350 struct gpio_bank
*bank
;
352 if (check_gpio(gpio
) < 0)
354 bank
= get_gpio_bank(gpio
);
355 spin_lock(&bank
->lock
);
356 _set_gpio_dataout(bank
, get_gpio_index(gpio
), enable
);
357 spin_unlock(&bank
->lock
);
360 int omap_get_gpio_datain(int gpio
)
362 struct gpio_bank
*bank
;
365 if (check_gpio(gpio
) < 0)
367 bank
= get_gpio_bank(gpio
);
369 switch (bank
->method
) {
371 reg
+= OMAP_MPUIO_INPUT_LATCH
;
373 case METHOD_GPIO_1510
:
374 reg
+= OMAP1510_GPIO_DATA_INPUT
;
376 case METHOD_GPIO_1610
:
377 reg
+= OMAP1610_GPIO_DATAIN
;
379 case METHOD_GPIO_730
:
380 reg
+= OMAP730_GPIO_DATA_INPUT
;
382 case METHOD_GPIO_24XX
:
383 reg
+= OMAP24XX_GPIO_DATAIN
;
389 return (__raw_readl(reg
)
390 & (1 << get_gpio_index(gpio
))) != 0;
393 #define MOD_REG_BIT(reg, bit_mask, set) \
395 int l = __raw_readl(base + reg); \
396 if (set) l |= bit_mask; \
397 else l &= ~bit_mask; \
398 __raw_writel(l, base + reg); \
401 static inline void set_24xx_gpio_triggering(void __iomem
*base
, int gpio
, int trigger
)
403 u32 gpio_bit
= 1 << gpio
;
405 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0
, gpio_bit
,
406 trigger
& __IRQT_LOWLVL
);
407 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1
, gpio_bit
,
408 trigger
& __IRQT_HIGHLVL
);
409 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT
, gpio_bit
,
410 trigger
& __IRQT_RISEDGE
);
411 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT
, gpio_bit
,
412 trigger
& __IRQT_FALEDGE
);
413 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
414 * triggering requested. */
417 static int _set_gpio_triggering(struct gpio_bank
*bank
, int gpio
, int trigger
)
419 void __iomem
*reg
= bank
->base
;
422 switch (bank
->method
) {
424 reg
+= OMAP_MPUIO_GPIO_INT_EDGE
;
425 l
= __raw_readl(reg
);
426 if (trigger
& __IRQT_RISEDGE
)
428 else if (trigger
& __IRQT_FALEDGE
)
433 case METHOD_GPIO_1510
:
434 reg
+= OMAP1510_GPIO_INT_CONTROL
;
435 l
= __raw_readl(reg
);
436 if (trigger
& __IRQT_RISEDGE
)
438 else if (trigger
& __IRQT_FALEDGE
)
443 case METHOD_GPIO_1610
:
445 reg
+= OMAP1610_GPIO_EDGE_CTRL2
;
447 reg
+= OMAP1610_GPIO_EDGE_CTRL1
;
449 /* We allow only edge triggering, i.e. two lowest bits */
450 if (trigger
& (__IRQT_LOWLVL
| __IRQT_HIGHLVL
))
452 l
= __raw_readl(reg
);
453 l
&= ~(3 << (gpio
<< 1));
454 if (trigger
& __IRQT_RISEDGE
)
455 l
|= 2 << (gpio
<< 1);
456 if (trigger
& __IRQT_FALEDGE
)
457 l
|= 1 << (gpio
<< 1);
459 case METHOD_GPIO_730
:
460 reg
+= OMAP730_GPIO_INT_CONTROL
;
461 l
= __raw_readl(reg
);
462 if (trigger
& __IRQT_RISEDGE
)
464 else if (trigger
& __IRQT_FALEDGE
)
469 case METHOD_GPIO_24XX
:
470 set_24xx_gpio_triggering(reg
, gpio
, trigger
);
476 __raw_writel(l
, reg
);
482 static int gpio_irq_type(unsigned irq
, unsigned type
)
484 struct gpio_bank
*bank
;
488 if (irq
> IH_MPUIO_BASE
)
489 gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
491 gpio
= irq
- IH_GPIO_BASE
;
493 if (check_gpio(gpio
) < 0)
496 if (type
& IRQT_PROBE
)
498 if (!cpu_is_omap24xx() && (type
& (__IRQT_LOWLVL
|__IRQT_HIGHLVL
)))
501 bank
= get_gpio_bank(gpio
);
502 spin_lock(&bank
->lock
);
503 retval
= _set_gpio_triggering(bank
, get_gpio_index(gpio
), type
);
504 spin_unlock(&bank
->lock
);
508 static void _clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
510 void __iomem
*reg
= bank
->base
;
512 switch (bank
->method
) {
514 /* MPUIO irqstatus is reset by reading the status register,
515 * so do nothing here */
517 case METHOD_GPIO_1510
:
518 reg
+= OMAP1510_GPIO_INT_STATUS
;
520 case METHOD_GPIO_1610
:
521 reg
+= OMAP1610_GPIO_IRQSTATUS1
;
523 case METHOD_GPIO_730
:
524 reg
+= OMAP730_GPIO_INT_STATUS
;
526 case METHOD_GPIO_24XX
:
527 reg
+= OMAP24XX_GPIO_IRQSTATUS1
;
533 __raw_writel(gpio_mask
, reg
);
535 /* Workaround for clearing DSP GPIO interrupts to allow retention */
536 if (cpu_is_omap2420())
537 __raw_writel(gpio_mask
, bank
->base
+ OMAP24XX_GPIO_IRQSTATUS2
);
540 static inline void _clear_gpio_irqstatus(struct gpio_bank
*bank
, int gpio
)
542 _clear_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
));
545 static u32
_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
547 void __iomem
*reg
= bank
->base
;
552 switch (bank
->method
) {
554 reg
+= OMAP_MPUIO_GPIO_MASKIT
;
558 case METHOD_GPIO_1510
:
559 reg
+= OMAP1510_GPIO_INT_MASK
;
563 case METHOD_GPIO_1610
:
564 reg
+= OMAP1610_GPIO_IRQENABLE1
;
567 case METHOD_GPIO_730
:
568 reg
+= OMAP730_GPIO_INT_MASK
;
572 case METHOD_GPIO_24XX
:
573 reg
+= OMAP24XX_GPIO_IRQENABLE1
;
581 l
= __raw_readl(reg
);
588 static void _enable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
, int enable
)
590 void __iomem
*reg
= bank
->base
;
593 switch (bank
->method
) {
595 reg
+= OMAP_MPUIO_GPIO_MASKIT
;
596 l
= __raw_readl(reg
);
602 case METHOD_GPIO_1510
:
603 reg
+= OMAP1510_GPIO_INT_MASK
;
604 l
= __raw_readl(reg
);
610 case METHOD_GPIO_1610
:
612 reg
+= OMAP1610_GPIO_SET_IRQENABLE1
;
614 reg
+= OMAP1610_GPIO_CLEAR_IRQENABLE1
;
617 case METHOD_GPIO_730
:
618 reg
+= OMAP730_GPIO_INT_MASK
;
619 l
= __raw_readl(reg
);
625 case METHOD_GPIO_24XX
:
627 reg
+= OMAP24XX_GPIO_SETIRQENABLE1
;
629 reg
+= OMAP24XX_GPIO_CLEARIRQENABLE1
;
636 __raw_writel(l
, reg
);
639 static inline void _set_gpio_irqenable(struct gpio_bank
*bank
, int gpio
, int enable
)
641 _enable_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
), enable
);
645 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
646 * 1510 does not seem to have a wake-up register. If JTAG is connected
647 * to the target, system will wake up always on GPIO events. While
648 * system is running all registered GPIO interrupts need to have wake-up
649 * enabled. When system is suspended, only selected GPIO interrupts need
650 * to have wake-up enabled.
652 static int _set_gpio_wakeup(struct gpio_bank
*bank
, int gpio
, int enable
)
654 switch (bank
->method
) {
655 case METHOD_GPIO_1610
:
656 case METHOD_GPIO_24XX
:
657 spin_lock(&bank
->lock
);
659 bank
->suspend_wakeup
|= (1 << gpio
);
661 bank
->suspend_wakeup
&= ~(1 << gpio
);
662 spin_unlock(&bank
->lock
);
665 printk(KERN_ERR
"Can't enable GPIO wakeup for method %i\n",
671 static void _reset_gpio(struct gpio_bank
*bank
, int gpio
)
673 _set_gpio_direction(bank
, get_gpio_index(gpio
), 1);
674 _set_gpio_irqenable(bank
, gpio
, 0);
675 _clear_gpio_irqstatus(bank
, gpio
);
676 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQT_NOEDGE
);
679 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
680 static int gpio_wake_enable(unsigned int irq
, unsigned int enable
)
682 unsigned int gpio
= irq
- IH_GPIO_BASE
;
683 struct gpio_bank
*bank
;
686 if (check_gpio(gpio
) < 0)
688 bank
= get_gpio_bank(gpio
);
689 retval
= _set_gpio_wakeup(bank
, get_gpio_index(gpio
), enable
);
694 int omap_request_gpio(int gpio
)
696 struct gpio_bank
*bank
;
698 if (check_gpio(gpio
) < 0)
701 bank
= get_gpio_bank(gpio
);
702 spin_lock(&bank
->lock
);
703 if (unlikely(bank
->reserved_map
& (1 << get_gpio_index(gpio
)))) {
704 printk(KERN_ERR
"omap-gpio: GPIO %d is already reserved!\n", gpio
);
706 spin_unlock(&bank
->lock
);
709 bank
->reserved_map
|= (1 << get_gpio_index(gpio
));
711 /* Set trigger to none. You need to enable the desired trigger with
712 * request_irq() or set_irq_type().
714 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQT_NOEDGE
);
716 #ifdef CONFIG_ARCH_OMAP15XX
717 if (bank
->method
== METHOD_GPIO_1510
) {
720 /* Claim the pin for MPU */
721 reg
= bank
->base
+ OMAP1510_GPIO_PIN_CONTROL
;
722 __raw_writel(__raw_readl(reg
) | (1 << get_gpio_index(gpio
)), reg
);
725 #ifdef CONFIG_ARCH_OMAP16XX
726 if (bank
->method
== METHOD_GPIO_1610
) {
727 /* Enable wake-up during idle for dynamic tick */
728 void __iomem
*reg
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
729 __raw_writel(1 << get_gpio_index(gpio
), reg
);
732 #ifdef CONFIG_ARCH_OMAP24XX
733 if (bank
->method
== METHOD_GPIO_24XX
) {
734 /* Enable wake-up during idle for dynamic tick */
735 void __iomem
*reg
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
736 __raw_writel(1 << get_gpio_index(gpio
), reg
);
739 spin_unlock(&bank
->lock
);
744 void omap_free_gpio(int gpio
)
746 struct gpio_bank
*bank
;
748 if (check_gpio(gpio
) < 0)
750 bank
= get_gpio_bank(gpio
);
751 spin_lock(&bank
->lock
);
752 if (unlikely(!(bank
->reserved_map
& (1 << get_gpio_index(gpio
))))) {
753 printk(KERN_ERR
"omap-gpio: GPIO %d wasn't reserved!\n", gpio
);
755 spin_unlock(&bank
->lock
);
758 #ifdef CONFIG_ARCH_OMAP16XX
759 if (bank
->method
== METHOD_GPIO_1610
) {
760 /* Disable wake-up during idle for dynamic tick */
761 void __iomem
*reg
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
762 __raw_writel(1 << get_gpio_index(gpio
), reg
);
765 #ifdef CONFIG_ARCH_OMAP24XX
766 if (bank
->method
== METHOD_GPIO_24XX
) {
767 /* Disable wake-up during idle for dynamic tick */
768 void __iomem
*reg
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
769 __raw_writel(1 << get_gpio_index(gpio
), reg
);
772 bank
->reserved_map
&= ~(1 << get_gpio_index(gpio
));
773 _reset_gpio(bank
, gpio
);
774 spin_unlock(&bank
->lock
);
778 * We need to unmask the GPIO bank interrupt as soon as possible to
779 * avoid missing GPIO interrupts for other lines in the bank.
780 * Then we need to mask-read-clear-unmask the triggered GPIO lines
781 * in the bank to avoid missing nested interrupts for a GPIO line.
782 * If we wait to unmask individual GPIO lines in the bank after the
783 * line's interrupt handler has been run, we may miss some nested
786 static void gpio_irq_handler(unsigned int irq
, struct irqdesc
*desc
)
788 void __iomem
*isr_reg
= NULL
;
790 unsigned int gpio_irq
;
791 struct gpio_bank
*bank
;
795 desc
->chip
->ack(irq
);
797 bank
= get_irq_data(irq
);
798 if (bank
->method
== METHOD_MPUIO
)
799 isr_reg
= bank
->base
+ OMAP_MPUIO_GPIO_INT
;
800 #ifdef CONFIG_ARCH_OMAP15XX
801 if (bank
->method
== METHOD_GPIO_1510
)
802 isr_reg
= bank
->base
+ OMAP1510_GPIO_INT_STATUS
;
804 #if defined(CONFIG_ARCH_OMAP16XX)
805 if (bank
->method
== METHOD_GPIO_1610
)
806 isr_reg
= bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
;
808 #ifdef CONFIG_ARCH_OMAP730
809 if (bank
->method
== METHOD_GPIO_730
)
810 isr_reg
= bank
->base
+ OMAP730_GPIO_INT_STATUS
;
812 #ifdef CONFIG_ARCH_OMAP24XX
813 if (bank
->method
== METHOD_GPIO_24XX
)
814 isr_reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS1
;
817 u32 isr_saved
, level_mask
= 0;
820 enabled
= _get_gpio_irqbank_mask(bank
);
821 isr_saved
= isr
= __raw_readl(isr_reg
) & enabled
;
823 if (cpu_is_omap15xx() && (bank
->method
== METHOD_MPUIO
))
826 if (cpu_is_omap24xx()) {
828 __raw_readl(bank
->base
+
829 OMAP24XX_GPIO_LEVELDETECT0
) |
830 __raw_readl(bank
->base
+
831 OMAP24XX_GPIO_LEVELDETECT1
);
832 level_mask
&= enabled
;
835 /* clear edge sensitive interrupts before handler(s) are
836 called so that we don't miss any interrupt occurred while
838 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 0);
839 _clear_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
840 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 1);
842 /* if there is only edge sensitive GPIO pin interrupts
843 configured, we could unmask GPIO bank interrupt immediately */
844 if (!level_mask
&& !unmasked
) {
846 desc
->chip
->unmask(irq
);
854 gpio_irq
= bank
->virtual_irq_start
;
855 for (; isr
!= 0; isr
>>= 1, gpio_irq
++) {
860 d
= irq_desc
+ gpio_irq
;
861 /* Don't run the handler if it's already running
862 * or was disabled lazely.
864 if (unlikely((d
->depth
||
865 (d
->status
& IRQ_INPROGRESS
)))) {
867 (gpio_irq
- bank
->virtual_irq_start
);
868 /* The unmasking will be done by
869 * enable_irq in case it is disabled or
870 * after returning from the handler if
871 * it's already running.
873 _enable_gpio_irqbank(bank
, irq_mask
, 0);
875 /* Level triggered interrupts
876 * won't ever be reentered
878 BUG_ON(level_mask
& irq_mask
);
879 d
->status
|= IRQ_PENDING
;
884 desc_handle_irq(gpio_irq
, d
);
886 if (unlikely((d
->status
& IRQ_PENDING
) && !d
->depth
)) {
888 (gpio_irq
- bank
->virtual_irq_start
);
889 d
->status
&= ~IRQ_PENDING
;
890 _enable_gpio_irqbank(bank
, irq_mask
, 1);
891 retrigger
|= irq_mask
;
895 if (cpu_is_omap24xx()) {
896 /* clear level sensitive interrupts after handler(s) */
897 _enable_gpio_irqbank(bank
, isr_saved
& level_mask
, 0);
898 _clear_gpio_irqbank(bank
, isr_saved
& level_mask
);
899 _enable_gpio_irqbank(bank
, isr_saved
& level_mask
, 1);
903 /* if bank has any level sensitive GPIO pin interrupt
904 configured, we must unmask the bank interrupt only after
905 handler(s) are executed in order to avoid spurious bank
908 desc
->chip
->unmask(irq
);
912 static void gpio_irq_shutdown(unsigned int irq
)
914 unsigned int gpio
= irq
- IH_GPIO_BASE
;
915 struct gpio_bank
*bank
= get_gpio_bank(gpio
);
917 _reset_gpio(bank
, gpio
);
920 static void gpio_ack_irq(unsigned int irq
)
922 unsigned int gpio
= irq
- IH_GPIO_BASE
;
923 struct gpio_bank
*bank
= get_gpio_bank(gpio
);
925 _clear_gpio_irqstatus(bank
, gpio
);
928 static void gpio_mask_irq(unsigned int irq
)
930 unsigned int gpio
= irq
- IH_GPIO_BASE
;
931 struct gpio_bank
*bank
= get_gpio_bank(gpio
);
933 _set_gpio_irqenable(bank
, gpio
, 0);
936 static void gpio_unmask_irq(unsigned int irq
)
938 unsigned int gpio
= irq
- IH_GPIO_BASE
;
939 unsigned int gpio_idx
= get_gpio_index(gpio
);
940 struct gpio_bank
*bank
= get_gpio_bank(gpio
);
942 _set_gpio_irqenable(bank
, gpio_idx
, 1);
945 static void mpuio_ack_irq(unsigned int irq
)
947 /* The ISR is reset automatically, so do nothing here. */
950 static void mpuio_mask_irq(unsigned int irq
)
952 unsigned int gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
953 struct gpio_bank
*bank
= get_gpio_bank(gpio
);
955 _set_gpio_irqenable(bank
, gpio
, 0);
958 static void mpuio_unmask_irq(unsigned int irq
)
960 unsigned int gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
961 struct gpio_bank
*bank
= get_gpio_bank(gpio
);
963 _set_gpio_irqenable(bank
, gpio
, 1);
966 static struct irq_chip gpio_irq_chip
= {
968 .shutdown
= gpio_irq_shutdown
,
970 .mask
= gpio_mask_irq
,
971 .unmask
= gpio_unmask_irq
,
972 .set_type
= gpio_irq_type
,
973 .set_wake
= gpio_wake_enable
,
976 static struct irq_chip mpuio_irq_chip
= {
978 .ack
= mpuio_ack_irq
,
979 .mask
= mpuio_mask_irq
,
980 .unmask
= mpuio_unmask_irq
983 static int initialized
;
984 static struct clk
* gpio_ick
;
985 static struct clk
* gpio_fck
;
987 static int __init
_omap_gpio_init(void)
990 struct gpio_bank
*bank
;
994 if (cpu_is_omap15xx()) {
995 gpio_ick
= clk_get(NULL
, "arm_gpio_ck");
996 if (IS_ERR(gpio_ick
))
997 printk("Could not get arm_gpio_ck\n");
999 clk_enable(gpio_ick
);
1001 if (cpu_is_omap24xx()) {
1002 gpio_ick
= clk_get(NULL
, "gpios_ick");
1003 if (IS_ERR(gpio_ick
))
1004 printk("Could not get gpios_ick\n");
1006 clk_enable(gpio_ick
);
1007 gpio_fck
= clk_get(NULL
, "gpios_fck");
1008 if (IS_ERR(gpio_fck
))
1009 printk("Could not get gpios_fck\n");
1011 clk_enable(gpio_fck
);
1014 #ifdef CONFIG_ARCH_OMAP15XX
1015 if (cpu_is_omap15xx()) {
1016 printk(KERN_INFO
"OMAP1510 GPIO hardware\n");
1017 gpio_bank_count
= 2;
1018 gpio_bank
= gpio_bank_1510
;
1021 #if defined(CONFIG_ARCH_OMAP16XX)
1022 if (cpu_is_omap16xx()) {
1025 gpio_bank_count
= 5;
1026 gpio_bank
= gpio_bank_1610
;
1027 rev
= omap_readw(gpio_bank
[1].base
+ OMAP1610_GPIO_REVISION
);
1028 printk(KERN_INFO
"OMAP GPIO hardware version %d.%d\n",
1029 (rev
>> 4) & 0x0f, rev
& 0x0f);
1032 #ifdef CONFIG_ARCH_OMAP730
1033 if (cpu_is_omap730()) {
1034 printk(KERN_INFO
"OMAP730 GPIO hardware\n");
1035 gpio_bank_count
= 7;
1036 gpio_bank
= gpio_bank_730
;
1039 #ifdef CONFIG_ARCH_OMAP24XX
1040 if (cpu_is_omap24xx()) {
1043 gpio_bank_count
= 4;
1044 gpio_bank
= gpio_bank_24xx
;
1045 rev
= omap_readl(gpio_bank
[0].base
+ OMAP24XX_GPIO_REVISION
);
1046 printk(KERN_INFO
"OMAP24xx GPIO hardware version %d.%d\n",
1047 (rev
>> 4) & 0x0f, rev
& 0x0f);
1050 for (i
= 0; i
< gpio_bank_count
; i
++) {
1051 int j
, gpio_count
= 16;
1053 bank
= &gpio_bank
[i
];
1054 bank
->reserved_map
= 0;
1055 bank
->base
= IO_ADDRESS(bank
->base
);
1056 spin_lock_init(&bank
->lock
);
1057 if (bank
->method
== METHOD_MPUIO
) {
1058 omap_writew(0xFFFF, OMAP_MPUIO_BASE
+ OMAP_MPUIO_GPIO_MASKIT
);
1060 #ifdef CONFIG_ARCH_OMAP15XX
1061 if (bank
->method
== METHOD_GPIO_1510
) {
1062 __raw_writew(0xffff, bank
->base
+ OMAP1510_GPIO_INT_MASK
);
1063 __raw_writew(0x0000, bank
->base
+ OMAP1510_GPIO_INT_STATUS
);
1066 #if defined(CONFIG_ARCH_OMAP16XX)
1067 if (bank
->method
== METHOD_GPIO_1610
) {
1068 __raw_writew(0x0000, bank
->base
+ OMAP1610_GPIO_IRQENABLE1
);
1069 __raw_writew(0xffff, bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
);
1070 __raw_writew(0x0014, bank
->base
+ OMAP1610_GPIO_SYSCONFIG
);
1073 #ifdef CONFIG_ARCH_OMAP730
1074 if (bank
->method
== METHOD_GPIO_730
) {
1075 __raw_writel(0xffffffff, bank
->base
+ OMAP730_GPIO_INT_MASK
);
1076 __raw_writel(0x00000000, bank
->base
+ OMAP730_GPIO_INT_STATUS
);
1078 gpio_count
= 32; /* 730 has 32-bit GPIOs */
1081 #ifdef CONFIG_ARCH_OMAP24XX
1082 if (bank
->method
== METHOD_GPIO_24XX
) {
1083 __raw_writel(0x00000000, bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
1084 __raw_writel(0xffffffff, bank
->base
+ OMAP24XX_GPIO_IRQSTATUS1
);
1089 for (j
= bank
->virtual_irq_start
;
1090 j
< bank
->virtual_irq_start
+ gpio_count
; j
++) {
1091 if (bank
->method
== METHOD_MPUIO
)
1092 set_irq_chip(j
, &mpuio_irq_chip
);
1094 set_irq_chip(j
, &gpio_irq_chip
);
1095 set_irq_handler(j
, do_simple_IRQ
);
1096 set_irq_flags(j
, IRQF_VALID
);
1098 set_irq_chained_handler(bank
->irq
, gpio_irq_handler
);
1099 set_irq_data(bank
->irq
, bank
);
1102 /* Enable system clock for GPIO module.
1103 * The CAM_CLK_CTRL *is* really the right place. */
1104 if (cpu_is_omap16xx())
1105 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL
) | 0x04, ULPD_CAM_CLK_CTRL
);
1110 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1111 static int omap_gpio_suspend(struct sys_device
*dev
, pm_message_t mesg
)
1115 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1118 for (i
= 0; i
< gpio_bank_count
; i
++) {
1119 struct gpio_bank
*bank
= &gpio_bank
[i
];
1120 void __iomem
*wake_status
;
1121 void __iomem
*wake_clear
;
1122 void __iomem
*wake_set
;
1124 switch (bank
->method
) {
1125 case METHOD_GPIO_1610
:
1126 wake_status
= bank
->base
+ OMAP1610_GPIO_WAKEUPENABLE
;
1127 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1128 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1130 case METHOD_GPIO_24XX
:
1131 wake_status
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1132 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1133 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1139 spin_lock(&bank
->lock
);
1140 bank
->saved_wakeup
= __raw_readl(wake_status
);
1141 __raw_writel(0xffffffff, wake_clear
);
1142 __raw_writel(bank
->suspend_wakeup
, wake_set
);
1143 spin_unlock(&bank
->lock
);
1149 static int omap_gpio_resume(struct sys_device
*dev
)
1153 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1156 for (i
= 0; i
< gpio_bank_count
; i
++) {
1157 struct gpio_bank
*bank
= &gpio_bank
[i
];
1158 void __iomem
*wake_clear
;
1159 void __iomem
*wake_set
;
1161 switch (bank
->method
) {
1162 case METHOD_GPIO_1610
:
1163 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1164 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1166 case METHOD_GPIO_24XX
:
1167 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1168 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1174 spin_lock(&bank
->lock
);
1175 __raw_writel(0xffffffff, wake_clear
);
1176 __raw_writel(bank
->saved_wakeup
, wake_set
);
1177 spin_unlock(&bank
->lock
);
1183 static struct sysdev_class omap_gpio_sysclass
= {
1184 set_kset_name("gpio"),
1185 .suspend
= omap_gpio_suspend
,
1186 .resume
= omap_gpio_resume
,
1189 static struct sys_device omap_gpio_device
= {
1191 .cls
= &omap_gpio_sysclass
,
1196 * This may get called early from board specific init
1197 * for boards that have interrupts routed via FPGA.
1199 int omap_gpio_init(void)
1202 return _omap_gpio_init();
1207 static int __init
omap_gpio_sysinit(void)
1212 ret
= _omap_gpio_init();
1214 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1215 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1217 ret
= sysdev_class_register(&omap_gpio_sysclass
);
1219 ret
= sysdev_register(&omap_gpio_device
);
1227 EXPORT_SYMBOL(omap_request_gpio
);
1228 EXPORT_SYMBOL(omap_free_gpio
);
1229 EXPORT_SYMBOL(omap_set_gpio_direction
);
1230 EXPORT_SYMBOL(omap_set_gpio_dataout
);
1231 EXPORT_SYMBOL(omap_get_gpio_datain
);
1233 arch_initcall(omap_gpio_sysinit
);