arch/arm/mach-ep93xx/core.c

   1 /*
   2  * arch/arm/mach-ep93xx/core.c
   3  * Core routines for Cirrus EP93xx chips.
   4  *
   5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
   6  *
   7  * Thanks go to Michael Burian and Ray Lehtiniemi for their key
   8  * role in the ep93xx linux community.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or (at
  13  * your option) any later version.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/sched.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/serial.h>
  22 #include <linux/tty.h>
  23 #include <linux/bitops.h>
  24 #include <linux/serial.h>
  25 #include <linux/serial_8250.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/device.h>
  28 #include <linux/mm.h>
  29 #include <linux/time.h>
  30 #include <linux/timex.h>
  31 #include <linux/delay.h>
  32 #include <linux/termios.h>
  33 #include <linux/amba/bus.h>
  34 #include <linux/amba/serial.h>
  35
  36 #include <asm/types.h>
  37 #include <asm/setup.h>
  38 #include <asm/memory.h>
  39 #include <asm/hardware.h>
  40 #include <asm/irq.h>
  41 #include <asm/system.h>
  42 #include <asm/tlbflush.h>
  43 #include <asm/pgtable.h>
  44 #include <asm/io.h>
  45
  46 #include <asm/mach/map.h>
  47 #include <asm/mach/time.h>
  48 #include <asm/mach/irq.h>
  49 #include <asm/arch/gpio.h>
  50
  51 #include <asm/hardware/vic.h>
  52
  53
  54 /*************************************************************************
  55  * Static I/O mappings that are needed for all EP93xx platforms
  56  *************************************************************************/
  57 static struct map_desc ep93xx_io_desc[] __initdata = {
  58         {
  59                 .virtual        = EP93XX_AHB_VIRT_BASE,
  60                 .pfn            = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
  61                 .length         = EP93XX_AHB_SIZE,
  62                 .type           = MT_DEVICE,
  63         }, {
  64                 .virtual        = EP93XX_APB_VIRT_BASE,
  65                 .pfn            = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
  66                 .length         = EP93XX_APB_SIZE,
  67                 .type           = MT_DEVICE,
  68         },
  69 };
  70
  71 void __init ep93xx_map_io(void)
  72 {
  73         iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
  74 }
  75
  76
  77 /*************************************************************************
  78  * Timer handling for EP93xx
  79  *************************************************************************
  80  * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
  81  * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
  82  * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
  83  * is free-running, and can't generate interrupts.
  84  *
  85  * The 508 kHz timers are ideal for use for the timer interrupt, as the
  86  * most common values of HZ divide 508 kHz nicely.  We pick one of the 16
  87  * bit timers (timer 1) since we don't need more than 16 bits of reload
  88  * value as long as HZ >= 8.
  89  *
  90  * The higher clock rate of timer 4 makes it a better choice than the
  91  * other timers for use in gettimeoffset(), while the fact that it can't
  92  * generate interrupts means we don't have to worry about not being able
  93  * to use this timer for something else.  We also use timer 4 for keeping
  94  * track of lost jiffies.
  95  */
  96 static unsigned int last_jiffy_time;
  97
  98 #define TIMER4_TICKS_PER_JIFFY          ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
  99
 100 static int ep93xx_timer_interrupt(int irq, void *dev_id)
 101 {
 102         write_seqlock(&xtime_lock);
 103
 104         __raw_writel(1, EP93XX_TIMER1_CLEAR);
 105         while ((signed long)
 106                 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
 107                                                 >= TIMER4_TICKS_PER_JIFFY) {
 108                 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
 109                 timer_tick();
 110         }
 111
 112         write_sequnlock(&xtime_lock);
 113
 114         return IRQ_HANDLED;
 115 }
 116
 117 static struct irqaction ep93xx_timer_irq = {
 118         .name           = "ep93xx timer",
 119         .flags          = IRQF_DISABLED | IRQF_TIMER,
 120         .handler        = ep93xx_timer_interrupt,
 121 };
 122
 123 static void __init ep93xx_timer_init(void)
 124 {
 125         /* Enable periodic HZ timer.  */
 126         __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
 127         __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
 128         __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
 129
 130         /* Enable lost jiffy timer.  */
 131         __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
 132
 133         setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
 134 }
 135
 136 static unsigned long ep93xx_gettimeoffset(void)
 137 {
 138         int offset;
 139
 140         offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
 141
 142         /* Calculate (1000000 / 983040) * offset.  */
 143         return offset + (53 * offset / 3072);
 144 }
 145
 146 struct sys_timer ep93xx_timer = {
 147         .init           = ep93xx_timer_init,
 148         .offset         = ep93xx_gettimeoffset,
 149 };
 150
 151
 152 /*************************************************************************
 153  * GPIO handling for EP93xx
 154  *************************************************************************/
 155 static unsigned char gpio_int_enable[2];
 156 static unsigned char gpio_int_type1[2];
 157 static unsigned char gpio_int_type2[2];
 158
 159 static void update_gpio_ab_int_params(int port)
 160 {
 161         if (port == 0) {
 162                 __raw_writeb(0, EP93XX_GPIO_A_INT_ENABLE);
 163                 __raw_writeb(gpio_int_type2[0], EP93XX_GPIO_A_INT_TYPE2);
 164                 __raw_writeb(gpio_int_type1[0], EP93XX_GPIO_A_INT_TYPE1);
 165                 __raw_writeb(gpio_int_enable[0], EP93XX_GPIO_A_INT_ENABLE);
 166         } else if (port == 1) {
 167                 __raw_writeb(0, EP93XX_GPIO_B_INT_ENABLE);
 168                 __raw_writeb(gpio_int_type2[1], EP93XX_GPIO_B_INT_TYPE2);
 169                 __raw_writeb(gpio_int_type1[1], EP93XX_GPIO_B_INT_TYPE1);
 170                 __raw_writeb(gpio_int_enable[1], EP93XX_GPIO_B_INT_ENABLE);
 171         }
 172 }
 173
 174
 175 static unsigned char data_register_offset[8] = {
 176         0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40,
 177 };
 178
 179 static unsigned char data_direction_register_offset[8] = {
 180         0x10, 0x14, 0x18, 0x1c, 0x24, 0x34, 0x3c, 0x44,
 181 };
 182
 183 void gpio_line_config(int line, int direction)
 184 {
 185         unsigned int data_direction_register;
 186         unsigned long flags;
 187         unsigned char v;
 188
 189         data_direction_register =
 190                 EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
 191
 192         local_irq_save(flags);
 193         if (direction == GPIO_OUT) {
 194                 if (line >= 0 && line < 16) {
 195                         gpio_int_enable[line >> 3] &= ~(1 << (line & 7));
 196                         update_gpio_ab_int_params(line >> 3);
 197                 }
 198
 199                 v = __raw_readb(data_direction_register);
 200                 v |= 1 << (line & 7);
 201                 __raw_writeb(v, data_direction_register);
 202         } else if (direction == GPIO_IN) {
 203                 v = __raw_readb(data_direction_register);
 204                 v &= ~(1 << (line & 7));
 205                 __raw_writeb(v, data_direction_register);
 206         }
 207         local_irq_restore(flags);
 208 }
 209 EXPORT_SYMBOL(gpio_line_config);
 210
 211 int gpio_line_get(int line)
 212 {
 213         unsigned int data_register;
 214
 215         data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
 216
 217         return !!(__raw_readb(data_register) & (1 << (line & 7)));
 218 }
 219 EXPORT_SYMBOL(gpio_line_get);
 220
 221 void gpio_line_set(int line, int value)
 222 {
 223         unsigned int data_register;
 224         unsigned long flags;
 225         unsigned char v;
 226
 227         data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
 228
 229         local_irq_save(flags);
 230         if (value == EP93XX_GPIO_HIGH) {
 231                 v = __raw_readb(data_register);
 232                 v |= 1 << (line & 7);
 233                 __raw_writeb(v, data_register);
 234         } else if (value == EP93XX_GPIO_LOW) {
 235                 v = __raw_readb(data_register);
 236                 v &= ~(1 << (line & 7));
 237                 __raw_writeb(v, data_register);
 238         }
 239         local_irq_restore(flags);
 240 }
 241 EXPORT_SYMBOL(gpio_line_set);
 242
 243
 244 /*************************************************************************
 245  * EP93xx IRQ handling
 246  *************************************************************************/
 247 static void ep93xx_gpio_ab_irq_handler(unsigned int irq,
 248                 struct irqdesc *desc)
 249 {
 250         unsigned char status;
 251         int i;
 252
 253         status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
 254         for (i = 0; i < 8; i++) {
 255                 if (status & (1 << i)) {
 256                         desc = irq_desc + IRQ_EP93XX_GPIO(0) + i;
 257                         desc_handle_irq(IRQ_EP93XX_GPIO(0) + i, desc);
 258                 }
 259         }
 260
 261         status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
 262         for (i = 0; i < 8; i++) {
 263                 if (status & (1 << i)) {
 264                         desc = irq_desc + IRQ_EP93XX_GPIO(8) + i;
 265                         desc_handle_irq(IRQ_EP93XX_GPIO(8) + i, desc);
 266                 }
 267         }
 268 }
 269
 270 static void ep93xx_gpio_ab_irq_mask_ack(unsigned int irq)
 271 {
 272         int line = irq - IRQ_EP93XX_GPIO(0);
 273         int port = line >> 3;
 274
 275         gpio_int_enable[port] &= ~(1 << (line & 7));
 276         update_gpio_ab_int_params(port);
 277
 278         if (line >> 3) {
 279                 __raw_writel(1 << (line & 7), EP93XX_GPIO_B_INT_ACK);
 280         } else {
 281                 __raw_writel(1 << (line & 7), EP93XX_GPIO_A_INT_ACK);
 282         }
 283 }
 284
 285 static void ep93xx_gpio_ab_irq_mask(unsigned int irq)
 286 {
 287         int line = irq - IRQ_EP93XX_GPIO(0);
 288         int port = line >> 3;
 289
 290         gpio_int_enable[port] &= ~(1 << (line & 7));
 291         update_gpio_ab_int_params(port);
 292 }
 293
 294 static void ep93xx_gpio_ab_irq_unmask(unsigned int irq)
 295 {
 296         int line = irq - IRQ_EP93XX_GPIO(0);
 297         int port = line >> 3;
 298
 299         gpio_int_enable[port] |= 1 << (line & 7);
 300         update_gpio_ab_int_params(port);
 301 }
 302
 303
 304 /*
 305  * gpio_int_type1 controls whether the interrupt is level (0) or
 306  * edge (1) triggered, while gpio_int_type2 controls whether it
 307  * triggers on low/falling (0) or high/rising (1).
 308  */
 309 static int ep93xx_gpio_ab_irq_type(unsigned int irq, unsigned int type)
 310 {
 311         int port;
 312         int line;
 313
 314         line = irq - IRQ_EP93XX_GPIO(0);
 315         gpio_line_config(line, GPIO_IN);
 316
 317         port = line >> 3;
 318         line &= 7;
 319
 320         if (type & IRQT_RISING) {
 321                 gpio_int_type1[port] |= 1 << line;
 322                 gpio_int_type2[port] |= 1 << line;
 323         } else if (type & IRQT_FALLING) {
 324                 gpio_int_type1[port] |= 1 << line;
 325                 gpio_int_type2[port] &= ~(1 << line);
 326         } else if (type & IRQT_HIGH) {
 327                 gpio_int_type1[port] &= ~(1 << line);
 328                 gpio_int_type2[port] |= 1 << line;
 329         } else if (type & IRQT_LOW) {
 330                 gpio_int_type1[port] &= ~(1 << line);
 331                 gpio_int_type2[port] &= ~(1 << line);
 332         }
 333         update_gpio_ab_int_params(port);
 334
 335         return 0;
 336 }
 337
 338 static struct irqchip ep93xx_gpio_ab_irq_chip = {
 339         .ack            = ep93xx_gpio_ab_irq_mask_ack,
 340         .mask           = ep93xx_gpio_ab_irq_mask,
 341         .unmask         = ep93xx_gpio_ab_irq_unmask,
 342         .set_type       = ep93xx_gpio_ab_irq_type,
 343 };
 344
 345
 346 void __init ep93xx_init_irq(void)
 347 {
 348         int irq;
 349
 350         vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
 351         vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
 352
 353         for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) {
 354                 set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip);
 355                 set_irq_handler(irq, do_level_IRQ);
 356                 set_irq_flags(irq, IRQF_VALID);
 357         }
 358         set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
 359 }
 360
 361
 362 /*************************************************************************
 363  * EP93xx peripheral handling
 364  *************************************************************************/
 365 #define EP93XX_UART_MCR_OFFSET          (0x0100)
 366
 367 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
 368                                   void __iomem *base, unsigned int mctrl)
 369 {
 370         unsigned int mcr;
 371
 372         mcr = 0;
 373         if (!(mctrl & TIOCM_RTS))
 374                 mcr |= 2;
 375         if (!(mctrl & TIOCM_DTR))
 376                 mcr |= 1;
 377
 378         __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
 379 }
 380
 381 static struct amba_pl010_data ep93xx_uart_data = {
 382         .set_mctrl      = ep93xx_uart_set_mctrl,
 383 };
 384
 385 static struct amba_device uart1_device = {
 386         .dev            = {
 387                 .bus_id         = "apb:uart1",
 388                 .platform_data  = &ep93xx_uart_data,
 389         },
 390         .res            = {
 391                 .start  = EP93XX_UART1_PHYS_BASE,
 392                 .end    = EP93XX_UART1_PHYS_BASE + 0x0fff,
 393                 .flags  = IORESOURCE_MEM,
 394         },
 395         .irq            = { IRQ_EP93XX_UART1, NO_IRQ },
 396         .periphid       = 0x00041010,
 397 };
 398
 399 static struct amba_device uart2_device = {
 400         .dev            = {
 401                 .bus_id         = "apb:uart2",
 402                 .platform_data  = &ep93xx_uart_data,
 403         },
 404         .res            = {
 405                 .start  = EP93XX_UART2_PHYS_BASE,
 406                 .end    = EP93XX_UART2_PHYS_BASE + 0x0fff,
 407                 .flags  = IORESOURCE_MEM,
 408         },
 409         .irq            = { IRQ_EP93XX_UART2, NO_IRQ },
 410         .periphid       = 0x00041010,
 411 };
 412
 413 static struct amba_device uart3_device = {
 414         .dev            = {
 415                 .bus_id         = "apb:uart3",
 416                 .platform_data  = &ep93xx_uart_data,
 417         },
 418         .res            = {
 419                 .start  = EP93XX_UART3_PHYS_BASE,
 420                 .end    = EP93XX_UART3_PHYS_BASE + 0x0fff,
 421                 .flags  = IORESOURCE_MEM,
 422         },
 423         .irq            = { IRQ_EP93XX_UART3, NO_IRQ },
 424         .periphid       = 0x00041010,
 425 };
 426
 427
 428 static struct platform_device ep93xx_rtc_device = {
 429        .name           = "ep93xx-rtc",
 430        .id             = -1,
 431        .num_resources  = 0,
 432 };
 433
 434
 435 static struct resource ep93xx_ohci_resources[] = {
 436         [0] = {
 437                 .start  = EP93XX_USB_PHYS_BASE,
 438                 .end    = EP93XX_USB_PHYS_BASE + 0x0fff,
 439                 .flags  = IORESOURCE_MEM,
 440         },
 441         [1] = {
 442                 .start  = IRQ_EP93XX_USB,
 443                 .end    = IRQ_EP93XX_USB,
 444                 .flags  = IORESOURCE_IRQ,
 445         },
 446 };
 447
 448 static struct platform_device ep93xx_ohci_device = {
 449         .name           = "ep93xx-ohci",
 450         .id             = -1,
 451         .dev            = {
 452                 .dma_mask               = (void *)0xffffffff,
 453                 .coherent_dma_mask      = 0xffffffff,
 454         },
 455         .num_resources  = ARRAY_SIZE(ep93xx_ohci_resources),
 456         .resource       = ep93xx_ohci_resources,
 457 };
 458
 459
 460 void __init ep93xx_init_devices(void)
 461 {
 462         unsigned int v;
 463
 464         ep93xx_clock_init();
 465
 466         /*
 467          * Disallow access to MaverickCrunch initially.
 468          */
 469         v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
 470         v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
 471         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
 472         __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
 473
 474         amba_device_register(&uart1_device, &iomem_resource);
 475         amba_device_register(&uart2_device, &iomem_resource);
 476         amba_device_register(&uart3_device, &iomem_resource);
 477
 478         platform_device_register(&ep93xx_rtc_device);
 479         platform_device_register(&ep93xx_ohci_device);
 480 }