include/asm-blackfin/cplbinit.h

   1 /*
   2  * File:         include/asm-blackfin/cplbinit.h
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Modified:
  10  *               Copyright 2004-2006 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #include <asm/blackfin.h>
  31 #include <asm/cplb.h>
  32
  33 #define INITIAL_T 0x1
  34 #define SWITCH_T  0x2
  35 #define I_CPLB    0x4
  36 #define D_CPLB    0x8
  37
  38 #define IN_KERNEL 1
  39
  40 enum
  41 {ZERO_P, L1I_MEM, L1D_MEM, SDRAM_KERN , SDRAM_RAM_MTD, SDRAM_DMAZ, RES_MEM, ASYNC_MEM, L2_MEM};
  42
  43 struct cplb_desc {
  44         u32 start; /* start address */
  45         u32 end; /* end address */
  46         u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
  47         u16 attr;/* attributes */
  48         u16 i_conf;/* I-CPLB DATA */
  49         u16 d_conf;/* D-CPLB DATA */
  50         u16 valid;/* valid */
  51         const s8 name[30];/* name */
  52 };
  53
  54 struct cplb_tab {
  55   u_long *tab;
  56         u16 pos;
  57         u16 size;
  58 };
  59
  60 u_long icplb_table[MAX_CPLBS+1];
  61 u_long dcplb_table[MAX_CPLBS+1];
  62
  63 /* Till here we are discussing about the static memory management model.
  64  * However, the operating envoronments commonly define more CPLB
  65  * descriptors to cover the entire addressable memory than will fit into
  66  * the available on-chip 16 CPLB MMRs. When this happens, the below table
  67  * will be used which will hold all the potentially required CPLB descriptors
  68  *
  69  * This is how Page descriptor Table is implemented in uClinux/Blackfin.
  70  */
  71
  72 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
  73 u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
  74 u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
  75
  76 #ifdef CONFIG_CPLB_INFO
  77 u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
  78 u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
  79 #endif /* CONFIG_CPLB_INFO */
  80
  81 #else
  82
  83 u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
  84 u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
  85
  86 #ifdef CONFIG_CPLB_INFO
  87 u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
  88 u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
  89 #endif /* CONFIG_CPLB_INFO */
  90
  91 #endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
  92
  93 struct s_cplb {
  94         struct cplb_tab init_i;
  95         struct cplb_tab init_d;
  96         struct cplb_tab switch_i;
  97         struct cplb_tab switch_d;
  98 };
  99
 100 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
 101 static struct cplb_desc cplb_data[] = {
 102         {
 103                 .start = 0,
 104                 .end = SIZE_4K,
 105                 .psize = SIZE_4K,
 106                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
 107                 .i_conf = SDRAM_OOPS,
 108                 .d_conf = SDRAM_OOPS,
 109 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
 110                 .valid = 1,
 111 #else
 112                 .valid = 0,
 113 #endif
 114                 .name = "ZERO Pointer Saveguard",
 115         },
 116         {
 117                 .start = L1_CODE_START,
 118                 .end = L1_CODE_START + L1_CODE_LENGTH,
 119                 .psize = SIZE_4M,
 120                 .attr = INITIAL_T | SWITCH_T | I_CPLB,
 121                 .i_conf = L1_IMEMORY,
 122                 .d_conf = 0,
 123                 .valid = 1,
 124                 .name = "L1 I-Memory",
 125         },
 126         {
 127                 .start = L1_DATA_A_START,
 128                 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
 129                 .psize = SIZE_4M,
 130                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 131                 .i_conf = 0,
 132                 .d_conf = L1_DMEMORY,
 133 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
 134                 .valid = 1,
 135 #else
 136                 .valid = 0,
 137 #endif
 138                 .name = "L1 D-Memory",
 139         },
 140         {
 141                 .start = 0,
 142                 .end = 0,  /* dynamic */
 143                 .psize = 0,
 144                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
 145                 .i_conf =  SDRAM_IGENERIC,
 146                 .d_conf =  SDRAM_DGENERIC,
 147                 .valid = 1,
 148                 .name = "SDRAM Kernel",
 149         },
 150         {
 151                 .start = 0, /* dynamic */
 152                 .end = 0, /* dynamic */
 153                 .psize = 0,
 154                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 155                 .i_conf =  SDRAM_IGENERIC,
 156                 .d_conf =  SDRAM_DNON_CHBL,
 157                 .valid = 1,
 158                 .name = "SDRAM RAM MTD",
 159         },
 160         {
 161                 .start = 0, /* dynamic */
 162                 .end = 0,   /* dynamic */
 163                 .psize = SIZE_1M,
 164                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 165                 .d_conf = SDRAM_DNON_CHBL,
 166                 .valid = 1,//(DMA_UNCACHED_REGION > 0),
 167                 .name = "SDRAM Uncached DMA ZONE",
 168         },
 169         {
 170                 .start = 0, /* dynamic */
 171                 .end = 0, /* dynamic */
 172                 .psize = 0,
 173                 .attr = SWITCH_T | D_CPLB,
 174                 .i_conf = 0, /* dynamic */
 175                 .d_conf = 0, /* dynamic */
 176                 .valid = 1,
 177                 .name = "SDRAM Reserved Memory",
 178         },
 179         {
 180                 .start = ASYNC_BANK0_BASE,
 181                 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
 182                 .psize = 0,
 183                 .attr = SWITCH_T | D_CPLB,
 184                 .d_conf = SDRAM_EBIU,
 185                 .valid = 1,
 186                 .name = "ASYNC Memory",
 187         },
 188         {
 189 #if defined(CONFIG_BF561)
 190                 .start = L2_SRAM,
 191                 .end = L2_SRAM_END,
 192                 .psize = SIZE_1M,
 193                 .attr = SWITCH_T | D_CPLB,
 194                 .i_conf = L2_MEMORY,
 195                 .d_conf = L2_MEMORY,
 196                 .valid = 1,
 197 #else
 198                 .valid = 0,
 199 #endif
 200                 .name = "L2 Memory",
 201         }
 202 };
 203 #endif