arch/sh/drivers/pci/pci.c

   1 /*
   2  * arch/sh/drivers/pci/pci.c
   3  *
   4  * Copyright (c) 2002 M. R. Brown  <mrbrown@linux-sh.org>
   5  * Copyright (c) 2004 - 2006 Paul Mundt  <lethal@linux-sh.org>
   6  *
   7  * These functions are collected here to reduce duplication of common
   8  * code amongst the many platform-specific PCI support code files.
   9  *
  10  * These routines require the following board-specific routines:
  11  * void pcibios_fixup_irqs();
  12  *
  13  * See include/asm-sh/pci.h for more information.
  14  *
  15  * This file is subject to the terms and conditions of the GNU General Public
  16  * License.  See the file "COPYING" in the main directory of this archive
  17  * for more details.
  18  */
  19 #include <linux/kernel.h>
  20 #include <linux/pci.h>
  21 #include <linux/init.h>
  22 #include <asm/io.h>
  23
  24 static inline u8 bridge_swizzle(u8 pin, u8 slot)
  25 {
  26         return (((pin - 1) + slot) % 4) + 1;
  27 }
  28
  29 static u8 __init simple_swizzle(struct pci_dev *dev, u8 *pinp)
  30 {
  31         u8 pin = *pinp;
  32
  33         while (dev->bus->parent) {
  34                 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
  35                 /* Move up the chain of bridges. */
  36                 dev = dev->bus->self;
  37         }
  38         *pinp = pin;
  39
  40         /* The slot is the slot of the last bridge. */
  41         return PCI_SLOT(dev->devfn);
  42 }
  43
  44 static int __init pcibios_init(void)
  45 {
  46         struct pci_channel *p;
  47         struct pci_bus *bus;
  48         int busno;
  49
  50 #ifdef CONFIG_PCI_AUTO
  51         /* assign resources */
  52         busno = 0;
  53         for (p = board_pci_channels; p->pci_ops != NULL; p++)
  54                 busno = pciauto_assign_resources(busno, p) + 1;
  55 #endif
  56
  57         /* scan the buses */
  58         busno = 0;
  59         for (p = board_pci_channels; p->pci_ops != NULL; p++) {
  60                 bus = pci_scan_bus(busno, p->pci_ops, p);
  61                 busno = bus->subordinate + 1;
  62         }
  63
  64         pci_fixup_irqs(simple_swizzle, pcibios_map_platform_irq);
  65
  66         return 0;
  67 }
  68 subsys_initcall(pcibios_init);
  69
  70 /*
  71  *  Called after each bus is probed, but before its children
  72  *  are examined.
  73  */
  74 void __devinit __weak pcibios_fixup_bus(struct pci_bus *bus)
  75 {
  76         pci_read_bridge_bases(bus);
  77 }
  78
  79 void pcibios_align_resource(void *data, struct resource *res,
  80                             resource_size_t size, resource_size_t align)
  81                             __attribute__ ((weak));
  82
  83 /*
  84  * We need to avoid collisions with `mirrored' VGA ports
  85  * and other strange ISA hardware, so we always want the
  86  * addresses to be allocated in the 0x000-0x0ff region
  87  * modulo 0x400.
  88  */
  89 void pcibios_align_resource(void *data, struct resource *res,
  90                             resource_size_t size, resource_size_t align)
  91 {
  92         if (res->flags & IORESOURCE_IO) {
  93                 resource_size_t start = res->start;
  94
  95                 if (start & 0x300) {
  96                         start = (start + 0x3ff) & ~0x3ff;
  97                         res->start = start;
  98                 }
  99         }
 100 }
 101
 102 int pcibios_enable_device(struct pci_dev *dev, int mask)
 103 {
 104         u16 cmd, old_cmd;
 105         int idx;
 106         struct resource *r;
 107
 108         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 109         old_cmd = cmd;
 110         for(idx=0; idx<6; idx++) {
 111                 if (!(mask & (1 << idx)))
 112                         continue;
 113                 r = &dev->resource[idx];
 114                 if (!r->start && r->end) {
 115                         printk(KERN_ERR "PCI: Device %s not available because "
 116                                "of resource collisions\n", pci_name(dev));
 117                         return -EINVAL;
 118                 }
 119                 if (r->flags & IORESOURCE_IO)
 120                         cmd |= PCI_COMMAND_IO;
 121                 if (r->flags & IORESOURCE_MEM)
 122                         cmd |= PCI_COMMAND_MEMORY;
 123         }
 124         if (dev->resource[PCI_ROM_RESOURCE].start)
 125                 cmd |= PCI_COMMAND_MEMORY;
 126         if (cmd != old_cmd) {
 127                 printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n",
 128                        pci_name(dev), old_cmd, cmd);
 129                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 130         }
 131         return 0;
 132 }
 133
 134 /*
 135  *  If we set up a device for bus mastering, we need to check and set
 136  *  the latency timer as it may not be properly set.
 137  */
 138 unsigned int pcibios_max_latency = 255;
 139
 140 void pcibios_set_master(struct pci_dev *dev)
 141 {
 142         u8 lat;
 143         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 144         if (lat < 16)
 145                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 146         else if (lat > pcibios_max_latency)
 147                 lat = pcibios_max_latency;
 148         else
 149                 return;
 150         printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
 151                pci_name(dev), lat);
 152         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 153 }
 154
 155 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
 156 {
 157         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 158 }
 159
 160 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
 161 {
 162         resource_size_t start = pci_resource_start(dev, bar);
 163         resource_size_t len = pci_resource_len(dev, bar);
 164         unsigned long flags = pci_resource_flags(dev, bar);
 165
 166         if (unlikely(!len || !start))
 167                 return NULL;
 168         if (maxlen && len > maxlen)
 169                 len = maxlen;
 170
 171         /*
 172          * Presently the IORESOURCE_MEM case is a bit special, most
 173          * SH7751 style PCI controllers have PCI memory at a fixed
 174          * location in the address space where no remapping is desired
 175          * (typically at 0xfd000000, but is_pci_memaddr() will know
 176          * best). With the IORESOURCE_MEM case more care has to be taken
 177          * to inhibit page table mapping for legacy cores, but this is
 178          * punted off to __ioremap().
 179          *                                      -- PFM.
 180          */
 181         if (flags & IORESOURCE_IO)
 182                 return ioport_map(start, len);
 183         if (flags & IORESOURCE_MEM)
 184                 return ioremap(start, len);
 185
 186         return NULL;
 187 }
 188 EXPORT_SYMBOL(pci_iomap);
 189
 190 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
 191 {
 192         iounmap(addr);
 193 }
 194 EXPORT_SYMBOL(pci_iounmap);